CA1041325A - Electronic musical instrument using integrated circuit components - Google Patents
Electronic musical instrument using integrated circuit componentsInfo
- Publication number
- CA1041325A CA1041325A CA225,605A CA225605A CA1041325A CA 1041325 A CA1041325 A CA 1041325A CA 225605 A CA225605 A CA 225605A CA 1041325 A CA1041325 A CA 1041325A
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- Prior art keywords
- output
- gate
- circuit
- programmable
- musical instrument
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Classifications
-
- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
- G10H7/00—Instruments in which the tones are synthesised from a data store, e.g. computer organs
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Multimedia (AREA)
- Electrophonic Musical Instruments (AREA)
Abstract
ELECTRONIC MUSICAL INSTRUMENT USING
INTEGRATED CIRCUIT COMPONENTS
Abstract of the Disclosure The embodiment of the invention disclosed herein is directed to an electronic musical instrument of the keyboard type wherein the audio frequency signal information is derived from a multi-frequency generator formed by an electronic oscillator and a plurality of divider circuits, and wherein programmable divider circuits are associated with the various keys of the keyboard to generate associated tone signal information. The programmable divider circuits are formed on a large scale integrated circuit chip and enable alteration of the numerical divisor so that different tone signals can be obtained from the same electronic circuitry thereby enabling the same type of LSI chip to be used for many different circuit configurations. The LSI chip also provides a scanning circuit that scans an X-Y matrix switching arrangement to determine which one of a plurality of key switches is closed. The inte-grated circuit unit has a plurality of such programmable divisors arranged to be operated from the same frequency, preferably there being four programmable divisors to obtain a multitude of output audio signal frequencies. Actuation of a key switch, chord button switch, or foot pedal will enable gate circuit components to cause a signal transfer from a matrix array to a read-only-memory circuit, which, in turn, enables selected ones of the programmable divisors for devel-oping the desired audio signal frequencies.
INTEGRATED CIRCUIT COMPONENTS
Abstract of the Disclosure The embodiment of the invention disclosed herein is directed to an electronic musical instrument of the keyboard type wherein the audio frequency signal information is derived from a multi-frequency generator formed by an electronic oscillator and a plurality of divider circuits, and wherein programmable divider circuits are associated with the various keys of the keyboard to generate associated tone signal information. The programmable divider circuits are formed on a large scale integrated circuit chip and enable alteration of the numerical divisor so that different tone signals can be obtained from the same electronic circuitry thereby enabling the same type of LSI chip to be used for many different circuit configurations. The LSI chip also provides a scanning circuit that scans an X-Y matrix switching arrangement to determine which one of a plurality of key switches is closed. The inte-grated circuit unit has a plurality of such programmable divisors arranged to be operated from the same frequency, preferably there being four programmable divisors to obtain a multitude of output audio signal frequencies. Actuation of a key switch, chord button switch, or foot pedal will enable gate circuit components to cause a signal transfer from a matrix array to a read-only-memory circuit, which, in turn, enables selected ones of the programmable divisors for devel-oping the desired audio signal frequencies.
Description
~0 ~ ~ 3 Zs Background of the Invention This invention relates generally to electronic musical instruments, and more particularly to electronic organs and the like, wherein a multi-frequency generator is used to generate a plurality of audio frequencies corres-ponding to the plurality of notes associated with various keys or foot pedals on a musical instrument. The keys or foot pedals are arranged to give either a single note tone or a chord note tone as desired.
Electronic organs have become relatively common in the musical industry and provide means for simulating the sounds produced by larger wind operated pipe organs, and the like. Such electronic organs differ from one another substantially in certaln speciic respects, such as whether the tone produced from the organ is obtained by a tone generator associated with additive or subtractive circuits.
They also differ as to the specific type of generator used to obtain the base frequency, as for example, whether they are transistor or tube oscillators, wind-driven reed elements, rotating tone wheels and the like. However, all of these electronic organs can be distinguished by certain common features. In particular, each organ has a plurality of tone generators, there being one tone generator for each note of the keyboard and foot pedal associated wîth a two-manual type organ. Furthermore, associated with the least expensive .~
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~ 04~325 types of electronic organs there is a single tone generator which is to be associated with the plurality of pedal tones, these tones being driven by one or more divider circuits connected to the single tone generator, which divides the frequency from the keyboard to obtain the desired notes.
This is accomplished without difficulty because only a single :
pedal note is played at a time so that only a single genera-tor is needed to produce the varlous signals.
It will be immediately apparent that there is a rather significant redundancy of tone generators used in prior art types of electronic organs. However, since the maximum number of notes that normally can be played at any one time is twelve, one note for each finger of the two hands and one note for each foot when manipulating the foot pedals, there are a multitude of tone generators that are not in use during this time. In popular organ playing, it is unusual to use more than one pedal tone at a given time and it is to be expected that no more than perhaps five notes will be played at any given time by the fingers of both hands. Some effort has been made to reduce the redun-dancy of tone generators needed by using tunable oscillators, wherein an oscillator is shared with two or three adjacent notes on the keyboard. This is done under the presumption that only one of these notes will be played at any given time. However, the presumption does not always hold true, ! `
and this is at best a low cost approach to developing ~
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eiectronic musical instruments of this type. In any event, there are still more tone generators needed than can be uitlized at any one time by a single person playing with both hands and both feet.
The oscillators or other tone generator devices provide an audio ~requency oscillation which bears a direct relation to the frequency of the note being played by the particular key on the keyboard or foot pedal. In the case of subtractive organ circuits, the note generated is the fun-damental of the note played. In this case a large number ofharmonics are provided by the particu^lar generator, and the undesired harmonics are filtered out in accordance with the organ stop which is then being used. On the other hand, in the case of additive organ circuits, the tone generated may be a sub-harmonic of the tone played and the sub-harmonlc is then multiplied to achieve the desired audio-frequency output.
All of the electronic organ circuitry heretofore utilized have been of the type which require discrete active and passive components formed in relatively large chassis or secured to large circuit boards or the like. These large circuit boards generally may be of the printed circuit type formed on fiberglass or other non-conductive sheet material.
These discrete components may take the form of individual ~
tubes or transistors as well as including a multitude of ~; -inductance and capacitance elements which provide the ~;
' .
~ V~325 necessary LC circuits for the oscillators~ Furthermore, coupling capacitors and voltage developing resistors may be -~
included in the plurality of discrete electronic components.
This type of prior art configuration, and any of the above types of organ arrangements, is relatively complex to manufacture, and furthermore, requires a substantial amount of maintenance over the life of the organ. As well as corrective and preventative maintenance, occasional tuning of the oscillator circuits is required to maintain the organ tone qualities in tune `~
Summary of the Invention Accordingly, it is an ob~ect of this invention to provide a new and improved electronic musical instrument circuit arrangement which can have the major portion thereof ormed as an integrated circuit component and which is com-pletely free of tuned circuits requiring induc~ance and ca-pacitance elements such as that used in oscillator circuits.
Another object of this invention is to provide a new and improved electronic musical instrument wherein a plurality of keys are connected in a matrix array configura-tion and the actuation of any particular key is determined as a result oftime-frame sequence scanning of the matrix array to produce an output pulse at a particular point in time of the scanned sequence. This output pulse is then used to energize or gate appropriate tone signal generators.
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Still another object of this invention is to provide a new and improved electronic musical instrument wherein a plurality of programmable divisor circuits are energized ~rom a common clock generator, and wherein the programmable divisor can be changed to produce the desired divisor output signal.
Many other objects, features and advantages of this invention will be more fully realized and understood from the ollowing detailed description when taken in conjunction with the accompanying drawings wherein like reference numerals throughout the various views of the drawings are intended to designate similar elements or components.
Brie~ Description of the Drawin~s Fig. 1 is a detailed block diagram of a portion of a logic circuit used in accordance with the principles . ~
o~ this invention;
Fig. 2 illustrates still another portion of the logic circuit utilized in accordance with the principles ;
of this invention;
Fig. 3 illustrates a single one of the programmable divisor circuits utilized in accordance with the principles of this invention and further illustrates a divide-by-two circuit arrangement wherein a sub-harmonic may be desired ~-to develop the appropriate tone signal; and Fig. 4 illustrates a plurality of programmable divisor circuits operated from a single input frequency and having their ~413Z5 ~ ~
outputs connected to a plurality of groups of dividers which, in turn, develop the appropriate tone signal information.
Detailed Description of the Illustratocl E~ di~nt Referring now to Fig. 1 there is seen a schematic logic diagram of an electronic musical instrument circuit con-figuration constructed in accordance with the principles o this invention and designated generally by reference numeral 10. Here the electronic ~usical instrument circuit 10 is pro-vided with a matrix array 12 which is formed in an X-Y pattern having a plurality of cross over points, each cross over point corresponding to a particular one of a plurality of keys to be actuated on the musical instrument. Each of the cross over points includesswitches 13 associated with the Y or ver-tical lines and which are to be actuated to short circuit or ;
engage with the X or horizontal lines of the matrix array.
Each of the switches 13 may correspond to a selected one of the pedal keys or to one of the chord keys or to one of the synthesizer keyboard keys to be played.
The matrix array 12 is scanned in a time-frame sequencing manner so that each cross over point is interrogated at a particular point in time of a given time-frame sequencer ~' In the illustrated embodiment there are twenty-eight cross over points provided by four horizontal lines and seven verti- ~
cal lines. ;
A scanning clock pulse signal is applied to an input -line 14, which is one of the inputs of an AND gate 16 to control the scanning sequence of operation of the electronic circuit 10.
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lV4~L32~
Thls scanning clock pulse is 5~ KHz and is obtained from a divide-by-ten circuit 40 connected to the main clock oscillator line 112 which uperates at 500 KHz. A second input line 17 is coupled to the AND gate 16 via an INVERTER 18 which is used to control or gate the clock pulse "on" or-"off". The output of AND gate 16 is delivered to a three-bit counter circuit 19 having the three binary outputs 31, 32 and 33 thereof coupled to a one-of-eight decoder network 20. The third stage of the three-stage divider 19 is coupled to an input terminal o~ a two-stage divider 21 which, in turn, has its binary outputs 34 and 35 coupled to a one-of-four output decoder circuit 22. The outputs o~ the one-of-four decoder circuit 22 which are 36, 37, 38 and 39 are coupled to each one o~ the horizontal lines oE the matrix array while the output o~ the one-oE-eight decoder circuit 20 is coupled to an associated one of a plurality of NAND gates 23, 24, 25, 26, 27, 28 and 29 associated with the seven vertical lines of the matrix array~ It will be understood that the dividers 19 and 21 together with the decoders 20 and 22 can be replaced with an eight-bit and a four-bit shi~t register.
The one-o~-four decoder 22 applies a logic one state ;-to each of the lines sequentially while the one-of-eight decoder 20 applies an enable signal also sequentially to the :~
associated one of a plurality of NAND gates 23, 24, 25, 26, .
27, 28 and 29. Thus, this 32 count counter system sequentially looks for closed switches starting with line 36 being high and then looking at the plurality of NAND gates one at a time.
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; ' 104~25 : ~
Therevre, whell one of the switches 13 is closed to have the horizontal associated line coupled to the vertical line~ a pulse signal will pass througll the NAND gate associated therewith. `~ ~
The outputs of the N~ND gates 23, 24, 25, 26, 27, 28 and 29 are ~ ?
delivered to a multi-input NAN~ gate 30 which, in turn, has its output coupled to line 41. This line 41 goes high whenever a switch closure in encountered at the proper switch count position of the scan counter formed by the one-of-~our decoder 22 and the one-of-eight decoder 20. The output of NAND gate 30 10 is also coupled to the input of a 32 bit shift register 42, the ;~
reset line of a two-bit shift register 43, AND gates 44 and 59 an INVERT~R 45, and two internally progranuned switcll~s 46 and 47. These two intervally progra~ned switches ~re connected as shown for the chord button system in what is called the ~-"lockout" mode or system. Whenever a closed switch is encoun~
tered, a high signal on line 41 passes through switch 46 and INVERTER 18 and then to AND gate 16. This signal will turn off the scan clock input, the scan counter system. l`hese signals will remain in this state until the chord button .:,: . , switch 13 is released, thus the signal on line 41 and line 17 will reverse and the clock will again start scanning until a ~ -new switch closure is encountered. This same switch closure `~
signal also passes through the internal switch 47 to line 48, which in Fig. 2 is the signal line for transierring and storing the closed chord switch count position. This same signal line 41 also goes to the reset input of a two-bit shift re~ister 43.
The output oE this shift register 43 goes one input of NOR
gate 4g. The other input of NOR gate 49 is the input terminal ..
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i~)4~325 51 which is the encode inhibit input. When the encode inhi~it input 51 is low and NOR gate 49 is enabled then when a chord switch closure is encountered, a signal on line 41 will reset the output of 43 ~o a low and the output of NOR
gate 49,which is output terminal 50,goes high. -This output terminal 50 is the D.C. gate output signal denoting that a switch is closed and thus turning "on" the proper audio frequencies from within the chip. Upon the release of the chord button switch it will take two clock input pulses on line 53 to this shift register 43 to return its output to a high level, thus, turning "off" terminal 50. Clock line 53 is the output of AND gate 52 whose inputs are H and 39 ~rom the switch scanning decoders above, thus, resu~ting ln an output at scan count 32 (end of a complete scan cycle).
Therefore, the scanning system must scan at least one com~
plete cycle without encountering a switch closure before ~;
ouput 50 will turn "off". -If the two internally programmed switches 46 and 47 are in the opposite position as shown, we have a "priority Z0 system" which is used for the pedal and synthesizer or manual keyboards. Switch closure signal line 41 also passes through INVERTER 45 to signal line 54. Line 54 is one input to AND
gate 5S whose outpu~ is the clock input to shift register 56.
Scan count 32~ line 53 is the "set" input to this shi~t register setting the output lines 57 and 58 to a high level. Thus, when the first switch closure of the scan is encountered, the signal line 41 to AND gate 44 will result in a high signal on the AND gate output to switch 47 and, thus, line - 10 - ' , .. . ~, , .
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10413ZS `
48 for trans~ering the switcll count position. Because the scan does not stop on the closed switch, at the next scan ~ :
count, signal line 41 returns to a low level and signal 54 to a high level resulting in a clock pulse to shift register :~
56 through AND gate 55. This clock pulse will. shift a low level to output lines 57 and 58, thus deactivating AND gates :~
44 and 55. Thus, any other switch closures o~ this same scan cycle will not be entered into this system until the set pulse at count 32 reactivates the system for the irst entry 10 of the next scan~ Thus, the first switch position at the :
cross over of line 36 and NAND gate 23 will be the lowest note on the pedal for "low note priority" and it will be the : :,. . .
highest note on a manual keyboard Eor llhigll note priority".
Switch closure signal line 41 also goes to the input oE a 32 bit shift register 42 and one input of AND gate 59. -This shift register has the same clock input as the scanning counter and decoders so each bit of the shift register coin~
cides with one position of the 32 count scan counter. When the ~irst switch closure is encountered the output line 61 ~.
20 of shift register is at a low level then AND gate 59 turns : :~
"on" while a high level is entered on tlle input o~ shi~t ;:
register 42. The output o~ AND gate 59 denotes a "new switch closure" and is the start input line to a nine-bit counter :
decoder system 62. This block 62 allows the clock input to . :
the counter and turns on an output line 65.
This output remains high until count 400 of the 512 ~ ;
count counter at which time the output goes low. At count 512 . - ~ . ..: , ,. , , : : : .
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the counter stops and r~mains off until a new start signal is received. The start signal starts the counter only if it is setting at count 512, so once the counter is operating a ~-new start signal will not do anything unless it occurs after the 512 counts. This 400 count at 50 KHz resulting in an 8 ms. pulse output signal on line 65 is used as a -control for keying percussive type voices from the keyboard. ~ ;
[banjo, wah-wah trumpet~ bass drum, etc.]. As the scanning of this system continues, on the next time around to the same swi.tch closure, signal line 41 to shift register 42 and AND
gate 59 is high again except the other input to AND gate 59 is low, however, because the output line 61 of the shi~t register is high. The shift register 42 is high because the switch closure was entered at the last scan of this switch position and the shift register "remembers" that the switch was closed before, thus, no pulse output on line 65. If a second switch closure is encountered, the AND gate 59 and, `
thus, output pulse on line 65 will again occur, even if this new switch is not entered on line 48 because of lower priority. As the scanning continues, and the key switch is released then at this key switch position there will be no signal on line 41, however, output line 61 of the shift register is high because this switch was still closed on the last scan. AND gate 63 will turn on the one-shot 64 because line 61 is high (switch closed on last scan) and line 54 (switch not closed on present scan) is high. The one-shot pulse width is controlled with the R-C values of the external ~ : ' - 12 - ~
ild .~ ' .. . ..
`- ~04:1~25 resistor 66a and capacitor 66. This one-shot output passes through internally programmed switch 46, through INVERTER 18 ;~
to AND gate 16 to stop the scan. This procedure is to insure against false pulse output signals due to contact bounce.
This one shot and scan stop will occur for the total delay o the one-shot of about 1 or 2 ms. If at any time, because o contact bounce, line 41 goes high and thus line 54 and AND gate 63 go low then the one-shot will immediatedly turn off and the scanning will again begin, but the switch closure ;
will still be retained in the shift register 42. Thus, if the : . .
switch is open again then on the next scan the same one-shot ;
signal with the scan stop will occur-with the same delay as -~
long as the switch closure is open for the entire delay. ` ;~
This one-shot delay can also occur on key closure if contact ` `
bounce is still present on the second scan o this switch closure. Howffver, here the delay will be long enough to ~;
insure the key closure remains entered. It should be noted this system gives a time delay built into the key switch relaease before releasing the shift re~ister 42, but the system can be ;
changed so the output of AND gate 59 dri~es the one-shot 64 and the delay occurs on key closure instead of key release. The on~y other change would be that the start input to the counter 62 would occur only at end of the complete time delay cycle of the `
one-shot which thus insures accepting a key closure. -Referring now to Fig. 2 the remainder of the logic circuit, which may be constructed on the same large scale inte~
grated circuit chip, is illustrated, Here the output pulse signal from line 48 is applied to the input o a storage latch ~. , , . .... , ~
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10~L3ZS
decoder circuit 68. This decoder circuit has a plurality of input lines corresponding to the output lines A-G of the eight output decoder 20, Fig. 1. Also connected to the storage latch decoder circùit 68 are a pair of input lines 34 and 35 which correspond to the outputs of the two-stage divider 21 of Fig. 1. The output of the storage latch decoder is delivered ;~
to a read-only-memory matrix 67 which has a plurality of groups of outputs 69 designated generally by Ml, M2, M3, M4' ;~
and M4 ", and C. The read-only-memory may be formed of two ;~ ~
memories, each having fourteen columns, thus praviding ~ `
a capacity for twenty-eight switches. However, when a twenty- ~ ; ;-one or a twenty-eight switch chord arrangement is used, only fourteen of the read-only columns are used with the sevenths added for the other seven or fourteen. Each o~ the M outputs provides a group of signal lines to be delivered to ;~
selected ones of a corresponding plurality of programmable divisor circuits to be described in more detail hereinbelow.
The oupput of the NOR gate 49, an output terminal 50, Fig. l, -is coupled to a line 70 to indicate that a key is closed.
This D.C. control signal is delivered to a NOR gate 72 and to ;
an OR gate 73. The NOR gate 72 has a second input which pro-vides automatic bass signal information at a terminal 74 to produce a first output signal across a line 76 and a second `
output signal, which is inverted from the first, over a line 77. These two output signals are delivered to selected ones of the inputs of a group of twelve pairs of NAND gates 78 and 79, respectively, NAND gates 78 and 79 have their outputs - 14 - ;
~.~ ~. .
104~325 coupled to the input of a second NAND gate 80. Therefore~ `
these twelve outputs wil-l produce either the M4' or the entire M4" output group by enabling ei~her of the NAND gates 78 or 79 in response to the output of the NOR gate 72 or the inverter 81 connected in series therewith. For the chord switches, the information stored in the storage latch circuit 68 will remain until a subsequent signal on line 48 is received.
It will be noted that the outputs of the latch 68 on lines 68a are delivered to an inverter 82 and a buffer 83 ~ ~
10 which, in turn, are connected to appropriate terminals for appli- ;
cation to various electronic components associated therewith, as -for example, in the "ORBIT" TM synthesizer system it is desirable to know which octave is being keyed in order to select the proper ilters for the flute voice frequency outputs. Besides the read-only-memory circuit 67 there is also five-bit memory cell 71 for controlling some of the chip functions. Two ~-~
control outputs go into a pair of NAND gates 86 and 87 which, in turn, are tied together at a pair of inputs of a NAND
gate 88. The second input to NAND gate 86 is the output line from INVERTER 82 above and the second input to the NAND gate 87 is from the output of the buffer 83. The output of NAND
gate 88 is applied to a first terminal 90 while the output ;
is also applied to a second terminal 91 through an inverter 92 which produces the same D.C. control but opposite in polarity. The use of these signals is to drive an output circuit associated with each of the programmable divisors, as set forth more clearly in Fig. 3 hereinbelow. Output ., - , . . . - .
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~ 04~32S
90 can be internally program~ed to be always high, always low, high for first fourteen switches only, or high for second fourteen switches only. Also associated with this memory cell 71 ls a three input ~ND gate 93 whose other two inputs are lines 77 ~BC) and output line of I~ERTER 82.
The output of this gate is the input of NAND gate 94 with the other input also being from the memory cell 71. The final output line 95 is a control line that can be programmed to always be high, always be low, or to be high only on the second fourteen swi~ches but only if control line 77 is such that the M4' instead of the M4' t control is tied to the last programmable divisor. Another line from this memory cell 71 goes to OR gate 73 to control output line 97. Output line 97 thus will either always be high or it will be high only during key closure. The memory cell also has an output line 96 which will be associated with the circuitry of Fig. 4. ~ ~
For a better understanding of the M outputs of the `
read-only-memory, reference is now made to Fig. 3 which illus- ~-trates one of the programmable divisor circuits associated with the circuit of Fig. 4. The programmable dlvisor circuit may be formed by a plurality of shift registers and gates.
The programmable divisor circuit is capable of changing the divisor from L00 to over 1,000 in order to obtain any preset audio frequency range of 500 Hz to 5 KHz using the 500 KHz input. Changing the input frequency will also change this range. However, to obtain more accurate frequency outputs, , , `:' ` ................................................................. . .
-~43~32S ~:
the divisor is maintained between 20~0 and 1,000. The M input .. ~ -is to be understood as containing a plurality of input lines which will obtain the appropriate interrogating code to activate : : -the programmable divisor here illustrated by reference numeral 100. The output of the programmable divisor is then dellvered ~ ~
over a line 101 to the input of a divide-by-two flip-flop cir- ~ , cuit 102 and to one input of a NAND gate 103, The output of :
the divide-by-two flip-flop circuit 102 is also delivered to a NAND gate 104. The outputs of each of the NAND gates 103 and 104 are delivered to a second NAND gate 106, The NAND gate :
103 or 104 which is enabled by application of an enabling signal ~-will determine whether or not the output of the programmable ;~
divisor is divided by one or divided by two. This is :;
determined by connecting the output lines 90 and 91 to the inputs of the NAND gates 103 and 104. If NAND gate 103 is enabled, the output of NAND gate 106 will be a divide-by-one output, while on the other hand, if NAND gate 104 is enabled, the output will be a divide-by-two. For the chord LSI, the extra divide-by-two is never used, for the pedal, the extra :
divide-by-two occurs on the closure of the first of the switches 13 only, and on the keyboard (synthesizer, etc.) the extra divide-by-two occurs on the closure of the second 14 of switches 13. The divide-by-one or divide-by-two circuit is designated generally by reference numeral 110 and is associated with each of the programmable divisors to be discussed with regard to Fig. 4.
1041;~Z5 Referring now to Fig. 4 there'is seen a logic circuit diagram which forms part of the present invention, and which may be constructed together with the rest of the components illustrated herein on a single large scale inte-grated circuit chip. Here an input line 112 receives a clock frequency which may vary between 0.2 to 2.5 megahertz. When the circuit as shown is used to produce chords and pedal notes, the input clock fre~uency will be 500 KHz. However, when using the principle of this circuit arrangement as a syn-thesizer, the input clock frequency will be 1.5 MHz. Thisinput clock frequency is applied to an input terminal of each of a plurality of programmable divisor circuits lOOa, lOOb, lOOc and lOOd as described with regard to Fig. 3. The M lnputs from the read-only-memory are connected to the control for the divisors designated generally by reference numerals 112, 113, 114 and 115. In accordance with the present invention, each of the prograMmable divisors is adapted to be changed so that the divisible factor associated therewith can be selected to produce any desired frequency type of output signal information. At present the programmable dlvisors are of the type which are set individually at the place of manufacture at the request of a potential purchaser by the program preset into the read-only-memory 67. However, it will be understood that the programmable divisors may include input memory means so that their par-ticular divisor factor at any given time can be altered ~0 ~ ~ ~ Z 5 ;
selectively~ The output of each of the programmable divisors -~
is delivered to a divide-by-one or divide-by-~wo circuit~ as ;
. , .
set forth in Fig. 3, llOa, llOb, llOc and llOd.
The output of the divide-by-one or divide-by-two network llOa is delivered to an output terminal lll and to the input of a first divide-by-two flip-flop circuit 114 which, ;~
in turn, has its output delivered to a divide--by-two flip-flop circuit 115 and a divide-by three flip-flop circuit 116 and to an input of an OR gate 117. This then starts the . . .
generation of a plurality of completely distinct output signals but which are to be considered as many octaves of the funda-mental frequencies. For example, the output of the divide-by-one or divide-by-two network llOa is delivered to one input of an OR gate 118 which, in turn, has its output delivered to an AND gate 119. However, the output of divide-by-two circuit `~
114 is also delivered to AND gate 119 and produces a first sub-harmonic output signal at a terminal 120. This signal includes both a high octave fundamental and a second har-monic frequency, The output of flip-flop 114 is also delivered through OR gate 117 to an AND gate 121 which, in turn, has another input thereof connected to the output of flip-flop circuit 115. ~ gate control circuit line 97 is applied to -a terminal 122 thereby providing a second output signal at terminal 123. This signal also incorporates a mid-octave fundamental frequen~y and a second harmonic, but this being one octave displaced from the signal developed at terminal ~, . . . . . . .
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~ 04132S
120. If the control line 96 from Fig. 2 is O (as in the chord chip) then the outputs at terminals 120 and 123 are one quarter duty cycle outputs, because the fundamentaL and second harmonic are gated together. This has a more desirable `~:
harmonic structure for voicing the two octaves of chords tha~
are generated. For the pedal and the synthesizer line 96 is ~:
high so only the square wave of each fundamental appears on these AND gate outputs. For all three systems control 97 is always high so all frequency outputs (terminals 120 and 123,, etc.) remain "on" even after the key or chord switch is re~
leased.
The output of flip-flop circuit 115 is delivered to ~:
a divide-by-two 1ip-flop circuit 124 which, in turn, has its output delivered to a second flip-flop circuit 126 and to the input of a NAND gate 127. The NAND gate 127 has a second :
input connected from control line 200 which is one of the 4 C control lines of the read-only-memory 67 of Fig. 2, thereby gat.ing therethrough the flip-flop signal to a NAND gate 128.
The output of flip-flop circuit 126 is delivered through an i:
OR gate 129 which, in turn, has its output also connected to the NAND gate 128. Control line 200 which is also an ~
input to OR gate 129 determines whether the output of NAND ::
gate 128 is from flip-flop 124 or from flip-flop 126. Thus, - control line 200 controls whether NAND gate 128 is one octav~
or two octaves below the chord frequency at terminal 123. :
This is used to obtain "chord inversion" on the chord chip ,', ~, . .
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.. . . .. - . . . . .: .
.
1~4~
where individual chord frequencies but not bass frequencies will revert up or down to remain in a one octave range. The output of NAND gate 128 is connected to both the AND gate .
130, which has its output connected to a terminal 131, and `~
also to the input of a divide-by-two flip-flop circuit 132.
This flip-flop circuit 132 is connected to an output terminal `
133 to produce a frequency signal which is an octave below that developed at terminal 131.
Referring back now to flip-flop circuit 114, the :~
output thereof is delivered to a series of flip-flop circuits :
beginning with a divide-by-three circuit 116 and continuing through a pair of flip-flop circuits 134 and 136. The output :
of flip-flop circuit 134 is delivered to the input of a NAND
gate 137 while the output of flip-flop circuit 136 ls delivered ~
to an OR gate 138. The outputs of NAND gate 137 and OR gate .
138 are brought together at AND gate 139 to combine signals and de:velop an audio signal at output terminal 140. The same control line 200 is the second input to NAND gate 137 and OR ~ :
gate 138. The particular frequency developed at the various output terminals is readily changeable by predetermined selec- ~ :
tion of the particular divisor factor obtained by the program- :
mable divider 100a.
Referring now to the output of divide-by-one and :
divide-by-two network 110b, it is connected to a :Elip-flop -divide;~by-two circuit 142 and to the input of an OR gate 143.
However, also connected to the output of this network is an ~()413Z5 ;, output terminal 144 which provides a first signal output to be utilized. The output of flip-flop 142 is connected to an OR
ga~e 146 and to an AND gate 147 which, in turn, produces an output signal at terminal 148 which is reducecl rom that deliv ered in terminal 144 by one octave. Flip-flop 142 is connected to the input of a second 1ip-flop 149 which, in turn, has its output connected to a flip-flop circuit 150 and to one of the inputs of an AND gate 151. The output of AND gate 151 is con-nected to an output terminal 152 which, in turn, delivers a 10 frequency which is one harmonic below that delivered to output :: :
terminal 148. Flip-flop circuit 150 is then coupled both to a .
flip-flop circuit 153 and to a NAND gate 154. The output of 1ip-flop 153 is delivered through OR gate 156 and is connected ;
to an AND gate 157 together with the output NAND gate 154. The :~
output signal developed at terminal 158 is one or two octaves .
below that developed at terminal 152 depending on the input ~ .
control line 201 from the C output lines of the read-only-memory .-67. The other control inputs are the same lines 96 and 97 ~ ~
.~ :
from above. - :
The output of the divide-by-one or divide-by-two network 110c is delivered to a divide-by-two flip-flop 160 and ~:
to the input of an OR gate 161 which, in turn, has its output delivered to an AND gate 162. The output of the divide-by-one :
or divide-by-two network 110c is also delivered to an output terminal 163 while the output of flip-flop circuit 160 is delivered to an output terminal 164 through AND gate 162 .. .. ... ~ ,. . .
. . ~ .. . .. . , ~, .. . , . - , . .. ...
lV4~ZS . -: -and is one octave lower in frequency than that delivered to terminal 163. The output of flip-flop 160 is aIso delivered to OR gate 164 which, in turn~ has its output delivered to AND gate 166 which has its output connected to tenminal 167.
Flip-flop 160 is also connected to flip-flop divide-by-two clrcuit 168 which, in turn, has its output cormected to a flip-flop 169 and to one of the inputs of AND gate 166. The output of flip-flop 168 is also deli-vered to NAND gate 170. ;
The output of NAND gate 170 is combined at an AND gate 171 `
with an output of flip-flop 169 which passes through OR gate ..
172. This then develops a signal at terminal 173 which is `;~
either one octave-below or the same frequency as that of the ~`
signal developed at terminal 167 depending on whether the control input line 202 from the read-only-memory 67 is low or high. Control lines 200, 201 and 202 are individually programmed in the read-only-memory for each chord button switch position.
The output of divide-by-one or divide-by-two circuit ~ `
110d is delivered to a flip-flop divider 180 and to an OR gate 181 which, in turn, each have an output connected to one of the inputs of an AND gate 182. The output of AND gate 182 is delivered to~a terminal 183 which produces the desired output signal. The output of flip-flop circuit 180 is also delivered to an OR gate 184, which has an output delivered to an AND gate 188, and to a flip-flop circuit 186 which, in turn, has its output delivered to a flip-flop circuit 187. The output of flip-flop circuit 186 is also delivered to the - 23 - ;
.: -; . . . . . . . .. .
: ~
~NO gate 188 which produces a signal at terminal 189. Flip-flop circuit 187 is delivered to AND gate 190 which has its output coupled back to one of the inputs of AND gate 130.
The control line inputs 96 and 97 to the OR and AND gates have -a similar function as above, however, there is an extra input control line 95 (from Fig. 2) to the two AND gates. This allows ~ `
that the outputs on terminals 183 and 189 be allowed only when the M4' divisor control (BC is high) is acting on the programmable divisor llOd and also one of the seventh's chord switches has been closed last. Any time the BC control goes low then the ~;~
programmable divisor llOd reverts to the M4 " control input, and ` -output terminal 131 reverts from NAND gate 128 to NAND gate 190, thus, changing what is normally programmed as the bass root frequency from programmable divisor I (lOOa) to the bass second frequency derived from the M4 " controlled programmable divisor IV (lOOd). This is used for the auto-bass (bass riff) on the chord button or pedal keyboard system.
Therefore, a single frequency input line 112, when deli.vered to four programmable divider circuits lOOa, lOOb, lOOc and lOOd can produce a multitude of different frequency ;
output signals at the various terminals located on the logic circuit of Fig. 4. The input line 112 is also connected to a divide-by-ten circuit 40 which produces the 50 RHz scanning pulses as shown in Fig. 1. This circuit may be a divide-by-thirty when the input clock is 1.5 MHz.
In this case all four programmable divisors are programmed by any one individual key switch of up to twenty-eight ~ V4~
~or more with more inputs and larger counter systems) key switches. If it is desirable to play up to four key switches simultaneously then this can be done with a separate decoder/ .
latch 68 and read-only memory 67 for each of the four (or more~
programmable divisors. Signals developed by gates 86, 87, 88 and 92 must be duplicated for each of the ~our latch output control lines 68a. Also these four latches would have to have four signal trans~er lines 48. This can be obtained by using a four-bit shift register for block 56 in Fig. 1 along with four AND gates 44. The line 58 input to each AND gate will be separate lines, one from each of the shift register outputs. If the count 32 reset signal puts a 1 in the first shift register and O's in the others (and remove AND gate 55 and connect line 54 as the CL input to 56), the first key switch in each scan will control programmable divisor I from shift register bit 1 through gate 44A, the second ;key switch closure in each scan will control programmable divisor I from shift register bit 1 through gate 44A, the second key switch closure in each scan will control program divisor II through shift register bit 2 and gate 44B, etc., for up to four key switches at a time. This can, there-fore, be used for a low cost single chip organ keyboard for up to 25, 37 or 44 keys by expanding on the key switch counter de-coder and matrix system and more key switches simultaneously by adding more latches and read-only-memories. -, - 25 -~.
- . . . ,. : : ,.,. : .... . .
.. : : . .. ; , . . . .. . .. . .
. . . .. .. . -. . - . ... .
.. . : . . . - . . . . ..... .. . ... . .. .... . .. . ....... .
~3413Z~; `
The entire circuitry illustrated on the drawings is formed on a large scale integrated circuit. The specific .~
embodiment illustrated herein is obtainable from The Wurlitzer ~ :
Company under part No. 141099. Other large scale integrated ;~
circuit chips which can be used in accordance with this invention are obtainable under part Nos. 142168 and 142169.
While a single specific embodiment of the invention , .. ~ . " .
is disclosed herein, it will be understood that a multitude of variations and modifications may be effected without :
departing from the spirit and scope thereof as set forth in the specification and claims disclosed herein.
''',' ~' ;`
`, - .
..;
::`
~ - 26 - ~
;'"' ,: . ,. ; . . ,: - : ~ - .: ..
.
..... ;, - . .. , ~ . : , , . . :,
Electronic organs have become relatively common in the musical industry and provide means for simulating the sounds produced by larger wind operated pipe organs, and the like. Such electronic organs differ from one another substantially in certaln speciic respects, such as whether the tone produced from the organ is obtained by a tone generator associated with additive or subtractive circuits.
They also differ as to the specific type of generator used to obtain the base frequency, as for example, whether they are transistor or tube oscillators, wind-driven reed elements, rotating tone wheels and the like. However, all of these electronic organs can be distinguished by certain common features. In particular, each organ has a plurality of tone generators, there being one tone generator for each note of the keyboard and foot pedal associated wîth a two-manual type organ. Furthermore, associated with the least expensive .~
.~
.
.. . . .. . . .
.: ~ . i . .. i....................... . . . . . .
~ 04~325 types of electronic organs there is a single tone generator which is to be associated with the plurality of pedal tones, these tones being driven by one or more divider circuits connected to the single tone generator, which divides the frequency from the keyboard to obtain the desired notes.
This is accomplished without difficulty because only a single :
pedal note is played at a time so that only a single genera-tor is needed to produce the varlous signals.
It will be immediately apparent that there is a rather significant redundancy of tone generators used in prior art types of electronic organs. However, since the maximum number of notes that normally can be played at any one time is twelve, one note for each finger of the two hands and one note for each foot when manipulating the foot pedals, there are a multitude of tone generators that are not in use during this time. In popular organ playing, it is unusual to use more than one pedal tone at a given time and it is to be expected that no more than perhaps five notes will be played at any given time by the fingers of both hands. Some effort has been made to reduce the redun-dancy of tone generators needed by using tunable oscillators, wherein an oscillator is shared with two or three adjacent notes on the keyboard. This is done under the presumption that only one of these notes will be played at any given time. However, the presumption does not always hold true, ! `
and this is at best a low cost approach to developing ~
-3- ~`
, . .
: `
4;~3~5 ~ `
eiectronic musical instruments of this type. In any event, there are still more tone generators needed than can be uitlized at any one time by a single person playing with both hands and both feet.
The oscillators or other tone generator devices provide an audio ~requency oscillation which bears a direct relation to the frequency of the note being played by the particular key on the keyboard or foot pedal. In the case of subtractive organ circuits, the note generated is the fun-damental of the note played. In this case a large number ofharmonics are provided by the particu^lar generator, and the undesired harmonics are filtered out in accordance with the organ stop which is then being used. On the other hand, in the case of additive organ circuits, the tone generated may be a sub-harmonic of the tone played and the sub-harmonlc is then multiplied to achieve the desired audio-frequency output.
All of the electronic organ circuitry heretofore utilized have been of the type which require discrete active and passive components formed in relatively large chassis or secured to large circuit boards or the like. These large circuit boards generally may be of the printed circuit type formed on fiberglass or other non-conductive sheet material.
These discrete components may take the form of individual ~
tubes or transistors as well as including a multitude of ~; -inductance and capacitance elements which provide the ~;
' .
~ V~325 necessary LC circuits for the oscillators~ Furthermore, coupling capacitors and voltage developing resistors may be -~
included in the plurality of discrete electronic components.
This type of prior art configuration, and any of the above types of organ arrangements, is relatively complex to manufacture, and furthermore, requires a substantial amount of maintenance over the life of the organ. As well as corrective and preventative maintenance, occasional tuning of the oscillator circuits is required to maintain the organ tone qualities in tune `~
Summary of the Invention Accordingly, it is an ob~ect of this invention to provide a new and improved electronic musical instrument circuit arrangement which can have the major portion thereof ormed as an integrated circuit component and which is com-pletely free of tuned circuits requiring induc~ance and ca-pacitance elements such as that used in oscillator circuits.
Another object of this invention is to provide a new and improved electronic musical instrument wherein a plurality of keys are connected in a matrix array configura-tion and the actuation of any particular key is determined as a result oftime-frame sequence scanning of the matrix array to produce an output pulse at a particular point in time of the scanned sequence. This output pulse is then used to energize or gate appropriate tone signal generators.
''`'''' .' :
.~ ' . ; . . . . . . : . - . , .
Still another object of this invention is to provide a new and improved electronic musical instrument wherein a plurality of programmable divisor circuits are energized ~rom a common clock generator, and wherein the programmable divisor can be changed to produce the desired divisor output signal.
Many other objects, features and advantages of this invention will be more fully realized and understood from the ollowing detailed description when taken in conjunction with the accompanying drawings wherein like reference numerals throughout the various views of the drawings are intended to designate similar elements or components.
Brie~ Description of the Drawin~s Fig. 1 is a detailed block diagram of a portion of a logic circuit used in accordance with the principles . ~
o~ this invention;
Fig. 2 illustrates still another portion of the logic circuit utilized in accordance with the principles ;
of this invention;
Fig. 3 illustrates a single one of the programmable divisor circuits utilized in accordance with the principles of this invention and further illustrates a divide-by-two circuit arrangement wherein a sub-harmonic may be desired ~-to develop the appropriate tone signal; and Fig. 4 illustrates a plurality of programmable divisor circuits operated from a single input frequency and having their ~413Z5 ~ ~
outputs connected to a plurality of groups of dividers which, in turn, develop the appropriate tone signal information.
Detailed Description of the Illustratocl E~ di~nt Referring now to Fig. 1 there is seen a schematic logic diagram of an electronic musical instrument circuit con-figuration constructed in accordance with the principles o this invention and designated generally by reference numeral 10. Here the electronic ~usical instrument circuit 10 is pro-vided with a matrix array 12 which is formed in an X-Y pattern having a plurality of cross over points, each cross over point corresponding to a particular one of a plurality of keys to be actuated on the musical instrument. Each of the cross over points includesswitches 13 associated with the Y or ver-tical lines and which are to be actuated to short circuit or ;
engage with the X or horizontal lines of the matrix array.
Each of the switches 13 may correspond to a selected one of the pedal keys or to one of the chord keys or to one of the synthesizer keyboard keys to be played.
The matrix array 12 is scanned in a time-frame sequencing manner so that each cross over point is interrogated at a particular point in time of a given time-frame sequencer ~' In the illustrated embodiment there are twenty-eight cross over points provided by four horizontal lines and seven verti- ~
cal lines. ;
A scanning clock pulse signal is applied to an input -line 14, which is one of the inputs of an AND gate 16 to control the scanning sequence of operation of the electronic circuit 10.
.. .. . ~ . . , ~ , . . . . . ... . . .
lV4~L32~
Thls scanning clock pulse is 5~ KHz and is obtained from a divide-by-ten circuit 40 connected to the main clock oscillator line 112 which uperates at 500 KHz. A second input line 17 is coupled to the AND gate 16 via an INVERTER 18 which is used to control or gate the clock pulse "on" or-"off". The output of AND gate 16 is delivered to a three-bit counter circuit 19 having the three binary outputs 31, 32 and 33 thereof coupled to a one-of-eight decoder network 20. The third stage of the three-stage divider 19 is coupled to an input terminal o~ a two-stage divider 21 which, in turn, has its binary outputs 34 and 35 coupled to a one-of-four output decoder circuit 22. The outputs o~ the one-of-four decoder circuit 22 which are 36, 37, 38 and 39 are coupled to each one o~ the horizontal lines oE the matrix array while the output o~ the one-oE-eight decoder circuit 20 is coupled to an associated one of a plurality of NAND gates 23, 24, 25, 26, 27, 28 and 29 associated with the seven vertical lines of the matrix array~ It will be understood that the dividers 19 and 21 together with the decoders 20 and 22 can be replaced with an eight-bit and a four-bit shi~t register.
The one-o~-four decoder 22 applies a logic one state ;-to each of the lines sequentially while the one-of-eight decoder 20 applies an enable signal also sequentially to the :~
associated one of a plurality of NAND gates 23, 24, 25, 26, .
27, 28 and 29. Thus, this 32 count counter system sequentially looks for closed switches starting with line 36 being high and then looking at the plurality of NAND gates one at a time.
- 8 - :
`
; ' 104~25 : ~
Therevre, whell one of the switches 13 is closed to have the horizontal associated line coupled to the vertical line~ a pulse signal will pass througll the NAND gate associated therewith. `~ ~
The outputs of the N~ND gates 23, 24, 25, 26, 27, 28 and 29 are ~ ?
delivered to a multi-input NAN~ gate 30 which, in turn, has its output coupled to line 41. This line 41 goes high whenever a switch closure in encountered at the proper switch count position of the scan counter formed by the one-of-~our decoder 22 and the one-of-eight decoder 20. The output of NAND gate 30 10 is also coupled to the input of a 32 bit shift register 42, the ;~
reset line of a two-bit shift register 43, AND gates 44 and 59 an INVERT~R 45, and two internally progranuned switcll~s 46 and 47. These two intervally progra~ned switches ~re connected as shown for the chord button system in what is called the ~-"lockout" mode or system. Whenever a closed switch is encoun~
tered, a high signal on line 41 passes through switch 46 and INVERTER 18 and then to AND gate 16. This signal will turn off the scan clock input, the scan counter system. l`hese signals will remain in this state until the chord button .:,: . , switch 13 is released, thus the signal on line 41 and line 17 will reverse and the clock will again start scanning until a ~ -new switch closure is encountered. This same switch closure `~
signal also passes through the internal switch 47 to line 48, which in Fig. 2 is the signal line for transierring and storing the closed chord switch count position. This same signal line 41 also goes to the reset input of a two-bit shift re~ister 43.
The output oE this shift register 43 goes one input of NOR
gate 4g. The other input of NOR gate 49 is the input terminal ..
. ' -9-. :. :. . : .. .. : . . . . . ..
i~)4~325 51 which is the encode inhibit input. When the encode inhi~it input 51 is low and NOR gate 49 is enabled then when a chord switch closure is encountered, a signal on line 41 will reset the output of 43 ~o a low and the output of NOR
gate 49,which is output terminal 50,goes high. -This output terminal 50 is the D.C. gate output signal denoting that a switch is closed and thus turning "on" the proper audio frequencies from within the chip. Upon the release of the chord button switch it will take two clock input pulses on line 53 to this shift register 43 to return its output to a high level, thus, turning "off" terminal 50. Clock line 53 is the output of AND gate 52 whose inputs are H and 39 ~rom the switch scanning decoders above, thus, resu~ting ln an output at scan count 32 (end of a complete scan cycle).
Therefore, the scanning system must scan at least one com~
plete cycle without encountering a switch closure before ~;
ouput 50 will turn "off". -If the two internally programmed switches 46 and 47 are in the opposite position as shown, we have a "priority Z0 system" which is used for the pedal and synthesizer or manual keyboards. Switch closure signal line 41 also passes through INVERTER 45 to signal line 54. Line 54 is one input to AND
gate 5S whose outpu~ is the clock input to shift register 56.
Scan count 32~ line 53 is the "set" input to this shi~t register setting the output lines 57 and 58 to a high level. Thus, when the first switch closure of the scan is encountered, the signal line 41 to AND gate 44 will result in a high signal on the AND gate output to switch 47 and, thus, line - 10 - ' , .. . ~, , .
.,. . . ~ .. ,. . , , ~"~.. , :.... : .
10413ZS `
48 for trans~ering the switcll count position. Because the scan does not stop on the closed switch, at the next scan ~ :
count, signal line 41 returns to a low level and signal 54 to a high level resulting in a clock pulse to shift register :~
56 through AND gate 55. This clock pulse will. shift a low level to output lines 57 and 58, thus deactivating AND gates :~
44 and 55. Thus, any other switch closures o~ this same scan cycle will not be entered into this system until the set pulse at count 32 reactivates the system for the irst entry 10 of the next scan~ Thus, the first switch position at the :
cross over of line 36 and NAND gate 23 will be the lowest note on the pedal for "low note priority" and it will be the : :,. . .
highest note on a manual keyboard Eor llhigll note priority".
Switch closure signal line 41 also goes to the input oE a 32 bit shift register 42 and one input of AND gate 59. -This shift register has the same clock input as the scanning counter and decoders so each bit of the shift register coin~
cides with one position of the 32 count scan counter. When the ~irst switch closure is encountered the output line 61 ~.
20 of shift register is at a low level then AND gate 59 turns : :~
"on" while a high level is entered on tlle input o~ shi~t ;:
register 42. The output o~ AND gate 59 denotes a "new switch closure" and is the start input line to a nine-bit counter :
decoder system 62. This block 62 allows the clock input to . :
the counter and turns on an output line 65.
This output remains high until count 400 of the 512 ~ ;
count counter at which time the output goes low. At count 512 . - ~ . ..: , ,. , , : : : .
~ . . . .
ZS ``
the counter stops and r~mains off until a new start signal is received. The start signal starts the counter only if it is setting at count 512, so once the counter is operating a ~-new start signal will not do anything unless it occurs after the 512 counts. This 400 count at 50 KHz resulting in an 8 ms. pulse output signal on line 65 is used as a -control for keying percussive type voices from the keyboard. ~ ;
[banjo, wah-wah trumpet~ bass drum, etc.]. As the scanning of this system continues, on the next time around to the same swi.tch closure, signal line 41 to shift register 42 and AND
gate 59 is high again except the other input to AND gate 59 is low, however, because the output line 61 of the shi~t register is high. The shift register 42 is high because the switch closure was entered at the last scan of this switch position and the shift register "remembers" that the switch was closed before, thus, no pulse output on line 65. If a second switch closure is encountered, the AND gate 59 and, `
thus, output pulse on line 65 will again occur, even if this new switch is not entered on line 48 because of lower priority. As the scanning continues, and the key switch is released then at this key switch position there will be no signal on line 41, however, output line 61 of the shift register is high because this switch was still closed on the last scan. AND gate 63 will turn on the one-shot 64 because line 61 is high (switch closed on last scan) and line 54 (switch not closed on present scan) is high. The one-shot pulse width is controlled with the R-C values of the external ~ : ' - 12 - ~
ild .~ ' .. . ..
`- ~04:1~25 resistor 66a and capacitor 66. This one-shot output passes through internally programmed switch 46, through INVERTER 18 ;~
to AND gate 16 to stop the scan. This procedure is to insure against false pulse output signals due to contact bounce.
This one shot and scan stop will occur for the total delay o the one-shot of about 1 or 2 ms. If at any time, because o contact bounce, line 41 goes high and thus line 54 and AND gate 63 go low then the one-shot will immediatedly turn off and the scanning will again begin, but the switch closure ;
will still be retained in the shift register 42. Thus, if the : . .
switch is open again then on the next scan the same one-shot ;
signal with the scan stop will occur-with the same delay as -~
long as the switch closure is open for the entire delay. ` ;~
This one-shot delay can also occur on key closure if contact ` `
bounce is still present on the second scan o this switch closure. Howffver, here the delay will be long enough to ~;
insure the key closure remains entered. It should be noted this system gives a time delay built into the key switch relaease before releasing the shift re~ister 42, but the system can be ;
changed so the output of AND gate 59 dri~es the one-shot 64 and the delay occurs on key closure instead of key release. The on~y other change would be that the start input to the counter 62 would occur only at end of the complete time delay cycle of the `
one-shot which thus insures accepting a key closure. -Referring now to Fig. 2 the remainder of the logic circuit, which may be constructed on the same large scale inte~
grated circuit chip, is illustrated, Here the output pulse signal from line 48 is applied to the input o a storage latch ~. , , . .... , ~
: , ~. .
"
10~L3ZS
decoder circuit 68. This decoder circuit has a plurality of input lines corresponding to the output lines A-G of the eight output decoder 20, Fig. 1. Also connected to the storage latch decoder circùit 68 are a pair of input lines 34 and 35 which correspond to the outputs of the two-stage divider 21 of Fig. 1. The output of the storage latch decoder is delivered ;~
to a read-only-memory matrix 67 which has a plurality of groups of outputs 69 designated generally by Ml, M2, M3, M4' ;~
and M4 ", and C. The read-only-memory may be formed of two ;~ ~
memories, each having fourteen columns, thus praviding ~ `
a capacity for twenty-eight switches. However, when a twenty- ~ ; ;-one or a twenty-eight switch chord arrangement is used, only fourteen of the read-only columns are used with the sevenths added for the other seven or fourteen. Each o~ the M outputs provides a group of signal lines to be delivered to ;~
selected ones of a corresponding plurality of programmable divisor circuits to be described in more detail hereinbelow.
The oupput of the NOR gate 49, an output terminal 50, Fig. l, -is coupled to a line 70 to indicate that a key is closed.
This D.C. control signal is delivered to a NOR gate 72 and to ;
an OR gate 73. The NOR gate 72 has a second input which pro-vides automatic bass signal information at a terminal 74 to produce a first output signal across a line 76 and a second `
output signal, which is inverted from the first, over a line 77. These two output signals are delivered to selected ones of the inputs of a group of twelve pairs of NAND gates 78 and 79, respectively, NAND gates 78 and 79 have their outputs - 14 - ;
~.~ ~. .
104~325 coupled to the input of a second NAND gate 80. Therefore~ `
these twelve outputs wil-l produce either the M4' or the entire M4" output group by enabling ei~her of the NAND gates 78 or 79 in response to the output of the NOR gate 72 or the inverter 81 connected in series therewith. For the chord switches, the information stored in the storage latch circuit 68 will remain until a subsequent signal on line 48 is received.
It will be noted that the outputs of the latch 68 on lines 68a are delivered to an inverter 82 and a buffer 83 ~ ~
10 which, in turn, are connected to appropriate terminals for appli- ;
cation to various electronic components associated therewith, as -for example, in the "ORBIT" TM synthesizer system it is desirable to know which octave is being keyed in order to select the proper ilters for the flute voice frequency outputs. Besides the read-only-memory circuit 67 there is also five-bit memory cell 71 for controlling some of the chip functions. Two ~-~
control outputs go into a pair of NAND gates 86 and 87 which, in turn, are tied together at a pair of inputs of a NAND
gate 88. The second input to NAND gate 86 is the output line from INVERTER 82 above and the second input to the NAND gate 87 is from the output of the buffer 83. The output of NAND
gate 88 is applied to a first terminal 90 while the output ;
is also applied to a second terminal 91 through an inverter 92 which produces the same D.C. control but opposite in polarity. The use of these signals is to drive an output circuit associated with each of the programmable divisors, as set forth more clearly in Fig. 3 hereinbelow. Output ., - , . . . - .
:,: . . . , i . ...
~ 04~32S
90 can be internally program~ed to be always high, always low, high for first fourteen switches only, or high for second fourteen switches only. Also associated with this memory cell 71 ls a three input ~ND gate 93 whose other two inputs are lines 77 ~BC) and output line of I~ERTER 82.
The output of this gate is the input of NAND gate 94 with the other input also being from the memory cell 71. The final output line 95 is a control line that can be programmed to always be high, always be low, or to be high only on the second fourteen swi~ches but only if control line 77 is such that the M4' instead of the M4' t control is tied to the last programmable divisor. Another line from this memory cell 71 goes to OR gate 73 to control output line 97. Output line 97 thus will either always be high or it will be high only during key closure. The memory cell also has an output line 96 which will be associated with the circuitry of Fig. 4. ~ ~
For a better understanding of the M outputs of the `
read-only-memory, reference is now made to Fig. 3 which illus- ~-trates one of the programmable divisor circuits associated with the circuit of Fig. 4. The programmable dlvisor circuit may be formed by a plurality of shift registers and gates.
The programmable divisor circuit is capable of changing the divisor from L00 to over 1,000 in order to obtain any preset audio frequency range of 500 Hz to 5 KHz using the 500 KHz input. Changing the input frequency will also change this range. However, to obtain more accurate frequency outputs, , , `:' ` ................................................................. . .
-~43~32S ~:
the divisor is maintained between 20~0 and 1,000. The M input .. ~ -is to be understood as containing a plurality of input lines which will obtain the appropriate interrogating code to activate : : -the programmable divisor here illustrated by reference numeral 100. The output of the programmable divisor is then dellvered ~ ~
over a line 101 to the input of a divide-by-two flip-flop cir- ~ , cuit 102 and to one input of a NAND gate 103, The output of :
the divide-by-two flip-flop circuit 102 is also delivered to a NAND gate 104. The outputs of each of the NAND gates 103 and 104 are delivered to a second NAND gate 106, The NAND gate :
103 or 104 which is enabled by application of an enabling signal ~-will determine whether or not the output of the programmable ;~
divisor is divided by one or divided by two. This is :;
determined by connecting the output lines 90 and 91 to the inputs of the NAND gates 103 and 104. If NAND gate 103 is enabled, the output of NAND gate 106 will be a divide-by-one output, while on the other hand, if NAND gate 104 is enabled, the output will be a divide-by-two. For the chord LSI, the extra divide-by-two is never used, for the pedal, the extra :
divide-by-two occurs on the closure of the first of the switches 13 only, and on the keyboard (synthesizer, etc.) the extra divide-by-two occurs on the closure of the second 14 of switches 13. The divide-by-one or divide-by-two circuit is designated generally by reference numeral 110 and is associated with each of the programmable divisors to be discussed with regard to Fig. 4.
1041;~Z5 Referring now to Fig. 4 there'is seen a logic circuit diagram which forms part of the present invention, and which may be constructed together with the rest of the components illustrated herein on a single large scale inte-grated circuit chip. Here an input line 112 receives a clock frequency which may vary between 0.2 to 2.5 megahertz. When the circuit as shown is used to produce chords and pedal notes, the input clock fre~uency will be 500 KHz. However, when using the principle of this circuit arrangement as a syn-thesizer, the input clock frequency will be 1.5 MHz. Thisinput clock frequency is applied to an input terminal of each of a plurality of programmable divisor circuits lOOa, lOOb, lOOc and lOOd as described with regard to Fig. 3. The M lnputs from the read-only-memory are connected to the control for the divisors designated generally by reference numerals 112, 113, 114 and 115. In accordance with the present invention, each of the prograMmable divisors is adapted to be changed so that the divisible factor associated therewith can be selected to produce any desired frequency type of output signal information. At present the programmable dlvisors are of the type which are set individually at the place of manufacture at the request of a potential purchaser by the program preset into the read-only-memory 67. However, it will be understood that the programmable divisors may include input memory means so that their par-ticular divisor factor at any given time can be altered ~0 ~ ~ ~ Z 5 ;
selectively~ The output of each of the programmable divisors -~
is delivered to a divide-by-one or divide-by-~wo circuit~ as ;
. , .
set forth in Fig. 3, llOa, llOb, llOc and llOd.
The output of the divide-by-one or divide-by-two network llOa is delivered to an output terminal lll and to the input of a first divide-by-two flip-flop circuit 114 which, ;~
in turn, has its output delivered to a divide--by-two flip-flop circuit 115 and a divide-by three flip-flop circuit 116 and to an input of an OR gate 117. This then starts the . . .
generation of a plurality of completely distinct output signals but which are to be considered as many octaves of the funda-mental frequencies. For example, the output of the divide-by-one or divide-by-two network llOa is delivered to one input of an OR gate 118 which, in turn, has its output delivered to an AND gate 119. However, the output of divide-by-two circuit `~
114 is also delivered to AND gate 119 and produces a first sub-harmonic output signal at a terminal 120. This signal includes both a high octave fundamental and a second har-monic frequency, The output of flip-flop 114 is also delivered through OR gate 117 to an AND gate 121 which, in turn, has another input thereof connected to the output of flip-flop circuit 115. ~ gate control circuit line 97 is applied to -a terminal 122 thereby providing a second output signal at terminal 123. This signal also incorporates a mid-octave fundamental frequen~y and a second harmonic, but this being one octave displaced from the signal developed at terminal ~, . . . . . . .
.
.. . ..
~ 04132S
120. If the control line 96 from Fig. 2 is O (as in the chord chip) then the outputs at terminals 120 and 123 are one quarter duty cycle outputs, because the fundamentaL and second harmonic are gated together. This has a more desirable `~:
harmonic structure for voicing the two octaves of chords tha~
are generated. For the pedal and the synthesizer line 96 is ~:
high so only the square wave of each fundamental appears on these AND gate outputs. For all three systems control 97 is always high so all frequency outputs (terminals 120 and 123,, etc.) remain "on" even after the key or chord switch is re~
leased.
The output of flip-flop circuit 115 is delivered to ~:
a divide-by-two 1ip-flop circuit 124 which, in turn, has its output delivered to a second flip-flop circuit 126 and to the input of a NAND gate 127. The NAND gate 127 has a second :
input connected from control line 200 which is one of the 4 C control lines of the read-only-memory 67 of Fig. 2, thereby gat.ing therethrough the flip-flop signal to a NAND gate 128.
The output of flip-flop circuit 126 is delivered through an i:
OR gate 129 which, in turn, has its output also connected to the NAND gate 128. Control line 200 which is also an ~
input to OR gate 129 determines whether the output of NAND ::
gate 128 is from flip-flop 124 or from flip-flop 126. Thus, - control line 200 controls whether NAND gate 128 is one octav~
or two octaves below the chord frequency at terminal 123. :
This is used to obtain "chord inversion" on the chord chip ,', ~, . .
. . ... . . .
.. . . .. - . . . . .: .
.
1~4~
where individual chord frequencies but not bass frequencies will revert up or down to remain in a one octave range. The output of NAND gate 128 is connected to both the AND gate .
130, which has its output connected to a terminal 131, and `~
also to the input of a divide-by-two flip-flop circuit 132.
This flip-flop circuit 132 is connected to an output terminal `
133 to produce a frequency signal which is an octave below that developed at terminal 131.
Referring back now to flip-flop circuit 114, the :~
output thereof is delivered to a series of flip-flop circuits :
beginning with a divide-by-three circuit 116 and continuing through a pair of flip-flop circuits 134 and 136. The output :
of flip-flop circuit 134 is delivered to the input of a NAND
gate 137 while the output of flip-flop circuit 136 ls delivered ~
to an OR gate 138. The outputs of NAND gate 137 and OR gate .
138 are brought together at AND gate 139 to combine signals and de:velop an audio signal at output terminal 140. The same control line 200 is the second input to NAND gate 137 and OR ~ :
gate 138. The particular frequency developed at the various output terminals is readily changeable by predetermined selec- ~ :
tion of the particular divisor factor obtained by the program- :
mable divider 100a.
Referring now to the output of divide-by-one and :
divide-by-two network 110b, it is connected to a :Elip-flop -divide;~by-two circuit 142 and to the input of an OR gate 143.
However, also connected to the output of this network is an ~()413Z5 ;, output terminal 144 which provides a first signal output to be utilized. The output of flip-flop 142 is connected to an OR
ga~e 146 and to an AND gate 147 which, in turn, produces an output signal at terminal 148 which is reducecl rom that deliv ered in terminal 144 by one octave. Flip-flop 142 is connected to the input of a second 1ip-flop 149 which, in turn, has its output connected to a flip-flop circuit 150 and to one of the inputs of an AND gate 151. The output of AND gate 151 is con-nected to an output terminal 152 which, in turn, delivers a 10 frequency which is one harmonic below that delivered to output :: :
terminal 148. Flip-flop circuit 150 is then coupled both to a .
flip-flop circuit 153 and to a NAND gate 154. The output of 1ip-flop 153 is delivered through OR gate 156 and is connected ;
to an AND gate 157 together with the output NAND gate 154. The :~
output signal developed at terminal 158 is one or two octaves .
below that developed at terminal 152 depending on the input ~ .
control line 201 from the C output lines of the read-only-memory .-67. The other control inputs are the same lines 96 and 97 ~ ~
.~ :
from above. - :
The output of the divide-by-one or divide-by-two network 110c is delivered to a divide-by-two flip-flop 160 and ~:
to the input of an OR gate 161 which, in turn, has its output delivered to an AND gate 162. The output of the divide-by-one :
or divide-by-two network 110c is also delivered to an output terminal 163 while the output of flip-flop circuit 160 is delivered to an output terminal 164 through AND gate 162 .. .. ... ~ ,. . .
. . ~ .. . .. . , ~, .. . , . - , . .. ...
lV4~ZS . -: -and is one octave lower in frequency than that delivered to terminal 163. The output of flip-flop 160 is aIso delivered to OR gate 164 which, in turn~ has its output delivered to AND gate 166 which has its output connected to tenminal 167.
Flip-flop 160 is also connected to flip-flop divide-by-two clrcuit 168 which, in turn, has its output cormected to a flip-flop 169 and to one of the inputs of AND gate 166. The output of flip-flop 168 is also deli-vered to NAND gate 170. ;
The output of NAND gate 170 is combined at an AND gate 171 `
with an output of flip-flop 169 which passes through OR gate ..
172. This then develops a signal at terminal 173 which is `;~
either one octave-below or the same frequency as that of the ~`
signal developed at terminal 167 depending on whether the control input line 202 from the read-only-memory 67 is low or high. Control lines 200, 201 and 202 are individually programmed in the read-only-memory for each chord button switch position.
The output of divide-by-one or divide-by-two circuit ~ `
110d is delivered to a flip-flop divider 180 and to an OR gate 181 which, in turn, each have an output connected to one of the inputs of an AND gate 182. The output of AND gate 182 is delivered to~a terminal 183 which produces the desired output signal. The output of flip-flop circuit 180 is also delivered to an OR gate 184, which has an output delivered to an AND gate 188, and to a flip-flop circuit 186 which, in turn, has its output delivered to a flip-flop circuit 187. The output of flip-flop circuit 186 is also delivered to the - 23 - ;
.: -; . . . . . . . .. .
: ~
~NO gate 188 which produces a signal at terminal 189. Flip-flop circuit 187 is delivered to AND gate 190 which has its output coupled back to one of the inputs of AND gate 130.
The control line inputs 96 and 97 to the OR and AND gates have -a similar function as above, however, there is an extra input control line 95 (from Fig. 2) to the two AND gates. This allows ~ `
that the outputs on terminals 183 and 189 be allowed only when the M4' divisor control (BC is high) is acting on the programmable divisor llOd and also one of the seventh's chord switches has been closed last. Any time the BC control goes low then the ~;~
programmable divisor llOd reverts to the M4 " control input, and ` -output terminal 131 reverts from NAND gate 128 to NAND gate 190, thus, changing what is normally programmed as the bass root frequency from programmable divisor I (lOOa) to the bass second frequency derived from the M4 " controlled programmable divisor IV (lOOd). This is used for the auto-bass (bass riff) on the chord button or pedal keyboard system.
Therefore, a single frequency input line 112, when deli.vered to four programmable divider circuits lOOa, lOOb, lOOc and lOOd can produce a multitude of different frequency ;
output signals at the various terminals located on the logic circuit of Fig. 4. The input line 112 is also connected to a divide-by-ten circuit 40 which produces the 50 RHz scanning pulses as shown in Fig. 1. This circuit may be a divide-by-thirty when the input clock is 1.5 MHz.
In this case all four programmable divisors are programmed by any one individual key switch of up to twenty-eight ~ V4~
~or more with more inputs and larger counter systems) key switches. If it is desirable to play up to four key switches simultaneously then this can be done with a separate decoder/ .
latch 68 and read-only memory 67 for each of the four (or more~
programmable divisors. Signals developed by gates 86, 87, 88 and 92 must be duplicated for each of the ~our latch output control lines 68a. Also these four latches would have to have four signal trans~er lines 48. This can be obtained by using a four-bit shift register for block 56 in Fig. 1 along with four AND gates 44. The line 58 input to each AND gate will be separate lines, one from each of the shift register outputs. If the count 32 reset signal puts a 1 in the first shift register and O's in the others (and remove AND gate 55 and connect line 54 as the CL input to 56), the first key switch in each scan will control programmable divisor I from shift register bit 1 through gate 44A, the second ;key switch closure in each scan will control programmable divisor I from shift register bit 1 through gate 44A, the second key switch closure in each scan will control program divisor II through shift register bit 2 and gate 44B, etc., for up to four key switches at a time. This can, there-fore, be used for a low cost single chip organ keyboard for up to 25, 37 or 44 keys by expanding on the key switch counter de-coder and matrix system and more key switches simultaneously by adding more latches and read-only-memories. -, - 25 -~.
- . . . ,. : : ,.,. : .... . .
.. : : . .. ; , . . . .. . .. . .
. . . .. .. . -. . - . ... .
.. . : . . . - . . . . ..... .. . ... . .. .... . .. . ....... .
~3413Z~; `
The entire circuitry illustrated on the drawings is formed on a large scale integrated circuit. The specific .~
embodiment illustrated herein is obtainable from The Wurlitzer ~ :
Company under part No. 141099. Other large scale integrated ;~
circuit chips which can be used in accordance with this invention are obtainable under part Nos. 142168 and 142169.
While a single specific embodiment of the invention , .. ~ . " .
is disclosed herein, it will be understood that a multitude of variations and modifications may be effected without :
departing from the spirit and scope thereof as set forth in the specification and claims disclosed herein.
''',' ~' ;`
`, - .
..;
::`
~ - 26 - ~
;'"' ,: . ,. ; . . ,: - : ~ - .: ..
.
..... ;, - . .. , ~ . : , , . . :,
Claims (10)
1. In an electronic musical instrument including audio output means for reproducing different tones, a tone signal generator coupled to said audio output means for elec-tronically generating signals corresponding to selected tones comprising: means for generating a plurality of tone signals, a plurality of key switches each selectively actuatable for the selection of predetermined ones of said tone signals to form a chord, means for scanning said key switches to determine a switch closure, and circuit means including a ROM interconnected with said generating means and said scanning means for causing said generating means to produce output electronic signals cor-responding to predetermined tones of a chord which is associated with the particular key switch being actuated, said circuit means continuously causing said generating means to produce said out-put electronic signals at a substantially constant level after said key switch is released.
2. In an electronic musical instrument as set forth in claim 1 and further including means operable upon the actuation of a subsequent key switch for causing said generating means to discontinue production of said first mentioned output electronic signals and to cause said generator means to produce second output electronic signals corresponding to predetermined tones of a chord which is associated with said subsequent key switch.
3. In an electronic musical instrument including audio output means for reproducing different tones, a tone signal generator coupled to said audio output means for electroni-cally generating signals corresponding to selected tones com-prising: means for generating a plurality of tone signals, a plurality of key switches, means for selectively actuating said key switches for the selection of predetermined ones of said tone signals, means for scanning said key switches to determine switch closures, circuit means including a ROM interconnected with said generating means and said scanning means for causing said generating means to produce output electronic signals cor-responding to predetermined tones associated with said particular key switches being actuated, said circuit means causing said generating means to produce said output electronic signals of substantially constant level until said key switches are released.
4. A tone signal generator as set forth in claim 1 or claim 3 wherein said scanning means comprises a matrix array formed by a plurality of lines having a multitude of cross-over points, each of which define a particular one of the plural-ity of key switches and means coupled to said plurality of lines to sequentially scan said multitude of cross-over points at a predetermined scanning rate to determine which ones of said plurality of key switches are closed and produce a time-frame output pulse in response thereto.
5. A tone signal generator as set forth in claim 1 wherein said circuit means further includes a plurality of gate circuits and means operated in sequence with said scanning means to provide gate signals to predetermined ones of said plurality of gate circuits.
6. A tone signal generator as set forth in claim 5 wherein said generating means comprise a plurality of groups of dividers, a plurality of programmable divisor circuits each having an input terminal coupled to a frequency source which is above audio frequencies, and each having an output terminal coupled to a selected one of said groups of dividers, said groups of dividers each connected to selected ones of said plurality of gate circuits to produce said output electronic signals therefrom when said gate circuits are energized in response to said time-frame output pulse, each of said plurality of programmable divisor circuits providing a different base frequency to be applied to its associated group of dividers, said programmable divisor cir-cuits including means to have their divisor number altered, so that the base frequency therefrom can be changed as desired.
7. In the electronic musical instrument as set forth in claim 6 wherein said circuit means, said scanning means, said programmable divisor circuits, said plurality of dividers, and said plurality of gate circuits are formed on single large scale integrated circuit chip.
8. In the electronic musical instrument as set forth in claim 7, further including second circuit means also formed on said large scale integrated circuit chip and coupled to said scanning means to produce a pulse signal output indicative of the actuation of a key of said plurality of keys, said pulse output coupled to percussion circuitry associated with the electronic musical instrument.
9. In the electronic musical instrument as set forth in claim 7, wherein each one of the dividers associated with a selected group of dividers provides an output which is a sub-harmonic of the output frequency of its associated divisor and a harmonic of the output of each other one of the dividers in that group.
10. In the electronic musical instrument as set forth in claim 9, wherein said means for altering the divisor numbers includes a control input circuit coupled to each of said programmable divisors and said ROM includes a plurality of outputs, each of the outputs from said ROM being applied to selected ones of said control input circuits and wherein each of said programmable divisors is operatively energized in response only to the output of said ROM.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA311,784A CA1057983A (en) | 1974-06-03 | 1978-09-21 | Electronic musical instrument using integrated circuit components |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US47544974A | 1974-06-03 | 1974-06-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1041325A true CA1041325A (en) | 1978-10-31 |
Family
ID=23887606
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA225,605A Expired CA1041325A (en) | 1974-06-03 | 1975-04-28 | Electronic musical instrument using integrated circuit components |
Country Status (5)
Country | Link |
---|---|
JP (2) | JPS516012A (en) |
CA (1) | CA1041325A (en) |
DE (1) | DE2523422A1 (en) |
GB (3) | GB1515182A (en) |
IT (1) | IT1035817B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4228403A (en) * | 1977-06-17 | 1980-10-14 | Nippon Gakki Seizo Kabushiki Kaisha | Submultiple-related-frequency wave generator |
JPS5420712A (en) * | 1977-07-15 | 1979-02-16 | Seiko Epson Corp | Electronic sounding apparatus |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3610806A (en) * | 1969-10-30 | 1971-10-05 | North American Rockwell | Adaptive sustain system for digital electronic organ |
-
1975
- 1975-04-28 CA CA225,605A patent/CA1041325A/en not_active Expired
- 1975-05-07 GB GB4490177A patent/GB1515182A/en not_active Expired
- 1975-05-07 GB GB4490277A patent/GB1515183A/en not_active Expired
- 1975-05-07 GB GB1908175A patent/GB1515181A/en not_active Expired
- 1975-05-21 IT IT4971375A patent/IT1035817B/en active
- 1975-05-27 DE DE19752523422 patent/DE2523422A1/en not_active Withdrawn
- 1975-06-03 JP JP50066134A patent/JPS516012A/ja active Pending
-
1979
- 1979-10-16 JP JP14225979U patent/JPS5565699U/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE2523422A1 (en) | 1975-12-11 |
JPS5565699U (en) | 1980-05-06 |
IT1035817B (en) | 1979-10-20 |
JPS516012A (en) | 1976-01-19 |
GB1515181A (en) | 1978-06-21 |
GB1515182A (en) | 1978-06-21 |
GB1515183A (en) | 1978-06-21 |
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