CA1031250A - Method of etching silicon oxide to produce a tapered edge thereon - Google Patents

Method of etching silicon oxide to produce a tapered edge thereon

Info

Publication number
CA1031250A
CA1031250A CA207,038A CA207038A CA1031250A CA 1031250 A CA1031250 A CA 1031250A CA 207038 A CA207038 A CA 207038A CA 1031250 A CA1031250 A CA 1031250A
Authority
CA
Canada
Prior art keywords
produce
silicon oxide
tapered edge
etching silicon
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA207,038A
Other languages
English (en)
French (fr)
Other versions
CA207038S (en
Inventor
Edward J. Ham
Ralph R. Soden
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Application granted granted Critical
Publication of CA1031250A publication Critical patent/CA1031250A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H01L23/4855Overhang structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/978Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CA207,038A 1973-08-20 1974-08-14 Method of etching silicon oxide to produce a tapered edge thereon Expired CA1031250A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00389718A US3839111A (en) 1973-08-20 1973-08-20 Method of etching silicon oxide to produce a tapered edge thereon

Publications (1)

Publication Number Publication Date
CA1031250A true CA1031250A (en) 1978-05-16

Family

ID=23539436

Family Applications (1)

Application Number Title Priority Date Filing Date
CA207,038A Expired CA1031250A (en) 1973-08-20 1974-08-14 Method of etching silicon oxide to produce a tapered edge thereon

Country Status (13)

Country Link
US (1) US3839111A (it)
JP (1) JPS5633858B2 (it)
BE (1) BE818991A (it)
BR (1) BR7406683D0 (it)
CA (1) CA1031250A (it)
DE (1) DE2439300C2 (it)
FR (1) FR2241876B1 (it)
GB (1) GB1445659A (it)
IN (1) IN139623B (it)
IT (1) IT1022509B (it)
NL (1) NL7410810A (it)
SE (1) SE389427B (it)
YU (1) YU40106B (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2359511C2 (de) * 1973-11-29 1987-03-05 Siemens AG, 1000 Berlin und 8000 München Verfahren zum lokalisierten Ätzen von Gräben in Siliciumkristallen
DE2432719B2 (de) * 1974-07-08 1977-06-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum erzeugen von feinen strukturen aus aufdampfbaren materialien auf einer unterlage und anwendung des verfahrens
NL7607298A (nl) * 1976-07-02 1978-01-04 Philips Nv Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze.
US4052253A (en) * 1976-09-27 1977-10-04 Motorola, Inc. Semiconductor-oxide etchant
DE2658124C3 (de) * 1976-12-22 1982-05-06 Dynamit Nobel Ag, 5210 Troisdorf Verfahren zur Herstellung von Elektroschmelzkorund
NL7701559A (nl) * 1977-02-15 1978-08-17 Philips Nv Het maken van schuine hellingen aan metaal- patronen, alsmede substraat voor een geinte- greerde schakeling voorzien van een dergelijk patroon.
JPS55163860A (en) * 1979-06-06 1980-12-20 Toshiba Corp Manufacture of semiconductor device
US4351698A (en) * 1981-10-16 1982-09-28 Memorex Corporation Variable sloped etching of thin film heads
JPS5898934A (ja) * 1981-12-08 1983-06-13 Matsushita Electronics Corp 半導体装置の製造方法
JPS58216445A (ja) * 1982-06-10 1983-12-16 Nec Corp 半導体装置およびその製造方法
US4698132A (en) * 1986-09-30 1987-10-06 Rca Corporation Method of forming tapered contact openings
JP2852355B2 (ja) * 1989-06-26 1999-02-03 ステラケミファ株式会社 微細加工表面処理剤
US5928969A (en) * 1996-01-22 1999-07-27 Micron Technology, Inc. Method for controlled selective polysilicon etching
WO1997036209A1 (en) * 1996-03-22 1997-10-02 Merck Patent Gmbh Solutions and processes for removal of sidewall residue after dry-etching________________________________________________________
US5838055A (en) * 1997-05-29 1998-11-17 International Business Machines Corporation Trench sidewall patterned by vapor phase etching
US5876879A (en) * 1997-05-29 1999-03-02 International Business Machines Corporation Oxide layer patterned by vapor phase etching
US6074951A (en) * 1997-05-29 2000-06-13 International Business Machines Corporation Vapor phase etching of oxide masked by resist or masking material
US5930644A (en) * 1997-07-23 1999-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a shallow trench isolation using oxide slope etching
US6762132B1 (en) * 2000-08-31 2004-07-13 Micron Technology, Inc. Compositions for dissolution of low-K dielectric films, and methods of use
US20050133479A1 (en) * 2003-12-19 2005-06-23 Youngner Dan W. Equipment and process for creating a custom sloped etch in a substrate
JP2007234754A (ja) * 2006-02-28 2007-09-13 Fujitsu Ltd レジストパターン形成方法及びレジストパターン形成装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1092740A (en) * 1966-07-15 1967-11-29 Standard Telephones Cables Ltd A method of masking the surface of a substrate
US3515607A (en) * 1967-06-21 1970-06-02 Western Electric Co Method of removing polymerised resist material from a substrate
US3642528A (en) * 1968-06-05 1972-02-15 Matsushita Electronics Corp Semiconductor device and method of making same
US3772102A (en) * 1969-10-27 1973-11-13 Gen Electric Method of transferring a desired pattern in silicon to a substrate layer
US3627598A (en) * 1970-02-05 1971-12-14 Fairchild Camera Instr Co Nitride passivation of mesa transistors by phosphovapox lifting
US3700508A (en) * 1970-06-25 1972-10-24 Gen Instrument Corp Fabrication of integrated microcircuit devices

Also Published As

Publication number Publication date
NL7410810A (nl) 1975-02-24
SE389427B (sv) 1976-11-01
BE818991A (fr) 1974-12-16
JPS5073574A (it) 1975-06-17
BR7406683D0 (pt) 1975-06-03
AU7229374A (en) 1976-02-19
YU40106B (en) 1985-08-31
JPS5633858B2 (it) 1981-08-06
FR2241876A1 (it) 1975-03-21
DE2439300A1 (de) 1975-03-06
SE7409819L (it) 1975-02-21
US3839111A (en) 1974-10-01
DE2439300C2 (de) 1982-06-24
GB1445659A (en) 1976-08-11
IN139623B (it) 1976-07-10
FR2241876B1 (it) 1978-01-27
YU227474A (en) 1982-05-31
IT1022509B (it) 1978-04-20

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