CA1031250A - Method of etching silicon oxide to produce a tapered edge thereon - Google Patents
Method of etching silicon oxide to produce a tapered edge thereonInfo
- Publication number
- CA1031250A CA1031250A CA207,038A CA207038A CA1031250A CA 1031250 A CA1031250 A CA 1031250A CA 207038 A CA207038 A CA 207038A CA 1031250 A CA1031250 A CA 1031250A
- Authority
- CA
- Canada
- Prior art keywords
- produce
- silicon oxide
- tapered edge
- etching silicon
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title 1
- 238000005530 etching Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 229910052814 silicon oxide Inorganic materials 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
- H01L23/4855—Overhang structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Weting (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US00389718A US3839111A (en) | 1973-08-20 | 1973-08-20 | Method of etching silicon oxide to produce a tapered edge thereon |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1031250A true CA1031250A (en) | 1978-05-16 |
Family
ID=23539436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA207,038A Expired CA1031250A (en) | 1973-08-20 | 1974-08-14 | Method of etching silicon oxide to produce a tapered edge thereon |
Country Status (13)
Country | Link |
---|---|
US (1) | US3839111A (it) |
JP (1) | JPS5633858B2 (it) |
BE (1) | BE818991A (it) |
BR (1) | BR7406683D0 (it) |
CA (1) | CA1031250A (it) |
DE (1) | DE2439300C2 (it) |
FR (1) | FR2241876B1 (it) |
GB (1) | GB1445659A (it) |
IN (1) | IN139623B (it) |
IT (1) | IT1022509B (it) |
NL (1) | NL7410810A (it) |
SE (1) | SE389427B (it) |
YU (1) | YU40106B (it) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2359511C2 (de) * | 1973-11-29 | 1987-03-05 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum lokalisierten Ätzen von Gräben in Siliciumkristallen |
DE2432719B2 (de) * | 1974-07-08 | 1977-06-02 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum erzeugen von feinen strukturen aus aufdampfbaren materialien auf einer unterlage und anwendung des verfahrens |
NL7607298A (nl) * | 1976-07-02 | 1978-01-04 | Philips Nv | Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze. |
US4052253A (en) * | 1976-09-27 | 1977-10-04 | Motorola, Inc. | Semiconductor-oxide etchant |
DE2658124C3 (de) * | 1976-12-22 | 1982-05-06 | Dynamit Nobel Ag, 5210 Troisdorf | Verfahren zur Herstellung von Elektroschmelzkorund |
NL7701559A (nl) * | 1977-02-15 | 1978-08-17 | Philips Nv | Het maken van schuine hellingen aan metaal- patronen, alsmede substraat voor een geinte- greerde schakeling voorzien van een dergelijk patroon. |
JPS55163860A (en) * | 1979-06-06 | 1980-12-20 | Toshiba Corp | Manufacture of semiconductor device |
US4351698A (en) * | 1981-10-16 | 1982-09-28 | Memorex Corporation | Variable sloped etching of thin film heads |
JPS5898934A (ja) * | 1981-12-08 | 1983-06-13 | Matsushita Electronics Corp | 半導体装置の製造方法 |
JPS58216445A (ja) * | 1982-06-10 | 1983-12-16 | Nec Corp | 半導体装置およびその製造方法 |
US4698132A (en) * | 1986-09-30 | 1987-10-06 | Rca Corporation | Method of forming tapered contact openings |
JP2852355B2 (ja) * | 1989-06-26 | 1999-02-03 | ステラケミファ株式会社 | 微細加工表面処理剤 |
US5928969A (en) * | 1996-01-22 | 1999-07-27 | Micron Technology, Inc. | Method for controlled selective polysilicon etching |
WO1997036209A1 (en) * | 1996-03-22 | 1997-10-02 | Merck Patent Gmbh | Solutions and processes for removal of sidewall residue after dry-etching________________________________________________________ |
US5838055A (en) * | 1997-05-29 | 1998-11-17 | International Business Machines Corporation | Trench sidewall patterned by vapor phase etching |
US5876879A (en) * | 1997-05-29 | 1999-03-02 | International Business Machines Corporation | Oxide layer patterned by vapor phase etching |
US6074951A (en) * | 1997-05-29 | 2000-06-13 | International Business Machines Corporation | Vapor phase etching of oxide masked by resist or masking material |
US5930644A (en) * | 1997-07-23 | 1999-07-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a shallow trench isolation using oxide slope etching |
US6762132B1 (en) * | 2000-08-31 | 2004-07-13 | Micron Technology, Inc. | Compositions for dissolution of low-K dielectric films, and methods of use |
US20050133479A1 (en) * | 2003-12-19 | 2005-06-23 | Youngner Dan W. | Equipment and process for creating a custom sloped etch in a substrate |
JP2007234754A (ja) * | 2006-02-28 | 2007-09-13 | Fujitsu Ltd | レジストパターン形成方法及びレジストパターン形成装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1092740A (en) * | 1966-07-15 | 1967-11-29 | Standard Telephones Cables Ltd | A method of masking the surface of a substrate |
US3515607A (en) * | 1967-06-21 | 1970-06-02 | Western Electric Co | Method of removing polymerised resist material from a substrate |
US3642528A (en) * | 1968-06-05 | 1972-02-15 | Matsushita Electronics Corp | Semiconductor device and method of making same |
US3772102A (en) * | 1969-10-27 | 1973-11-13 | Gen Electric | Method of transferring a desired pattern in silicon to a substrate layer |
US3627598A (en) * | 1970-02-05 | 1971-12-14 | Fairchild Camera Instr Co | Nitride passivation of mesa transistors by phosphovapox lifting |
US3700508A (en) * | 1970-06-25 | 1972-10-24 | Gen Instrument Corp | Fabrication of integrated microcircuit devices |
-
1973
- 1973-08-20 US US00389718A patent/US3839111A/en not_active Expired - Lifetime
-
1974
- 1974-06-26 IN IN1422/CAL/74A patent/IN139623B/en unknown
- 1974-07-30 SE SE7409819A patent/SE389427B/xx not_active IP Right Cessation
- 1974-07-31 IT IT25798/74A patent/IT1022509B/it active
- 1974-08-08 FR FR7427583A patent/FR2241876B1/fr not_active Expired
- 1974-08-13 NL NL7410810A patent/NL7410810A/xx not_active Application Discontinuation
- 1974-08-14 CA CA207,038A patent/CA1031250A/en not_active Expired
- 1974-08-14 BR BR6683/74A patent/BR7406683D0/pt unknown
- 1974-08-15 GB GB3597674A patent/GB1445659A/en not_active Expired
- 1974-08-16 DE DE2439300A patent/DE2439300C2/de not_active Expired
- 1974-08-19 YU YU227474A patent/YU40106B/xx unknown
- 1974-08-19 JP JP9546874A patent/JPS5633858B2/ja not_active Expired
- 1974-08-19 BE BE147738A patent/BE818991A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
NL7410810A (nl) | 1975-02-24 |
SE389427B (sv) | 1976-11-01 |
BE818991A (fr) | 1974-12-16 |
JPS5073574A (it) | 1975-06-17 |
BR7406683D0 (pt) | 1975-06-03 |
AU7229374A (en) | 1976-02-19 |
YU40106B (en) | 1985-08-31 |
JPS5633858B2 (it) | 1981-08-06 |
FR2241876A1 (it) | 1975-03-21 |
DE2439300A1 (de) | 1975-03-06 |
SE7409819L (it) | 1975-02-21 |
US3839111A (en) | 1974-10-01 |
DE2439300C2 (de) | 1982-06-24 |
GB1445659A (en) | 1976-08-11 |
IN139623B (it) | 1976-07-10 |
FR2241876B1 (it) | 1978-01-27 |
YU227474A (en) | 1982-05-31 |
IT1022509B (it) | 1978-04-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1031250A (en) | Method of etching silicon oxide to produce a tapered edge thereon | |
AU8594475A (en) | Method of etching a semiconductor device | |
AU485283B2 (en) | Method of making a razorblade | |
CA1028545A (en) | Method of forming a hydrophobic surface | |
CA1023059A (en) | Method of doping a semiconductor body | |
CA1001535A (en) | Process for etching silicon wafers | |
CA957250A (en) | Method of producing semiconducting monocrystalline silicon and spinel substrates | |
GB1540450A (en) | Self-aligning double polycrystalline silicon etching process | |
CA1035258A (en) | Oxide etchant | |
CA1026939A (en) | Method of making a silicon carbide article | |
AU1851576A (en) | Mechanical etching ofthe edges of semiconductor plates | |
CA959388A (en) | Silicon nitride-silicon oxide etchant | |
CA1009765A (en) | Method of manufacturing multi-function lsi wafers | |
AU485868B2 (en) | A method of etching silicon oxide to produce a tapered edge thereon | |
CA1007459A (en) | Method of concentrating gallium | |
CA988817A (en) | Etching of group iii-v semiconductors | |
CA1032397A (en) | Method of manufacturing a device | |
AU472151B2 (en) | A method of grinding | |
CA906681A (en) | Method of oxidizing a silicon wafer | |
CA980918A (en) | Method of forming a nickel electrode on a silicon substrate | |
CA1036283A (en) | Method of hydrolyzing polyacrylamide | |
CA1017430A (en) | Method of positioning a substrate with respect to a reference axis | |
CA935364A (en) | Method of etching a polyimide surface | |
AU7460174A (en) | Method of making a semiconductor device | |
CA903650A (en) | Preferential etching of silicon |