BRPI0820983A2 - aperfeiçoando estabilidade de leitura de memória usando precarga de seção de linha de bit. - Google Patents
aperfeiçoando estabilidade de leitura de memória usando precarga de seção de linha de bit.Info
- Publication number
- BRPI0820983A2 BRPI0820983A2 BRPI0820983A BRPI0820983A BRPI0820983A2 BR PI0820983 A2 BRPI0820983 A2 BR PI0820983A2 BR PI0820983 A BRPI0820983 A BR PI0820983A BR PI0820983 A BRPI0820983 A BR PI0820983A BR PI0820983 A2 BRPI0820983 A2 BR PI0820983A2
- Authority
- BR
- Brazil
- Prior art keywords
- bit line
- line section
- memory read
- read stability
- optimizing memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US1403807P | 2007-12-15 | 2007-12-15 | |
| US61/014,038 | 2007-12-15 | ||
| US12/334,817 | 2008-12-15 | ||
| US12/334,817 US8223567B2 (en) | 2007-12-15 | 2008-12-15 | Memory read stability using selective precharge |
| PCT/US2008/086829 WO2009079455A1 (en) | 2007-12-15 | 2008-12-15 | Improving memory read stability using selective precharge of bit line sections |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| BRPI0820983A2 true BRPI0820983A2 (pt) | 2015-10-13 |
| BRPI0820983A8 BRPI0820983A8 (pt) | 2019-02-05 |
| BRPI0820983B1 BRPI0820983B1 (pt) | 2019-06-25 |
| BRPI0820983B8 BRPI0820983B8 (pt) | 2021-08-10 |
Family
ID=40456819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BRPI0820983A BRPI0820983B8 (pt) | 2007-12-15 | 2008-12-15 | aperfeiçoando estabilidade de leitura de memória usando pré-carga seletiva de seções de linha de bits |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US8223567B2 (pt) |
| EP (1) | EP2243140B1 (pt) |
| JP (2) | JP5855342B2 (pt) |
| KR (1) | KR101251360B1 (pt) |
| CN (1) | CN101919003A (pt) |
| BR (1) | BRPI0820983B8 (pt) |
| CA (1) | CA2709400C (pt) |
| MX (1) | MX2010006666A (pt) |
| RU (1) | RU2444073C1 (pt) |
| WO (1) | WO2009079455A1 (pt) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2243140B1 (en) * | 2007-12-15 | 2018-06-06 | QUALCOMM Incorporated | Improving memory read stability using selective precharge of bit line sections |
| US7881137B2 (en) * | 2008-10-23 | 2011-02-01 | Qualcomm Incorporated | Read assist for memory circuits with different precharge voltage levels for bit line pair |
| US8208290B2 (en) * | 2009-08-26 | 2012-06-26 | Qualcomm Incorporated | System and method to manufacture magnetic random access memory |
| US8375173B2 (en) * | 2009-10-09 | 2013-02-12 | Qualcomm Incorporated | Accessing a multi-channel memory system having non-uniform page sizes |
| US8279659B2 (en) * | 2009-11-12 | 2012-10-02 | Qualcomm Incorporated | System and method of operating a memory device |
| US9385308B2 (en) | 2010-03-26 | 2016-07-05 | Qualcomm Incorporated | Perpendicular magnetic tunnel junction structure |
| US8339882B2 (en) * | 2010-07-12 | 2012-12-25 | Promos Technologies Pte. Ltd. | Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM |
| KR101781616B1 (ko) | 2010-07-16 | 2017-09-26 | 삼성전자주식회사 | 어시스트 회로를 포함하는 스태틱 랜덤 액세스 메모리 장치 |
| US9014749B2 (en) | 2010-08-12 | 2015-04-21 | Qualcomm Incorporated | System and method to initiate a housekeeping operation at a mobile device |
| US8638590B2 (en) | 2010-09-28 | 2014-01-28 | Qualcomm Incorporated | Resistance based memory having two-diode access device |
| JP5760829B2 (ja) * | 2011-08-09 | 2015-08-12 | 富士通セミコンダクター株式会社 | スタティックｒａｍ |
| US8582380B2 (en) * | 2011-12-21 | 2013-11-12 | Micron Technology, Inc. | Systems, circuits, and methods for charge sharing |
| BR112014015863B1 (pt) * | 2011-12-28 | 2021-04-20 | Intel Corporation | aparelho, sistema e método para fornecimento de energia em uma memória |
| US8861285B2 (en) | 2012-02-09 | 2014-10-14 | Micron Technology, Inc. | Apparatuses and methods for line charge sharing |
| US9224453B2 (en) * | 2013-03-13 | 2015-12-29 | Qualcomm Incorporated | Write-assisted memory with enhanced speed |
| US9123430B2 (en) * | 2013-06-14 | 2015-09-01 | Sandisk 3D Llc | Differential current sense amplifier and method for non-volatile memory |
| US9508405B2 (en) * | 2013-10-03 | 2016-11-29 | Stmicroelectronics International N.V. | Method and circuit to enable wide supply voltage difference in multi-supply memory |
| KR102173431B1 (ko) * | 2014-05-02 | 2020-11-03 | 삼성전자주식회사 | 동작 전류가 감소된 메모리 장치 |
| GB2525904B (en) | 2014-05-08 | 2018-05-09 | Surecore Ltd | Memory unit |
| US9672898B1 (en) | 2016-08-15 | 2017-06-06 | Samsung Electronics Co., Ltd. | Read column select negative boost driver circuit, system, and method |
| US10431278B2 (en) * | 2017-08-14 | 2019-10-01 | Qualcomm Incorporated | Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature |
| CN109817260B (zh) * | 2017-11-20 | 2021-02-09 | 中芯国际集成电路制造(上海)有限公司 | 位线预置电路、读操作电路、sram和方法 |
| JP7236574B2 (ja) * | 2018-02-27 | 2023-03-09 | ラピスセミコンダクタ株式会社 | 半導体装置及び半導体メモリのデータ読出方法 |
| CN108665931B (zh) * | 2018-05-21 | 2021-04-13 | 上海华力集成电路制造有限公司 | 位线预降压器 |
| US10657089B2 (en) | 2018-07-30 | 2020-05-19 | Texas Instruments Incorporated | Embedded universal serial bus 2 repeater |
| US11386036B2 (en) * | 2018-08-06 | 2022-07-12 | Texas Instruments Incorporated | Embedded universal serial bus 2 repeater |
| US11100964B1 (en) | 2020-02-10 | 2021-08-24 | Taiwan Semiconductor Manufacturing Company Limited | Multi-stage bit line pre-charge |
| US11532351B2 (en) * | 2020-05-08 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device with additional write bit lines |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2615011B2 (ja) * | 1986-06-13 | 1997-05-28 | 株式会社日立製作所 | 半導体記憶回路 |
| JPH0821236B2 (ja) * | 1987-01-26 | 1996-03-04 | 株式会社日立製作所 | 半導体記憶装置 |
| JPH03102698A (ja) * | 1989-09-14 | 1991-04-30 | Hitachi Ltd | 半導体記憶装置 |
| RU2060564C1 (ru) | 1993-06-24 | 1996-05-20 | Научно-исследовательский институт точных приборов | Усилитель считывания для запоминающего устройства |
| JPH10222985A (ja) * | 1998-03-09 | 1998-08-21 | Hitachi Ltd | 半導体記憶装置 |
| US6282137B1 (en) * | 1999-09-14 | 2001-08-28 | Agere Systems Guardian Corp. | SRAM method and apparatus |
| JP4087570B2 (ja) * | 2001-01-19 | 2008-05-21 | 富士通株式会社 | 半導体メモリおよびその制御方法 |
| CA2345845C (en) * | 2001-04-30 | 2012-03-27 | Mosaid Technologies Incorporated | Bitline precharge |
| JP4370100B2 (ja) * | 2003-01-10 | 2009-11-25 | パナソニック株式会社 | 半導体記憶装置 |
| US6934213B2 (en) * | 2003-06-11 | 2005-08-23 | Artisan Components, Inc. | Method and apparatus for reducing write power consumption in random access memories |
| US7009886B1 (en) * | 2004-07-19 | 2006-03-07 | Silicon Storage Technology, Inc. | Integrated circuit memory device with bit line pre-charging based upon partial address decoding |
| US7573775B2 (en) * | 2006-02-09 | 2009-08-11 | Fujitsu Limited | Setting threshold voltages of cells in a memory block to reduce leakage in the memory block |
| EP2243140B1 (en) * | 2007-12-15 | 2018-06-06 | QUALCOMM Incorporated | Improving memory read stability using selective precharge of bit line sections |
| US7881137B2 (en) * | 2008-10-23 | 2011-02-01 | Qualcomm Incorporated | Read assist for memory circuits with different precharge voltage levels for bit line pair |
-
2008
- 2008-12-15 EP EP08862363.2A patent/EP2243140B1/en active Active
- 2008-12-15 JP JP2010538225A patent/JP5855342B2/ja active Active
- 2008-12-15 US US12/334,817 patent/US8223567B2/en active Active
- 2008-12-15 KR KR1020107015737A patent/KR101251360B1/ko active IP Right Grant
- 2008-12-15 MX MX2010006666A patent/MX2010006666A/es active IP Right Grant
- 2008-12-15 CA CA2709400A patent/CA2709400C/en not_active Expired - Fee Related
- 2008-12-15 CN CN2008801250308A patent/CN101919003A/zh active Pending
- 2008-12-15 WO PCT/US2008/086829 patent/WO2009079455A1/en active Application Filing
- 2008-12-15 BR BRPI0820983A patent/BRPI0820983B8/pt active IP Right Grant
- 2008-12-15 RU RU2010129245/08A patent/RU2444073C1/ru active
-
2015
- 2015-06-02 JP JP2015112568A patent/JP2015207336A/ja not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| BRPI0820983B1 (pt) | 2019-06-25 |
| JP2015207336A (ja) | 2015-11-19 |
| WO2009079455A1 (en) | 2009-06-25 |
| KR101251360B1 (ko) | 2013-04-05 |
| CA2709400A1 (en) | 2009-06-25 |
| CA2709400C (en) | 2013-12-17 |
| US8223567B2 (en) | 2012-07-17 |
| BRPI0820983B8 (pt) | 2021-08-10 |
| US20090154274A1 (en) | 2009-06-18 |
| RU2444073C1 (ru) | 2012-02-27 |
| EP2243140B1 (en) | 2018-06-06 |
| RU2010129245A (ru) | 2012-01-20 |
| JP5855342B2 (ja) | 2016-02-09 |
| JP2011507139A (ja) | 2011-03-03 |
| BRPI0820983A8 (pt) | 2019-02-05 |
| CN101919003A (zh) | 2010-12-15 |
| MX2010006666A (es) | 2010-09-07 |
| KR20100092971A (ko) | 2010-08-23 |
| EP2243140A1 (en) | 2010-10-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| BRPI0820983A2 (pt) | aperfeiçoando estabilidade de leitura de memória usando precarga de seção de linha de bit. | |
| BRPI0813304A2 (pt) | Cabeça de furadeira. | |
| FR2909857B1 (fr) | Endovalve. | |
| BRPI0813235A2 (pt) | Combinação anti-helmíntica. | |
| NL2000627A1 (nl) | Cycloalkylaminoderivaten. | |
| DE602006002243D1 (de) | Externes Speichermedium | |
| BRPI0812887A2 (pt) | Furadeira ajustável. | |
| BRPI0919066A2 (pt) | aparelho de perfuração. | |
| BRPI0813398A2 (pt) | Gerenciamento de dados digitais utilizando pool de memória partilhada | |
| CL2008000919S1 (es) | Grifo. | |
| CL2008000920S1 (es) | Grifo. | |
| NL1033745A1 (nl) | Sleepboot. | |
| FI7604U1 (fi) | Tuntoelin | |
| FR2898372B1 (fr) | Regle a niveler reglable. | |
| DK2165040T3 (da) | Forbedret indgrebssystem til borebrønd | |
| NL1032940A1 (nl) | Boorinstallatie. | |
| FR2909834B1 (fr) | Andaineuse transversale. | |
| DE602005018067D1 (de) | Nichtflüchtige Speicheranordnung | |
| FR2935064B1 (fr) | Memoire a circuits de lecture/ecriture partage | |
| ITCE20060002A1 (it) | Patok. | |
| NO20053259D0 (no) | Minnemodul. | |
| FR2902621B3 (fr) | Bloc de rangement transformable en chaise | |
| FI20065346A0 (fi) | Välimuistijärjestely | |
| FI7227U1 (fi) | Varasto | |
| ITRM20070496A1 (it) | Macchina perforatrice. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B06T | Formal requirements before examination [chapter 6.20 patent gazette] | ||
| B06F | Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette] | ||
| B15K | Others concerning applications: alteration of classification |
Free format text: A CLASSIFICACAO ANTERIOR ERA: G11C 7/12 Ipc: G11C 7/12 (2000.01), G11C 11/419 (1990.01), G11C 7 |
|
| B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
| B16A | Patent or certificate of addition of invention granted [chapter 16.1 patent gazette] |
Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 25/06/2019, OBSERVADAS AS CONDICOES LEGAIS. (CO) 10 (DEZ) ANOS CONTADOS A PARTIR DE 25/06/2019, OBSERVADAS AS CONDICOES LEGAIS |
|
| B16C | Correction of notification of the grant [chapter 16.3 patent gazette] |
Free format text: REF. RPI 2529 DE 25/06/2019 QUANTO AO INVENTOR. |