BRPI0811497A2 - Arquitetura multiprocessador com encadeamento otimizado - Google Patents

Arquitetura multiprocessador com encadeamento otimizado

Info

Publication number
BRPI0811497A2
BRPI0811497A2 BRPI0811497-8A2A BRPI0811497A BRPI0811497A2 BR PI0811497 A2 BRPI0811497 A2 BR PI0811497A2 BR PI0811497 A BRPI0811497 A BR PI0811497A BR PI0811497 A2 BRPI0811497 A2 BR PI0811497A2
Authority
BR
Brazil
Prior art keywords
multiprocessor architecture
optimized chain
optimized
chain
multiprocessor
Prior art date
Application number
BRPI0811497-8A2A
Other languages
English (en)
Inventor
Russell H Fish Iii
Original Assignee
Russell H Fish Iii
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Russell H Fish Iii filed Critical Russell H Fish Iii
Publication of BRPI0811497A2 publication Critical patent/BRPI0811497A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846—On-chip cache and off-chip main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30163—Decoding the operand specifier, e.g. specifier format with implied specifier, e.g. top of stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Semiconductor Memories (AREA)
BRPI0811497-8A2A 2008-06-26 2008-06-27 Arquitetura multiprocessador com encadeamento otimizado BRPI0811497A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/147,332 US8984256B2 (en) 2006-02-03 2008-06-26 Thread optimized multiprocessor architecture
PCT/US2008/068566 WO2009157943A1 (en) 2008-06-26 2008-06-27 Thread optimized multiprocessor architecture

Publications (1)

Publication Number Publication Date
BRPI0811497A2 true BRPI0811497A2 (pt) 2014-11-18

Family

ID=41444820

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0811497-8A2A BRPI0811497A2 (pt) 2008-06-26 2008-06-27 Arquitetura multiprocessador com encadeamento otimizado

Country Status (10)

Country Link
US (2) US8984256B2 (pt)
EP (1) EP2288988A4 (pt)
JP (1) JP2010532905A (pt)
KR (1) KR101121606B1 (pt)
CN (2) CN101796484B (pt)
AU (1) AU2008355072C1 (pt)
BR (1) BRPI0811497A2 (pt)
CA (1) CA2684753A1 (pt)
RU (1) RU2450339C2 (pt)
WO (1) WO2009157943A1 (pt)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007092528A2 (en) 2006-02-03 2007-08-16 Fish Russell H Iii Thread optimized multiprocessor architecture
US8984256B2 (en) 2006-02-03 2015-03-17 Russell Fish Thread optimized multiprocessor architecture
US8209597B2 (en) * 2009-03-23 2012-06-26 Cognitive Electronics, Inc. System and method for achieving improved accuracy from efficient computer architectures
US8612687B2 (en) 2010-05-26 2013-12-17 International Business Machines Corporation Latency-tolerant 3D on-chip memory organization
US20120151232A1 (en) * 2010-12-12 2012-06-14 Fish Iii Russell Hamilton CPU in Memory Cache Architecture
US9823928B2 (en) * 2011-09-30 2017-11-21 Qualcomm Incorporated FIFO load instruction
KR101946455B1 (ko) * 2013-03-14 2019-02-11 삼성전자주식회사 시스템 온-칩 및 이의 동작 방법
RU2538920C2 (ru) * 2013-05-06 2015-01-10 Общество с ограниченной ответственностью "Аби ИнфоПоиск" Способ распределения задач сервером вычислительной системы, машиночитаемый носитель информации и система для реализации способа
US10521387B2 (en) * 2014-02-07 2019-12-31 Toshiba Memory Corporation NAND switch
US9870401B2 (en) * 2014-04-17 2018-01-16 Wisoncsin Alumni Research Foundation Database system with highly denormalized database structure
RU2579899C1 (ru) * 2014-09-30 2016-04-10 Общество с ограниченной ответственностью "Аби Девелопмент" Обработка документа с использованием нескольких потоков обработки
US20160147667A1 (en) * 2014-11-24 2016-05-26 Samsung Electronics Co., Ltd. Address translation in memory
US11567911B2 (en) * 2014-12-19 2023-01-31 Sergey Anatol'evich GORISHNIY System and method for management of functionally linked data
CN104598319B (zh) * 2015-01-13 2017-06-30 浪潮电子信息产业股份有限公司 一种实现应用性能优化的节点分配方法
RU2612569C2 (ru) * 2015-01-27 2017-03-09 Акционерное общество "Научно-исследовательский институт Авиационного оборудования" Способ автоматического управления избыточностью неоднородной вычислительной системы и устройство для его реализации
US9959208B2 (en) 2015-06-02 2018-05-01 Goodrich Corporation Parallel caching architecture and methods for block-based data processing
CN105808256B (zh) * 2016-03-08 2017-06-23 武汉斗鱼网络科技有限公司 一种构造合法堆栈返回值绕过函数调用检测的方法与***
RU2644535C2 (ru) * 2016-06-01 2018-02-12 Владимир Викторович Ермишин Архитектура параллельной вычислительной системы
US20180113840A1 (en) * 2016-10-25 2018-04-26 Wisconsin Alumni Research Foundation Matrix Processor with Localized Memory
DE102016224747A1 (de) * 2016-12-12 2018-06-14 Robert Bosch Gmbh Steuergerät
US10459771B2 (en) 2017-02-22 2019-10-29 Red Hat Israel, Ltd. Lightweight thread synchronization using shared memory state
EP4187539B1 (en) 2017-07-30 2024-06-05 NeuroBlade Ltd. A memory-based distributed processor architecture
RU2665224C1 (ru) * 2017-11-09 2018-08-28 Российская Федерация, от имени которой выступает Государственная корпорация по космической деятельности "РОСКОСМОС" Способ динамического контроля конфликтных ситуаций в сложных технических системах со средой облачных вычислений
US10613955B2 (en) * 2017-12-28 2020-04-07 Intel Corporation Platform debug and testing with secured hardware
US11030148B2 (en) * 2018-04-04 2021-06-08 Lawrence Livermore National Security, Llc Massively parallel hierarchical control system and method
CN111382091A (zh) * 2018-12-30 2020-07-07 德克萨斯仪器股份有限公司 用于低周期存储器访问和附加功能的宽边随机访问存储器
JP7107275B2 (ja) * 2019-04-25 2022-07-27 株式会社デンソー 並列化方法、半導体制御装置、及び車載制御装置
CN111209042B (zh) * 2020-01-06 2022-08-26 北京字节跳动网络技术有限公司 一种建立函数栈的方法、装置、介质和电子设备
KR20210156058A (ko) 2020-06-17 2021-12-24 삼성전자주식회사 인-메모리 프로세싱을 수행하는 메모리 디바이스
CN117555599B (zh) * 2024-01-10 2024-04-05 睿思芯科(成都)科技有限公司 加快关键数据访问速度的芯片设计方法、***及相关设备

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US553890A (en) * 1896-02-04 zeidlee
US3990054A (en) * 1974-11-05 1976-11-02 Honeywell Inc. Microprogram organization techniques
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4641238A (en) * 1984-12-10 1987-02-03 Itt Corporation Multiprocessor system employing dynamically programmable processing elements controlled by a master processor
US5440749A (en) 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
US5590345A (en) * 1990-11-13 1996-12-31 International Business Machines Corporation Advanced parallel array processor(APAP)
EP0715251B1 (en) * 1994-11-29 2000-07-26 International Business Machines Corporation One cycle processor for real time processing
US6524019B1 (en) * 1995-03-27 2003-02-25 Nec Corporation Inter-cluster data transfer system and data transfer method
JP3075184B2 (ja) * 1996-08-02 2000-08-07 日本電気株式会社 演算処理機能付主記憶システム及びその制御方法
JPH1111021A (ja) 1997-06-23 1999-01-19 Nippon Kayaku Co Ltd 感熱記録材料
JP3099290B2 (ja) * 1997-10-03 2000-10-16 啓介 進藤 マルチスレッドプログラムを使用する情報処理装置
US7373440B2 (en) * 1997-12-17 2008-05-13 Src Computers, Inc. Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
US6076152A (en) * 1997-12-17 2000-06-13 Src Computers, Inc. Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
NO308149B1 (no) * 1998-06-02 2000-07-31 Thin Film Electronics Asa Skalerbar, integrert databehandlingsinnretning
JP3156670B2 (ja) * 1998-06-26 2001-04-16 日本電気株式会社 演算処理機能付パケット型メモリシステムおよびその制御方法
FI117523B (fi) * 1998-10-07 2006-11-15 Nokia Corp Menetelmä tehonkulutuksen säätämiseksi
JP2000207248A (ja) * 1999-01-14 2000-07-28 Toshiba Corp 並列プログラムの挙動生成装置及び方法並びに並列プログラムの挙動生成用ソフトウェアを記録した記録媒体
US6606704B1 (en) 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
JP2002108691A (ja) * 2000-09-29 2002-04-12 Mitsubishi Electric Corp 半導体記憶装置および半導体記憶装置の制御方法
US7043416B1 (en) * 2001-07-27 2006-05-09 Lsi Logic Corporation System and method for state restoration in a diagnostic module for a high-speed microprocessor
US7064579B2 (en) * 2002-07-08 2006-06-20 Viciciv Technology Alterable application specific integrated circuit (ASIC)
US6803786B1 (en) * 2003-03-11 2004-10-12 Xilinx, Inc. Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks
US7558920B2 (en) * 2004-06-30 2009-07-07 Intel Corporation Apparatus and method for partitioning a shared cache of a chip multi-processor
US7676646B2 (en) 2005-03-02 2010-03-09 Cisco Technology, Inc. Packet processor with wide register set architecture
US20070028010A1 (en) 2005-08-01 2007-02-01 Texas Instruments, Inc. Peripheral device utilization monitoring
US7421566B2 (en) * 2005-08-12 2008-09-02 International Business Machines Corporation Implementing instruction set architectures with non-contiguous register file specifiers
WO2007092528A2 (en) * 2006-02-03 2007-08-16 Fish Russell H Iii Thread optimized multiprocessor architecture
US8984256B2 (en) * 2006-02-03 2015-03-17 Russell Fish Thread optimized multiprocessor architecture
TW200737188A (en) * 2006-03-27 2007-10-01 Memocom Corp Complex memory chip
EP1855181A2 (en) * 2006-05-10 2007-11-14 Marvell World Trade Ltd. System with high power and low power processors and thread transfer
US7870551B2 (en) * 2006-05-18 2011-01-11 International Business Machines Corporation Optimization of thread wake up for shared processor partitions
US7917788B2 (en) * 2006-11-01 2011-03-29 Freescale Semiconductor, Inc. SOC with low power and performance modes
US20120151232A1 (en) 2010-12-12 2012-06-14 Fish Iii Russell Hamilton CPU in Memory Cache Architecture

Also Published As

Publication number Publication date
US9934196B2 (en) 2018-04-03
US20080320277A1 (en) 2008-12-25
KR101121606B1 (ko) 2012-02-28
EP2288988A4 (en) 2012-06-27
CN104536723A (zh) 2015-04-22
RU2450339C2 (ru) 2012-05-10
KR20100032359A (ko) 2010-03-25
CN101796484A (zh) 2010-08-04
EP2288988A1 (en) 2011-03-02
AU2008355072C1 (en) 2012-11-29
JP2010532905A (ja) 2010-10-14
WO2009157943A1 (en) 2009-12-30
CN101796484B (zh) 2015-02-04
US8984256B2 (en) 2015-03-17
US20150234777A1 (en) 2015-08-20
CA2684753A1 (en) 2009-12-28
RU2009145519A (ru) 2011-06-20
AU2008355072B2 (en) 2012-05-31
AU2008355072A1 (en) 2010-01-14

Similar Documents

Publication Publication Date Title
BRPI0811497A2 (pt) Arquitetura multiprocessador com encadeamento otimizado
DE602009000328D1 (de) Parallelmechanismus
DE602007005217D1 (de) Fahrradkette
BRPI0914889A2 (pt) peptídeo glp-1 adicionado de cadeia oligossacarídica
BRPI0912271A2 (pt) co-autoria estruturada
BRPI0913515A2 (pt) fechamento com mecanismo limitador
BRPI0913513A2 (pt) fechamento com mecanismo limitador
BRPI0919561A2 (pt) tensionador
BRPI0919170A2 (pt) tensionador
BRPI0914098A2 (pt) biosensor
DE112009001379A5 (de) Laschenkette
DK2278899T3 (da) Bryggemekanisme
AT504336B8 (de) Kettenrad
DE102009004382A8 (de) Uhr mit Schlagwerk
DE602007012675D1 (de) Riemenspanner
FI8011U1 (fi) Heijastin
ES1068660Y (es) Llavero
ITLE20080006A1 (it) Vanga con fulcro
SE0800637L (sv) Snöskoter
ITTO20080015U1 (it) Illuminatore essenziale
AT504284A3 (de) Kurbelwelle
DE112009001031A5 (de) Lichtkreuz
CN301068590S (zh) 灯
CN301073663S (zh) 灯
CN301100168S (zh) 灯

Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE AS 6A E 7A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2329 DE 25-08-2015 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.