BR9907844A - Dispositivo e método de entrelaçamento e desentrelaçamento para sistema de comunicação - Google Patents

Dispositivo e método de entrelaçamento e desentrelaçamento para sistema de comunicação

Info

Publication number
BR9907844A
BR9907844A BR9907844A BR9907844A BR9907844A BR 9907844 A BR9907844 A BR 9907844A BR 9907844 A BR9907844 A BR 9907844A BR 9907844 A BR9907844 A BR 9907844A BR 9907844 A BR9907844 A BR 9907844A
Authority
BR
Brazil
Prior art keywords
input data
interlacing
communication system
size
deinterlacing
Prior art date
Application number
BR9907844A
Other languages
English (en)
Other versions
BR9907844B1 (pt
Inventor
Min-Goo Kim
Beong-Jo Kim
Young-Hwan Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of BR9907844A publication Critical patent/BR9907844A/pt
Publication of BR9907844B1 publication Critical patent/BR9907844B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

<B>DISPOSITIVO E MéTODO DE ENTRELAçAMENTO E DESENTRELAçAMENTO PARA SISTEMA DE COMUNICAçãO<D> Um método para entrelaçar dados de entrada tendo um tamanho diferente de um múltiplo de 2^ m^ (m>1) é revelado. O método compreende o armazenamento seq³êncial de dados de entrada em uma memória; acrescentar um valor de deslocamento ao tamanho dos dados de entrada para fornecer um endereço virtual com tamanho 2^ m^ em que (m>1), e gerar endereços aleatórios nas áreas de geração de endereço e ler os dados de entrada da memória utilizando os endereços aleatórios gerados das áreas de geração de endereço.
BR9907844A 1998-12-21 1999-12-21 dispositivo e mÉtodo de entrelaÇamento e desentrelaÇamento para sistema de comunicaÇço. BR9907844B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019980057959A KR100346170B1 (ko) 1998-12-21 1998-12-21 통신시스템의인터리빙/디인터리빙장치및방법
PCT/KR1999/000795 WO2000038333A1 (en) 1998-12-21 1999-12-21 Interleaving/deinterleaving device and method for communication system

Publications (2)

Publication Number Publication Date
BR9907844A true BR9907844A (pt) 2000-10-24
BR9907844B1 BR9907844B1 (pt) 2013-03-05

Family

ID=19565176

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9907844A BR9907844B1 (pt) 1998-12-21 1999-12-21 dispositivo e mÉtodo de entrelaÇamento e desentrelaÇamento para sistema de comunicaÇço.

Country Status (10)

Country Link
US (1) US6668343B1 (pt)
EP (1) EP1060564B1 (pt)
JP (1) JP3961770B2 (pt)
KR (1) KR100346170B1 (pt)
CN (2) CN1121095C (pt)
AU (1) AU738762B2 (pt)
BR (1) BR9907844B1 (pt)
CA (1) CA2319726C (pt)
RU (1) RU2217864C2 (pt)
WO (1) WO2000038333A1 (pt)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6871303B2 (en) 1998-12-04 2005-03-22 Qualcomm Incorporated Random-access multi-directional CDMA2000 turbo code interleaver
KR100468249B1 (ko) * 1999-10-07 2005-01-27 마츠시타 덴끼 산교 가부시키가이샤 인터리브 어드레스 생성 장치, 터보 부호화 장치, 터보 복호화 장치, 통신 단말 장치, 기지국 장치 및 인터리브 어드레스 생성 방법
US7302621B2 (en) * 2000-01-03 2007-11-27 Icoding Technology, Inc. High spread highly randomized generatable interleavers
US7187708B1 (en) * 2000-10-03 2007-03-06 Qualcomm Inc. Data buffer structure for physical and transport channels in a CDMA system
KR100846017B1 (ko) * 2000-10-30 2008-07-11 가부시키가이샤 히타치세이사쿠쇼 데이터 인터리브/디인터리브 효율을 향상시키기 위한 반도체 장치, 무선 통신 장치, 컴퓨터 프로그램 제품 및 방법
US7586993B2 (en) * 2001-12-06 2009-09-08 Texas Instruments Incorporated Interleaver memory selectably receiving PN or counter chain read address
KR100860660B1 (ko) * 2002-01-09 2008-09-26 삼성전자주식회사 통신시스템의 인터리빙 장치 및 방법
AU2003268814B2 (en) * 2002-02-06 2005-07-28 Samsung Electronics Co., Ltd. Interleaver and interleaving method in a communication system
JP3880964B2 (ja) * 2002-02-06 2007-02-14 サムスン エレクトロニクス カンパニー リミテッド 通信システムにおけるインターリーバー及びインターリービング方法
KR20030069431A (ko) * 2002-02-20 2003-08-27 삼성전자주식회사 통신 시스템에 적용되는 모뎀 에이직의 터보 부호화 장치및 그 부호화 방법
US7051261B1 (en) * 2002-10-29 2006-05-23 Lattice Semiconductor Corporation Turbo encoder with reduced processing delay
KR100925429B1 (ko) * 2002-12-28 2009-11-06 엘지전자 주식회사 터보 코더
DE10306302A1 (de) * 2003-02-14 2004-08-26 Infineon Technologies Ag Verfahren und Schaltung zur Adressgenerierung von Pseudo-Zufalls-Interleavern oder -Deinterleavern
US7702968B2 (en) 2004-02-27 2010-04-20 Qualcomm Incorporated Efficient multi-symbol deinterleaver
WO2005099099A1 (en) * 2004-03-05 2005-10-20 Thomson Licensing Address generation apparatus for turbo interleaver and deinterleaver in w-cdma systems
TWI264653B (en) * 2004-05-19 2006-10-21 Mediatek Inc Method and apparatus for convolutional interleaving/de-interleaving technique
US7543197B2 (en) 2004-12-22 2009-06-02 Qualcomm Incorporated Pruned bit-reversal interleaver
US7437650B2 (en) * 2005-04-12 2008-10-14 Agere Systems Inc. Pre-emptive interleaver address generator for turbo decoders
US8082479B2 (en) 2006-02-02 2011-12-20 Qualcomm Incorporated Methods and apparatus for generating permutations
US7925956B2 (en) * 2006-10-03 2011-04-12 Motorola Mobility, Inc. Method and apparatus for encoding and decoding data
US8356232B2 (en) * 2006-10-06 2013-01-15 Motorola Mobility Llc Method and apparatus for encoding and decoding data
US7949926B2 (en) * 2006-11-30 2011-05-24 Motorola Mobility, Inc. Method and apparatus for encoding and decoding data
KR101133907B1 (ko) 2007-07-06 2012-04-12 주식회사 코아로직 디인터리브 장치와 방법 및 인터리빙 인덱스 산출장치 및방법과 그 기록매체
WO2009014298A1 (en) * 2007-07-20 2009-01-29 Electronics And Telecommunications Research Institute Address generation apparatus and method of data interleaver/deinterleaver
US8200733B1 (en) 2008-04-15 2012-06-12 Freescale Semiconductor, Inc. Device having interleaving capabilities and a method for applying an interleaving function
KR101585936B1 (ko) * 2011-11-22 2016-01-18 한국전자통신연구원 가상 사설 망 관리 시스템 및 그 방법
US10203881B2 (en) * 2011-12-19 2019-02-12 Apple Inc. Optimized execution of interleaved write operations in solid state drives
EP3906625B1 (en) * 2019-02-15 2024-04-24 Apple Inc. Method for initialization seed generation for pn sequences in remote interference management

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4637021A (en) * 1983-09-28 1987-01-13 Pioneer Electronic Corporation Multiple pass error correction
FR2592258B1 (fr) * 1985-12-23 1991-05-03 Thomson Csf Procede et dispositif de transmission radioelectrique d'informations codees, resistant au brouillage
JPS62190932A (ja) 1986-02-18 1987-08-21 Nippon Telegr & Teleph Corp <Ntt> インタリ−ブ方式
JPS648717A (en) * 1987-07-01 1989-01-12 Nec Corp Pseudo noise series code generating circuit
US5111389A (en) * 1987-10-29 1992-05-05 International Business Machines Corporation Aperiodic mapping system using power-of-two stride access to interleaved devices
JPH0210574A (ja) * 1988-06-28 1990-01-16 Matsushita Electric Ind Co Ltd 復調回路
FR2639781B1 (fr) * 1988-11-25 1991-01-04 Alcatel Thomson Faisceaux Procede d'entrelacement pour dispositif de transmission numerique
JPH0430231A (ja) * 1990-05-25 1992-02-03 Hitachi Ltd 主記憶アドレッシング方式
US5293607A (en) * 1991-04-03 1994-03-08 Hewlett-Packard Company Flexible N-way memory interleaving
FR2675971B1 (fr) 1991-04-23 1993-08-06 France Telecom Procede de codage correcteur d'erreurs a au moins deux codages convolutifs systematiques en parallele, procede de decodage iteratif, module de decodage et decodeur correspondants.
KR0140382B1 (ko) * 1991-11-22 1998-07-01 강진구 Dat의 오류정정을 위한 어드레스 발생회로
KR0142315B1 (ko) * 1992-10-30 1998-07-01 윤종용 디지탈통신방법 및 그 장치
JPH06216882A (ja) 1993-01-19 1994-08-05 Matsushita Electric Ind Co Ltd 誤り訂正送信装置及び受信装置
US5446474A (en) 1994-01-19 1995-08-29 Lockheed Missiles & Space Company, Inc. Redeployable furlable rib reflector
JPH0974361A (ja) 1995-09-04 1997-03-18 Nec Eng Ltd 変復調装置
JPH09102748A (ja) 1995-10-04 1997-04-15 Matsushita Electric Ind Co Ltd インターリーブ回路
JPH09116444A (ja) 1995-10-23 1997-05-02 Sony Corp インターリーブ装置、符号化装置、デインターリーブ装置、復号装置、及び伝送方法
US5956757A (en) * 1996-03-22 1999-09-21 Adaptec, Inc. Method and apparatus for generating addresses
US5721745A (en) * 1996-04-19 1998-02-24 General Electric Company Parallel concatenated tail-biting convolutional code and decoder therefor
EP0931290A1 (en) * 1997-03-21 1999-07-28 International Business Machines Corporation Address mapping for system memory
JP3239084B2 (ja) * 1997-05-30 2001-12-17 株式会社次世代デジタルテレビジョン放送システム研究所 マルチキャリア伝送インターリーブ装置及び方法
KR100330980B1 (ko) * 1997-11-10 2002-04-01 다치카와 게이지 인터리빙 방법, 인터리빙 장치 및 인터리빙 패턴 생성 프로그램이 기록된 기록 매체
WO2000010257A1 (en) * 1998-08-17 2000-02-24 Hughes Electronics Corporation Turbo code interleaver with near optimal performance
US6657000B1 (en) * 1999-06-25 2003-12-02 Kraton Polymers U.S. Llc Hot melt pressure sensitive positioning adhesive (III)

Also Published As

Publication number Publication date
CN1496023A (zh) 2004-05-12
US6668343B1 (en) 2003-12-23
CN1291379A (zh) 2001-04-11
CA2319726C (en) 2005-05-10
KR20000041934A (ko) 2000-07-15
WO2000038333A1 (en) 2000-06-29
CA2319726A1 (en) 2000-06-29
AU1695600A (en) 2000-07-12
BR9907844B1 (pt) 2013-03-05
RU2217864C2 (ru) 2003-11-27
EP1060564A4 (en) 2006-06-28
JP2002533976A (ja) 2002-10-08
EP1060564B1 (en) 2017-10-18
AU738762B2 (en) 2001-09-27
EP1060564A1 (en) 2000-12-20
KR100346170B1 (ko) 2002-11-30
CN100345390C (zh) 2007-10-24
JP3961770B2 (ja) 2007-08-22
CN1121095C (zh) 2003-09-10

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Legal Events

Date Code Title Description
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 05/03/2013, OBSERVADAS AS CONDICOES LEGAIS.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

Free format text: REFERENTE A 22A ANUIDADE.

B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2649 DE 13-10-2021 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.