BR112018070176A2 - aparelho e sistema de conexão cruzada - Google Patents

aparelho e sistema de conexão cruzada

Info

Publication number
BR112018070176A2
BR112018070176A2 BR112018070176A BR112018070176A BR112018070176A2 BR 112018070176 A2 BR112018070176 A2 BR 112018070176A2 BR 112018070176 A BR112018070176 A BR 112018070176A BR 112018070176 A BR112018070176 A BR 112018070176A BR 112018070176 A2 BR112018070176 A2 BR 112018070176A2
Authority
BR
Brazil
Prior art keywords
cross
clock signal
transparent
clock
input port
Prior art date
Application number
BR112018070176A
Other languages
English (en)
Inventor
Buabbud George
Boura Jihad
Original Assignee
Ipg Photonics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ipg Photonics Corp filed Critical Ipg Photonics Corp
Publication of BR112018070176A2 publication Critical patent/BR112018070176A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1652—Optical Transport Network [OTN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/076—Distributing frame; Cross connect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Optical Communication System (AREA)
  • Optics & Photonics (AREA)

Abstract

a presente invenção refere-se a um aparelho ou sistema de conexão cruzada com relógio transparente, que conecta uma porta de origem ou entrada selecionada a uma porta de destino ou saída selecionada e sincronizada dados a partir da porta de saída selecionada usando um sinal de relógio sintetizado ajustado para combinar com um sinal de relógio recuperado a partir da porta de entrada selecionada. um sistema de relógio transparente pode gerar o sinal de relógio sintetizado com ajustes em resposta a uma taxa de partes por milhão (ppm) detectada para o sinal de relógio recuperado associado, proporcionado pela porta de entrada selecionada. o sistema de conexão cruzada com relógio transparente pode ser um sistema de conexão cruzada de 400g com uma resolução de 10g. o sistema de conexão cruzada com relógio transparente pode ser usado em aplicações de rede ótica de transporte (otn), por exemplo, para proporcionar um agregador e/ou um multiplexador de adição-queda (adm) ou para proporcionar um multiplexador ótico reconfigurável de adição-queda (roadm) atualizado para uma taxa de dados mais alta.
BR112018070176A 2016-04-01 2017-03-31 aparelho e sistema de conexão cruzada BR112018070176A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662317194P 2016-04-01 2016-04-01
PCT/US2017/025387 WO2017173277A1 (en) 2016-04-01 2017-03-31 Transparent clocking in a cross connect system

Publications (1)

Publication Number Publication Date
BR112018070176A2 true BR112018070176A2 (pt) 2019-01-29

Family

ID=59959911

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018070176A BR112018070176A2 (pt) 2016-04-01 2017-03-31 aparelho e sistema de conexão cruzada

Country Status (8)

Country Link
US (2) US10298348B2 (pt)
EP (1) EP3436887A4 (pt)
CN (1) CN109074120B (pt)
BR (1) BR112018070176A2 (pt)
CA (1) CA3019585A1 (pt)
RU (1) RU2743413C2 (pt)
SA (1) SA518400156B1 (pt)
WO (1) WO2017173277A1 (pt)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10298348B2 (en) * 2016-04-01 2019-05-21 Ipg Photonics Corporation Transparent clocking in a cross connect system

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Also Published As

Publication number Publication date
CA3019585A1 (en) 2017-10-05
SA518400156B1 (ar) 2023-12-05
RU2018136626A (ru) 2020-05-12
CN109074120A (zh) 2018-12-21
US20200076525A1 (en) 2020-03-05
RU2018136626A3 (pt) 2020-07-29
EP3436887A1 (en) 2019-02-06
RU2743413C2 (ru) 2021-02-18
US10298348B2 (en) 2019-05-21
EP3436887A4 (en) 2019-12-04
CN109074120B (zh) 2022-11-18
WO2017173277A1 (en) 2017-10-05
US10693579B2 (en) 2020-06-23
US20170288849A1 (en) 2017-10-05

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: AS CLASSIFICACOES ANTERIORES ERAM: G06F 1/12 , H04J 3/22 , H04L 7/00 , H04L 12/28

Ipc: H04J 3/06 (2006.01)

B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements