BR112015020828A2 - indutor de fator de alta qualidade implementado em empacotamento de nível de wafer (wlp) - Google Patents

indutor de fator de alta qualidade implementado em empacotamento de nível de wafer (wlp)

Info

Publication number
BR112015020828A2
BR112015020828A2 BR112015020828A BR112015020828A BR112015020828A2 BR 112015020828 A2 BR112015020828 A2 BR 112015020828A2 BR 112015020828 A BR112015020828 A BR 112015020828A BR 112015020828 A BR112015020828 A BR 112015020828A BR 112015020828 A2 BR112015020828 A2 BR 112015020828A2
Authority
BR
Brazil
Prior art keywords
layer
pcb
wlp
high quality
quality factor
Prior art date
Application number
BR112015020828A
Other languages
English (en)
Other versions
BR112015020828B1 (pt
Inventor
Hadjichristos Aristotele
Nejati Babak
D Lane Ryan
Chen Xiaoming
Zhang Xiaonan
K Song Young
Park Yunseo
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112015020828A2 publication Critical patent/BR112015020828A2/pt
Publication of BR112015020828B1 publication Critical patent/BR112015020828B1/pt

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

1/1 resumo "indutor de fator de alta qualidade implementado em empacotamento de nível de wafer (wlp)" algumas características de novidade pertencem a um primeiro exemplo que fornece um dispositivo semicondutor que inclui um painel de circuito impresso (pcb), esferas de solda e uma matriz. o pcb inclui uma primeira camada metálica. o conjunto de esferas de solda é acoplado ao pcb. a matriz é acoplada a uma segunda camada metálica e a uma terceira camada metálica. a primeira camada metálica do pcb, o conjunto de esferas de solda, as segunda e terceira camadas metálicas da matriz são configurados para operar como um indutor no dispositivo semicondutor. em algumas implementações, a matriz inclui adicionalmente uma camada de passivação. a camada de passivação é posicionada entre a segunda camada metálica e a terceira camada metálica. em algumas implementações, a segunda camada metálica é posicionada entre a camada de passivação e o conjunto de esferas de solda.
BR112015020828-2A 2013-03-01 2014-02-21 Dispositivo semicondutor e método de fornecimento de um indutor no mesmo BR112015020828B1 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361771717P 2013-03-01 2013-03-01
US61/771,717 2013-03-01
US13/787,219 US9035421B2 (en) 2013-03-01 2013-03-06 High quality factor inductor implemented in wafer level packaging (WLP)
US13/787,219 2013-03-06
PCT/US2014/017580 WO2014133883A1 (en) 2013-03-01 2014-02-21 High quality factor inductor implemented in wafer level packaging (wlp)

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BR112015020828A2 true BR112015020828A2 (pt) 2017-07-18
BR112015020828B1 BR112015020828B1 (pt) 2022-02-08

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US (1) US9035421B2 (pt)
EP (1) EP2962329B1 (pt)
JP (1) JP2016510172A (pt)
KR (1) KR101780047B1 (pt)
CN (1) CN105009282A (pt)
AR (1) AR095457A1 (pt)
BR (1) BR112015020828B1 (pt)
ES (1) ES2864881T3 (pt)
TW (1) TWI585938B (pt)
WO (1) WO2014133883A1 (pt)

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Publication number Publication date
AR095457A1 (es) 2015-10-21
TWI585938B (zh) 2017-06-01
ES2864881T3 (es) 2021-10-14
WO2014133883A1 (en) 2014-09-04
KR20150121200A (ko) 2015-10-28
EP2962329A1 (en) 2016-01-06
KR101780047B1 (ko) 2017-09-19
TW201440198A (zh) 2014-10-16
EP2962329B1 (en) 2021-03-31
US20140246753A1 (en) 2014-09-04
BR112015020828B1 (pt) 2022-02-08
US9035421B2 (en) 2015-05-19
JP2016510172A (ja) 2016-04-04
CN105009282A (zh) 2015-10-28

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B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
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