BR112014009920A2 - método para segmentar um cache, meio de armazenamento não transitório legível por computador e dispositivo - Google Patents

método para segmentar um cache, meio de armazenamento não transitório legível por computador e dispositivo

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Publication number
BR112014009920A2
BR112014009920A2 BR112014009920A BR112014009920A BR112014009920A2 BR 112014009920 A2 BR112014009920 A2 BR 112014009920A2 BR 112014009920 A BR112014009920 A BR 112014009920A BR 112014009920 A BR112014009920 A BR 112014009920A BR 112014009920 A2 BR112014009920 A2 BR 112014009920A2
Authority
BR
Brazil
Prior art keywords
segmenting
cache
computer
storage media
readable non
Prior art date
Application number
BR112014009920A
Other languages
English (en)
Other versions
BR112014009920B1 (pt
Inventor
W So Chi
Charles Iii Thomas Fred
A Gaspard Walter
Original Assignee
Hewlett Packard Development Co Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co Lp filed Critical Hewlett Packard Development Co Lp
Publication of BR112014009920A2 publication Critical patent/BR112014009920A2/pt
Publication of BR112014009920B1 publication Critical patent/BR112014009920B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/222—Non-volatile memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6042—Allocation of cache space to multiple users or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

resumo “método para segmentar um cache, meio de armazenamento não transitório legível por computador e dispositivo” as concretizações aqui se relacionam a segmentação e fixação de uma primeira memória não volátil para armazenar informações de cache. em uma concretização, a primeira memória não volátil é dividida em uma pluralidade de segmentos. então, um primeiro tipo de software de uma pluralidade de tipos de software é fixado a um primeiro segmento de uma pluralidade de segmentos. o primeiro segmento fixado armazena as informações de cache associadas ao primeiro tipo de software. 1/1
BR112014009920-0A 2011-10-26 2011-10-26 Método para segmentar um cache, meio de armazenamento não transitório legível por computador e dispositivo BR112014009920B1 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/057913 WO2013062542A1 (en) 2011-10-26 2011-10-26 Segmented caches

Publications (2)

Publication Number Publication Date
BR112014009920A2 true BR112014009920A2 (pt) 2017-04-25
BR112014009920B1 BR112014009920B1 (pt) 2021-06-15

Family

ID=48168213

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112014009920-0A BR112014009920B1 (pt) 2011-10-26 2011-10-26 Método para segmentar um cache, meio de armazenamento não transitório legível por computador e dispositivo

Country Status (9)

Country Link
US (1) US9697115B2 (pt)
EP (1) EP2771795B1 (pt)
JP (1) JP2014534520A (pt)
KR (1) KR101842321B1 (pt)
CN (1) CN103999062A (pt)
BR (1) BR112014009920B1 (pt)
IN (1) IN2014CN02958A (pt)
TW (2) TWI498811B (pt)
WO (1) WO2013062542A1 (pt)

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US10613982B1 (en) 2012-01-06 2020-04-07 Seagate Technology Llc File-aware caching driver
US9542324B1 (en) * 2012-04-05 2017-01-10 Seagate Technology Llc File associated pinning
US9268692B1 (en) * 2012-04-05 2016-02-23 Seagate Technology Llc User selectable caching
US10185501B2 (en) * 2015-09-25 2019-01-22 Intel Corporation Method and apparatus for pinning memory pages in a multi-level system memory
US11165825B2 (en) * 2017-02-16 2021-11-02 Emerald Cactus Ventures, Inc. System and method for creating encrypted virtual private network hotspot
US11122013B2 (en) * 2017-02-16 2021-09-14 Emerald Cactus Ventures, Inc. System and method for encrypting data interactions delineated by zones
US11165751B2 (en) * 2017-02-16 2021-11-02 Emerald Cactus Ventures, Inc. System and method for establishing simultaneous encrypted virtual private networks from a single computing device
US20180336131A1 (en) * 2017-05-22 2018-11-22 Dell Products L.P. Optimizing Memory/Caching Relative to Application Profile
TWI649652B (zh) * 2017-12-29 2019-02-01 國科美國研究實驗室 Fast and safe data storage device and method

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JPH06282488A (ja) 1993-03-25 1994-10-07 Mitsubishi Electric Corp キャッシュ記憶装置
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Also Published As

Publication number Publication date
BR112014009920B1 (pt) 2021-06-15
TWI498811B (zh) 2015-09-01
TWI574203B (zh) 2017-03-11
IN2014CN02958A (pt) 2015-07-03
WO2013062542A8 (en) 2014-07-03
TW201329858A (zh) 2013-07-16
EP2771795A4 (en) 2015-08-05
CN103999062A (zh) 2014-08-20
KR101842321B1 (ko) 2018-03-26
TW201546712A (zh) 2015-12-16
JP2014534520A (ja) 2014-12-18
EP2771795A1 (en) 2014-09-03
US20140297937A1 (en) 2014-10-02
KR20140091532A (ko) 2014-07-21
EP2771795B1 (en) 2016-06-01
WO2013062542A1 (en) 2013-05-02
US9697115B2 (en) 2017-07-04

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B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

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B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

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Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2746 DE 22-08-2023 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.