BR0207882A - Formação de modelo metálico - Google Patents

Formação de modelo metálico

Info

Publication number
BR0207882A
BR0207882A BR0207882-1A BR0207882A BR0207882A BR 0207882 A BR0207882 A BR 0207882A BR 0207882 A BR0207882 A BR 0207882A BR 0207882 A BR0207882 A BR 0207882A
Authority
BR
Brazil
Prior art keywords
varnish
layer
metal surface
base metal
ablated
Prior art date
Application number
BR0207882-1A
Other languages
English (en)
Inventor
Heirinch Meyer
Udo Grieser
Original Assignee
Atotech Deutschland Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atotech Deutschland Gmbh filed Critical Atotech Deutschland Gmbh
Publication of BR0207882A publication Critical patent/BR0207882A/pt

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G03F7/2014—Contact or film exposure of light sensitive plates such as lithographic plates or circuit boards, e.g. in a vacuum frame
    • G03F7/2016—Contact mask being integral part of the photosensitive element and subject to destructive removal during post-exposure processing
    • G03F7/202—Masking pattern being obtained by thermal means, e.g. laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1333—Deposition techniques, e.g. coating
    • H05K2203/135—Electrophoretic deposition of insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0076—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the composition of the mask
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Chemically Coating (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Paints Or Removers (AREA)

Abstract

"FORMAçãO DE MODELO METáLICO". Um método de produzir-se reprodutivamente condutores de circuito com estruturas de circuito muito finas e um verniz eletroforético a ser aplicado neste método são descritos, nos quais um substrato dielétrico compreendendo uma superfície de metal base é fornecido. Uma camada de verniz é aplicada à superfície do substrato eletrodepositando o verniz eletroforético, portanto a camada de verniz sofre ablação em pelo menos partes das regiões que não correspondem ao modelo metálico a ser formado por meio de radiação ultravioleta, a superfície do metal base sendo deixada descoberta, e finalmente a superfície do metal base descoberta é causticada.
BR0207882-1A 2001-03-07 2002-02-12 Formação de modelo metálico BR0207882A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10112023A DE10112023A1 (de) 2001-03-07 2001-03-07 Verfahren zum Bilden eines Metallmusters auf einen dielektrischen Substrat
PCT/EP2002/001464 WO2002071466A1 (en) 2001-03-07 2002-02-12 Metal pattern formation

Publications (1)

Publication Number Publication Date
BR0207882A true BR0207882A (pt) 2004-03-02

Family

ID=7677266

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0207882-1A BR0207882A (pt) 2001-03-07 2002-02-12 Formação de modelo metálico

Country Status (14)

Country Link
US (2) US6593249B2 (pt)
EP (1) EP1366511B1 (pt)
JP (1) JP2004530291A (pt)
KR (1) KR20040030528A (pt)
CN (1) CN1305120C (pt)
AT (1) ATE301872T1 (pt)
BR (1) BR0207882A (pt)
CA (1) CA2435755A1 (pt)
DE (2) DE10112023A1 (pt)
HK (1) HK1057129A1 (pt)
MX (1) MXPA03007648A (pt)
MY (1) MY141591A (pt)
TW (1) TW573446B (pt)
WO (1) WO2002071466A1 (pt)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19944908A1 (de) * 1999-09-10 2001-04-12 Atotech Deutschland Gmbh Verfahren zum Bilden eines Leitermusters auf dielektrischen Substraten
DE10112023A1 (de) * 2001-03-07 2002-10-02 Atotech Deutschland Gmbh Verfahren zum Bilden eines Metallmusters auf einen dielektrischen Substrat
KR100577406B1 (ko) * 2003-09-17 2006-05-10 박재상 Ｐｃｂ 방식을 이용한 히터 제조방법 및 히터
KR101255866B1 (ko) * 2004-11-30 2013-04-17 가부시끼가이샤 다이셀 지환식 에폭시(메트)아크릴레이트 및 그의 제조 방법, 및공중합체
US20060250744A1 (en) * 2005-05-05 2006-11-09 Mctigue Michael T Micro gap method and ESD protection device
CN102490526B (zh) * 2011-11-15 2013-09-25 东莞市泉硕五金加工有限公司 一种在工件表面镀膜和设置图案的方法
JP2015023251A (ja) * 2013-07-23 2015-02-02 ソニー株式会社 多層配線基板およびその製造方法、並びに半導体製品
US10438812B2 (en) * 2017-03-30 2019-10-08 Intel Corporation Anisotropic etching systems and methods using a photochemically enhanced etchant
FR3077302B1 (fr) * 2018-01-29 2019-12-27 Avipo Depot de pvd en fond de gravure
CN110634999A (zh) * 2018-06-21 2019-12-31 君泰创新（北京）科技有限公司 太阳能电池及其制作方法
CN112892619B (zh) * 2019-12-04 2022-07-15 香港城市大学深圳研究院 弧形边缘截面的pdms母模、微流控阀和芯片及其制备
CN110996553B (zh) * 2019-12-17 2021-06-04 中国电子科技集团公司第五十八研究所 一种适用于深腔型印制板的焊膏分配方法
DE102020201869A1 (de) 2020-02-14 2021-08-19 Robert Bosch Gesellschaft mit beschränkter Haftung Schaltungsträger mit einer keramischen Lotstopp-Barriere

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DE1811377A1 (de) * 1968-11-28 1970-06-18 Telefunken Patent Verfahren zur Herstellung gedruckter Leiterplatten
US3755119A (en) * 1971-04-29 1973-08-28 American Cyanamid Co Article electrocoated with adhesively bondable acrylic resin containing bis-urea
US4345969A (en) * 1981-03-23 1982-08-24 Motorola, Inc. Metal etch solution and method
DE3113855A1 (de) * 1981-04-06 1982-10-21 Fritz Wittig Herstellung gedruckter Schaltungen, 8000 München Verfahren zur herstellung von leiterplatten
JPS59227186A (ja) 1983-06-08 1984-12-20 株式会社ヤマトヤ商会 銅スル・ホ−ル基板の製造方法
US4592816A (en) * 1984-09-26 1986-06-03 Rohm And Haas Company Electrophoretic deposition process
US4708925A (en) * 1984-12-11 1987-11-24 Minnesota Mining And Manufacturing Company Photosolubilizable compositions containing novolac phenolic resin
JPH0644150B2 (ja) 1986-05-09 1994-06-08 関西ペイント株式会社 プリント配線フオトレジスト用電着塗料組成物
EP0662636A3 (en) 1986-10-23 1995-11-22 Ciba Geigy Ag Imaging processes.
US4871591A (en) 1987-01-27 1989-10-03 Kansai Paint Company, Limited Finish coating method
DE3732249A1 (de) * 1987-09-24 1989-04-13 Siemens Ag Verfahren zur herstellung von dreidimensionalen leiterplatten
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JPH0539444A (ja) * 1990-11-30 1993-02-19 Hitachi Chem Co Ltd ポジ型感光性アニオン電着塗料樹脂組成物、これを用いた電着塗装浴、電着塗装法及びプリント回路板の製造方法
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Also Published As

Publication number Publication date
ATE301872T1 (de) 2005-08-15
HK1057129A1 (en) 2004-03-12
CN1305120C (zh) 2007-03-14
TW573446B (en) 2004-01-21
CN1541409A (zh) 2004-10-27
DE60205464T2 (de) 2006-05-24
US20040069636A1 (en) 2004-04-15
US20030036288A1 (en) 2003-02-20
EP1366511B1 (en) 2005-08-10
DE60205464D1 (de) 2005-09-15
MXPA03007648A (es) 2003-12-04
KR20040030528A (ko) 2004-04-09
MY141591A (en) 2010-05-14
US6593249B2 (en) 2003-07-15
EP1366511A1 (en) 2003-12-03
DE10112023A1 (de) 2002-10-02
CA2435755A1 (en) 2002-09-12
WO2002071466A1 (en) 2002-09-12
JP2004530291A (ja) 2004-09-30

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Legal Events

Date Code Title Description
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements