BE844571A - Dispositif de reconfiguration de memoire - Google Patents
Dispositif de reconfiguration de memoireInfo
- Publication number
- BE844571A BE844571A BE2055208A BE2055208A BE844571A BE 844571 A BE844571 A BE 844571A BE 2055208 A BE2055208 A BE 2055208A BE 2055208 A BE2055208 A BE 2055208A BE 844571 A BE844571 A BE 844571A
- Authority
- BE
- Belgium
- Prior art keywords
- reconfiguration device
- memory reconfiguration
- memory
- reconfiguration
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7523418A FR2319953A1 (fr) | 1975-07-28 | 1975-07-28 | Dispositif de reconfiguration de memoire |
Publications (1)
Publication Number | Publication Date |
---|---|
BE844571A true BE844571A (fr) | 1977-01-28 |
Family
ID=9158412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BE2055208A BE844571A (fr) | 1975-07-28 | 1976-07-28 | Dispositif de reconfiguration de memoire |
Country Status (3)
Country | Link |
---|---|
BE (1) | BE844571A (fr) |
FR (1) | FR2319953A1 (fr) |
GB (1) | GB1536436A (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4130886A (en) * | 1976-12-27 | 1978-12-19 | Rca Corporation | Circuit for rearranging word bits |
DE2823457C2 (de) * | 1978-05-30 | 1982-12-30 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Schaltungsanordnung zur Fehlerüberwachung eines Speichers einer digitalen Rechenanlage |
US4321667A (en) * | 1979-10-31 | 1982-03-23 | International Business Machines Corp. | Add-on programs with code verification and control |
DE3032630C2 (de) * | 1980-08-29 | 1983-12-22 | Siemens AG, 1000 Berlin und 8000 München | Halbleiterspeicher aus Speicherbausteinen mit redundanten Speicherbereichen und Verfahren zu dessen Betrieb |
US4507730A (en) * | 1981-10-01 | 1985-03-26 | Honeywell Information Systems Inc. | Memory system with automatic memory configuration |
US4872166A (en) * | 1986-09-10 | 1989-10-03 | Nec Corporation | Information processing system capable of reducing invalid memory operations by detecting an error in a main memory |
GB8902365D0 (en) * | 1989-02-03 | 1989-03-22 | Int Computers Ltd | Data processing system |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3312947A (en) * | 1963-12-31 | 1967-04-04 | Bell Telephone Labor Inc | Plural memory system with internal memory transfer and duplicated information |
BE789991A (fr) * | 1971-10-12 | 1973-04-12 | Siemens Ag | Dispositif logique, en particulier decodeur a elements redondants |
FR2217769B1 (fr) * | 1973-02-09 | 1984-03-09 | Cii Honeywell Bull |
-
1975
- 1975-07-28 FR FR7523418A patent/FR2319953A1/fr active Granted
-
1976
- 1976-07-22 GB GB3060376A patent/GB1536436A/en not_active Expired
- 1976-07-28 BE BE2055208A patent/BE844571A/fr unknown
Also Published As
Publication number | Publication date |
---|---|
GB1536436A (en) | 1978-12-20 |
FR2319953A1 (fr) | 1977-02-25 |
FR2319953B1 (fr) | 1979-08-24 |
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