AU604997B2

AU604997B2 - A digital phase locked loop

Info

Publication number: AU604997B2
Application number: AU26684/88A
Authority: AU
Inventors: David Lawrence Archer; Bruce Francis Orr; Colin Rudolph
Original assignee: Standard Telephone and Cables Pty Ltd; Standard Telephone and Cables PLC
Current assignee: Nokia Services Ltd
Priority date: 1988-02-26
Filing date: 1988-12-09
Publication date: 1991-01-03
Anticipated expiration: 2008-12-09
Also published as: AU2668488A

Description

Authorized Signatory To: The Commissioner of Patents Tw v_

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60499 g7 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 4 4 0 04 00 0 0 COMPLETE SPECIICAOllN FOR TM IMNM 1 ION ENTITLED "A DITGITAL PHASE LOCKS) WOPH 'De following statement is a full description of this inventlon, including the best method of performing it known to us:n TO: T he Commissioner of Patents.

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00 0 0 0 0 This invention relates to a digital phase locked loop (DPLL) arrangement intended for use primarily, though not exclusively, in digital communications systems.

In many electronic systems a need arises for a phase locked loop (PLL) function to control the phase or a clock signal relative to the pluse of a reference clock. In digital communication systems phase locked loops are often used to extract a smoothed clock from data or a clock containing jitter or from a clock containing gaps or discontinuities. In this application a filter is placed into the Afedback path to suppress high frequency noise and to provide a smoothed control voltage to a voltage controlled 000 oscillator (VCO). Such PLL circuits are typically implemented using ana- 00 0 0 00 It is an object of the present invention to provide a digital replace- 0 0 0 0 merit for analogue phase locked loops while exhibiting filtering characteristics similar to those obtainable using analogue components.

0 0 0 00 A further object of~ the present invention is to provide a digital re- 00 00 placement for a clock extractor circuit while exhibiting filtering chrao.- *6 teristics similar to those obtainable using analogue components.

00 According to a first aspect of the invention there is provided a dig.i tal phase locked loop arrangement for synchronizing a local clock signal with an incoming signal, the loop comprising a source of phase separated local clock signals derived from a master clock and connected to a phase selector switch, and phase comparator means to which the incoming signal and the output of the phase selection switch are connected to produce a phase error signal being fed to a phase adjusting signal generator which generates a control signal to control selection of the local clock signal by said phase selector switch.

According to a second appect of the present invention there is provided a digital phase locked loop arrangement comprising a digital phase comparator, a phase adjusting Qgrial geherator, a phase selector switch, L -L U NT T ;i ir 1 a :i n; and a multiphase clock generator, wherein phase error between the input signal and the output of said phase selection switch is coiverted to a phase error signal by said digital phase comparator, said phase adjusting signal generator processing said phase error signal to produce a phase advance/retard control signal, said control signal being used to advance or retard the phase selector switch whose output provides the phase locked loop output.

Alternatively, an offset master clock (either offset above or below the desired output frequency) can be adapted, with the output frequency then controlled by advancing only or retarding only the phase. According to a third aspect of the invention therefore, there is provided a digital phase locked loop arrangement comprising a digital phase comparator, a phase adjusting signal generator, a phase selector switch and a multiphase S clock generator, wherein phase error between an input signal and the output of said phase selection switch is converted to a phase error signal by said C C r S digital phase comparator, said phase adjusting signal generator processing said phase error signal to produce a phase advance (retard) control signal being used to advance (retard) said phase selector switch whose output provides the phase locked loop output, said multiphase clock generator having 'gO, a negative (positive) frequency offset from the desired output frequency.

By adding a frequency divider stage between the multiphase generator and the phase comparator and/or between the input signal and the phase comparator, the ratio of the irput frequency to the output frequency may be adjusted. Preferably, the divider stages may be digital counter/divider circuits, and the division ratio(s) may be programmable.

In applications, such as clock extraction, where the input signal to the phase looked loop is discontinuous, a phase detector disable feature may be incorporated to disable phase comparisons when no data transitiono are available, 3 A possible application of this invention is in digital multiplex equipment employing pulse justification, Cor example as spfcified in CCITT Recommendations G742, G743, G751 and G752.

In this type of equipment the multiplex inserts justification (additional) bits into a frame structure in a controlled manner to compensate for bitrate variations of the input and output parts. When the signal is evontually demultiplexed the justification bits must be removed, leaving gaps in the data strean. The frame alignment pattern bits are also removed giving rise to additional gaps. An elastic store is generally used to buffer the output data from the gapped data source and a phase locked loop is provided to control the occupancy of the store and to provide a smoothed readout clock, Conventional implementations of such phase locked loops use analogue filters and voltage controlled crystal oscillators. This approach can however be quite costly and the analog circuits are subjrst to drift and noise problems. The circuits also generally require adjustment at the time of manufacture.

The present invention replaces the analogue filter and voltage controlled oscillator cirauits with digital counter parts which are adjustment free and yield highly reproducable performance.

In c 4 'der that the invention may be fully understood, embodiments thereof will now be described with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a digital phase locked loop arrangement incorporating the present invention; Fig. 2 is an alternative arrangement of that shown in Fig. 1; Fig. 3 illustrates the various controlled output pulses of the arrangement of the present invention.

Fig. 4 is a block diagram of a higher order multiplexer/demultiplexer embodying the digital phase locked loop of the present invention.

L I i Fig. 5 is a block diagram of a primary multiplexer/demultiplexer embodying the digital phase locked loop of the present invention.

Referring to Fig. 1, the input signal to the phase locked loop and the A derived output signal from the loop are connected to a digital phase comparator which produces a phase error signal. In a preferred embodiment the phase comparator may be a simple exclusive-OR gate, a magnitude comparator, or set/reset flipf lop arrangement, all, of which produce a square wave output with a duty cycle proportional to the phase error.

The phase error output from the phase comparator is passed to an aver- 1Y 0 aging logic circuit which reduces high tCrequency variations (jitter) and co 0o produces a smoothed phase error output.

00 00Preferably, the duty cycle modulated signal from the pulse comparator ooo is converted into a signed binary code such that a 50% duty cycle code is o0D represented by a binary code of zero. A number of duty cycle codes are then averaged by generating a digital sum and [-hen !jcaling the result. By 0 0 controlling the averaging period or averaging function the frequency re- 0 0 sponse of the loop may be adjusted.

00 00 The averaged phase error output is passed to a pulse rate coaverter 0~0~ circuit which produces phase advance pulses or phase relavd pulses depend- 0 D ing on the sign of the phase error. The rate of pulses produced is proportional to the magnitude of the phase error. Preferably, separate control lines and provided for the advance and retard pulses.

The addition of a pulse rate converter effectively adds an integration operation to the feedback loop thus converting the transfer function from a A ~zero order response to a first order response. This type of response is necessary for many communication applications, The phase advance/retard pulse signal is passed to the phase selector switch. The phase advance pulse causes the switch to select the next phase from the multiphase generator whle a phase retard pulse causes the previous phase to be selected. The switch operates in a circular or cormmutator fashion with phase 1 and phase N adjacent i.e. phase 1 is reached if the phase is advanced from phase N and phase N is reached if the phase is retarded from phase 1. Preferably, the phase selector switch is implemented using a digital mnltiplexer driven by a modulo-N up/down counter.

The multiphase generator produces N equally spaced phases from a master clock input. In one embodiment a counter/divider circuit is used to generate the phases. Alternatively a digital or analogue tapped delay line may be utilised as a multiphase generator. The frequency of the pulses generated determines the free running frequency of the DPLL.

0,1 Referring to Fig. 2, in an alternative embodiment the phase selector S switch and the multiphase generator as described previously are replaced by a programmable divider arrangement. Te programmable divider divides a fixed frequency clock by a fixed number N except when triggered by a phase 0 00 advance pulse or phase retard pulse from the pulse rate converter. A phase advance pulse causes the division ratio to be reduced for one output cycle 0 00 S of the divider and phase retard pulse causes the division ratio to be in- 0 00 C O o

S

s o creased for one output cycle.

00 0 0 The use of the multiphase selector has the advantage over the programmable divider in that it allows the use of a lower clock frequency than o. 20 that required for the divider, as the selector can easily make use of both edges of the master clock while the divider, unless it is excessively complex, only uses one edge of the master clock.

In operation the phase locked loop controls the advancement or retardation of the output phase by compressing or expanding the width of the output pulses. The more expanded (or compressed) cycles that are produced per second by the switch, the lower (or higher) the average frequency output will be. Fig. 3 illustrates this process. By utilising a suitably large value for N, small ,hase increments are produced and the residual output jitter can be made to approach that obtainable with an analogue PLL.

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The locking range of the DPLL is determined by the maximum rate of pulses produced by the pulse rate converter circuit. The control loop gain is determined by the relationship between the input to the pulse rate converter and the rate at which pulses are produced. The more rapidly the rate of pulses increases as the phase error increases, the higher will be the gain of the control loop, The above parameters may be made programmable if required.

Referring to Fig. 4 there is shown a higher order digital multiplexer/demultiplexer arrangement comprising a demultiplexer (DEMUX) having a composite input and four tributary output circuits Tl-T4 each of which is coupled to an elastic store means and associated digital phase locked loop arrangement (DPLL) of the present invention. (only one elastic store means and DPLL being shown), the readout of data from the elastic S store being controlled by the DPLL which incorporates a pulse rate converter. The composite output of the multiplexer/demultiplexer arrangement is provided by the multiplexer (MUX) having four tributary circuits. Each tributa ,y circuit is coupled to an elastic store means via a data input means and a clock output means, and each elastic store means is coupled to an associated DPLL of the present invention incorporating a phase window detector to extract a clock signal from the incoming data signal.

Referring to Fig. 5, there is shown a primary multiplexer/multiplexer arrangement comprising a demultiplexer (DEMUX) having composite input and channel data output means, a multiplexer having a channel data input means and a composite output means, and two digital phase locked loop arrangements (DPLL) of the present invention, and a clock source switch means for switching to an external clock input means for optionally providing centralized network synchronization. DPLL incorporates a pulse rate converter to produce a filtered transit clock from either the extracted receive clock or the external clock input. DPLL incorporates a sl 4 phase window detection arranged to extract a clock signal from the composite data input.

Because the DPLL described herein is completely digital in nature it is very suitable for implementation as an integrated circuit, either separately or as part of a larger system such as a digital multiplexer/demultiplexer.

While the present invention has been described with regard to many particulars, it is to be understood that equivalents may be readily substituted without departing from the scope of the invention.

Claims

1. A digital phase locked loop arrangement for synchronizing a local clock signal selected from a plurality of selectable, phase separated local clock signals with an incoming signal, the loop comprising a source of said plurality of phase separated local clock signals derived from a master clock and connected to a phase selector switch, and phase comparator means to which the incoming signal end the output of the phase selection switch are connected to produce a phase error signal indicating when the selected local clock signal needs to be advanced or retarded with respect to the in- coming signal, the phase error signal being fed to a phase adjusting signal generator which generates a control signal to control selection of the lo- cal clock signal by said phase selector switch.

2. A digital phase locked loop arrangement comprising a digital phase C 0 comparator, a phase adjusting signal generator, and a phase selection switch, wherein a multiphase clock generator provides a plurality of pahse o separated local clock signals to the phase selection switch, wherein phase S error between an input signal and the output of said phase selection switch is converted to a phase error signal by said digital phase comparator, said phase adjusting signal generator processing said phase error signal to produce a phase advance/retard control signal, said control signal being S° used to advance or retard the phase selection switch whose output provides the phase locked loop output. 0 3, A digital phase locked loop arrangement as claimed in claim 2, wherein said phase adjusting signal generator processes the said phase er- ror signal to produce a phase advance control signal being used to advance said phase selector switch whose output provides the phase locked loop out- put, said nultiphase clock generator having a negative frequency offset from the input signal clock rate.

4. A digital phase locked loop arrangement as claimed in claim 2, I 3J> wherein said phase adjusting signal generator processes said phase error i- i C \i. N:VV i -i 2 -i signal to produce a phase retard signal being used to retard said phase se-. lector switch whose output provides the phase locked loop output, said multiphase clock generator having a positive frequency offset from the in- put signal clock rate. An arrangement as claimed in claim 2, 3 or 4, wherein a frequency divider means is connected between said multiphase generator and said phase comparator for adjusting the ratio of input frequency to output frequency.

6. An arrangement as claimed in claim 2, 3 or 4, wherein a frequency divider means is connected between said input signal and said phase comparator for adjusting the ratio of input frequency to output frequency.

7. An arrangement as claimed in claim 2, 3 or 4 wherein a frequency divider means is connected between said multipbase generator and said phase coparator, and a further frequency divider means is connected between said input signal and said phase comparator, for adjusting the ratio of input frequency to output frequency.

8. An arr-genent as claimed in any one of claims 5 to 7, wherein the or each frequt divider/further frequency divider means comprises a dig- ital counter operating as a circuit.

9. An arrangement as claimed in any one of claim 5 to 8, wherein the division ratio of the or at least one of divider means is selectable to al- loW adjustment of the ratio of the input frequency to tbhe output frequency, An arrangement as claimed in any one of claims 2 to 9, wherein said iUtiphase generator is a counter/divider circuit driven by a master clock signal.

11. An arrangement as claimed in claims 2 to 9, wherein said multiphase generator is a digital or analogue tapped delay line driven by a master clock signal.

12. An arrangement as claimed in any one of claims 2 to 11, wherein the phase adjusting signal generator comprises averaging logic which averages the phase error over an averaging period of a number of clock pulses in ac- S cordance with an averaging function to produce an averaged phase error sig- nal.

13. An arrangement as claimed in claim 12, wherein the averaging period or averaging function of said averaging logic is selectable to allow ad- justment of loop bandwidth.

14. An arrangement as claimed in claim 12 or 13, wherein the averaged phase error signal is fed to a pulse rate converter which produces phase advance or phase retard pulses at a rate proportional to the average phase error signal. An arrangement as claimd in claim l14, wherein the degree of' pro- portionality between said phase error signal and the output of the pulse rate converter iLs adjustable to allow adjustment of loop gain,

16. An arrangement as claimed in claim 14 or 15, wherein the maximum rate of pulses generated by said pulse rate converter Is selectable to al- low adjustment of loop locking range.

17. An arrangement as claimed in any one oV claims 2 to 11, wherein the phase adjusting signal generator comprises a phase window detector, said phase window detector dividing -the phase error range into three adjacent sectio!ns, 'wherein a phase error value falling in section I causes the phase adjusting signal generator to produce a phase retard pulse, a phaee error *value falling in section 2 causes the phase adjusting signal iW\,rto produce no pulse and a phase error value falling in section 3 causes the phase adjusting signal generator to produce a phase advance pule

18. An arrangement as claimed in any one of claim 2 to 17 wherein said phase selector switch and said multiphase generc.tor are replaced by a pro- a grarmable divi1der arrangement, said programimble divider arrangement divid- ing a fixed frequency master clock by a fixed number N eXcept when triggered by a phase advance pulse or phase retard pulse, said phase ad- vance pulse causing t~he division ratio to be reduced for one output cycle comparator, a phase adjusting signal generator, and a phase selection /2 IL l 1 I i L and said phase retard pulse causes the division ratio to be increased for one output cycle.

19. An arrangement as claimed in any one of claims 10 to 18, wherein the master clock frequency is selectable to allow adjustment of the free rurmnning frequency of the DPLL. A digital multiplexer incorporating one or more digital phase locked loop arrangenents as claimed in any one of claims 1 to 19, said dig- I ital phase locked l )ops being interconnected to extract one or more I smoothed clock signals from one or more incoming data streams.

21. A digital demultiplexer incorporating one or more digital phase locked loop arrangements as claimed in any one of (laims 1 to 19, said phase locked loop(s) being interconnecbed to produce a smoothed data clock from a data clock containing gaps or discontinuities due to a 6-multiplex- ing or dejustification operation.

42. A digital multiplexer/deltiplexer comprising a digital multiplexer as claimed in claim 20 combined with a digital demultiplexer as claimed in claim 21. 23. A digital i multiplexer and/or deuultiplexer as claimed in any one of claims 20, 21 or 22 wherein the multiplexing and/or demultiplexing process s is defined by any one of COITI recommendations G742, G743, G751 or G752. 24. A primary PCM multiplexer incorporating one or more digital phase locked loop arrangements as claimed in any one of claims 1 to 19, said dig- ital phase locked loop being arranged to urovide Ulock extraction and/or clock filtering phase locked loop func-.,jons. A pr:imary PCM nultiplexer is claimed in claim 24, wherein the mul- S tiplexing process is defined by any of the CCITT recommendations G732 or G733. 26. A digital phase locked loop arrangement substantially as herein de- scribed with reference to Figs° 1 to 3 of the accompanying drawings. 7 \12 27. An integrated circuit incorporating any one or, more of the arrange- ments claied in claims 1 to 26. DATED THIS ELEVENTH DAY OF SEPTEMBER, 1990 STANDARD TELEPHONES AND CABLES PTY. LIMITED 44, 4 4 4-' 4 44 *4 4 4 404w 44 4 4 44 4- I 94 *4 4 4 6 4440*4 0