AU5490200A - Active dynamic random access memory - Google Patents
Active dynamic random access memoryInfo
- Publication number
- AU5490200A AU5490200A AU54902/00A AU5490200A AU5490200A AU 5490200 A AU5490200 A AU 5490200A AU 54902/00 A AU54902/00 A AU 54902/00A AU 5490200 A AU5490200 A AU 5490200A AU 5490200 A AU5490200 A AU 5490200A
- Authority
- AU
- Australia
- Prior art keywords
- random access
- access memory
- dynamic random
- active dynamic
- active
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
- G06F15/7857—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using interleaved memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US34397199A | 1999-06-30 | 1999-06-30 | |
US09343971 | 1999-06-30 | ||
PCT/US2000/016451 WO2001001242A1 (en) | 1999-06-30 | 2000-06-15 | Active dynamic random access memory |
Publications (1)
Publication Number | Publication Date |
---|---|
AU5490200A true AU5490200A (en) | 2001-01-31 |
Family
ID=23348463
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU54902/00A Abandoned AU5490200A (en) | 1999-06-30 | 2000-06-15 | Active dynamic random access memory |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU5490200A (en) |
WO (1) | WO2001001242A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2395298B (en) * | 2002-09-17 | 2007-02-14 | Micron Technology Inc | Flexible results pipeline for processing element |
GB2396442B (en) | 2002-09-17 | 2006-03-01 | Micron Technology Inc | Host memory interface for a parallel processor |
US10732866B2 (en) | 2016-10-27 | 2020-08-04 | Samsung Electronics Co., Ltd. | Scaling out architecture for DRAM-based processing unit (DPU) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5581773A (en) * | 1992-05-12 | 1996-12-03 | Glover; Michael A. | Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements |
US5895487A (en) * | 1996-11-13 | 1999-04-20 | International Business Machines Corporation | Integrated processing and L2 DRAM cache |
-
2000
- 2000-06-15 WO PCT/US2000/016451 patent/WO2001001242A1/en active Application Filing
- 2000-06-15 AU AU54902/00A patent/AU5490200A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2001001242A1 (en) | 2001-01-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |