AU2001284924A1 - Method and system for using dynamic random access memory as cache memory - Google Patents

Method and system for using dynamic random access memory as cache memory

Info

Publication number
AU2001284924A1
AU2001284924A1 AU2001284924A AU8492401A AU2001284924A1 AU 2001284924 A1 AU2001284924 A1 AU 2001284924A1 AU 2001284924 A AU2001284924 A AU 2001284924A AU 8492401 A AU8492401 A AU 8492401A AU 2001284924 A1 AU2001284924 A1 AU 2001284924A1
Authority
AU
Australia
Prior art keywords
random access
dynamic random
memory
access memory
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001284924A
Inventor
Charles H Dennison
Brent Keeth
Kevin J. Ryan
Brian M. Shirley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU2001284924A1 publication Critical patent/AU2001284924A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/043—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
AU2001284924A 2000-08-17 2001-08-14 Method and system for using dynamic random access memory as cache memory Abandoned AU2001284924A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/642,546 US6862654B1 (en) 2000-08-17 2000-08-17 Method and system for using dynamic random access memory as cache memory
US09642546 2000-08-17
PCT/US2001/025494 WO2002015019A1 (en) 2000-08-17 2001-08-14 Method and system for using dynamic random access memory as cache memory

Publications (1)

Publication Number Publication Date
AU2001284924A1 true AU2001284924A1 (en) 2002-02-25

Family

ID=24577039

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001284924A Abandoned AU2001284924A1 (en) 2000-08-17 2001-08-14 Method and system for using dynamic random access memory as cache memory

Country Status (3)

Country Link
US (5) US6862654B1 (en)
AU (1) AU2001284924A1 (en)
WO (1) WO2002015019A1 (en)

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US7123521B1 (en) 2005-04-27 2006-10-17 Micron Technology, Inc. Random cache read
US8601207B2 (en) * 2006-04-26 2013-12-03 The Invention Science Fund I, Llc Management of memory refresh power consumption
US9455035B2 (en) * 2006-04-26 2016-09-27 Invention Science Fund I, Llc Management of memory refresh power consumption
KR101975528B1 (en) 2012-07-17 2019-05-07 삼성전자주식회사 semiconductor memory cell array having fast array area and semiconductor memory including the same
US20140146589A1 (en) * 2012-11-29 2014-05-29 Samsung Electronics Co., Ltd. Semiconductor memory device with cache function in dram
US20140264915A1 (en) * 2013-03-15 2014-09-18 Chao-Yuan Huang Stacked Integrated Circuit System
WO2015065426A1 (en) * 2013-10-31 2015-05-07 Hewlett-Packard Development Company, L.P. Memory access for busy memory
KR102373544B1 (en) 2015-11-06 2022-03-11 삼성전자주식회사 Memory Device and Memory System Performing Request-based Refresh and Operating Method of Memory Device

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Also Published As

Publication number Publication date
WO2002015019A1 (en) 2002-02-21
US20040186957A1 (en) 2004-09-23
US20060015679A1 (en) 2006-01-19
US7155561B2 (en) 2006-12-26
US7350018B2 (en) 2008-03-25
US20080177943A1 (en) 2008-07-24
US7917692B2 (en) 2011-03-29
US20070055818A1 (en) 2007-03-08
US6948027B2 (en) 2005-09-20
US6862654B1 (en) 2005-03-01

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