AU2019388A - Synchronising apparatus for a digital signal demultiplexer - Google Patents
Synchronising apparatus for a digital signal demultiplexerInfo
- Publication number
- AU2019388A AU2019388A AU20193/88A AU2019388A AU2019388A AU 2019388 A AU2019388 A AU 2019388A AU 20193/88 A AU20193/88 A AU 20193/88A AU 2019388 A AU2019388 A AU 2019388A AU 2019388 A AU2019388 A AU 2019388A
- Authority
- AU
- Australia
- Prior art keywords
- digital signal
- bit
- signal demultiplexer
- slip
- synchronising apparatus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
The object consists of equalising a bit slip during the demultiplexing of a multiplex signal. A bit-slip detection device (10) detects a bit slip and controls a clock frequency switching circuit (11) in such a manner that the number of the bits output to the outputs (4a-4d) of the demultiplexer (3) is returned to the nominal value by accelerating or decelerating the clock at the main frame counter (8). The invention is used in digital signal demultiplexers. <IMAGE>
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3725477 | 1987-07-31 | ||
DE3725477 | 1987-07-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
AU2019388A true AU2019388A (en) | 1989-02-02 |
AU587947B2 AU587947B2 (en) | 1989-08-31 |
Family
ID=6332834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU20193/88A Ceased AU587947B2 (en) | 1987-07-31 | 1988-07-29 | Synchronising apparatus for a digital signal demultiplexer |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0301481B1 (en) |
AT (1) | ATE75087T1 (en) |
AU (1) | AU587947B2 (en) |
DE (1) | DE3870073D1 (en) |
ES (1) | ES2030476T3 (en) |
GR (1) | GR3004923T3 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5241541A (en) * | 1990-03-15 | 1993-08-31 | International Business Machines Corporation | Burst time division multiplex interface for integrated data link controller |
FR2682842B1 (en) * | 1991-10-18 | 1994-07-22 | France Telecom | METHOD AND DEVICE FOR COUNTING CLOCK SLIDES. |
FR2689709B1 (en) | 1992-04-01 | 1995-01-06 | France Telecom | Method for correcting uncontrolled slippage of data sequences carried by digital links and device for implementing this method. |
DE10154252B4 (en) * | 2001-11-05 | 2005-12-01 | Siemens Ag | Method for detecting and compensating for bit-slip errors in the serial transmission of digital data and circuit arrangement that can be used for this purpose on the receiver side |
JP3945287B2 (en) * | 2002-03-28 | 2007-07-18 | 日本電気株式会社 | Data receiving circuit and data receiving method |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2930586A1 (en) * | 1979-07-27 | 1981-02-12 | Siemens Ag | CIRCUIT ARRANGEMENT FOR SYNCHRONIZING A SUBordinate DEVICE, IN PARTICULAR A DIGITAL SUBSCRIBER STATION, BY A SUPERIOR DEVICE, IN PARTICULAR A DIGITAL SWITCHING CENTER OF A PCM REMOTE |
DE3212450A1 (en) * | 1982-04-02 | 1983-10-13 | Siemens AG, 1000 Berlin und 8000 München | SYNCHRONIZING DEVICE OF A DIGITAL SIGNAL DEMULTIPLEX DEVICE |
EP0134374B1 (en) * | 1983-09-07 | 1987-12-02 | International Business Machines Corporation | Phase-locked clock |
-
1988
- 1988-07-26 ES ES198888112055T patent/ES2030476T3/en not_active Expired - Lifetime
- 1988-07-26 EP EP88112055A patent/EP0301481B1/en not_active Expired - Lifetime
- 1988-07-26 DE DE8888112055T patent/DE3870073D1/en not_active Expired - Fee Related
- 1988-07-26 AT AT88112055T patent/ATE75087T1/en active
- 1988-07-29 AU AU20193/88A patent/AU587947B2/en not_active Ceased
-
1992
- 1992-06-17 GR GR920400686T patent/GR3004923T3/el unknown
Also Published As
Publication number | Publication date |
---|---|
EP0301481A1 (en) | 1989-02-01 |
EP0301481B1 (en) | 1992-04-15 |
AU587947B2 (en) | 1989-08-31 |
DE3870073D1 (en) | 1992-05-21 |
GR3004923T3 (en) | 1993-04-28 |
ATE75087T1 (en) | 1992-05-15 |
ES2030476T3 (en) | 1992-11-01 |
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