AU2002232520A1 - Method for removing etch residue resulting from a process for forming a via - Google Patents

Method for removing etch residue resulting from a process for forming a via

Info

Publication number
AU2002232520A1
AU2002232520A1 AU2002232520A AU3252002A AU2002232520A1 AU 2002232520 A1 AU2002232520 A1 AU 2002232520A1 AU 2002232520 A AU2002232520 A AU 2002232520A AU 3252002 A AU3252002 A AU 3252002A AU 2002232520 A1 AU2002232520 A1 AU 2002232520A1
Authority
AU
Australia
Prior art keywords
forming
etch residue
residue resulting
removing etch
resulting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002232520A
Inventor
Douglas J. Dopp
Valentin Medina Jr.
Thien T. Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2002232520A1 publication Critical patent/AU2002232520A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/42Stripping or agents therefor
    • G03F7/427Stripping or agents therefor using plasma means only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S134/00Cleaning and liquid contact with solids
    • Y10S134/902Semiconductor wafer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/906Cleaning of wafer as interim step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
AU2002232520A 2000-11-07 2001-11-06 Method for removing etch residue resulting from a process for forming a via Abandoned AU2002232520A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/707,595 2000-11-07
US09/707,595 US6554004B1 (en) 2000-11-07 2000-11-07 Method for removing etch residue resulting from a process for forming a via
PCT/US2001/047140 WO2002039489A2 (en) 2000-11-07 2001-11-06 Method for removing etch residue resulting from a process for forming a via

Publications (1)

Publication Number Publication Date
AU2002232520A1 true AU2002232520A1 (en) 2002-05-21

Family

ID=24842325

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002232520A Abandoned AU2002232520A1 (en) 2000-11-07 2001-11-06 Method for removing etch residue resulting from a process for forming a via

Country Status (7)

Country Link
US (1) US6554004B1 (en)
JP (1) JP2004517470A (en)
KR (1) KR20030093186A (en)
CN (1) CN1265443C (en)
AU (1) AU2002232520A1 (en)
TW (1) TW523827B (en)
WO (1) WO2002039489A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6911349B2 (en) * 2001-02-16 2005-06-28 Boxer Cross Inc. Evaluating sidewall coverage in a semiconductor wafer
JP4838464B2 (en) * 2001-09-26 2011-12-14 東京エレクトロン株式会社 Processing method
US7235489B2 (en) * 2004-05-21 2007-06-26 Agere Systems Inc. Device and method to eliminate shorting induced by via to metal misalignment
US8399360B1 (en) * 2005-11-17 2013-03-19 Cypress Semiconductor Corporation Process for post contact-etch clean
US20070269975A1 (en) * 2006-05-18 2007-11-22 Savas Stephen E System and method for removal of photoresist and stop layer following contact dielectric etch
US7510965B2 (en) * 2006-11-30 2009-03-31 United Microelectronics Corp. Method for fabricating a dual damascene structure
KR20080060017A (en) * 2006-12-26 2008-07-01 주식회사 하이닉스반도체 Method for manufacturing of semiconductor device
CN102468144B (en) * 2010-11-12 2015-11-25 北大方正集团有限公司 A kind of method improving titanium and titanium nitride filling capacity in through hole
CN103361690B (en) * 2012-03-31 2016-08-24 北大方正集团有限公司 The blind hole cleaning method of PCB
CN103377913B (en) * 2012-04-18 2016-08-31 中芯国际集成电路制造(上海)有限公司 The forming method of opening
CN103972055B (en) * 2013-01-31 2016-09-07 中微半导体设备(上海)有限公司 Photoresist minimizing technology
CN110299285B (en) * 2019-06-19 2021-10-15 上海华力集成电路制造有限公司 Method for improving surface defects of wafer

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5595707A (en) * 1990-03-02 1997-01-21 Ventana Medical Systems, Inc. Automated biological reaction apparatus
JP3259380B2 (en) 1992-12-04 2002-02-25 ソニー株式会社 Method for manufacturing semiconductor device
JP3529849B2 (en) 1994-05-23 2004-05-24 富士通株式会社 Method for manufacturing semiconductor device
US5780359A (en) * 1995-12-11 1998-07-14 Applied Materials, Inc. Polymer removal from top surfaces and sidewalls of a semiconductor wafer
KR100194789B1 (en) * 1995-12-16 1999-06-15 김영환 Polymer removal method of semiconductor device
US5817579A (en) 1997-04-09 1998-10-06 Vanguard International Semiconductor Corporation Two step plasma etch method for forming self aligned contact
US6117786A (en) 1998-05-05 2000-09-12 Lam Research Corporation Method for etching silicon dioxide using fluorocarbon gas chemistry
US6432830B1 (en) 1998-05-15 2002-08-13 Applied Materials, Inc. Semiconductor fabrication process
WO2000012231A1 (en) 1998-08-27 2000-03-09 Anon, Inc. Method of removing organic materials from substrates
US6207583B1 (en) * 1998-09-04 2001-03-27 Alliedsignal Inc. Photoresist ashing process for organic and inorganic polymer dielectric materials
US6130166A (en) * 1999-02-01 2000-10-10 Vlsi Technology, Inc. Alternative plasma chemistry for enhanced photoresist removal
US6376384B1 (en) * 2000-04-24 2002-04-23 Vanguard International Semiconductor Corporation Multiple etch contact etching method incorporating post contact etch etching

Also Published As

Publication number Publication date
US6554004B1 (en) 2003-04-29
JP2004517470A (en) 2004-06-10
KR20030093186A (en) 2003-12-06
CN1265443C (en) 2006-07-19
WO2002039489A3 (en) 2003-12-11
TW523827B (en) 2003-03-11
CN1526161A (en) 2004-09-01
WO2002039489A2 (en) 2002-05-16

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