AU2002222335A1 - Encoding system for transmitting data and clock signals jointly across two wires - Google Patents
Encoding system for transmitting data and clock signals jointly across two wiresInfo
- Publication number
- AU2002222335A1 AU2002222335A1 AU2002222335A AU2233502A AU2002222335A1 AU 2002222335 A1 AU2002222335 A1 AU 2002222335A1 AU 2002222335 A AU2002222335 A AU 2002222335A AU 2233502 A AU2233502 A AU 2233502A AU 2002222335 A1 AU2002222335 A1 AU 2002222335A1
- Authority
- AU
- Australia
- Prior art keywords
- signal
- sender
- criterion
- receiver
- wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
An information processing system contains a sender, a receiver and a communication channel coupled between the sender and the receiver. The communication channel transmits a first and second binary logic signal. The sender encodes data values and information distinguishing successive clock phases into a combination of the first and second signal. The receiver receives the data values and the information. The sender uses alternately a first and a second data dependent criterion to select which one of the first and second signal has a logic level change between immediately successive clock phases. As a result so that the first and second signal are alternately mutually opposite and mutually equal. The first criterion selects the level of the first signal dependent on the data value. The second criterion provides for a level change of either the first or the second signal depending on the data value.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP00204652.2 | 2000-12-20 | ||
| EP00204652 | 2000-12-20 | ||
| PCT/IB2001/002395 WO2002051081A2 (en) | 2000-12-20 | 2001-12-06 | Encoding system for transmitting data and clock signals jointly across two wires |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2002222335A1 true AU2002222335A1 (en) | 2002-07-01 |
Family
ID=8172480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2002222335A Abandoned AU2002222335A1 (en) | 2000-12-20 | 2001-12-06 | Encoding system for transmitting data and clock signals jointly across two wires |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US7020154B2 (en) |
| EP (1) | EP1254543B1 (en) |
| JP (1) | JP3989839B2 (en) |
| KR (1) | KR100810800B1 (en) |
| CN (1) | CN1251464C (en) |
| AT (1) | ATE363173T1 (en) |
| AU (1) | AU2002222335A1 (en) |
| DE (1) | DE60128541T2 (en) |
| WO (1) | WO2002051081A2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3973630B2 (en) * | 2004-01-20 | 2007-09-12 | シャープ株式会社 | Data transmission apparatus and data transmission method |
| WO2007060620A1 (en) | 2005-11-22 | 2007-05-31 | Nxp B.V. | Synchronized receiver |
| CN101620663B (en) * | 2008-07-02 | 2012-05-09 | 中兴通讯股份有限公司 | Data coding method in passive radio frequency identification system |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7313756A (en) * | 1972-10-11 | 1974-04-16 | ||
| US4928289A (en) * | 1988-12-19 | 1990-05-22 | Systran Corporation | Apparatus and method for binary data transmission |
| GB9011700D0 (en) * | 1990-05-25 | 1990-07-18 | Inmos Ltd | Communication interface |
| US6037884A (en) * | 1996-11-13 | 2000-03-14 | Int Labs, Inc. | Technique to encode multiple digital data streams in limited bandwidth for transmission in a single medium |
| US5912928A (en) * | 1997-06-27 | 1999-06-15 | International Business Machines Corporation | High speed serial data transmission encoder |
| TW391116B (en) * | 1998-07-24 | 2000-05-21 | Koninkl Philips Electronics Nv | High-speed serial data communication system |
-
2001
- 2001-12-06 KR KR1020027010789A patent/KR100810800B1/en not_active IP Right Cessation
- 2001-12-06 EP EP01271722A patent/EP1254543B1/en not_active Expired - Lifetime
- 2001-12-06 CN CNB018051286A patent/CN1251464C/en not_active Expired - Fee Related
- 2001-12-06 WO PCT/IB2001/002395 patent/WO2002051081A2/en active IP Right Grant
- 2001-12-06 AT AT01271722T patent/ATE363173T1/en not_active IP Right Cessation
- 2001-12-06 JP JP2002552257A patent/JP3989839B2/en not_active Expired - Fee Related
- 2001-12-06 DE DE60128541T patent/DE60128541T2/en not_active Expired - Lifetime
- 2001-12-06 AU AU2002222335A patent/AU2002222335A1/en not_active Abandoned
- 2001-12-17 US US10/023,121 patent/US7020154B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002051081A2 (en) | 2002-06-27 |
| WO2002051081A3 (en) | 2002-08-29 |
| KR100810800B1 (en) | 2008-03-06 |
| JP2004516744A (en) | 2004-06-03 |
| ATE363173T1 (en) | 2007-06-15 |
| DE60128541T2 (en) | 2008-01-24 |
| JP3989839B2 (en) | 2007-10-10 |
| KR20020079872A (en) | 2002-10-19 |
| EP1254543A2 (en) | 2002-11-06 |
| US7020154B2 (en) | 2006-03-28 |
| US20020085576A1 (en) | 2002-07-04 |
| DE60128541D1 (en) | 2007-07-05 |
| CN1404674A (en) | 2003-03-19 |
| EP1254543B1 (en) | 2007-05-23 |
| CN1251464C (en) | 2006-04-12 |
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