AU2001288555A1 - Epitaxial template and barrier for the integration of functional thin film heterostructures on silicon - Google Patents

Epitaxial template and barrier for the integration of functional thin film heterostructures on silicon

Info

Publication number
AU2001288555A1
AU2001288555A1 AU2001288555A AU8855501A AU2001288555A1 AU 2001288555 A1 AU2001288555 A1 AU 2001288555A1 AU 2001288555 A AU2001288555 A AU 2001288555A AU 8855501 A AU8855501 A AU 8855501A AU 2001288555 A1 AU2001288555 A1 AU 2001288555A1
Authority
AU
Australia
Prior art keywords
integration
barrier
silicon
thin film
functional thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001288555A
Inventor
Ramamoorthy Ramesh
Darrell G. Schlom
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Penn State Research Foundation
University of Maryland at Baltimore
Original Assignee
Penn State Research Foundation
University of Maryland at Baltimore
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Penn State Research Foundation, University of Maryland at Baltimore filed Critical Penn State Research Foundation
Publication of AU2001288555A1 publication Critical patent/AU2001288555A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
AU2001288555A 2000-08-31 2001-08-30 Epitaxial template and barrier for the integration of functional thin film heterostructures on silicon Abandoned AU2001288555A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/652,798 2000-08-31
US09/652,798 US6518609B1 (en) 2000-08-31 2000-08-31 Niobium or vanadium substituted strontium titanate barrier intermediate a silicon underlayer and a functional metal oxide film
PCT/US2001/027050 WO2002019389A2 (en) 2000-08-31 2001-08-30 Epitaxial template and barrier for the integration of functional thin film heterostructures on silicon

Publications (1)

Publication Number Publication Date
AU2001288555A1 true AU2001288555A1 (en) 2002-03-13

Family

ID=24618201

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001288555A Abandoned AU2001288555A1 (en) 2000-08-31 2001-08-30 Epitaxial template and barrier for the integration of functional thin film heterostructures on silicon

Country Status (3)

Country Link
US (3) US6518609B1 (en)
AU (1) AU2001288555A1 (en)
WO (1) WO2002019389A2 (en)

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Also Published As

Publication number Publication date
US20030127674A1 (en) 2003-07-10
US6518609B1 (en) 2003-02-11
WO2002019389A3 (en) 2002-08-15
US6781176B2 (en) 2004-08-24
US20030062553A1 (en) 2003-04-03
US6642539B2 (en) 2003-11-04
WO2002019389A2 (en) 2002-03-07

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