AU2001277190A1 - Phase locked loop with controlled switching of reference signals - Google Patents
Phase locked loop with controlled switching of reference signalsInfo
- Publication number
- AU2001277190A1 AU2001277190A1 AU2001277190A AU7719001A AU2001277190A1 AU 2001277190 A1 AU2001277190 A1 AU 2001277190A1 AU 2001277190 A AU2001277190 A AU 2001277190A AU 7719001 A AU7719001 A AU 7719001A AU 2001277190 A1 AU2001277190 A1 AU 2001277190A1
- Authority
- AU
- Australia
- Prior art keywords
- reference signals
- locked loop
- phase locked
- controlled switching
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/632,952 US6362670B1 (en) | 2000-08-04 | 2000-08-04 | Controlled slew reference switch for a phase locked loop |
US09/632,952 | 2000-08-04 | ||
PCT/US2001/023486 WO2002013390A2 (en) | 2000-08-04 | 2001-07-26 | Phase locked loop with controlled switching of reference signals |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001277190A1 true AU2001277190A1 (en) | 2002-02-18 |
Family
ID=24537667
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001277190A Abandoned AU2001277190A1 (en) | 2000-08-04 | 2001-07-26 | Phase locked loop with controlled switching of reference signals |
Country Status (3)
Country | Link |
---|---|
US (1) | US6362670B1 (en) |
AU (1) | AU2001277190A1 (en) |
WO (1) | WO2002013390A2 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6751743B1 (en) * | 2000-12-22 | 2004-06-15 | Cisco Technology, Inc. | Method and apparatus for selecting a first clock and second clock for first and second devices respectively from an up-converted clock and an aligned clock for synchronization |
US6934869B1 (en) * | 2001-09-12 | 2005-08-23 | Big Bear Networks, Inc. | Method and apparatus for eliminating dead zone in phase locked loops using binary quantized phase detectors |
US6531926B1 (en) | 2001-09-13 | 2003-03-11 | Overture Networks, Inc. | Dynamic control of phase-locked loop |
US6981168B2 (en) * | 2002-01-08 | 2005-12-27 | International Business Machines Corporation | Clock data recovery system |
US7471756B2 (en) * | 2002-02-21 | 2008-12-30 | Intersil Americas Inc. | Phase detector and method for a shortening phase-error-correction pulse |
JP4002460B2 (en) * | 2002-03-26 | 2007-10-31 | 本田技研工業株式会社 | Control device for throttle valve drive device |
JP3857169B2 (en) * | 2002-03-29 | 2006-12-13 | 本田技研工業株式会社 | Plant control equipment |
JP4155062B2 (en) * | 2003-03-03 | 2008-09-24 | セイコーエプソン株式会社 | Clock shaper and electronic equipment using it |
KR100510523B1 (en) * | 2003-03-13 | 2005-08-26 | 삼성전자주식회사 | Phase-frequency detector providing for reflecting clock transitions at an added delay for a zero dead zone in charge pump control and phase/frequency detection method thereof |
JP2005252354A (en) * | 2004-03-01 | 2005-09-15 | Seiko Epson Corp | Method of outputting clock signal, clock shaping device and electronic equipment using the same |
KR100574980B1 (en) * | 2004-04-26 | 2006-05-02 | 삼성전자주식회사 | Phase-Locked Loop for fast frequency locking |
US7042258B2 (en) * | 2004-04-29 | 2006-05-09 | Agere Systems Inc. | Signal generator with selectable mode control |
US8988122B2 (en) * | 2011-09-30 | 2015-03-24 | Intel Corporation | Apparatus and method for performing spread-spectrum clock control |
US11588489B1 (en) | 2021-10-06 | 2023-02-21 | Shaoxing Yuanfang Semiconductor Co., Ltd. | Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock |
US11923864B2 (en) | 2021-10-18 | 2024-03-05 | Shaoxing Yuanfang Semiconductor Co., Ltd. | Fast switching of output frequency of a phase locked loop (PLL) |
US11967965B2 (en) | 2021-11-03 | 2024-04-23 | Shaoxing Yuanfang Semiconductor Co., Ltd. | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0327620A (en) * | 1989-06-23 | 1991-02-06 | Fujitsu Ltd | Switching device for reference signal |
US5254955A (en) | 1989-08-25 | 1993-10-19 | Anritsu Corporation | Advanced phase locked loop circuit |
JPH07170584A (en) * | 1993-12-14 | 1995-07-04 | Nec Corp | Clock switching circuit |
US5684434A (en) * | 1995-10-30 | 1997-11-04 | Cypress Semiconductor | Erasable and programmable single chip clock generator |
JPH09252250A (en) * | 1996-03-18 | 1997-09-22 | Mitsubishi Electric Corp | Phase locked loop circuit |
JP3324401B2 (en) * | 1996-07-25 | 2002-09-17 | 松下電器産業株式会社 | PLL circuit |
US6188255B1 (en) * | 1998-09-28 | 2001-02-13 | Cypress Semiconductor Corp. | Configurable clock generator |
-
2000
- 2000-08-04 US US09/632,952 patent/US6362670B1/en not_active Expired - Fee Related
-
2001
- 2001-07-26 AU AU2001277190A patent/AU2001277190A1/en not_active Abandoned
- 2001-07-26 WO PCT/US2001/023486 patent/WO2002013390A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2002013390A3 (en) | 2002-09-19 |
US6362670B1 (en) | 2002-03-26 |
WO2002013390A2 (en) | 2002-02-14 |
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