AU2001248167A1 - Method and circuit for testing dc parameters of circuit input and output nodes - Google Patents

Method and circuit for testing dc parameters of circuit input and output nodes

Info

Publication number
AU2001248167A1
AU2001248167A1 AU2001248167A AU4816701A AU2001248167A1 AU 2001248167 A1 AU2001248167 A1 AU 2001248167A1 AU 2001248167 A AU2001248167 A AU 2001248167A AU 4816701 A AU4816701 A AU 4816701A AU 2001248167 A1 AU2001248167 A1 AU 2001248167A1
Authority
AU
Australia
Prior art keywords
circuit
testing
parameters
output nodes
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001248167A
Inventor
Stephen K. Sunter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LogicVision Inc
Original Assignee
LogicVision Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LogicVision Inc filed Critical LogicVision Inc
Publication of AU2001248167A1 publication Critical patent/AU2001248167A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
AU2001248167A 2000-05-12 2001-04-03 Method and circuit for testing dc parameters of circuit input and output nodes Abandoned AU2001248167A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/570,412 US6586921B1 (en) 2000-05-12 2000-05-12 Method and circuit for testing DC parameters of circuit input and output nodes
US09570412 2000-05-12
PCT/CA2001/000450 WO2001086314A2 (en) 2000-05-12 2001-04-03 Method and circuit for testing dc parameters of circuit input and output nodes

Publications (1)

Publication Number Publication Date
AU2001248167A1 true AU2001248167A1 (en) 2001-11-20

Family

ID=24279545

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001248167A Abandoned AU2001248167A1 (en) 2000-05-12 2001-04-03 Method and circuit for testing dc parameters of circuit input and output nodes

Country Status (6)

Country Link
US (1) US6586921B1 (en)
EP (1) EP1307754A2 (en)
JP (1) JP2003532902A (en)
AU (1) AU2001248167A1 (en)
CA (1) CA2406619A1 (en)
WO (1) WO2001086314A2 (en)

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WO2004044601A1 (en) * 2002-11-14 2004-05-27 Logicvision, Inc. Boundary scan with strobed pad driver enable
US7337160B2 (en) * 2002-12-31 2008-02-26 Bae Systems Information And Electronic Systems Integration Inc. Use of radiation-hardened chalcogenide technology for spaceborne reconfigurable digital processing systems
US6907377B2 (en) * 2003-03-31 2005-06-14 Intel Corporation Method and apparatus for interconnect built-in self test based system management performance tuning
US7088091B2 (en) * 2003-08-14 2006-08-08 Intel Corporation Testing a multi-channel device
TWI225933B (en) * 2003-09-01 2005-01-01 Faraday Tech Corp Universal test platform and test method for latch-up
US7453255B2 (en) * 2003-11-20 2008-11-18 Logicvision, Inc. Circuit and method for measuring delay of high speed signals
US7002365B2 (en) * 2003-12-30 2006-02-21 Intel Corporation Method and an apparatus for testing transmitter and receiver
US6963212B2 (en) * 2004-03-23 2005-11-08 Agilent Technologies, Inc. Self-testing input/output pad
DE102004025984A1 (en) * 2004-05-26 2005-12-15 Sms Demag Ag Method and device for assembly and functional testing of rolling fittings in rolling mills or in rolling mills, such as tandem rolling mills
WO2006117588A1 (en) * 2005-05-04 2006-11-09 Freescale Semiconductor, Inc. An integrated circuit and a method for designing a boundary scan super-cell
US7519888B2 (en) * 2005-09-12 2009-04-14 Virage Logic Corporation Input-output device testing
US7616036B1 (en) * 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
US7265696B2 (en) * 2005-11-10 2007-09-04 International Business Machines Corporation Methods and apparatus for testing an integrated circuit
US7511526B2 (en) * 2006-08-23 2009-03-31 Munt Kenneth A Circuit module testing apparatus and method
US7411407B2 (en) * 2006-10-13 2008-08-12 Agilent Technologies, Inc. Testing target resistances in circuit assemblies
US20080231310A1 (en) * 2006-10-20 2008-09-25 Stmicroelectronics Pvt. Ltd. Flexible on chip testing circuit for i/o's characterization
US7698610B2 (en) * 2007-07-25 2010-04-13 Freescale Semiconductor, Inc. Techniques for detecting open integrated circuit pins
JP2009048674A (en) * 2007-08-14 2009-03-05 Nec Electronics Corp Semiconductor integrated circuit
US7973563B2 (en) * 2008-02-15 2011-07-05 Silicon Labs Spectra, Inc. Programmable IO architecture
EP2113779A1 (en) 2008-04-30 2009-11-04 Nxp B.V. Testable integrated circuit and integrated circuit test method
US7839155B2 (en) * 2008-12-15 2010-11-23 Texas Instruments Incorporated Methods and apparatus to analyze on-chip controlled integrated circuits
US8572433B2 (en) 2010-03-10 2013-10-29 Texas Instruments Incorporated JTAG IC with commandable circuit controlling data register control router
KR101110792B1 (en) * 2009-07-02 2012-03-16 주식회사 하이닉스반도체 Semiconductor device and its driving method
US8489947B2 (en) * 2010-02-15 2013-07-16 Mentor Graphics Corporation Circuit and method for simultaneously measuring multiple changes in delay
US8680874B2 (en) 2010-07-30 2014-03-25 Imec On-chip testing using time-to-digital conversion
US8712718B1 (en) * 2011-07-20 2014-04-29 Xilinx, Inc. Predicting performance of an integrated circuit
CN103105570B (en) * 2013-01-23 2016-09-07 无锡华润上华科技有限公司 The method of testing of a kind of cut-in voltage and system
US10317463B2 (en) * 2015-10-27 2019-06-11 Nvidia Corporation Scan system interface (SSI) module
US10481203B2 (en) 2015-04-04 2019-11-19 Nvidia Corporation Granular dynamic test systems and methods
CN116256624A (en) 2017-11-15 2023-06-13 普罗泰克斯公司 Integrated circuit margin measurement and fault prediction apparatus
TWI802615B (en) * 2017-11-23 2023-05-21 以色列商普騰泰克斯有限公司 Integrated circuit pad failure detection
US10670649B2 (en) * 2018-02-02 2020-06-02 Texas Instruments Incorporated Bondwire testing of IC using pin diode signatures
KR102660897B1 (en) * 2019-01-11 2024-04-24 삼성전자주식회사 Multi-chip package
US11929131B2 (en) 2019-12-04 2024-03-12 Proteantecs Ltd. Memory device degradation monitoring
TWI770964B (en) * 2021-04-27 2022-07-11 華邦電子股份有限公司 Testing circuit and testing method thereof
CN113848498A (en) * 2021-08-11 2021-12-28 威凯检测技术有限公司 Method for verifying slow-falling and slow-rising test capability of power supply voltage of road vehicle electrical and electronic equipment
US11815551B1 (en) 2022-06-07 2023-11-14 Proteantecs Ltd. Die-to-die connectivity monitoring using a clocked receiver
US12013800B1 (en) 2023-02-08 2024-06-18 Proteantecs Ltd. Die-to-die and chip-to-chip connectivity monitoring

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US6158032A (en) * 1998-03-27 2000-12-05 International Business Machines Corporation Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof
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Also Published As

Publication number Publication date
EP1307754A2 (en) 2003-05-07
CA2406619A1 (en) 2001-11-15
JP2003532902A (en) 2003-11-05
US6586921B1 (en) 2003-07-01
WO2001086314A2 (en) 2001-11-15
WO2001086314A3 (en) 2002-05-10

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