AU1680697A - Virtual time loop - Google Patents
Virtual time loopInfo
- Publication number
- AU1680697A AU1680697A AU16806/97A AU1680697A AU1680697A AU 1680697 A AU1680697 A AU 1680697A AU 16806/97 A AU16806/97 A AU 16806/97A AU 1680697 A AU1680697 A AU 1680697A AU 1680697 A AU1680697 A AU 1680697A
- Authority
- AU
- Australia
- Prior art keywords
- network
- synchronized
- data
- switched
- packet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 claims description 57
- 230000005540 biological transmission Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 8
- 230000003044 adaptive effect Effects 0.000 description 10
- 239000000872 buffer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 3
- RPOCQUTXCSLYFJ-UHFFFAOYSA-N n-(4-ethylphenyl)-2-(2-methyl-3,5-dioxothiomorpholin-4-yl)acetamide Chemical compound C1=CC(CC)=CC=C1NC(=O)CN1C(=O)C(C)SCC1=O RPOCQUTXCSLYFJ-UHFFFAOYSA-N 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
- H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
- H04L2012/5654—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL1
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5663—Support of N-ISDN
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
- H04L2012/5674—Synchronisation, timing recovery or alignment
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Multimedia (AREA)
- Computer Hardware Design (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Magnetic Resonance Imaging Apparatus (AREA)
- Electrophonic Musical Instruments (AREA)
- Steroid Compounds (AREA)
Description
VIRTUAL TIME LOOP TECHNICAL FIELD
The present invention relates to the field of timing in a packet switched network, in particular an ATM network.
BACKGROUND AND STATE OF THE ART The timing of a digital transmission network is in most applications highly important. It is essential that the transmitting part and the receiving part of the transmission system use the same clock frequency and are in phase with each other. In order to obtain this, some form of synchronization is needed for most applications.
One application which does not need any synchronization is the ATM (Asynchronous Transfer Mode) transmission network. However, many devices or apparatuses connected to an ATM network require some form of synchronization, such as telephone conversation or a video conference.
Furthermore the transmission network used can also involve other transmission systems than the ATM network, such as the Public Switched Telephone Network (PSTN), which is often a synchronized network consisting of e.g. the Plesiochronous Digital Hierarchy (PDH) and the Synchronous Digital Hierarchy (SDH). Thus, the interface between the ATM network and the PSTN must provide a synchronization of the regenerated user data used by the ATM network.
The ATM standard states that the synchronization of the regenerated user data, which are transmitted from a synchronized source or transmitter, is obtained either by means of the Adaptive mechanism or the time stamping mechanism, both described in the existing standard for ATM Adaption layer used for circuit emulation (AAL1 in 1363.1).
SUMMARY
It is an object of the present invention to provide a device and a method, which accomplish a less complicated and less costly timing regeneration at the interface between a switched packed network, in particular an ATM network, and a synchronized network.
This object is obtained by means of providing a clock signal at said interface directly from the synchronized network. Thus, the synchronization is maintained. This is obtained in the following manner.
The clock of a synchronized master unit is recovered by a slave unit, e.g. by means of the adaptive mechanism. The slave unit uses the recovered clock for transmission over the packet switched network. The depacketizing at the master side of the system is then performed using a clock signal provided directly from the synchronized network, i.e. without recovering the clock by means of the adaptive mechanism or the like.
Thus, the regenerated user data received from the user terminal is recovered using the transmitting clocking by means of a method closing the time loop at the interface to a synchronized network when the user data is transmitted over an asynchronous packet o network to a terminal entity and new data is returned in a synchronous fashion and transmitted back to said interface where timing and data are merged together. Thereby, the method is offering an interface to the synchronized network that is fully in compliance with existing synchronous interfaces, by providing a network interface that is closing the time loop locally and merging it with the user data from the s external terminal entity.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will now be described in greater detail by way of a non-limiting embodiment with reference to the accompanying drawings, in which:
- Fig. 1 is a block diagram illustrating a transmission path over an ATM network. o - Figs. 2a - b are schematic views of AAL units.
DETAILED DESCRIPTION
Fig. 1 is a block diagram illustrating a transmission path using an ATM-network. In the diagram a terminal unit 1 wishes to access a synchronized network 3, which for instance can be the Public Switched Telephone Network (PSTN). The access path in 5 this case consists of an ATM (Asynchronous Transfer Mode) network 5.
The terminal unit 1 is in this case assumed to be a synchronized user, such as a telephone. The terminal unit must hence have access to a synchronization or clock signal. This signal can be provided in two different manners according to the ATM standard for circuit emulation (AAL1 in 1.363.1).
0 - By means of the adaptive mechanism.
- By means of time stamping.
Thus, the duplex communication path between the terminal unit 1 and the synchronized network 3 goes from the synchronized network 3, which is the master
of the system illustrated in fig. 1 , to an ATM Adaption Layer (AAL) unit 7, in which data originating from the synchronized network 3 are packetized into ATM cells. In addition of the data the AAL unit 7 receives a clock signal from the synchronized network 3. The data are supplied on a data transmission line 9 and the clock signal is supplied on a clock signal line 11. On their path from the synchronized network 3 to the AAL unit 7 the clock signal and the data signal cross a G.703 interface 13, described in the corresponding standard.
The AAL unit 7 puts the ATM cells on the ATM network 5, which transfers the cells to the receiving end of the network, which in this example is the AAL unit 15. The AAL unit 15 depacketizes the cells which arrive via the ATM network 5.
Furthermore, the AAL unit 15 needs to regenerate the data transmission rate in order to synchronize the terminal unit 1 , which is the slave in this system, with the synchronized network 3. This is done by means of the adaptive mechanism, which does not require a separate transmission line for obtaining the synchronization.
The data depacketized by the AAL unit 15 along with the regenerated (recovered) clock signal are then transmitted on a data line 17 and a clock line 19 via a G.703 interface 21 to the terminal unit 1. Thus, the terminal unit receives transmitted data and a synchronization signal.
When the terminal unit 1 sends data in the other direction it transmits data on the data line 23 via the G.703 interface 21 to the AAL unit 25. The terminal unit 1 will send its data using a clock that is fully synchronized with the incoming clock, which is provided by the AAL unit 15 by means of the adaptive mechanism. The outgoing timing will therefore be a mirrored representation of the timing received from AAL unit 15 on line 19. The timing signal is transmitted via a clock line 27 also passing the G.703 interface 21. This procedure is fully in line with existing units for synchronous operation.
Then the ATM network 5 transfers the cells to the intended receiver, in this case the synchronized network 3. At the receiving end there is an AAL 29, which depacketizes the cells arriving via the ATM network 5. In order to synchronize the data contained in the arriving cells the AAL 29 needs access to a synchronization signal. This signal can be obtained in the same manner as at the terminal unit end, i.e. by means of the adaptive mechanism.
However, since the terminal unit is a slave in the master/slave relationship between the synchronized network 3 and the terminal unit 1 , the terminal unit 1 will be
synchronized by the synchronized network. Therefore, the AAL 29 can use the synchronization or clock signal provided to the AAL 7. This is illustrated in the figure by the dotted line 31.
This type of timing scheme is possible, since the AAL unit 29 can presume that the ε timing of incoming data from the terminal unit 1 is the same as the timing of the data transmitted from the synchronized network. Thus, the G.703 interface is not altered, but remains bidirectional. The AAL unit 29 therefore can transmit data on a line 33, which is synchronized by the clock signal on line 35, with the synchronized network 3.
o In fig. 2a the packetizing of ATM cells is illustrated. The figure shows data arriving on a line 201 and a clock signal arriving on a line 203. The signals pass the G.703 interface 205 to a physical layer terminator block 207. In the block 207 the data are packetized into cells, which are transferred to a buffer 209 on the line 211. The block 207 also provides the buffer 209 with a clock signal on a line 213. The buffer 209 s then puts the cells on the ATM network 215 at the correct times.
Fig. 2b illustrates the depacketizing of ATM cells at the master side of the transmission system shown in Fig. 1 , i.e. at the synchronized network side. In Fig. 2b cells arrive from the ATM network 221 to the ATM cell buffer 223, which buffers the arrived cells and places out-of-order arrived cells in order. Further the buffer 223 0 depacketizes the cells and the data contained in the cells are put onto the synchronized network 225, via the G.703 interface 227.
In order to synchronize the data stream from the ATM cell buffer 223 a synchronization or clock signal must be provided. A clock signal is therefore connected to the buffer 223, which clock signal comes directly from the synchronized 5 network 225 via the G.703 interface 227 on the line 229.
The data is then put onto the synchronized network 225 in a synchronous manner via the data line 233 and the clock line 231.
By using the synchronization scheme described by means of an example above, it will be possible to fully compensate for the large cell delay variation, which is generated 0 by an ATM or another switched packet network, already in the AAL receiver 29 of Fig. 1. This makes it possible to compensate for the phase difference, which remains at this interface if the clocking is regenerated by means of the adaptive mechanism.
By providing the synchronization or clock signal directly from the synchronized network to the ATM buffer the time loop of the system becomes simplified. The scheme described above, however, requires that the timing (clock) recovering at the slave, i.e. the AAL by the terminal unit in the example given above, end is in function, since a malfunction thereof would result in too large deviations in arrivals of cells for the depacketizing ATM cell buffer at the master, i.e the synchronized network in the example above, side of the system to handle.
Thus, a clock scheme, which simplifies the clock mechanism when an ATM network is used as an access network between to units configured in a master - slave relationship has been described.
This is obtained with a system and a method for facilitating the synchronization management in a system comprising a synchronized master and a slave unit communicating over a packed switched network, in particular an ATM network. The clock of a synchronized master unit is recovered by the slave unit, e.g. by means of the adaptive mechanism. The slave unit uses the recovered clock for transmission over the packet switched network. The depacketizing at the master side of the system is then performed using a clock signal provided directly from the synchronized network, i.e. without recovering the clock by means of the adaptive mechanism or the like.
Claims (5)
-
- CLAIMS 1. A method of generating a synchronized clock signal at the receiving part at an interface between a synchronized network and a packet switched network, where the packet switched network is used to access the synchronized network from a terminal 5 unit, the terminal unit regenerates the clock from the synchronized network for receiving data over the switched packet network, characterized in that the receiving part located at the switched packet network - synchronized network interface uses a clock signal derived directly from the synchronized network for synchronizing the data from the switched packet network to the synchronized network.io 2. A method according to claim 1, characterized in that the switched packet network is an ATM (Asynchronous Transfer Mode) network and/or that the synchronized network is a PSTN (Public Switched Telephone Network).
- 3. A transmission system comprising of a synchronized network, a terminal unit, a packet switched network interconnecting the synchronized network and the terminal ie unit, means for synchronizing the terminal unit to the synchronized network and means for synchronizing data from the packet switched network to the synchronized network, characterized in that the means for synchronizing the data from the packet switched network to the synchronized network comprises a clock signal derived directly from the synchronized network.
- 20 4. A transmission system according to claim 3, characterized in that the switched packet network is an ATM (Asynchronous Transfer Mode) network and/or that the synchronized network is a PSTN (Public Switched Telephone Network).
- 5. A method of closing the time loop at the interface to a synchronized network, where user data is transmitted over an asynchronous packet network to a terminal 25 entity and new data is returned in a synchronous fashion and transmitted back to said interface where timing and data is merged together, offering an interface to the synchronized network that is fully in compliance with existing synchronous interfaces, characterized in that the time loop is closed locally at the network interface and that the time loop is merged with the user data from the external terminal entity.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9600386A SE506080C2 (en) | 1996-02-02 | 1996-02-02 | Virtual time loop |
SE9600386 | 1996-02-02 | ||
PCT/SE1997/000151 WO1997028625A1 (en) | 1996-02-02 | 1997-01-31 | Virtual time loop |
Publications (2)
Publication Number | Publication Date |
---|---|
AU1680697A true AU1680697A (en) | 1997-08-22 |
AU722056B2 AU722056B2 (en) | 2000-07-20 |
Family
ID=20401245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU16806/97A Ceased AU722056B2 (en) | 1996-02-02 | 1997-01-31 | Virtual time loop |
Country Status (10)
Country | Link |
---|---|
US (1) | US6532243B1 (en) |
EP (1) | EP0878076B1 (en) |
JP (1) | JP2000504513A (en) |
CN (1) | CN1143479C (en) |
AU (1) | AU722056B2 (en) |
CA (1) | CA2245184A1 (en) |
DE (1) | DE69732832T2 (en) |
NO (1) | NO323652B1 (en) |
SE (1) | SE506080C2 (en) |
WO (1) | WO1997028625A1 (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6788703B2 (en) | 1998-12-30 | 2004-09-07 | Nortel Networks Limited | DS0 on ATM, mapping and handling |
US6778538B2 (en) | 1998-12-30 | 2004-08-17 | Nortel Networks Limited | Virtual junctors |
US6768736B1 (en) * | 1998-12-30 | 2004-07-27 | Nortel Networks Limited | Using an ATM switch to grow the capacity of a switching stage |
US6885661B1 (en) | 1998-12-30 | 2005-04-26 | Nortel Networks Limited | Private branch exchange built using an ATM Network |
US6804229B2 (en) | 1998-12-30 | 2004-10-12 | Nortel Networks Limited | Multiple node network architecture |
JP3660517B2 (en) * | 1999-03-01 | 2005-06-15 | 三菱電機株式会社 | DATA RECEIVING DEVICE, SOURCE CLOCK REPRODUCTION METHOD USED FOR THE SAME, AND COMPUTER-READABLE RECORDING MEDIUM RECORDING PROGRAM FOR CAUSING COMPUTER TO EXECUTE THE METHOD |
US7230974B1 (en) * | 1999-05-18 | 2007-06-12 | Polytechnic University | Methods and apparatus for synchronizing and/or determining the location of nodes |
US7286470B1 (en) * | 2000-08-25 | 2007-10-23 | Agere Systems Inc. | Messaging system for a packet transport system and method of operation thereof |
CN100409636C (en) * | 2001-04-12 | 2008-08-06 | 中兴通讯股份有限公司 | High-speed serial data communication self-adaptive clock configuration method |
FR2843509B1 (en) * | 2002-08-08 | 2005-01-28 | Metova | METHOD FOR SYNCHRONIZING THE LINE INTERFACE OF AN ASYNCHRONOUS TRANSMISSION NETWORK, LINE TERMINATION INTERFACE OF AN ASYNCHRONOUS TRANSMISSION NETWORK, AND TELECOMMUNICATION SYSTEM BETWEEN TWO TERMINATION INTERFACES |
JP4594935B2 (en) * | 2004-07-06 | 2010-12-08 | 株式会社アドバンテスト | Data transmission method and data transmission apparatus |
US7238287B2 (en) * | 2004-09-10 | 2007-07-03 | Natural Chemistry, Inc. | Method for providing safe, clean chlorinated recreational water |
FI119164B (en) | 2005-04-08 | 2008-08-15 | Tellabs Oy | Method and apparatus for regenerating a timing signal in digital communication |
CN1859063A (en) * | 2005-08-29 | 2006-11-08 | 华为技术有限公司 | Service data transmitting method and device |
Family Cites Families (22)
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NL189062C (en) * | 1980-02-15 | 1992-12-16 | Philips Nv | METHOD AND SYSTEM FOR TRANSFER OF DATA PACKAGES. |
DE3410188C2 (en) * | 1984-03-20 | 1986-10-23 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Method and circuit arrangement for clock correction in a digital data transmission device |
US4961188A (en) * | 1989-09-07 | 1990-10-02 | Bell Communications Research, Inc. | Synchronous frequency encoding technique for clock timing recovery in a broadband network |
US5007070A (en) * | 1989-10-31 | 1991-04-09 | Bell Communications Research, Inc. | Service clock recovery circuit |
IL96392A0 (en) * | 1989-11-29 | 1991-08-16 | Motorola Inc | Wireless in-building telecommunications system for voice and data communications |
US5206857A (en) * | 1991-04-29 | 1993-04-27 | At&T Bell Laboratories | Apparatus and method for timing distribution over an asynchronous ring |
US5373537A (en) * | 1991-09-02 | 1994-12-13 | Siemens Aktiengesellschaft | Method and apparatus for the synchronization of a clock means of a telecommunication switching system |
US5260978A (en) * | 1992-10-30 | 1993-11-09 | Bell Communications Research, Inc. | Synchronous residual time stamp for timing recovery in a broadband network |
JPH07264214A (en) | 1994-02-07 | 1995-10-13 | Fujitsu Ltd | Interface device |
US5459722A (en) * | 1994-06-30 | 1995-10-17 | At&T Ipm Corp. | Asynchronous transfer mode (ATM) transport of voice-band signals |
EP0718995A1 (en) * | 1994-12-20 | 1996-06-26 | International Business Machines Corporation | Apparatus and method for synchronizing clock signals for digital links in a packet switching mode |
US5828696A (en) * | 1995-03-30 | 1998-10-27 | Lucent Technologies Inc. | Timing recovery in a network-synchronized modem |
EP0855116A4 (en) * | 1995-10-12 | 2000-04-26 | Next Level Comm | Burst mode preamble |
GB9601348D0 (en) * | 1996-01-24 | 1996-03-27 | Madge Networks Ltd | Clock synchronisation |
US5666366A (en) * | 1996-05-24 | 1997-09-09 | National Semiconductor Corporation | Inter-base synchronization technique for a TDMA communication system |
US5892764A (en) * | 1996-09-16 | 1999-04-06 | Sphere Communications Inc. | ATM LAN telephone system |
US6160805A (en) * | 1996-09-30 | 2000-12-12 | Motorola, Inc. | Method for synchronizing a session timer |
KR100197898B1 (en) * | 1996-11-30 | 1999-06-15 | 김영환 | Voice telephone service in atm |
US6026086A (en) * | 1997-01-08 | 2000-02-15 | Motorola, Inc. | Apparatus, system and method for a unified circuit switched and packet-based communications system architecture with network interworking functionality |
US6072794A (en) * | 1997-04-24 | 2000-06-06 | Daewoo Telecom Co., Ltd. | Digital trunk interface unit for use in remote access system |
EP0876016B1 (en) * | 1997-05-02 | 2006-03-22 | Lsi Logic Corporation | Adaptive digital clock recovery |
US6111878A (en) * | 1997-11-04 | 2000-08-29 | Alcatel | Low jitter timing recovery technique and device for asynchronous transfer mode (ATM) constant bit rate (CBR) payloads |
-
1996
- 1996-02-02 SE SE9600386A patent/SE506080C2/en not_active IP Right Cessation
-
1997
- 1997-01-31 CN CNB971919925A patent/CN1143479C/en not_active Expired - Fee Related
- 1997-01-31 JP JP9527568A patent/JP2000504513A/en not_active Ceased
- 1997-01-31 WO PCT/SE1997/000151 patent/WO1997028625A1/en active IP Right Grant
- 1997-01-31 CA CA002245184A patent/CA2245184A1/en not_active Abandoned
- 1997-01-31 EP EP97902802A patent/EP0878076B1/en not_active Expired - Lifetime
- 1997-01-31 DE DE69732832T patent/DE69732832T2/en not_active Expired - Lifetime
- 1997-01-31 AU AU16806/97A patent/AU722056B2/en not_active Ceased
-
1998
- 1998-07-13 US US09/120,225 patent/US6532243B1/en not_active Expired - Lifetime
- 1998-07-31 NO NO19983522A patent/NO323652B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1143479C (en) | 2004-03-24 |
CA2245184A1 (en) | 1997-08-07 |
DE69732832T2 (en) | 2006-05-18 |
WO1997028625A1 (en) | 1997-08-07 |
SE9600386D0 (en) | 1996-02-02 |
NO983522L (en) | 1998-10-02 |
US6532243B1 (en) | 2003-03-11 |
DE69732832D1 (en) | 2005-04-28 |
NO323652B1 (en) | 2007-06-18 |
EP0878076A1 (en) | 1998-11-18 |
SE9600386L (en) | 1997-08-03 |
AU722056B2 (en) | 2000-07-20 |
JP2000504513A (en) | 2000-04-11 |
NO983522D0 (en) | 1998-07-31 |
CN1210641A (en) | 1999-03-10 |
EP0878076B1 (en) | 2005-03-23 |
SE506080C2 (en) | 1997-11-10 |
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Legal Events
Date | Code | Title | Description |
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FGA | Letters patent sealed or granted (standard patent) |