AU1448397A - Finite field multiplier circuit and use thereof in an error corrector decoder - Google Patents
Finite field multiplier circuit and use thereof in an error corrector decoderInfo
- Publication number
- AU1448397A AU1448397A AU14483/97A AU1448397A AU1448397A AU 1448397 A AU1448397 A AU 1448397A AU 14483/97 A AU14483/97 A AU 14483/97A AU 1448397 A AU1448397 A AU 1448397A AU 1448397 A AU1448397 A AU 1448397A
- Authority
- AU
- Australia
- Prior art keywords
- multiplier circuit
- base
- finite field
- ordinates
- dual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Algebra (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
Multiplications on a finite field of cardinal 2<m> may be achieved by means of a multiplier circuit including j shift registers (R0, ..., Rj-1) into which dual-base co-ordinates of one operand are initially loaded, j being an integer greater than 1 divisor of m. The other operand is expressed in standard base. The shift registers are linked to combinatorial logics arranged to deliver the dual-base co-ordinates of the product of the two operands in m/j clock cycles, with j co-ordinates being delivered in each cycle. Multiplication execution rates may thus be increased relative to previously known dual-base multipliers that required at least m clock cycles per operation. The multiplier circuit is particularly useful in BCH decoders.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9600797A FR2743909B1 (en) | 1996-01-24 | 1996-01-24 | MULTIPLIER CIRCUIT ON A WALL BODY AND APPLICATIONS OF SUCH A CIRCUIT IN AN ERROR CORRECTING DECODER |
| FR9600797 | 1996-01-24 | ||
| PCT/FR1997/000111 WO1997027535A1 (en) | 1996-01-24 | 1997-01-21 | Finite field multiplier circuit and use thereof in an error corrector decoder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU1448397A true AU1448397A (en) | 1997-08-20 |
Family
ID=9488415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU14483/97A Abandoned AU1448397A (en) | 1996-01-24 | 1997-01-21 | Finite field multiplier circuit and use thereof in an error corrector decoder |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0876645B1 (en) |
| JP (1) | JP2000504158A (en) |
| AT (1) | ATE186788T1 (en) |
| AU (1) | AU1448397A (en) |
| CA (1) | CA2244975A1 (en) |
| DE (1) | DE69700806D1 (en) |
| FR (1) | FR2743909B1 (en) |
| WO (1) | WO1997027535A1 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4875211A (en) * | 1986-12-10 | 1989-10-17 | Matsushita Electric Industrial Co., Ltd. | Galois field arithmetic logic unit |
-
1996
- 1996-01-24 FR FR9600797A patent/FR2743909B1/en not_active Expired - Fee Related
-
1997
- 1997-01-21 WO PCT/FR1997/000111 patent/WO1997027535A1/en active IP Right Grant
- 1997-01-21 CA CA002244975A patent/CA2244975A1/en not_active Abandoned
- 1997-01-21 AT AT97901129T patent/ATE186788T1/en not_active IP Right Cessation
- 1997-01-21 EP EP97901129A patent/EP0876645B1/en not_active Expired - Lifetime
- 1997-01-21 AU AU14483/97A patent/AU1448397A/en not_active Abandoned
- 1997-01-21 JP JP9526595A patent/JP2000504158A/en active Pending
- 1997-01-21 DE DE69700806T patent/DE69700806D1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0876645A1 (en) | 1998-11-11 |
| JP2000504158A (en) | 2000-04-04 |
| WO1997027535A1 (en) | 1997-07-31 |
| FR2743909A1 (en) | 1997-07-25 |
| CA2244975A1 (en) | 1997-07-31 |
| ATE186788T1 (en) | 1999-12-15 |
| EP0876645B1 (en) | 1999-11-17 |
| FR2743909B1 (en) | 1998-04-10 |
| DE69700806D1 (en) | 1999-12-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK5 | Application lapsed section 142(2)(e) - patent request and compl. specification not accepted |