ATE554443T1 - Anweisungsgesteuerte datenverarbeitungseinrichtung und -verfahren - Google Patents
Anweisungsgesteuerte datenverarbeitungseinrichtung und -verfahrenInfo
- Publication number
- ATE554443T1 ATE554443T1 AT04744376T AT04744376T ATE554443T1 AT E554443 T1 ATE554443 T1 AT E554443T1 AT 04744376 T AT04744376 T AT 04744376T AT 04744376 T AT04744376 T AT 04744376T AT E554443 T1 ATE554443 T1 AT E554443T1
- Authority
- AT
- Austria
- Prior art keywords
- instruction
- type
- instructions
- cycle
- execution
- Prior art date
Links
- 230000001419 dependent effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Power Sources (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03101877 | 2003-06-25 | ||
PCT/IB2004/050964 WO2004114128A2 (en) | 2003-06-25 | 2004-06-22 | Instruction controlled data processing device |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE554443T1 true ATE554443T1 (de) | 2012-05-15 |
Family
ID=33522407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT04744376T ATE554443T1 (de) | 2003-06-25 | 2004-06-22 | Anweisungsgesteuerte datenverarbeitungseinrichtung und -verfahren |
Country Status (6)
Country | Link |
---|---|
US (1) | US7861062B2 (de) |
EP (1) | EP1658559B1 (de) |
JP (1) | JP2007519052A (de) |
CN (1) | CN1809810B (de) |
AT (1) | ATE554443T1 (de) |
WO (1) | WO2004114128A2 (de) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
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US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US20060155843A1 (en) * | 2004-12-30 | 2006-07-13 | Glass Richard J | Information transportation scheme from high functionality probe to logic analyzer |
US7903560B2 (en) * | 2004-12-30 | 2011-03-08 | Intel Corporation | Correlation technique for determining relative times of arrival/departure of core input/output packets within a multiple link-based computing system |
EP1849095B1 (de) | 2005-02-07 | 2013-01-02 | Richter, Thomas | Vorrichtung zur verarbeitung massiver paralleldaten mit geringer latenz |
US7668193B2 (en) | 2005-09-02 | 2010-02-23 | Stmicroelectronics S.R.L. | Data processor unit for high-throughput wireless communications |
CN103646009B (zh) | 2006-04-12 | 2016-08-17 | 索夫特机械公司 | 对载明并行和依赖运算的指令矩阵进行处理的装置和方法 |
CN101627365B (zh) | 2006-11-14 | 2017-03-29 | 索夫特机械公司 | 多线程架构 |
US7818550B2 (en) * | 2007-07-23 | 2010-10-19 | International Business Machines Corporation | Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system |
JP2009048264A (ja) * | 2007-08-14 | 2009-03-05 | Oki Electric Ind Co Ltd | 半導体集積回路装置 |
EP2366144B1 (de) | 2008-10-15 | 2015-09-30 | Hyperion Core, Inc. | Sequentieller prozessor mit einem alu-array |
CN103250131B (zh) | 2010-09-17 | 2015-12-16 | 索夫特机械公司 | 包括用于早期远分支预测的影子缓存的单周期多分支预测 |
WO2012135050A2 (en) | 2011-03-25 | 2012-10-04 | Soft Machines, Inc. | Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines |
CN103547993B (zh) | 2011-03-25 | 2018-06-26 | 英特尔公司 | 通过使用由可分割引擎实例化的虚拟核来执行指令序列代码块 |
TWI518504B (zh) | 2011-03-25 | 2016-01-21 | 軟體機器公司 | 使用可分割引擎實體化的虛擬核心以支援程式碼區塊執行的暫存器檔案節段 |
CN103649931B (zh) | 2011-05-20 | 2016-10-12 | 索夫特机械公司 | 用于支持由多个引擎执行指令序列的互连结构 |
TWI603198B (zh) | 2011-05-20 | 2017-10-21 | 英特爾股份有限公司 | 以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行 |
EP2783281B1 (de) | 2011-11-22 | 2020-05-13 | Intel Corporation | Durch einen mikroprozessor beschleunigter code-optimierer |
WO2013077875A1 (en) | 2011-11-22 | 2013-05-30 | Soft Machines, Inc. | An accelerated code optimizer for a multiengine microprocessor |
JP2014164659A (ja) * | 2013-02-27 | 2014-09-08 | Renesas Electronics Corp | プロセッサ |
EP2775395B1 (de) | 2013-03-07 | 2020-11-25 | Nxp B.V. | Integrierte Schaltung, elektronische Vorrichtung und Anweisungsplanungsverfahren |
US9569216B2 (en) | 2013-03-15 | 2017-02-14 | Soft Machines, Inc. | Method for populating a source view data structure by using register template snapshots |
WO2014150806A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for populating register view data structure by using register template snapshots |
US10275255B2 (en) | 2013-03-15 | 2019-04-30 | Intel Corporation | Method for dependency broadcasting through a source organized source view data structure |
US10140138B2 (en) | 2013-03-15 | 2018-11-27 | Intel Corporation | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
US9891924B2 (en) | 2013-03-15 | 2018-02-13 | Intel Corporation | Method for implementing a reduced size register view data structure in a microprocessor |
US9811342B2 (en) | 2013-03-15 | 2017-11-07 | Intel Corporation | Method for performing dual dispatch of blocks and half blocks |
KR101708591B1 (ko) | 2013-03-15 | 2017-02-20 | 소프트 머신즈, 인크. | 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법 |
US9904625B2 (en) | 2013-03-15 | 2018-02-27 | Intel Corporation | Methods, systems and apparatus for predicting the way of a set associative cache |
EP2972836B1 (de) | 2013-03-15 | 2022-11-09 | Intel Corporation | Verfahren zur emulierung einer zentralisierten gast-flag-architektur mithilfe einer nativen verteilten flag-architektur |
WO2014150991A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for implementing a reduced size register view data structure in a microprocessor |
US9886279B2 (en) | 2013-03-15 | 2018-02-06 | Intel Corporation | Method for populating and instruction view data structure by using register template snapshots |
WO2014150971A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for dependency broadcasting through a block organized source view data structure |
US20150234449A1 (en) * | 2014-02-14 | 2015-08-20 | Qualcomm Incorporated | Fast power gating of vector processors |
CN104735824B (zh) * | 2015-02-28 | 2018-03-13 | 华为技术有限公司 | 数据处理*** |
CN105701041B (zh) * | 2016-01-11 | 2018-09-28 | 福州瑞芯微电子股份有限公司 | 芯片自适应调节读数时序路径的方法和装置 |
CN105677593B (zh) * | 2016-01-11 | 2018-09-28 | 福州瑞芯微电子股份有限公司 | 芯片存储器写操作时序路径自适应调节方法及装置 |
CN105752077B (zh) * | 2016-02-25 | 2018-03-06 | 上海科梁信息工程股份有限公司 | 混合动力车辆的扭矩分配方法及*** |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
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US5829031A (en) * | 1996-02-23 | 1998-10-27 | Advanced Micro Devices, Inc. | Microprocessor configured to detect a group of instructions and to perform a specific function upon detection |
WO1998006030A1 (en) * | 1996-08-07 | 1998-02-12 | Sun Microsystems | Multifunctional execution unit |
US6256745B1 (en) * | 1998-06-05 | 2001-07-03 | Intel Corporation | Processor having execution core sections operating at different clock rates |
US6367003B1 (en) * | 1998-03-04 | 2002-04-02 | Micron Technology, Inc. | Digital signal processor having enhanced utilization of multiply accumulate (MAC) stage and method |
US6418527B1 (en) * | 1998-10-13 | 2002-07-09 | Motorola, Inc. | Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods |
US6442701B1 (en) * | 1998-11-25 | 2002-08-27 | Texas Instruments Incorporated | Power saving by disabling memory block access for aligned NOP slots during fetch of multiple instruction words |
US6289465B1 (en) * | 1999-01-11 | 2001-09-11 | International Business Machines Corporation | System and method for power optimization in parallel units |
CN1146785C (zh) | 1999-03-31 | 2004-04-21 | 皇家菲利浦电子有限公司 | 并行数据处理 |
US6606700B1 (en) * | 2000-02-26 | 2003-08-12 | Qualcomm, Incorporated | DSP with dual-mac processor and dual-mac coprocessor |
US20040225868A1 (en) * | 2003-05-07 | 2004-11-11 | International Business Machines Corporation | An integrated circuit having parallel execution units with differing execution latencies |
-
2004
- 2004-06-22 CN CN2004800176588A patent/CN1809810B/zh not_active Expired - Lifetime
- 2004-06-22 US US10/561,454 patent/US7861062B2/en active Active
- 2004-06-22 JP JP2006516736A patent/JP2007519052A/ja not_active Withdrawn
- 2004-06-22 EP EP04744376A patent/EP1658559B1/de not_active Expired - Lifetime
- 2004-06-22 AT AT04744376T patent/ATE554443T1/de active
- 2004-06-22 WO PCT/IB2004/050964 patent/WO2004114128A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
JP2007519052A (ja) | 2007-07-12 |
WO2004114128A2 (en) | 2004-12-29 |
US7861062B2 (en) | 2010-12-28 |
CN1809810B (zh) | 2010-06-09 |
WO2004114128A3 (en) | 2006-03-09 |
EP1658559A2 (de) | 2006-05-24 |
CN1809810A (zh) | 2006-07-26 |
US20080133880A1 (en) | 2008-06-05 |
EP1658559B1 (de) | 2012-04-18 |
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