ATE500609T1 - Verfahren zur herstellung eines bipolartransistors - Google Patents
Verfahren zur herstellung eines bipolartransistorsInfo
- Publication number
- ATE500609T1 ATE500609T1 AT06728019T AT06728019T ATE500609T1 AT E500609 T1 ATE500609 T1 AT E500609T1 AT 06728019 T AT06728019 T AT 06728019T AT 06728019 T AT06728019 T AT 06728019T AT E500609 T1 ATE500609 T1 AT E500609T1
- Authority
- AT
- Austria
- Prior art keywords
- trench
- bipolar transistor
- region
- producing
- aligned
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05103583 | 2005-04-29 | ||
| PCT/IB2006/051262 WO2006117712A1 (en) | 2005-04-29 | 2006-04-24 | Method of fabricating a bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE500609T1 true ATE500609T1 (de) | 2011-03-15 |
Family
ID=36741404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT06728019T ATE500609T1 (de) | 2005-04-29 | 2006-04-24 | Verfahren zur herstellung eines bipolartransistors |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7605027B2 (de) |
| EP (1) | EP1878046B1 (de) |
| JP (1) | JP2008539579A (de) |
| CN (1) | CN100565822C (de) |
| AT (1) | ATE500609T1 (de) |
| DE (1) | DE602006020430D1 (de) |
| TW (1) | TWI376750B (de) |
| WO (1) | WO2006117712A1 (de) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009147559A1 (en) * | 2008-06-02 | 2009-12-10 | Nxp B.V. | Local buried layer forming method and semiconductor device having such a layer |
| US8020128B2 (en) * | 2009-06-29 | 2011-09-13 | International Business Machines Corporation | Scaling of bipolar transistors |
| CN101719508B (zh) * | 2009-11-10 | 2013-09-04 | 上海宏力半导体制造有限公司 | 一种薄soi纵向双极型晶体管及其制造方法 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4519128A (en) * | 1983-10-05 | 1985-05-28 | International Business Machines Corporation | Method of making a trench isolated device |
| US4887144A (en) * | 1985-07-26 | 1989-12-12 | Texas Instruments Incorporated | Topside substrate contact in a trenched semiconductor structure and method of fabrication |
| US5583368A (en) * | 1994-08-11 | 1996-12-10 | International Business Machines Corporation | Stacked devices |
| KR0171000B1 (ko) * | 1995-12-15 | 1999-02-01 | 양승택 | 자동 정의된 베이스 전극을 갖는 바이폴라 트랜지스터 구조 및 그 제조방법 |
| KR100382319B1 (ko) * | 1997-03-18 | 2003-05-01 | 텔레폰악티에볼라겟엘엠에릭슨(펍) | 트렌치 절연 바이폴라 장치 |
| US6521974B1 (en) * | 1999-10-14 | 2003-02-18 | Hitachi, Ltd. | Bipolar transistor and manufacturing method thereof |
| US6506657B1 (en) * | 2000-04-19 | 2003-01-14 | National Semiconductor Corporation | Process for forming damascene-type isolation structure for BJT device formed in trench |
| US20030082882A1 (en) * | 2001-10-31 | 2003-05-01 | Babcock Jeffrey A. | Control of dopant diffusion from buried layers in bipolar integrated circuits |
| US6759731B2 (en) * | 2002-06-05 | 2004-07-06 | United Microelectronics Corp. | Bipolar junction transistor and fabricating method |
| FR2845522A1 (fr) * | 2002-10-03 | 2004-04-09 | St Microelectronics Sa | Circuit integre a couche enterree fortement conductrice |
-
2006
- 2006-04-24 AT AT06728019T patent/ATE500609T1/de not_active IP Right Cessation
- 2006-04-24 WO PCT/IB2006/051262 patent/WO2006117712A1/en active Application Filing
- 2006-04-24 CN CNB2006800143210A patent/CN100565822C/zh not_active Expired - Fee Related
- 2006-04-24 DE DE602006020430T patent/DE602006020430D1/de active Active
- 2006-04-24 US US11/913,049 patent/US7605027B2/en not_active Expired - Fee Related
- 2006-04-24 JP JP2008508376A patent/JP2008539579A/ja not_active Withdrawn
- 2006-04-24 EP EP06728019A patent/EP1878046B1/de not_active Not-in-force
- 2006-04-26 TW TW095114928A patent/TWI376750B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US20080233688A1 (en) | 2008-09-25 |
| EP1878046B1 (de) | 2011-03-02 |
| DE602006020430D1 (de) | 2011-04-14 |
| JP2008539579A (ja) | 2008-11-13 |
| TW200644125A (en) | 2006-12-16 |
| CN100565822C (zh) | 2009-12-02 |
| US7605027B2 (en) | 2009-10-20 |
| WO2006117712A1 (en) | 2006-11-09 |
| EP1878046A1 (de) | 2008-01-16 |
| CN101180713A (zh) | 2008-05-14 |
| TWI376750B (en) | 2012-11-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |