ATE407403T1 - Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange - Google Patents

Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange

Info

Publication number
ATE407403T1
ATE407403T1 AT05802300T AT05802300T ATE407403T1 AT E407403 T1 ATE407403 T1 AT E407403T1 AT 05802300 T AT05802300 T AT 05802300T AT 05802300 T AT05802300 T AT 05802300T AT E407403 T1 ATE407403 T1 AT E407403T1
Authority
AT
Austria
Prior art keywords
forming
command
commands
dma
memory access
Prior art date
Application number
AT05802300T
Other languages
English (en)
Inventor
Michael Day
Charles Johns
Peichun Liu
Thuong Truong
Takeshi Yamazaki
Original Assignee
Sony Computer Entertainment Inc
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc, Ibm filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE407403T1 publication Critical patent/ATE407403T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Details Of Television Systems (AREA)
  • Communication Control (AREA)
AT05802300T 2004-07-15 2005-07-06 Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange ATE407403T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/891,772 US7243200B2 (en) 2004-07-15 2004-07-15 Establishing command order in an out of order DMA command queue

Publications (1)

Publication Number Publication Date
ATE407403T1 true ATE407403T1 (de) 2008-09-15

Family

ID=35478627

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05802300T ATE407403T1 (de) 2004-07-15 2005-07-06 Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange

Country Status (9)

Country Link
US (1) US7243200B2 (de)
EP (1) EP1711899B1 (de)
JP (1) JP4553936B2 (de)
KR (1) KR100827510B1 (de)
CN (1) CN100504827C (de)
AT (1) ATE407403T1 (de)
DE (1) DE602005009494D1 (de)
TW (1) TWI294573B (de)
WO (1) WO2006006084A2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060090015A1 (en) * 2004-10-26 2006-04-27 Bradfield Travis A Pipelined circuit for tag availability with multi-threaded direct memory access (DMA) activity
US20060129764A1 (en) * 2004-12-09 2006-06-15 International Business Machines Corporation Methods and apparatus for storing a command
US7774512B2 (en) * 2005-02-08 2010-08-10 Sony Computer Entertainment Inc. Methods and apparatus for hybrid DMA queue and DMA table
US7596670B2 (en) * 2005-11-30 2009-09-29 International Business Machines Corporation Restricting access to improve data availability
GB2433333B (en) 2005-12-13 2011-07-13 Advanced Risc Mach Ltd Distributed direct memory access provision within a data processing system
US8285923B2 (en) * 2008-12-08 2012-10-09 Western Digital Technologies, Inc. Disk drive and method using native command queuing tags to identify logical block size and implement protection information
US8627017B2 (en) * 2008-12-30 2014-01-07 Intel Corporation Read and write monitoring attributes in transactional memory (TM) systems
GB2469299B (en) * 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
US8316219B2 (en) 2009-08-31 2012-11-20 International Business Machines Corporation Synchronizing commands and dependencies in an asynchronous command queue
US9779057B2 (en) 2009-09-11 2017-10-03 Micron Technology, Inc. Autonomous memory architecture
US8631284B2 (en) * 2010-04-30 2014-01-14 Western Digital Technologies, Inc. Method for providing asynchronous event notification in systems
US8762682B1 (en) 2010-07-02 2014-06-24 Western Digital Technologies, Inc. Data storage apparatus providing host full duplex operations using half duplex storage devices
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US9858241B2 (en) * 2013-11-05 2018-01-02 Oracle International Corporation System and method for supporting optimized buffer utilization for packet processing in a networking device
JP5730733B2 (ja) * 2011-09-28 2015-06-10 京セラドキュメントソリューションズ株式会社 情報処理装置及び情報処理方法
US9348775B2 (en) 2012-03-16 2016-05-24 Analog Devices, Inc. Out-of-order execution of bus transactions
JP2013242766A (ja) * 2012-05-22 2013-12-05 Denso Corp リクエスト処理装置
US9288257B2 (en) * 2013-05-01 2016-03-15 International Business Machines Corporation Managing file transfer commands
US9779138B2 (en) 2013-08-13 2017-10-03 Micron Technology, Inc. Methods and systems for autonomous memory searching
US10003675B2 (en) 2013-12-02 2018-06-19 Micron Technology, Inc. Packet processor receiving packets containing instructions, data, and starting location and generating packets containing instructions and data
US20160092118A1 (en) * 2014-09-26 2016-03-31 Intel Corporation Memory write management in a computer system
US20160092123A1 (en) * 2014-09-26 2016-03-31 Pankaj Kumar Memory write management in a computer system
US10489158B2 (en) 2014-09-26 2019-11-26 Intel Corporation Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent stores
US9715464B2 (en) 2015-03-27 2017-07-25 Microsoft Technology Licensing, Llc Direct memory access descriptor processing
US9584378B1 (en) 2015-12-22 2017-02-28 International Business Machines Corporation Computer-implemented command control in information technology service environment
US10534540B2 (en) * 2016-06-06 2020-01-14 Micron Technology, Inc. Memory protocol
US10223307B2 (en) 2017-06-15 2019-03-05 International Business Machines Corporation Management of data transaction from I/O devices
KR102262209B1 (ko) * 2018-02-09 2021-06-09 한양대학교 산학협력단 더미 입출력 요청을 이용한 배리어 명령 전달 방법 및 그 장치
EP4081898A1 (de) * 2020-01-17 2022-11-02 Huawei Technologies Co., Ltd. System und verfahren zur optimierung von zeit-overhead in der multi-core-synchronisierung
CN111522511B (zh) * 2020-04-22 2022-04-22 杭州宏杉科技股份有限公司 命令处理方法及装置
US11579801B2 (en) * 2020-06-09 2023-02-14 Samsung Electronics Co., Ltd. Write ordering in SSDs
WO2023235003A1 (en) * 2022-06-02 2023-12-07 Micron Technology, Inc. Command fencing for memory-based communication queues

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4739472A (en) * 1984-12-07 1988-04-19 Nec Corporation Information processing device capable of rapidly processing instructions of different groups
US5481694A (en) * 1991-09-26 1996-01-02 Hewlett-Packard Company High performance multiple-unit electronic data storage system with checkpoint logs for rapid failure recovery
JPH05120242A (ja) * 1991-10-30 1993-05-18 Toshiba Corp データ処理装置
JP3276516B2 (ja) * 1994-09-13 2002-04-22 株式会社リコー 三次元形状生成装置
JPH10105347A (ja) * 1996-10-02 1998-04-24 Hitachi Ltd ディスクアレイ制御システム
US6088772A (en) * 1997-06-13 2000-07-11 Intel Corporation Method and apparatus for improving system performance when reordering commands
US6047334A (en) * 1997-06-17 2000-04-04 Intel Corporation System for delaying dequeue of commands received prior to fence command until commands received before fence command are ordered for execution in a fixed sequence
EP0889413A3 (de) * 1997-06-30 2002-03-27 Sun Microsystems, Inc. Vorrichtung und Verfahren um einen Personalrechner und einen Rechnerarbeitsplatzzu verbinden
US6038646A (en) * 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
JP2000040057A (ja) * 1998-07-23 2000-02-08 Nec Eng Ltd 計算機システム、バッファ制御装置及び転送方法
US6205494B1 (en) * 1998-12-18 2001-03-20 Western Digital Corporation Controller with automatic generation of linked list of data transfer descriptors for sequential commands, with linked list being used for execution of sequential data transfers
JP2002196975A (ja) * 1999-07-12 2002-07-12 Matsushita Electric Ind Co Ltd データ処理装置
US6513109B1 (en) * 1999-08-31 2003-01-28 International Business Machines Corporation Method and apparatus for implementing execution predicates in a computer processing system
JP2003519833A (ja) * 2000-01-03 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 依存性連鎖の発行および再発行が可能なスケジューラ
US6694427B1 (en) * 2000-04-20 2004-02-17 International Business Machines Corporation Method system and apparatus for instruction tracing with out of order processors
JP4546629B2 (ja) * 2000-05-25 2010-09-15 株式会社日立製作所 記憶システム、記憶システムの応答方法及び記録媒体
US6609192B1 (en) * 2000-06-06 2003-08-19 International Business Machines Corporation System and method for asynchronously overlapping storage barrier operations with old and new storage operations
US6594736B1 (en) * 2000-08-15 2003-07-15 Src Computers, Inc. System and method for semaphore and atomic operation management in a multiprocessor
JP2002140234A (ja) * 2000-11-02 2002-05-17 Hitachi Ltd キャッシュ装置
US7398376B2 (en) * 2001-03-23 2008-07-08 International Business Machines Corporation Instructions for ordering execution in pipelined processes
JP3402600B2 (ja) * 2001-12-03 2003-05-06 株式会社リコー 三次元形状生成装置
JP2004129129A (ja) * 2002-10-07 2004-04-22 Seiko Epson Corp 通信制御回路、通信制御装置、マイクロコンピュータ及び電子機器
US7421694B2 (en) * 2003-02-18 2008-09-02 Microsoft Corporation Systems and methods for enhancing performance of a coprocessor
US7073043B2 (en) * 2003-04-28 2006-07-04 International Business Machines Corporation Multiprocessor system supporting multiple outstanding TLBI operations per partition
US7200688B2 (en) * 2003-05-29 2007-04-03 International Business Machines Corporation System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command
US7480754B2 (en) * 2003-06-27 2009-01-20 Seagate Technology, Llc Assignment of queue execution modes using tag values
US7203811B2 (en) * 2003-07-31 2007-04-10 International Business Machines Corporation Non-fenced list DMA command mechanism
US7725618B2 (en) 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment

Also Published As

Publication number Publication date
JP2007529833A (ja) 2007-10-25
EP1711899B1 (de) 2008-09-03
WO2006006084A3 (en) 2006-07-20
US20060015652A1 (en) 2006-01-19
KR100827510B1 (ko) 2008-05-06
EP1711899A2 (de) 2006-10-18
US7243200B2 (en) 2007-07-10
WO2006006084A8 (en) 2006-04-20
JP4553936B2 (ja) 2010-09-29
DE602005009494D1 (de) 2008-10-16
TWI294573B (en) 2008-03-11
WO2006006084A2 (en) 2006-01-19
KR20060132856A (ko) 2006-12-22
TW200617680A (en) 2006-06-01
CN101031897A (zh) 2007-09-05
CN100504827C (zh) 2009-06-24

Similar Documents

Publication Publication Date Title
ATE407403T1 (de) Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange
JP4678623B2 (ja) 非対称型異種混合マルチプロセッサ環境（ａｓｙｍｍｅｔｒｉｃ ｈｅｔｅｒｏｇｅｎｅｏｕｓ ｍｕｌｔｉｐｒｏｃｅｓｓｏｒ ｅｎｖｉｒｏｎｍｅｎｔ）におけるメモリバリア要素（Ｐｒｉｍｉｔｉｖｅ）
GB2460841B (en) Methods of providing access to I/O devices
WO2010043706A3 (fr) Procede d'execution deterministe et de synchronisation d'un systeme de traitement de l'information comportant plusieurs coeurs de traitement executant des taches systemes
BRPI1001929A2 (pt) Execução atômica remota de manipulação adaptativa
EP3230861B1 (de) Technologien für schnelle synchronisationsbarrieren für mehrkernige verarbeitung
EP1732004A4 (de) Computersystem, server der dieses darstellt, dessen verfahren zur ausführungssteuerung von aufträgen und programm
CN105453043B (zh) 在不受i/o协议或目标设备支持时提供队列屏障
EP1892626A3 (de) Verfahren und Vorrichtung zur Verwaltung der Leistung der sequestrierten Partition eines Bearbeitungssystems
WO2008108129A1 (ja) メモリアクセス制御システム、メモリアクセス制御方法およびそのプログラム
IN2014DN06232A (de)
EP1594061A3 (de) Verfahren und Vorrichtungen zum Gruppieren und Verwalten von Speicheranweisungen
BRPI0916290A2 (pt) aeronave, processo de comando de uma aeronave, programa de computador, e, suporte de registro de dados.
JP2003037763A5 (de)
JP2017520058A5 (de)
WO2008003536A3 (en) Method, system and computer program for determining the processing order of a plurality of events
DE60210748D1 (de) System und Verfahren zum Verbinden von Rahmendaten durch das Einfügen von Bestimmungsfeldern in Steuerblöcke
CN105245372A (zh) 一种基于缓存和异步机制的加载网络资源的优化方法
TW200609830A (en) Adaptive scheduler using inherent knowledge of operating system subsystems for managing resources in a data processing system
ATE373845T1 (de) Dmac-ausgabemechanismus über ein steaming-id- verfahren
TW200742970A (en) Virtual sleep method
TW200701198A (en) Method for executing scheduled record task
JP6138482B2 (ja) 組み込みシステム
SE0400090D0 (sv) Control system, method and computer program
EP3032407A3 (de) Vorrichtung und verfahren zum ausschliessen von schreibabhängigen lastwiedergaben durch kombinieren von speicherplatzzugriff in einem ausserordentlichen prozessor

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties