ATE187844T1 - Verfahren zur herstellung einer oxidschicht in der halbleitertechnik - Google Patents
Verfahren zur herstellung einer oxidschicht in der halbleitertechnikInfo
- Publication number
- ATE187844T1 ATE187844T1 AT95304917T AT95304917T ATE187844T1 AT E187844 T1 ATE187844 T1 AT E187844T1 AT 95304917 T AT95304917 T AT 95304917T AT 95304917 T AT95304917 T AT 95304917T AT E187844 T1 ATE187844 T1 AT E187844T1
- Authority
- AT
- Austria
- Prior art keywords
- layer
- semiconductor body
- oxide
- gate
- heavily
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 6
- 238000004519 manufacturing process Methods 0.000 title 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 4
- 229910052757 nitrogen Inorganic materials 0.000 abstract 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/280,416 US5498577A (en) | 1994-07-26 | 1994-07-26 | Method for fabricating thin oxides for a semiconductor technology |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE187844T1 true ATE187844T1 (de) | 2000-01-15 |
Family
ID=23072985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT95304917T ATE187844T1 (de) | 1994-07-26 | 1995-07-13 | Verfahren zur herstellung einer oxidschicht in der halbleitertechnik |
Country Status (5)
Country | Link |
---|---|
US (1) | US5498577A (de) |
EP (1) | EP0696051B1 (de) |
JP (2) | JPH08172138A (de) |
AT (1) | ATE187844T1 (de) |
DE (1) | DE69513899T2 (de) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0610643B1 (de) * | 1993-02-11 | 1997-09-10 | STMicroelectronics S.r.l. | EEPROM-Zelle und peripherer MOS-Transistor |
JP3305901B2 (ja) * | 1994-12-14 | 2002-07-24 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
US5869405A (en) | 1996-01-03 | 1999-02-09 | Micron Technology, Inc. | In situ rapid thermal etch and rapid thermal oxidation |
US5741737A (en) * | 1996-06-27 | 1998-04-21 | Cypress Semiconductor Corporation | MOS transistor with ramped gate oxide thickness and method for making same |
US6033943A (en) * | 1996-08-23 | 2000-03-07 | Advanced Micro Devices, Inc. | Dual gate oxide thickness integrated circuit and process for making same |
JP3593825B2 (ja) * | 1996-11-08 | 2004-11-24 | ソニー株式会社 | 半導体装置及びその製造方法、並びに固体撮像素子の製造方法 |
US6461984B1 (en) * | 1997-03-18 | 2002-10-08 | Korea Advanced Institute Of Science & Technology | Semiconductor device using N2O plasma oxide and a method of fabricating the same |
US5904542A (en) * | 1997-03-26 | 1999-05-18 | Advanced Micro Devices, Inc. | Performing a semiconductor fabrication sequence within a common chamber and without opening the chamber beginning with forming a field dielectric and concluding with a gate dielectric |
US5937308A (en) * | 1997-03-26 | 1999-08-10 | Advanced Micro Devices, Inc. | Semiconductor trench isolation structure formed substantially within a single chamber |
US5891793A (en) * | 1997-04-04 | 1999-04-06 | Advanced Micro Devices, Inc. | Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation |
US6051510A (en) * | 1997-05-02 | 2000-04-18 | Advanced Micro Devices, Inc. | Method of using a hard mask to grow dielectrics with varying characteristics |
US6037224A (en) * | 1997-05-02 | 2000-03-14 | Advanced Micro Devices, Inc. | Method for growing dual oxide thickness using nitrided oxides for oxidation suppression |
US6555484B1 (en) * | 1997-06-19 | 2003-04-29 | Cypress Semiconductor Corp. | Method for controlling the oxidation of implanted silicon |
US6100149A (en) * | 1997-07-01 | 2000-08-08 | Steag Rtp Systems | Method for rapid thermal processing (RTP) of silicon substrates |
US5935650A (en) * | 1997-10-17 | 1999-08-10 | Lerch; Wilfried | Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system |
US5918133A (en) * | 1997-12-18 | 1999-06-29 | Advanced Micro Devices | Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof |
US6146934A (en) * | 1997-12-19 | 2000-11-14 | Advanced Micro Devices, Inc. | Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof |
US6077751A (en) * | 1998-01-29 | 2000-06-20 | Steag Rtp Systems Gmbh | Method of rapid thermal processing (RTP) of ion implanted silicon |
US6221789B1 (en) * | 1998-07-29 | 2001-04-24 | Intel Corporation | Thin oxides of silicon |
US6235590B1 (en) | 1998-12-18 | 2001-05-22 | Lsi Logic Corporation | Fabrication of differential gate oxide thicknesses on a single integrated circuit chip |
KR100455737B1 (ko) | 1998-12-30 | 2005-04-19 | 주식회사 하이닉스반도체 | 반도체소자의게이트산화막형성방법 |
JP2000232222A (ja) | 1999-02-10 | 2000-08-22 | Nec Corp | 半導体装置の製造方法 |
US6110780A (en) * | 1999-04-01 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Using NO or N2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory |
US6284602B1 (en) * | 1999-09-20 | 2001-09-04 | Advanced Micro Devices, Inc. | Process to reduce post cycling program VT dispersion for NAND flash memory devices |
US6380033B1 (en) * | 1999-09-20 | 2002-04-30 | Advanced Micro Devices, Inc. | Process to improve read disturb for NAND flash memory devices |
US6407008B1 (en) | 2000-05-05 | 2002-06-18 | Integrated Device Technology, Inc. | Method of forming an oxide layer |
US6339001B1 (en) | 2000-06-16 | 2002-01-15 | International Business Machines Corporation | Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist |
US6261972B1 (en) * | 2000-11-06 | 2001-07-17 | Infineon Technologies Ag | Dual gate oxide process for uniform oxide thickness |
JP2003168796A (ja) * | 2001-11-30 | 2003-06-13 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
US6635584B2 (en) * | 2001-12-28 | 2003-10-21 | Texas Instruments Incorporated | Versatile system for forming uniform wafer surfaces |
US6821868B2 (en) * | 2002-12-27 | 2004-11-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming nitrogen enriched gate dielectric with low effective oxide thickness |
US9123572B2 (en) | 2004-05-06 | 2015-09-01 | Sidense Corporation | Anti-fuse memory cell |
KR101144218B1 (ko) * | 2004-05-06 | 2012-05-10 | 싸이던스 코포레이션 | 분리 채널 안티퓨즈 어레이 구조 |
US7879694B1 (en) | 2004-07-13 | 2011-02-01 | National Semiconductor Corporation | System and method for applying a pre-gate plasma etch in a semiconductor device manufacturing process |
KR100933835B1 (ko) * | 2007-11-12 | 2009-12-24 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
US20110147817A1 (en) * | 2009-12-17 | 2011-06-23 | Infineon Technologies Austria Ag | Semiconductor component having an oxide layer |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3945856A (en) * | 1974-07-15 | 1976-03-23 | Ibm Corporation | Method of ion implantation through an electrically insulative material |
US4329773A (en) * | 1980-12-10 | 1982-05-18 | International Business Machines Corp. | Method of making low leakage shallow junction IGFET devices |
JPS57128920A (en) * | 1981-02-03 | 1982-08-10 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS5963763A (ja) * | 1982-10-05 | 1984-04-11 | Fujitsu Ltd | 半導体装置の製造方法 |
US4567645A (en) * | 1983-09-16 | 1986-02-04 | International Business Machines Corporation | Method for forming a buried subcollector in a semiconductor substrate by ion implantation |
US4774197A (en) * | 1986-06-17 | 1988-09-27 | Advanced Micro Devices, Inc. | Method of improving silicon dioxide |
US4784975A (en) * | 1986-10-23 | 1988-11-15 | International Business Machines Corporation | Post-oxidation anneal of silicon dioxide |
US5225355A (en) * | 1988-02-26 | 1993-07-06 | Fujitsu Limited | Gettering treatment process |
US4894353A (en) * | 1988-04-29 | 1990-01-16 | Advanced Micro Devices, Inc. | Method of fabricating passivated tunnel oxide |
US5219774A (en) * | 1988-05-17 | 1993-06-15 | Xicor, Inc. | Deposited tunneling oxide |
US5215934A (en) * | 1989-12-21 | 1993-06-01 | Tzeng Jyh Cherng J | Process for reducing program disturbance in eeprom arrays |
US5057463A (en) * | 1990-02-28 | 1991-10-15 | Sgs-Thomson Microelectronics, Inc. | Thin oxide structure and method |
US5225361A (en) * | 1990-03-08 | 1993-07-06 | Matshshita Electronics Coropration | Non-volatile semiconductor memory device and a method for fabricating the same |
JPH0770629B2 (ja) * | 1990-03-20 | 1995-07-31 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
US5077230A (en) * | 1990-08-03 | 1991-12-31 | Intel Corporation | Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth |
JPH04148088A (ja) * | 1990-10-12 | 1992-05-21 | Daikin Ind Ltd | 密閉形圧縮機 |
KR940009597B1 (ko) * | 1991-08-22 | 1994-10-15 | 삼성전자 주식회사 | 반도체장치의 게이트산화막 형성법 |
US5316981A (en) * | 1992-10-09 | 1994-05-31 | Advanced Micro Devices, Inc. | Method for achieving a high quality thin oxide using a sacrificial oxide anneal |
US5362685A (en) * | 1992-10-29 | 1994-11-08 | Advanced Micro Devices, Inc. | Method for achieving a high quality thin oxide in integrated circuit devices |
US5296411A (en) * | 1993-04-28 | 1994-03-22 | Advanced Micro Devices, Inc. | Method for achieving an ultra-reliable thin oxide using a nitrogen anneal |
US5330920A (en) * | 1993-06-15 | 1994-07-19 | Digital Equipment Corporation | Method of controlling gate oxide thickness in the fabrication of semiconductor devices |
-
1994
- 1994-07-26 US US08/280,416 patent/US5498577A/en not_active Expired - Lifetime
-
1995
- 1995-07-13 DE DE69513899T patent/DE69513899T2/de not_active Expired - Lifetime
- 1995-07-13 EP EP95304917A patent/EP0696051B1/de not_active Expired - Lifetime
- 1995-07-13 AT AT95304917T patent/ATE187844T1/de not_active IP Right Cessation
- 1995-07-25 JP JP7189037A patent/JPH08172138A/ja active Pending
-
2007
- 2007-07-30 JP JP2007197305A patent/JP2008028403A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JP2008028403A (ja) | 2008-02-07 |
EP0696051B1 (de) | 1999-12-15 |
DE69513899D1 (de) | 2000-01-20 |
US5498577A (en) | 1996-03-12 |
EP0696051A1 (de) | 1996-02-07 |
JPH08172138A (ja) | 1996-07-02 |
DE69513899T2 (de) | 2000-06-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |