WO2024141108A1 - Current mirror circuit, protection circuit, bias circuit, and electronic device - Google Patents

Current mirror circuit, protection circuit, bias circuit, and electronic device Download PDF

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Publication number
WO2024141108A1
WO2024141108A1 PCT/CN2024/070234 CN2024070234W WO2024141108A1 WO 2024141108 A1 WO2024141108 A1 WO 2024141108A1 CN 2024070234 W CN2024070234 W CN 2024070234W WO 2024141108 A1 WO2024141108 A1 WO 2024141108A1
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transistor
current
circuit
branch
electrically connected
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PCT/CN2024/070234
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French (fr)
Chinese (zh)
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彭振飞
陆航
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尚睿微电子（上海）有限公司
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Publication of WO2024141108A1 publication Critical patent/WO2024141108A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc

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  • the present disclosure relates to, but is not limited to, the field of analog integrated circuit technology, and in particular to a current mirror circuit, a protection circuit, a bias circuit, and an electronic device.
  • the current mirror circuit is an important circuit module of the analog circuit. It is used to accurately copy the original current into one or more current paths, and provide accurate current proportional to the original current for the subsequent single or multiple circuit modules.
  • embodiments of the present disclosure provide a current mirror circuit, a protection circuit, a bias circuit and an electronic device.
  • the embodiment of the present disclosure provides a current mirror circuit, the current mirror circuit at least comprising a first branch, a second branch, a third branch, a control circuit and a current source;
  • the first end and the second end of the first branch are both electrically connected to the current source, and the first end of the first branch is electrically connected to the first end of the second branch and the first end of the third branch respectively;
  • the third end of the first branch, the third end of the second branch and the third end of the third branch are electrically connected to a power source respectively;
  • the second branch and the third branch operate in a linear region or a saturation region, so that a low resistance is seen from the third end of the second branch toward the current mirror circuit.
  • An embodiment of the present disclosure provides a protection circuit, which includes the above-mentioned current mirror circuit.
  • An embodiment of the present disclosure provides a radio frequency chip, wherein the radio frequency chip includes the above-mentioned current mirror circuit or protection circuit.
  • the embodiment of the present disclosure provides a bias circuit, wherein the bias circuit comprises the above-mentioned current mirror circuit and a bias crystal.
  • the output end of the second branch of the current mirror circuit is used to feed the bias transistor.
  • An embodiment of the present disclosure provides an electronic device, which includes the above-mentioned current mirror circuit or protection circuit or radio frequency chip.
  • the current mirror circuit, protection circuit, bias circuit and electronic device form two current mirrors through a first branch, a second branch and a third branch.
  • the voltage at the second end of the second branch is made the same as the voltage at the second end of the third branch through an operational amplifier circuit, so that the second branch and the third branch working in the linear region or the saturation region maintain the same state to achieve current mirror replication. Since the voltage at the second end of the second branch is the same as the voltage at the second end of the third branch, the current mirror current working in the linear region is not affected by the voltage, ensuring that the current mirror can be mirrored according to a preset ratio, so that the branch currents of the second branch and the third branch can both satisfy the mirror ratio relationship.
  • FIG1 is a structural schematic diagram 1 of a current mirror circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram showing the relationship between the critical temperature of the filter provided by an embodiment of the present disclosure and the ambient temperature.
  • the current mirror circuit can also be applied to the protection circuit.
  • Figure 5 is a structural schematic diagram of the protection circuit and the amplifier circuit provided in the embodiment of the present disclosure.
  • the protection circuit at least includes a filter analog circuit 501, a reference voltage circuit 502, a current mirror circuit 503 and a hysteresis circuit 504.
  • the embodiment of the present disclosure changes the current flowing through the filter and adjusts the power output of the power amplifier by comparing the filter voltage related to the filter temperature and the reference voltage related to the ambient temperature.
  • the present disclosure links the current and the filter temperature together based on the linear relationship between power and current, thereby realizing temperature monitoring of the filter and further protecting the filter.
  • the present disclosure directly samples the electrical signal and uses the resistance of the filter to indirectly monitor the filter temperature, thereby protecting the power module. There is no need to integrate a temperature detection element in the filter, which reduces the cost and the size of the filter.
  • the current mirror circuit 503 at least includes a control transistor MN1 , a first current source I LIMIT and a current mirror unit.
  • the magnitude of the second input current I M is determined by the output current I 3 of the third transistor MP3 and the second current source I QC , wherein the output current I 3 of the third transistor MP3 is proportional to the first input current I HBT , and the second current source I QC is a reference current that is not affected by temperature. Therefore, the magnitude of the second input current I M is related to the magnitude of the first input current I HBT .
  • the drain terminal of the fifth transistor MP5 outputs a reference voltage V REF through the voltage divider resistor R3 and the mirror current outputted from the drain terminal of the fifth transistor MP5 .
  • the reference voltage V REF changes with the ambient temperature.
  • the reference voltage V REF may be inversely proportional to the ambient temperature.
  • the current of the first transistor MP1 is limited to the current I limit output by the first current source I LIMIT , and the maximum value of the drain current I HBT of the second transistor MP2 after the second transistor MP2 mirrors the first transistor MP1 is limited to M*I limit , thereby limiting the current of the power amplifier, further limiting the output power of the power amplifier, thereby limiting the power of the filter, preventing the filter temperature from exceeding the critical temperature, and realizing the temperature adjustment of the filter.
  • the first end of the hysteresis transistor MN2 is electrically connected to the voltage divider resistor R3 and the hysteresis resistor R4, respectively, the other end of the hysteresis resistor R4 is grounded, the second end of the hysteresis transistor MN2 is grounded, and the third end of the hysteresis transistor MN2 is electrically connected to the comparison output end out1.
  • the first input current I HBT is used to feed the bias circuit 101 - 1 ; the power amplifier 10 is used to amplify the first input current I HBT and input the amplified first input current to the filter 30 .
  • a current that is linearly inversely proportional to the ambient temperature is obtained through the third current source I PTAT and the fourth current source IR , the current is converted through a current mirror formed by the fifth transistor MP5 and the sixth transistor MP6, and then the current is converted into a voltage through the voltage divider resistor R3 and the hysteresis resistor R4, thereby obtaining a reference voltage V REF for comparison with the filter thermal temperature, the reference voltage V REF changes with temperature, the reference voltage V REF is compared with the filter voltage V SNS through the comparator COMP, and the current I HBT of the power amplifier 10 is adjusted by controlling the transistor MN1.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
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  • Automation & Control Theory (AREA)
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  • Control Of Electrical Variables (AREA)

Abstract

A current mirror circuit, a protection circuit, a bias circuit, and an electronic device. The current mirror circuit comprises at least a first branch (101), a second branch (102), a third branch (103), a control circuit (105) and a current source (104), wherein a first end and a second end of the first branch (101) are both electrically connected to the current source (104), and the first end of the first branch (101) is separately electrically connected to a first end of the second branch (102) and a first end of the third branch (103); a second end of the second branch (102) and a second end of the third branch (103) are separately electrically connected to the control circuit (105); a third end of the first branch (101), a third end of the second branch (102) and a third end of the third branch (103) are separately electrically connected to a power source; and the second branch (102) and the third branch (103) operate in a linear region or a saturation region, such that the current mirror circuit is of a low resistance when viewed from the third end of the second branch (102).

Description

一种电流镜电路、保护电路、偏置电路及电子设备Current mirror circuit, protection circuit, bias circuit and electronic equipment
相关公开的交叉引用Cross-references to related publications
本公开基于公开号为202211740032.6、公开日为2022年12月31日、公开名称为“一种电流镜电路、保护电路、偏置电路及电子设备”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。This disclosure is based on the Chinese patent application with publication number 202211740032.6, publication date December 31, 2022, and publication name “A current mirror circuit, protection circuit, bias circuit and electronic device”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference.
技术领域Technical Field
本公开涉及但不限于模拟集成电路技术领域，尤其涉及一种电流镜电路、保护电路、偏置电路及电子设备。The present disclosure relates to, but is not limited to, the field of analog integrated circuit technology, and in particular to a current mirror circuit, a protection circuit, a bias circuit, and an electronic device.
背景技术Background technique
电流镜电路是模拟电路的重要电路模块，用于负载将原始的电流精确复制成一路或者多路电流，为后级的单个或者多个电路模块提供与原始电流成比例的精确电流。The current mirror circuit is an important circuit module of the analog circuit. It is used to accurately copy the original current into one or more current paths, and provide accurate current proportional to the original current for the subsequent single or multiple circuit modules.
目前，常规场效应晶体管电流镜电路工作在饱和区，双极晶体管电流镜工作在线性区，在一些应用中，从电流镜电路的输出端向上看需要看到一个低电阻，而工作在饱和区或放大区的电流镜电路看进去为高阻，不符合应用要求，需要进行转换。At present, conventional field effect transistor current mirror circuits operate in the saturation region, and bipolar transistor current mirror circuits operate in the linear region. In some applications, a low resistance needs to be seen when looking up from the output end of the current mirror circuit, while a current mirror circuit operating in the saturation region or amplification region appears as high resistance when looking inward, which does not meet the application requirements and needs to be converted.
因此，场效应晶体管电流镜电路需要工作在线性区，双极晶体管电流镜需要工作在饱和区，但是此时电流镜受电压影响较大，无法准确地实现电流镜的功能，因此，如何使场效应晶体管电流镜电路在线性区、双极晶体管电流镜需要工作在饱和区，也能精确的进行电流复制，是当前急需解决的问题。Therefore, the field effect transistor current mirror circuit needs to work in the linear region, and the bipolar transistor current mirror needs to work in the saturation region. However, at this time, the current mirror is greatly affected by the voltage and cannot accurately realize the function of the current mirror. Therefore, how to make the field effect transistor current mirror circuit work in the linear region and the bipolar transistor current mirror work in the saturation region and accurately replicate the current is a problem that needs to be solved urgently.
发明内容Summary of the invention
基于相关技术中的问题，本公开实施例提供一种电流镜电路、保护电路、偏置电路及电子设备。Based on the problems in the related art, embodiments of the present disclosure provide a current mirror circuit, a protection circuit, a bias circuit and an electronic device.
本公开实施例的技术方案是这样实现的：The technical solution of the embodiment of the present disclosure is implemented as follows:
本公开实施例提供一种电流镜电路，所述电流镜电路至少包括第一支路、第二支路、第三支路、控制电路和电流源；The embodiment of the present disclosure provides a current mirror circuit, the current mirror circuit at least comprising a first branch, a second branch, a third branch, a control circuit and a current source;
所述第一支路的第一端和第二端均与所述电流源电连接，所述第一支路的第一端分别与所述第二支路的第一端和所述第三支路的第一端电连接；The first end and the second end of the first branch are both electrically connected to the current source, and the first end of the first branch is electrically connected to the first end of the second branch and the first end of the third branch respectively;
所述第二支路的第二端和所述第三支路的第二端分别与所述控制电路电连接；The second end of the second branch and the second end of the third branch are electrically connected to the control circuit respectively;
所述第一支路的第三端、所述第二支路的第三端和所述第三支路的第三端分别与电源电连接；The third end of the first branch, the third end of the second branch and the third end of the third branch are electrically connected to a power source respectively;
所述第二支路和所述第三支路工作在线性区或饱和区，以使从所述第二支路的第三端看向所述电流镜电路为低阻。The second branch and the third branch operate in a linear region or a saturation region, so that a low resistance is seen from the third end of the second branch toward the current mirror circuit.
本公开实施例提供一种保护电路，所述保护电路包括上述电流镜电路。An embodiment of the present disclosure provides a protection circuit, which includes the above-mentioned current mirror circuit.
本公开实施例提供一种射频芯片，所述射频芯片包括上述电流镜电路或保护电路。An embodiment of the present disclosure provides a radio frequency chip, wherein the radio frequency chip includes the above-mentioned current mirror circuit or protection circuit.
本公开实施例提供一种偏置电路，所述偏置电路包括上述的电流镜电路及偏置晶 体管，所述电流镜电路的所述第二支路的输出端用于为所述偏置晶体管馈电。The embodiment of the present disclosure provides a bias circuit, wherein the bias circuit comprises the above-mentioned current mirror circuit and a bias crystal. The output end of the second branch of the current mirror circuit is used to feed the bias transistor.
本公开实施例提供一种电子设备，所述电子设备包括上述的电流镜电路或保护电路或射频芯片。An embodiment of the present disclosure provides an electronic device, which includes the above-mentioned current mirror circuit or protection circuit or radio frequency chip.
本公开实施例提供的电流镜电路、保护电路、偏置电路及电子设备，通过第一支路、第二支路和第三支路，形成两个电流镜，通过运放电路使第二支路的第二端的电压与第三支路的第二端的电压相同，以使得工作在线性区或饱和区的第二支路和第三支路保持相同的状态以达到电流镜像复制，且由于第二支路第二端电压与第三支路的第二端电压相同，使得在线性区工作的电流镜电流不受电压影响，保证了电流镜可以按照预设比例进行镜像，如此可以使得第二支路和第三支路的支路电流均满足镜像比例关系。The current mirror circuit, protection circuit, bias circuit and electronic device provided by the embodiments of the present disclosure form two current mirrors through a first branch, a second branch and a third branch. The voltage at the second end of the second branch is made the same as the voltage at the second end of the third branch through an operational amplifier circuit, so that the second branch and the third branch working in the linear region or the saturation region maintain the same state to achieve current mirror replication. Since the voltage at the second end of the second branch is the same as the voltage at the second end of the third branch, the current mirror current working in the linear region is not affected by the voltage, ensuring that the current mirror can be mirrored according to a preset ratio, so that the branch currents of the second branch and the third branch can both satisfy the mirror ratio relationship.
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，而非限制本公开。根据下面参考附图对示例性实施例的详细说明，本公开的其它特征及方面将变得清楚。It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例中所需要使用的附图进行说明。In order to more clearly illustrate the technical solution of the embodiments of the present disclosure, the drawings required to be used in the embodiments of the present disclosure will be described below.
此处的附图被并入说明书中并构成本说明书的一部分，这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.
图1是本公开实施例提供的电流镜电路的结构示意图一；FIG1 is a structural schematic diagram 1 of a current mirror circuit provided by an embodiment of the present disclosure;
图2是本公开实施例提供的电流镜电路的结构示意图二；FIG2 is a second structural schematic diagram of a current mirror circuit provided by an embodiment of the present disclosure;
图3是本公开实施例提供的电流镜电路的结构示意图三；FIG3 is a third structural diagram of a current mirror circuit provided by an embodiment of the present disclosure;
图4是本公开实施例提供的滤波器温度模拟电路的结构示意图；FIG4 is a schematic diagram of the structure of a filter temperature simulation circuit provided by an embodiment of the present disclosure;
图5是本公开实施例提供的保护电路及放大电路的结构示意图；FIG5 is a schematic diagram of the structure of a protection circuit and an amplifier circuit provided in an embodiment of the present disclosure;
图6是本公开实施例提供的滤波器的临界功率与环境温度的关系示意图；FIG6 is a schematic diagram showing the relationship between the critical power and the ambient temperature of the filter provided by an embodiment of the present disclosure;
图7是本公开实施例提供的滤波器的临界温度与环境温度的关系示意图。FIG. 7 is a schematic diagram showing the relationship between the critical temperature of the filter provided by an embodiment of the present disclosure and the ambient temperature.
具体实施方式Detailed ways
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，所描述的实施例不应视为对本公开的限制，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。除非另有定义，本公开实施例所使用的所有的技术和科学术语与属于本公开实施例的技术领域的技术人员通常理解的含义相同。本公开实施例所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. Unless otherwise defined, all technical and scientific terms used in the embodiments of the present disclosure have the same meaning as those commonly understood by those skilled in the art to which the embodiments of the present disclosure belong. The terms used in the embodiments of the present disclosure are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.
另外，为了更好地说明本公开，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本公开同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本公开的主旨。In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.
电流镜电路是模拟集成电路中最基本的单元，利用电流镜电路可以构成电流模式的 基本模块电路，如电流模式传输器、微分器、积分器等，也可以构成电流模式集成电路，如连续时间滤波器、A/D转换器等。The current mirror circuit is the most basic unit in analog integrated circuits. It can be used to form a current mode Basic module circuits, such as current-mode transmitters, differentiators, integrators, etc., can also constitute current-mode integrated circuits, such as continuous-time filters, A/D converters, etc.
在相关技术中，常规场效应晶体管电流镜工作在饱和区，双极晶体管电流镜工作在线性区，对一些应用来说，从电流镜输出端向上看需要看到一个低电阻，而工作在场效应晶体管电流镜饱和区或工作在双极晶体管电流镜线性区的电流镜看进去为高阻，因此本公开实施例令场效应晶体管电流镜工作在线性区，或者双极晶体管电流镜工作在饱和区。但是，此时电流镜电流受电压影响较大，并且有可能不同的晶体管处于不同工作状态，比如其中一个为线性区，另一个为饱和区，为了保证电流镜可以按照预设比例进行镜像，需要令不同的晶体管的漏极电压相同，才能保证电流镜电路的功能。In the related art, conventional field effect transistor current mirrors operate in the saturation region, and bipolar transistor current mirrors operate in the linear region. For some applications, a low resistance needs to be seen when looking upward from the output end of the current mirror, while a current mirror operating in the saturation region of the field effect transistor current mirror or in the linear region of the bipolar transistor current mirror is seen as a high resistance. Therefore, the disclosed embodiment enables the field effect transistor current mirror to operate in the linear region, or the bipolar transistor current mirror to operate in the saturation region. However, at this time, the current mirror current is greatly affected by the voltage, and it is possible that different transistors are in different working states, for example, one of them is in the linear region and the other is in the saturation region. In order to ensure that the current mirror can be mirrored according to a preset ratio, the drain voltages of different transistors need to be the same to ensure the function of the current mirror circuit.
请参阅图1，图1是本公开实施例提供的电流镜电路的结构示意图一。如图1所示，所述电流镜电路包括所述电流镜电路至少包括第一支路101、第二支路102、第三支路103、电流源104和控制电路105。其中，所述第一支路101的第一端和第二端均与所述电流源104电连接，所述第一支路101的第一端分别与所述第二支路102的第一端和所述第三支路103的第一端电连接。所述第二支路102的第二端和所述第三支路103的第二端分别与所述控制电路105电连接；所述第一支路101的第三端、所述第二支路102的第三端和所述第三支路103的第三端分别与电源VDD电连接；所述第二支路102和所述第三支路103工作在线性区或饱和区，以使从所述第二支路102的第三端看向所述电流镜电路为低阻。Please refer to FIG. 1, which is a schematic diagram of the structure of the current mirror circuit provided by the embodiment of the present disclosure. As shown in FIG. 1, the current mirror circuit includes the current mirror circuit at least including a first branch 101, a second branch 102, a third branch 103, a current source 104 and a control circuit 105. The first end and the second end of the first branch 101 are both electrically connected to the current source 104, and the first end of the first branch 101 is electrically connected to the first end of the second branch 102 and the first end of the third branch 103 respectively. The second end of the second branch 102 and the second end of the third branch 103 are electrically connected to the control circuit 105 respectively; the third end of the first branch 101, the third end of the second branch 102 and the third end of the third branch 103 are electrically connected to the power supply VDD respectively; the second branch 102 and the third branch 103 work in a linear region or a saturation region, so that the current mirror circuit is low-impedance when viewed from the third end of the second branch 102.
所述控制电路105，用于控制所述第二支路102的第二端的电压与所述第三支路103的第二端的电压相同，以使得工作在线性区或饱和区的所述第二支路102和所述第三支路103保持相同的状态以达到电流镜像复制。The control circuit 105 is used to control the voltage of the second end of the second branch 102 to be the same as the voltage of the second end of the third branch 103, so that the second branch 102 and the third branch 103 working in the linear region or the saturation region maintain the same state to achieve current mirror replication.
在一些实施例中，如图2所示，所述第一支路101至少包括第一晶体管MP1，第二支路102至少包括第二晶体管MP2，所述第三支路103至少包括第三晶体管MP3。所述第一晶体管MP1的第一端分别与所述第二晶体管MP2的第一端和所述第三晶体管MP3的第一端电连接；所述第一晶体管MP1的第三端、所述第二晶体管MP2的第三端和所述第三晶体管MP3的第三端分别与电源电连接。In some embodiments, as shown in Fig. 2, the first branch 101 includes at least a first transistor MP1, the second branch 102 includes at least a second transistor MP2, and the third branch 103 includes at least a third transistor MP3. The first end of the first transistor MP1 is electrically connected to the first end of the second transistor MP2 and the first end of the third transistor MP3 respectively; the third end of the first transistor MP1, the third end of the second transistor MP2, and the third end of the third transistor MP3 are electrically connected to a power supply respectively.
这里，第一端可以是指晶体管的栅极，第二端可以是指晶体管的漏极，第三端可以是指晶体管的源极。根据上述连接关系可知，所述第一晶体管MP1第一端与第三端之间的电压、所述第二晶体管MP2第一端与第三端之间的电压和所述第三晶体管MP3第一端与第三端之间的电压均相同，即第一晶体管MP1栅源之间的电压、所述第二晶体管MP2栅源之间的电压和所述第三晶体管MP3栅源之间的电压均相同。Here, the first terminal may refer to the gate of the transistor, the second terminal may refer to the drain of the transistor, and the third terminal may refer to the source of the transistor. According to the above connection relationship, the voltage between the first terminal and the third terminal of the first transistor MP1, the voltage between the first terminal and the third terminal of the second transistor MP2, and the voltage between the first terminal and the third terminal of the third transistor MP3 are all the same, that is, the voltage between the gate and source of the first transistor MP1, the voltage between the gate and source of the second transistor MP2, and the voltage between the gate and source of the third transistor MP3 are all the same.
在本公开实施例中，为了从所述第二支路的第三端看向所述电流镜电路为低阻，场效应晶体管电流镜电路需要工作在线性区，双极晶体管电流镜需要工作在饱和区。因此，当第一晶体管、第二晶体管和第三晶体管为场效应晶体管时，电流镜电路需要工作在线性区；当第一晶体管、第二晶体管和第三晶体管为双极晶体管时，电流镜电路需要工作在饱和区。下述实施例不再对晶体管的具体类型和工作状态进行描述。In the embodiment of the present disclosure, in order to make the current mirror circuit look low-resistance from the third end of the second branch, the field effect transistor current mirror circuit needs to operate in the linear region, and the bipolar transistor current mirror circuit needs to operate in the saturation region. Therefore, when the first transistor, the second transistor, and the third transistor are field effect transistors, the current mirror circuit needs to operate in the linear region; when the first transistor, the second transistor, and the third transistor are bipolar transistors, the current mirror circuit needs to operate in the saturation region. The following embodiments will no longer describe the specific types and operating states of the transistors.
在本公开实施例中，以场效应晶体管为例，为获得低阻抗电流镜，可以通过令电流镜电路的两个输出支路中的晶体管处于线性区，从而降低电流镜的阻抗，即令第二支路102、第三支路103中的晶体管处于线性区，对于第一支路101中的晶体管不作限制，也就是说，第一支路101中的晶体管可为任意工作状态的区域，而令第二支路102、第三支路103中的晶体管处于线性区，只需令其栅极电压与源级电压之间的压差减小。In the embodiments of the present disclosure, taking field effect transistors as an example, in order to obtain a low-impedance current mirror, the impedance of the current mirror can be reduced by placing the transistors in the two output branches of the current mirror circuit in a linear region, that is, placing the transistors in the second branch 102 and the third branch 103 in a linear region, and no restrictions are imposed on the transistors in the first branch 101, that is, the transistors in the first branch 101 can be in any operating state region, and placing the transistors in the second branch 102 and the third branch 103 in a linear region only requires reducing the voltage difference between their gate voltage and source voltage.
在本公开实施例中，如图2所示，电流源ILIMIT的一端接地，另一端与所述第一晶体管MP1的第二端电连接，用于为所述第一晶体管MP1的第二端提供输入电流，即第 一晶体管MP1的支路电流，另一端还与所述第一晶体管MP1的第一端电连接，第一晶体管MP1的第一端还分别与第二晶体管MP3的第一端和第三晶体管MP3的第一端电连接，因此，电流源ILIMIT还用于分别为所述第一晶体管MP1的第一端、所述第二晶体管MP2的第一端和所述第三晶体管MP3的第一端提供偏置电流。所述电流源ILIMIT的内阻相对负载阻抗很大，负载阻抗波动不会改变电流大小。In the embodiment of the present disclosure, as shown in FIG. 2 , one end of the current source I LIMIT is grounded, and the other end is electrically connected to the second end of the first transistor MP1, so as to provide an input current to the second end of the first transistor MP1. The branch current of the first transistor MP1, the other end is also electrically connected to the first end of the first transistor MP1, the first end of the first transistor MP1 is also electrically connected to the first end of the second transistor MP3 and the first end of the third transistor MP3, therefore, the current source I LIMIT is also used to provide bias current for the first end of the first transistor MP1, the first end of the second transistor MP2 and the first end of the third transistor MP3, respectively. The internal resistance of the current source I LIMIT is large relative to the load impedance, and the fluctuation of the load impedance will not change the current size.
这里，电流源ILIMIT与第一晶体管MP1的第一端和第二端电连接，在第一晶体管MP1的栅极和漏极之间产生偏置电压Vgate。Here, the current source I LIMIT is electrically connected to the first terminal and the second terminal of the first transistor MP1 , and generates a bias voltage Vgate between the gate and the drain of the first transistor MP1 .
在一些实施例中，第一晶体管MP1、第二晶体管MP2和第三晶体管MP3的第一端均接入固定电压Vgate，使得第一晶体管MP1、第二晶体管MP2和第三晶体管MP3的栅极电压相同。In some embodiments, first terminals of the first transistor MP1 , the second transistor MP2 , and the third transistor MP3 are all connected to a fixed voltage Vgate, so that the gate voltages of the first transistor MP1 , the second transistor MP2 , and the third transistor MP3 are the same.
在一些实施例中，控制电路105至少包括运放电路OPAMP，运放电路OPAMP包括第一输入端VN、第二输入端VP和输出端Vout。In some embodiments, the control circuit 105 at least includes an operational amplifier circuit OPAMP, and the operational amplifier circuit OPAMP includes a first input terminal VN, a second input terminal VP, and an output terminal Vout.
在一些实施例中，如图3所示，所述第二晶体管MP2的第二端和所述第三晶体管MP3的第二端分别与所述运放电路OPAMP电连接，所述运放电路控制所述第二晶体管MP2的第二端电压与所述第三晶体管MP3的第二端电压相同，即第二晶体管MP2与所述第三晶体管MP3的漏极电压相同，基于第二晶体管MP2与所述第三晶体管MP3的栅极电压Vgate，使所述第二晶体管MP2和所述第三晶体管MP3均工作于线性区或饱和区。In some embodiments, as shown in FIG. 3 , the second end of the second transistor MP2 and the second end of the third transistor MP3 are electrically connected to the operational amplifier circuit OPAMP, respectively. The operational amplifier circuit controls the second end voltage of the second transistor MP2 to be the same as the second end voltage of the third transistor MP3, that is, the drain voltage of the second transistor MP2 is the same as the drain voltage of the third transistor MP3. Based on the gate voltage Vgate of the second transistor MP2 and the third transistor MP3, the second transistor MP2 and the third transistor MP3 both operate in a linear region or a saturation region.
且由于镜像电路中第一晶体管MP1、第二晶体管MP2和第三晶体管MP3的栅极电压相同，第一晶体管MP1、第二晶体管MP2和第三晶体管MP3的源极均与VDD连接，使得第一晶体管MP1、第二晶体管MP2和第三晶体管MP3的源极电压相同，通过运放电路使得第二晶体管MP2和第三晶体管MP3的漏极电压相同，使得第二晶体管MP2和第三晶体管MP3能够保持相同的状态。从而使得栅极相连的第一晶体管MP1、第二晶体管MP2和第三晶体管MP3，栅源之间的电压相同，第二晶体管MP2的漏极和第三晶体管MP3的漏极对第一晶体管MP1的漏极进行电流复制，以达到电流镜像复制。Since the gate voltages of the first transistor MP1, the second transistor MP2 and the third transistor MP3 in the mirror circuit are the same, the sources of the first transistor MP1, the second transistor MP2 and the third transistor MP3 are all connected to VDD, so that the source voltages of the first transistor MP1, the second transistor MP2 and the third transistor MP3 are the same, and the drain voltages of the second transistor MP2 and the third transistor MP3 are the same through the operational amplifier circuit, so that the second transistor MP2 and the third transistor MP3 can maintain the same state. Therefore, the gate-source voltages of the first transistor MP1, the second transistor MP2 and the third transistor MP3 connected to each other are the same, and the drain of the second transistor MP2 and the drain of the third transistor MP3 replicate the current of the drain of the first transistor MP1, so as to achieve current mirror replication.
在一些实施例中，第一晶体管MP1、第二晶体管MP2和第三晶体管MP3可以是PMOS型晶体管，也可以是NMOS型晶体管。In some embodiments, the first transistor MP1 , the second transistor MP2 , and the third transistor MP3 may be PMOS transistors or NMOS transistors.
在本公开实施例提供的电流镜电路中，令晶体管工作在线性区或者饱和区，实现小阻抗的电流镜电路。本公开电流镜电路中的晶体管可以在线性区或者饱和区工作，也可以在两个工作区间内进行摆动，例如当晶体管为MOS管时，MOS管的工作区可以从线性区跳转到饱和区，此时需要控制电路保证晶体管稳定在线性区或者饱和区工作。In the current mirror circuit provided by the embodiment of the present disclosure, the transistor is made to work in the linear region or the saturation region to realize a current mirror circuit with low impedance. The transistor in the current mirror circuit of the present disclosure can work in the linear region or the saturation region, or can swing between the two working regions. For example, when the transistor is a MOS tube, the working region of the MOS tube can jump from the linear region to the saturation region. At this time, a control circuit is required to ensure that the transistor works stably in the linear region or the saturation region.
在一些实施例中，所述第一晶体管MP1的第二端用于接收所述电流源ILIMIT的输入电流I1。所述第二晶体管MP2的第二端根据所述输入电流I1输出第一镜像电流I2，所述第三晶体管MP3的第二端根据所述输入电流I1输出第二镜像电流I3。In some embodiments, the second end of the first transistor MP1 is used to receive the input current I 1 of the current source I LIMIT . The second end of the second transistor MP2 outputs a first mirror current I 2 according to the input current I 1 , and the second end of the third transistor MP3 outputs a second mirror current I 3 according to the input current I 1 .
在一些实施例中，电流镜电路用于将输入电流转换成一个或多个相等或成倍数的镜像电流。所述第一镜像电流I2与所述输入电流I1成第一镜像比例，所述第二镜像电流I3与所述输入电流I1成第二镜像比例。镜像比例可以是1或1的倍数。所述镜像比例与所述第一晶体管MP1、第二晶体管MP2和第三晶体管MP3的尺寸比例相关，即与晶体管的沟道长度和沟道宽度之间的尺寸比例有关。当所有工艺参数都相等时，输入电流和镜像电流仅是两个晶体管沟道宽长比的函数。In some embodiments, the current mirror circuit is used to convert the input current into one or more equal or multiple mirror currents. The first mirror current I2 is in a first mirror ratio with the input current I1 , and the second mirror current I3 is in a second mirror ratio with the input current I1 . The mirror ratio can be 1 or a multiple of 1. The mirror ratio is related to the size ratio of the first transistor MP1, the second transistor MP2 and the third transistor MP3, that is, it is related to the size ratio between the channel length and the channel width of the transistor. When all process parameters are equal, the input current and the mirror current are only functions of the width-to-length ratio of the two transistor channels.
在一些实施例中，在电流源ILIMIT的输入电流I1流经所述第一晶体管MP1时，在所述第一晶体管MP1的第一端和第二端之间产生偏置电压Vgate，即在第一晶体管MP1的栅极和漏极之间产生偏置电压Vgate，通过该偏置电压对第二晶体管MP2和第三晶体 管MP3进行偏置，使得第二晶体管MP2和第三晶体管MP3处于线性区或饱和区。In some embodiments, when the input current I1 of the current source I LIMIT flows through the first transistor MP1, a bias voltage Vgate is generated between the first end and the second end of the first transistor MP1, that is, a bias voltage Vgate is generated between the gate and the drain of the first transistor MP1, and the second transistor MP2 and the third transistor MP3 are biased by the bias voltage. The transistor MP3 is biased so that the second transistor MP2 and the third transistor MP3 are in a linear region or a saturation region.
在一些实施例中，当MOS晶体管的栅极电压和阈值电压的差值被决定后，MOS晶体管漏极电流仅有由其宽长比决定。因此，一些实施例可以通过调节第二晶体管MP2和第三晶体管MP3的沟道宽长比，来控制第二晶体管MP2输出的第一镜像电流I2和第三晶体管MP3输出的第二镜像电流I3。In some embodiments, when the difference between the gate voltage and the threshold voltage of the MOS transistor is determined, the drain current of the MOS transistor is only determined by its width-to-length ratio. Therefore, some embodiments can control the first mirror current I2 output by the second transistor MP2 and the second mirror current I3 output by the third transistor MP3 by adjusting the channel width-to-length ratio of the second transistor MP2 and the third transistor MP3.
在一些实施例中，输入电流与镜像电流的比值通过公式(1)和(2)进行计算：

In some embodiments, the ratio of the input current to the mirror current is calculated by equations (1) and (2):

其中，H为第一镜像比例；S为第二镜像比例；IMP1是第一晶体管的支路电流；IMP2是第二晶体管的支路电流；IMP3是第三晶体管的支路电流；WMP1、WMP2和WMP3分别是第一晶体管、第二晶体管和第三晶体管的沟道宽度；LMP1、LMP2和LMP3分别是第一晶体管、第二晶体管和第三晶体管的沟道长度。Among them, H is the first mirror ratio; S is the second mirror ratio; I MP1 is the branch current of the first transistor; I MP2 is the branch current of the second transistor; I MP3 is the branch current of the third transistor; W MP1 , W MP2 and W MP3 are the channel widths of the first transistor, the second transistor and the third transistor respectively; L MP1 , L MP2 and L MP3 are the channel lengths of the first transistor, the second transistor and the third transistor respectively.
在一些实施例中，第二晶体管MP2和第三晶体管MP3可以是完全相同的晶体管，使得第二晶体管MP2和第三晶体管MP3的支路电流相同，即I2和I3相同。In some embodiments, the second transistor MP2 and the third transistor MP3 may be identical transistors, so that the branch currents of the second transistor MP2 and the third transistor MP3 are the same, that is, I 2 and I 3 are the same.
在一些实施例中，I1、I2和I3可以相等，即第一镜像比例和第二镜像比例为1，实现了电流复制。In some embodiments, I 1 , I 2 , and I 3 may be equal, that is, the first mirror ratio and the second mirror ratio are 1, thereby achieving current replication.
接下来请参照图3，本公开实施例提供的所述电流镜电路可以位于无线收发机***的保护电路中，电流镜电路可以与所述功率放大器PA连接，功率放大器PA的输出端与滤波器连接，滤波器图2未显示。所述电流镜电路通过所述第二晶体管MP2的第二端HBT与所述功率放大器连接，为所述功率放大器提供偏置电流，即第二晶体管MP2的第一镜像电流I1。Next, please refer to Figure 3. The current mirror circuit provided in the embodiment of the present disclosure may be located in the protection circuit of the wireless transceiver system. The current mirror circuit may be connected to the power amplifier PA. The output end of the power amplifier PA is connected to the filter, which is not shown in Figure 2. The current mirror circuit is connected to the power amplifier through the second end HBT of the second transistor MP2 to provide a bias current for the power amplifier, i.e., the first mirror current I1 of the second transistor MP2.
如图3所示，运放电路OPAMP包括第一输入端VN、第二输入端VP和输出端Vout；所述第二晶体管MP2的第二端与所述第一输入端VN电连接，所述第三晶体管MP3的第二端与所述第二输入端VP电连接，形成负反馈电路。所述负反馈电路使所述第二晶体管MP2的第二端的电压与所述第三晶体管MP3的第二端的电压相同，即A点与HBT输出端的电压相同。这样，可以保证第二晶体管MP2和第三晶体管MP3的漏极电压相同，即工作状态相同，进而令第二晶体管MP2和第三晶体管MP3所处的两个支路电流都满足镜像比例关系，从而能够实现电流的镜像复制，使得晶体管工作在线性区也能实现电流的成比例复制。As shown in FIG3 , the operational amplifier circuit OPAMP includes a first input terminal VN, a second input terminal VP and an output terminal Vout; the second terminal of the second transistor MP2 is electrically connected to the first input terminal VN, and the second terminal of the third transistor MP3 is electrically connected to the second input terminal VP, forming a negative feedback circuit. The negative feedback circuit makes the voltage of the second terminal of the second transistor MP2 the same as the voltage of the second terminal of the third transistor MP3, that is, the voltage of point A is the same as the output terminal of the HBT. In this way, it can be ensured that the drain voltages of the second transistor MP2 and the third transistor MP3 are the same, that is, the working states are the same, and then the two branch currents where the second transistor MP2 and the third transistor MP3 are located both meet the mirror proportional relationship, so that the mirror copy of the current can be realized, so that the transistor can also realize the proportional copy of the current when working in the linear region.
本公开实施例提供了MP1-MP2和MP1-MP3两个电流镜，通过运放电路(即运算放大器)的两个输入端保证MP2和MP3的漏极端电压相同。在一些实施例中还可以有三个电流镜或更多电流镜，此时可以采用多输入运算放大器的多个输入端来保证多个需要电流复制的晶体管的漏极电压相同，或者通过多个具有两个输入端的运算放大器来保证多个需要电流复制的晶体管的漏极电压相同，进而实现在线性区的晶体管也能准确进行电流复制的目的。The disclosed embodiment provides two current mirrors, MP1-MP2 and MP1-MP3, and ensures that the drain terminal voltages of MP2 and MP3 are the same through the two input terminals of the operational amplifier circuit (i.e., the operational amplifier). In some embodiments, there may be three or more current mirrors, in which case the multiple input terminals of the multi-input operational amplifier may be used to ensure that the drain voltages of multiple transistors that require current replication are the same, or multiple operational amplifiers with two input terminals may be used to ensure that the drain voltages of multiple transistors that require current replication are the same, thereby achieving the purpose of accurately replicating current in transistors in the linear region.
在一些实施例中，输出端Vout与其他模拟电路连接，本公开实施例未示出。In some embodiments, the output terminal Vout is connected to other analog circuits, which are not shown in the embodiments of the present disclosure.
在一些实施例中，运放电路OPAMP分别与第二晶体管MP2的第二端和所述第三晶体管MP3的第二端连接，以使电流镜电路可以按照预设比例进行镜像，使得电流镜电路中MP1的输入电流按照预设倍数放大，进而使得第二晶体管MP2和第三晶体管MP3输出放大后的镜像电流。In some embodiments, the operational amplifier circuit OPAMP is connected to the second end of the second transistor MP2 and the second end of the third transistor MP3, respectively, so that the current mirror circuit can be mirrored according to a preset ratio, so that the input current of MP1 in the current mirror circuit is amplified according to a preset multiple, and then the second transistor MP2 and the third transistor MP3 output the amplified mirror current.
本公开实施例中利用运放电路控制第二晶体管第二端的电压与第三晶体管第二端 的电压相同，使第二晶体管和第三晶体管工作在线性区或饱和区仍然能够很好的镜像电流。In the embodiment of the present disclosure, an operational amplifier circuit is used to control the voltage of the second end of the second transistor and the voltage of the second end of the third transistor. The voltage of the second transistor and the third transistor is the same, so that they can still mirror the current well when working in the linear region or the saturation region.
在一些实施例中，所述电流镜电路还包括控制晶体管MN1；所述控制晶体管MN1的第一端与控制电源VCOMP电连接，所述控制晶体管MN1的第二端接地，所述控制晶体管MN1的第三端与所述第一晶体管MP1的第二端连接。In some embodiments, the current mirror circuit further includes a control transistor MN1; a first terminal of the control transistor MN1 is electrically connected to a control power supply V COMP , a second terminal of the control transistor MN1 is grounded, and a third terminal of the control transistor MN1 is connected to a second terminal of the first transistor MP1.
在一些实施例中，所述控制晶体管MN1的第一端与控制电源VCOMP电连接，当控制电源VCOMP给控制晶体管MN1的第一端高电平时，Vgate电压较低，第一晶体管MP1、第二晶体管MP2和第三晶体管MP3均工作在线性区。当控制晶体管MN1的第一端电压转换为低电平，第一晶体管MP1的电流被限定在Ilimit(即电流源提供的电流内)，则第二晶体管MP2和第三晶体管MP3镜像后的电流输出最大值被限定在M*Ilimit。In some embodiments, the first terminal of the control transistor MN1 is electrically connected to the control power supply V COMP . When the control power supply V COMP provides a high level to the first terminal of the control transistor MN1, the Vgate voltage is low, and the first transistor MP1, the second transistor MP2, and the third transistor MP3 all operate in a linear region. When the voltage at the first terminal of the control transistor MN1 is converted to a low level, the current of the first transistor MP1 is limited to I limit (i.e., within the current provided by the current source), and the maximum current output of the second transistor MP2 and the third transistor MP3 after mirroring is limited to M*I limit .
在一些实施例中，控制电源VCOMP用于改变控制晶体管MN1的漏极电流，进而用于对所述第一晶体管MP1的第二端的输入电流进行调节，进而可以调节所述第二晶体管MP2输出的第一镜像电流和所述第三晶体管MP3输出的第二镜像电流。In some embodiments, the control power supply V COMP is used to change the drain current of the control transistor MN1, and further to adjust the input current of the second end of the first transistor MP1, and further to adjust the first mirror current output by the second transistor MP2 and the second mirror current output by the third transistor MP3.
在一些实施例中，本公开实施例提供的电流镜电路位于与功率放大器连接的保护电路中，保护电路和功率放大器通过HBT端口连接。In some embodiments, the current mirror circuit provided by the embodiments of the present disclosure is located in a protection circuit connected to a power amplifier, and the protection circuit and the power amplifier are connected through an HBT port.
传统的电流镜MOS管一般工作在饱和区，以减小漏极电压对电流复制的影响。而本公开实施例提供的电流镜电路，使得电流镜电路工作在了线性区，也能实现电流镜电路的精确放大。Conventional current mirror MOS tubes generally operate in a saturation region to reduce the influence of drain voltage on current replication. However, the current mirror circuit provided by the embodiment of the present disclosure enables the current mirror circuit to operate in a linear region and can also achieve accurate amplification of the current mirror circuit.
本公开实施例提供的电流镜电路中，第一晶体管MP1分别与第二晶体管MP2和第三晶体管MP3形成两个电流镜，从而控制第二晶体管MP2和第三晶体管MP3的输出电流，具体地通过控制晶体管MN1的控制端对电流进行调节。In the current mirror circuit provided by the embodiment of the present disclosure, the first transistor MP1 forms two current mirrors with the second transistor MP2 and the third transistor MP3 respectively, thereby controlling the output current of the second transistor MP2 and the third transistor MP3, specifically, adjusting the current by controlling the control terminal of the transistor MN1.
本公开实施例的电流镜电路可以工作在线性区，而相关技术中的常规电流镜工作在饱和区。对于功率放大器PA来说，从输出端HBT向上看需要看到一个低电阻，而工作在饱和区的电流镜看进去为高阻，因此本公开实施例令电流镜电路工作在线性区。但是在线性区工作的电流镜电流受电压影响较大，并且第二晶体管MP2和第三晶体管MP3有可能处于不同工作状态，其中一个为线性区，另一个为饱和区，为了保证电流镜可以按照预设比例进行镜像，需要令第二晶体管MP2和第三晶体管MP3的漏极端电压相同，才能保证其电流镜的功能。The current mirror circuit of the embodiment of the present disclosure can operate in the linear region, while the conventional current mirror in the related art operates in the saturation region. For the power amplifier PA, a low resistance needs to be seen when looking upward from the output terminal HBT, while the current mirror operating in the saturation region is seen as a high resistance, so the embodiment of the present disclosure allows the current mirror circuit to operate in the linear region. However, the current mirror current operating in the linear region is greatly affected by the voltage, and the second transistor MP2 and the third transistor MP3 may be in different working states, one of which is in the linear region and the other is in the saturation region. In order to ensure that the current mirror can be mirrored according to a preset ratio, the drain terminal voltages of the second transistor MP2 and the third transistor MP3 need to be the same to ensure the function of the current mirror.
因此，本公开实施例通过运放电路OPAMP保证运放两个输入端的电压相同，基通过电路OPAMP的负反馈保证第二晶体管MP2和第三晶体管MP3的漏极电压相同，即A点与HBT输出端电压相同。这样，可以保证第二晶体管MP2和第三晶体管MP3的漏极电压相同，从而使得工作状态相同，进而令第二晶体管MP2和第三晶体管MP3所处的两个支路电流都满足比例关系。Therefore, the embodiment of the present disclosure ensures that the voltages of the two input terminals of the operational amplifier are the same through the operational amplifier circuit OPAMP, and the drain voltages of the second transistor MP2 and the third transistor MP3 are the same through the negative feedback of the circuit OPAMP, that is, the voltage of the point A is the same as the output terminal of the HBT. In this way, the drain voltages of the second transistor MP2 and the third transistor MP3 can be ensured to be the same, so that the working states are the same, and then the two branch currents of the second transistor MP2 and the third transistor MP3 are both proportional.
本公开实施例通过一个负反馈运放电路，使得第二晶体管MP2和第三晶体管MP3的漏极电压相同，从而能够实现电流的镜像检测，使得晶体管工作在线性区也能形成电流的成比例复制。The embodiment of the present disclosure uses a negative feedback operational amplifier circuit to make the drain voltages of the second transistor MP2 and the third transistor MP3 the same, thereby enabling current mirror detection and enabling the transistors to form a proportional copy of the current even when operating in a linear region.
在一些实施例中，电流镜电路可以应用在滤波器温度模拟电路中，图4是本公开实施例提供的滤波器温度模拟电路的结构示意图，如图4所示，滤波器温度模拟电路包括电流模拟模块、热阻模拟模块和电流镜电路。In some embodiments, a current mirror circuit can be applied in a filter temperature simulation circuit. Figure 4 is a structural schematic diagram of a filter temperature simulation circuit provided in an embodiment of the present disclosure. As shown in Figure 4, the filter temperature simulation circuit includes a current simulation module, a thermal resistance simulation module and a current mirror circuit.
其中，电流模拟模块至少包括第三晶体管MP3和电流模块IQC。热阻模拟模块至少包括模拟电阻R1和模拟电阻R2。The current simulation module at least includes a third transistor MP3 and a current module I QC . The thermal resistance simulation module at least includes a simulation resistor R1 and a simulation resistor R2 .
所述第三晶体管MP3的第一端与所述电源VDD电连接，所述第一晶体管2的第二端分别与所述热阻模拟模块和所述电流模块IQC的正极电连接，所述电流模块的负极接 地。所述第三晶体管MP3的第三端与第一控制端口A电连接；其中，所述第一控制端口A用于为所述第三晶体管MP3的第三端提供电压或电流。The first end of the third transistor MP3 is electrically connected to the power supply VDD, the second end of the first transistor 2 is electrically connected to the positive electrode of the thermal resistance simulation module and the current module IQC respectively, and the negative electrode of the current module is electrically connected to the positive electrode of the thermal resistance simulation module and the current module IQC respectively. The third end of the third transistor MP3 is electrically connected to the first control port A; wherein the first control port A is used to provide a voltage or a current to the third end of the third transistor MP3.
在一些实施例中，晶体管的第一端为源极，第二端为漏极，第三端为栅极。电流模块可以是电流源，电流源的内阻相对负载阻抗很大，因此负载阻抗波动不会改变电流源提供的电流大小。In some embodiments, the first terminal of the transistor is a source, the second terminal is a drain, and the third terminal is a gate. The current module can be a current source, and the internal resistance of the current source is large relative to the load impedance, so the load impedance fluctuation will not change the current provided by the current source.
在一些实施例中，如图4所示，所述电流模拟模块还包括第四晶体管MP4。其中，所述第四晶体管MP4的第一端与所述第三晶体管MP3的第二端和所述电流模块IQC的正极电连接，所述第四晶体管MP4的第二端与所述热阻模拟模块电连接，所述第四晶体管MP4的第三端与第二控制端口B电连接，所述第二控制端口B用于为所述第四晶体管MP4的第三端提供电压。In some embodiments, as shown in FIG4 , the current simulation module further includes a fourth transistor MP4. The first end of the fourth transistor MP4 is electrically connected to the second end of the third transistor MP3 and the positive electrode of the current module I QC , the second end of the fourth transistor MP4 is electrically connected to the thermal resistance simulation module, and the third end of the fourth transistor MP4 is electrically connected to the second control port B, and the second control port B is used to provide a voltage to the third end of the fourth transistor MP4.
在一些实施例中，滤波器温度模拟电路通过电流镜电路与功率放大器401电连接，所述功率放大器401的输出端与滤波器402电连接，输入射频信号RFin经功率放大器401和滤波器402输出。In some embodiments, the filter temperature simulation circuit is electrically connected to the power amplifier 401 through a current mirror circuit, the output end of the power amplifier 401 is electrically connected to the filter 402, and the input radio frequency signal RFin is output through the power amplifier 401 and the filter 402.
所述功率放大器至少包括放大晶体管Q，所述电路还包括第二晶体管MP2。其中，所述第二晶体管MP2的第一端与电源VDD电连接，所述第二晶体管MP2的第二端与放大晶体管Q的第三端b(即基极)连接，所述第二晶体管MP2的第三端与所述第一控制端口A连接。需要说明的是，功率放大器也可以包括MOS管，此处不做限制。The power amplifier at least includes an amplifying transistor Q, and the circuit further includes a second transistor MP2. The first end of the second transistor MP2 is electrically connected to the power supply VDD, the second end of the second transistor MP2 is connected to the third end b (i.e., the base) of the amplifying transistor Q, and the third end of the second transistor MP2 is connected to the first control port A. It should be noted that the power amplifier may also include a MOS tube, which is not limited here.
在一些实施例中，所述第三晶体管MP3和第二晶体管MP2构成电流镜电流，因此，所述第三晶体管MP3第二端的输出电流I3与所述第二晶体管MP2第二端的输出电流IHBT(即第一镜像电流I2)成比例关系，且所述第二晶体管MP2第二端的输出电流IHBT(即I2)为所述放大晶体管Q的偏置电流。In some embodiments, the third transistor MP3 and the second transistor MP2 form a current mirror current, therefore, the output current I3 of the second end of the third transistor MP3 is proportional to the output current IHBT (i.e., the first mirror current I2 ) of the second end of the second transistor MP2, and the output current IHBT (i.e., I2 ) of the second end of the second transistor MP2 is the bias current of the amplifying transistor Q.
在一些实施例中，第三晶体管MP3和第二晶体管MP2相同时，所述第三晶体管MP3第二端的输出电流I3与所述第二晶体管MP2第二端的输出电流IHBT(即I2)相等。In some embodiments, when the third transistor MP3 and the second transistor MP2 are the same, the output current I 3 of the second terminal of the third transistor MP3 is equal to the output current I HBT (ie, I 2 ) of the second terminal of the second transistor MP2.
在一些实施例中，由于第三晶体管MP3第二端的输出电流I3与所述第二晶体管MP2第二端的输出电流IHBT(即I2)成比例关系或者相等，因此，所述第三晶体管MP3第二端的输出电流I3可以用于模拟所述放大晶体管Q的偏置电流，所述电流模块IQC的输出电流Ic可以用于模拟所述放大晶体管Q的静态电流。所述第四晶体管MP4的电流等于所述第三晶体管MP3的第二端的输出电流I3与所述电流模块IQC的输出电流Ic之间的差值，所述第四晶体管MP4的电流用于模拟所述滤波器电流，即功率放大器流入滤波器的电流。In some embodiments, since the output current I3 of the second end of the third transistor MP3 is proportional to or equal to the output current I HBT (i.e., I2 ) of the second end of the second transistor MP2, the output current I3 of the second end of the third transistor MP3 can be used to simulate the bias current of the amplifier transistor Q, and the output current Ic of the current module IQC can be used to simulate the static current of the amplifier transistor Q. The current of the fourth transistor MP4 is equal to the difference between the output current I3 of the second end of the third transistor MP3 and the output current Ic of the current module IQC , and the current of the fourth transistor MP4 is used to simulate the filter current, that is, the current flowing from the power amplifier to the filter.
在一些实施例中，如图4所示，滤波器402还与电源VCC连接，因此，电流模块IQC的输出电流Ic还可以用于模拟放大晶体管Q的静态电流与电源VCC的电流之间的差值。此时，第四晶体管MP4的电流用于模拟放大晶体管Q的输出电流(即放大晶体管Q的偏置电流与放大晶体管Q的静态电流之间的差值)与电源VCC电流之间的差值。In some embodiments, as shown in FIG4 , the filter 402 is also connected to the power supply VCC, so the output current Ic of the current module IQC can also be used to simulate the difference between the quiescent current of the amplifier transistor Q and the current of the power supply VCC. At this time, the current of the fourth transistor MP4 is used to simulate the difference between the output current of the amplifier transistor Q (i.e., the difference between the bias current of the amplifier transistor Q and the quiescent current of the amplifier transistor Q) and the current of the power supply VCC.
在一些实施例中，如图4所示，所述电路还包括热容模拟模块，所述热容模拟模块至少包括模拟电容C1，所述热阻模拟模块至少包括模拟电阻R1。所述模拟电阻R1一端与所述电流模拟模块连接，另一端与所述模拟电容C1连接；所述模拟电容C1的另一端接地；所述模拟电容C1与所述模拟电阻R1并联。In some embodiments, as shown in FIG4 , the circuit further includes a thermal capacitance simulation module, the thermal capacitance simulation module includes at least a simulation capacitor C1, and the thermal resistance simulation module includes at least a simulation resistor R1. One end of the simulation resistor R1 is connected to the current simulation module, and the other end is connected to the simulation capacitor C1; the other end of the simulation capacitor C1 is grounded; the simulation capacitor C1 is connected in parallel with the simulation resistor R1.
在本公开实施例中，在确定了滤波器电流之后，模拟电阻R1将电流转换为电压，可以得到滤波器温度相关的电压VSNS。In the embodiment of the present disclosure, after the filter current is determined, the analog resistor R1 converts the current into a voltage, and a voltage V SNS related to the filter temperature can be obtained.
在一些实施例中，所述模拟电容用于模拟所述滤波器的热容，滤波器的热容可以用于对信号进行滤波，使输出信号较为平滑，不会出现太大的波动；也可以用于模拟滤波器温度上升的延迟时间，功率增加导致温度增加是有时间的，时间是由热容决定的。 In some embodiments, the simulated capacitor is used to simulate the thermal capacitance of the filter. The thermal capacitance of the filter can be used to filter the signal to make the output signal smoother without too much fluctuation. It can also be used to simulate the delay time of the filter temperature rise. The increase in power leads to an increase in temperature over a period of time, and the time is determined by the thermal capacitance.
在一些实施例中，如图4所示，所述电路还包括运算放大器OPAMP，所述运算放大器OPAMP包括第一输入端1、第二输入端2和运放输出端Out1。所述第二晶体管MP2的第二端分别与所述运算放大器OPAMP的第一输入端1和功率放大器401电连接，所述运算放大器OPAMP的第二输入端2与所述第三晶体管MP3的第二端电连接，所述运算放大器OPAMP的运放输出端Out1与所述第二控制端口B(即第四晶体管MP4的第三端)电连接。In some embodiments, as shown in FIG4 , the circuit further includes an operational amplifier OPAMP, and the operational amplifier OPAMP includes a first input terminal 1, a second input terminal 2, and an operational amplifier output terminal Out1. The second terminal of the second transistor MP2 is electrically connected to the first input terminal 1 of the operational amplifier OPAMP and the power amplifier 401, respectively, the second input terminal 2 of the operational amplifier OPAMP is electrically connected to the second terminal of the third transistor MP3, and the operational amplifier output terminal Out1 of the operational amplifier OPAMP is electrically connected to the second control port B (i.e., the third terminal of the fourth transistor MP4).
在一些实施例中，如图4所示，所述电路还包括第一晶体管MP1、控制晶体管MN1和第一电流模块ILIMIT。其中，所述第一晶体管MP1的第一端与电源VDD电连接，所述第一晶体管MP1的第二端与所述控制晶体管MN1的第一端电连接，所述控制晶体管MN1的第二端接地，所述控制晶体管MN1的第三端与第三控制端口C连接，所述第三控制端口C用于为所述控制晶体管MN1的第三端提供电压。所述第一晶体管MP1的第三端分别与所述第一控制端口A(即第三晶体管MP3的第三端)和所述第二晶体管MP2的第三端电连接。所述第一电流模块ILIMIT的正极分别与所述第一晶体管MP1的第二端和第三端电连接，所述第一电流模块ILIMIT的负极接地。其中，第一晶体管MP1与第二晶体管MP2、第三晶体管MP3形成电流镜，以使第二晶体管MP2、第三晶体管MP3成比例复制第一晶体管MP1的电流；控制晶体管MN1用于调节第一晶体管MP1的电流，进而调节电流IHBT(即I2)与I3。In some embodiments, as shown in FIG4 , the circuit further includes a first transistor MP1, a control transistor MN1 and a first current module I LIMIT . The first end of the first transistor MP1 is electrically connected to a power supply VDD, the second end of the first transistor MP1 is electrically connected to the first end of the control transistor MN1, the second end of the control transistor MN1 is grounded, and the third end of the control transistor MN1 is connected to a third control port C, and the third control port C is used to provide a voltage to the third end of the control transistor MN1. The third end of the first transistor MP1 is electrically connected to the first control port A (i.e., the third end of the third transistor MP3) and the third end of the second transistor MP2, respectively. The positive electrode of the first current module I LIMIT is electrically connected to the second end and the third end of the first transistor MP1, respectively, and the negative electrode of the first current module I LIMIT is grounded. The first transistor MP1 forms a current mirror with the second transistor MP2 and the third transistor MP3 so that the second transistor MP2 and the third transistor MP3 proportionally replicate the current of the first transistor MP1. The control transistor MN1 is used to adjust the current of the first transistor MP1, thereby adjusting the currents I HBT (ie, I 2 ) and I 3 .
在一些实施例中，热阻模拟模块还包括模拟电阻R2。In some embodiments, the thermal resistance simulation module further includes a simulation resistor R2.
在一些实施例中，所述电路还包括基准电压模拟模块403和比较器COMP；所述比较器COMP包括第三输入端3、第四输入端4和比较输出端Out2。其中，所述比较器COMP的第三输入端3与所述热阻模拟模块R2电连接，第四输入端4与所述基准电压模拟模块403电连接，所述比较输出端Out2与所述第三控制端口C(即控制晶体管MN1)电连接。In some embodiments, the circuit further includes a reference voltage simulation module 403 and a comparator COMP; the comparator COMP includes a third input terminal 3, a fourth input terminal 4 and a comparison output terminal Out2. The third input terminal 3 of the comparator COMP is electrically connected to the thermal resistance simulation module R2, the fourth input terminal 4 is electrically connected to the reference voltage simulation module 403, and the comparison output terminal Out2 is electrically connected to the third control port C (i.e., the control transistor MN1).
在一些实施例中，所述基准电压模块403用于生成基准电压VREF，基准电压VREF是根据与温度成线性的电流进行转换得到的，用于与滤波器的热温度VSNS进行比较。In some embodiments, the reference voltage module 403 is used to generate a reference voltage V REF , where the reference voltage V REF is converted according to a current that is linear with temperature, and is used to compare with a thermal temperature V SNS of the filter.
在一些实施例中，电路还包括反相器Inverter，反相器与比较器COMP的比较输出端Out2电连接。In some embodiments, the circuit further includes an inverter, which is electrically connected to a comparison output terminal Out2 of the comparator COMP.
在本公开实施例中，当滤波器温度低时，第三晶体管MP3和第二晶体管MP2通过两个电流镜电路，放大第一晶体管MP1的电流，得到第三晶体管MP3的电流I3和第二晶体管MP2的电流IHBT(即I2)，此时，第三晶体管MP3的电流I3和第二晶体管MP2的电流IHBT(即I2)都较小，使得第四晶体管MP4的电流也较小，经过热阻模拟模块(即模拟电阻R2)输出与温度相关的电压VSNS至比较器COMP的第三输入端3，基准电压模拟模块403输出基准电压VREF至比较器COMP的第四输入端4，比较器COMP对VSNS和VREF进行比较。In the embodiment of the present disclosure, when the filter temperature is low, the third transistor MP3 and the second transistor MP2 amplify the current of the first transistor MP1 through two current mirror circuits to obtain the current I3 of the third transistor MP3 and the current I HBT of the second transistor MP2 (i.e., I 2 ). At this time, the current I 3 of the third transistor MP3 and the current I HBT of the second transistor MP2 (i.e., I 2 ) are both small, so that the current of the fourth transistor MP4 is also small. A temperature-related voltage V SNS is output to the third input terminal 3 of the comparator COMP through the thermal resistance simulation module (i.e., the simulation resistor R2), and the reference voltage simulation module 403 outputs the reference voltage V REF to the fourth input terminal 4 of the comparator COMP. The comparator COMP compares V SNS and V REF .
在一些实施例中，当滤波器温度比较低时，VSNS小于VREF，比较器COMP的比较输出端Out2输出低电平，经过反相器Inverter转换为高电平，控制晶体管MN1导通，第一晶体管MP1的电流增加，镜像放大第一晶体管MP1电流的第三晶体管MP3、第二晶体管MP2的电流也增加，滤波器温度会上升，进而导致热阻模拟模块输出的与温度相关的电压VSNS增加。当滤波器温度上升到一定温度时，VSNS大于VREF，比较器COMP的比较输出端Out2输出高电平，经过反相器Inverter转换为低电平，控制晶体管MN1截止，第二晶体管MP2的电流被限制，镜像放大第二晶体管MP2电流的第三晶体管MP3电流也被限制，以避免滤波器温度进一步升高，造成损坏。In some embodiments, when the filter temperature is relatively low, V SNS is less than V REF , the comparison output terminal Out2 of the comparator COMP outputs a low level, which is converted to a high level by the inverter Inverter, the control transistor MN1 is turned on, the current of the first transistor MP1 increases, and the currents of the third transistor MP3 and the second transistor MP2 that mirror and amplify the current of the first transistor MP1 also increase, and the filter temperature rises, thereby causing the temperature-related voltage V SNS output by the thermal resistance simulation module to increase. When the filter temperature rises to a certain temperature, VSNS is greater than V REF , the comparison output terminal Out2 of the comparator COMP outputs a high level, which is converted to a low level by the inverter Inverter, the control transistor MN1 is turned off, the current of the second transistor MP2 is limited, and the current of the third transistor MP3 that mirrors and amplifies the current of the second transistor MP2 is also limited, so as to prevent the filter temperature from further rising and causing damage.
在一些实施例中，所述电路还包括分压电阻R1；所述分压电阻R1一端与所述热阻 模拟模块(即模拟电阻R2)电连接，另一端接地，所述分压电阻R1与所述热阻模拟模块并联。所述分压电阻R1用于将电流转换为电压。In some embodiments, the circuit further includes a voltage-dividing resistor R1; one end of the voltage-dividing resistor R1 is connected to the thermal resistor The analog module (ie, the analog resistor R2) is electrically connected, and the other end is grounded, and the voltage divider resistor R1 is connected in parallel with the thermal resistance analog module. The voltage divider resistor R1 is used to convert current into voltage.
在一些实施例中，功率放大器至少包括偏置电路4011、放大晶体管Q、滤波电容C2和电感L1，其中，偏置电路4011分别与第二晶体管MP2的第二端、电源VDD和放大晶体管Q的第三端b(即基极)连接，射频输入信号RFin经滤波电容C2后，输入放大晶体管Q，经放大晶体管放大后输出至滤波器402滤波，滤波后输出RFout。放大晶体管Q的集电极还连接电感L1，电感L1避免将射频信号中的高次谐波泄露至电源VCC。In some embodiments, the power amplifier at least includes a bias circuit 4011, an amplifier transistor Q, a filter capacitor C2, and an inductor L1, wherein the bias circuit 4011 is respectively connected to the second end of the second transistor MP2, the power supply VDD, and the third end b (i.e., the base) of the amplifier transistor Q. The RF input signal RFin is input to the amplifier transistor Q after passing through the filter capacitor C2, and is output to the filter 402 for filtering after being amplified by the amplifier transistor, and is output RFout after filtering. The collector of the amplifier transistor Q is also connected to the inductor L1, and the inductor L1 prevents the high-order harmonics in the RF signal from leaking to the power supply VCC.
本公开实施例通过电流模拟模块模拟并输出所述滤波器的滤波器电流，通过热阻模拟模块和滤波器电流输出与滤波器温度相关的滤波器电压。如此，本公开实施例通过滤波器温度模拟电路模拟滤波器的电流和滤波器的热敏电阻和热敏电容等元器件，以模拟滤波器发热情况，从而得到与滤波器温相关的电信号，间接获得滤波器的温度，无需在滤波器中集成温度检测元件，既降低了成本，也减小了滤波器的尺寸。The disclosed embodiment simulates and outputs the filter current of the filter through the current simulation module, and outputs the filter voltage related to the filter temperature through the thermal resistance simulation module and the filter current. In this way, the disclosed embodiment simulates the filter current and the filter's thermistor, thermistor and thermistor capacitor and other components through the filter temperature simulation circuit to simulate the filter heating condition, thereby obtaining an electrical signal related to the filter temperature, and indirectly obtaining the filter temperature, without integrating a temperature detection element in the filter, which reduces both the cost and the size of the filter.
电流模拟模块用于模拟与Q连接的滤波器的电流。其中，第三晶体管MP3的电流用于模拟放大晶体管Q的偏置电流，IQC用于模拟放大晶体管Q的静态电流，从而使两者的差值第四晶体管MP4的电流可以模拟得到流经滤波器的电流。其中，IQC为不受温度影响的电流基准。The current simulation module is used to simulate the current of the filter connected to Q. Among them, the current of the third transistor MP3 is used to simulate the bias current of the amplifier transistor Q, and I QC is used to simulate the static current of the amplifier transistor Q, so that the difference between the two, the current of the fourth transistor MP4, can simulate the current flowing through the filter. Among them, I QC is a current reference that is not affected by temperature.
滤波器热阻模拟模块和热容模拟模块用于模拟滤波器的热阻和热容，进而通过模拟滤波器的电流、热阻、热容得到与滤波器的热温度相关的电压VSNS。从而实现通过电路模拟滤波器发热情况，从而间接获得滤波器温度的目的。The filter thermal resistance simulation module and thermal capacitance simulation module are used to simulate the thermal resistance and thermal capacitance of the filter, and then obtain the voltage V SNS related to the thermal temperature of the filter by simulating the current, thermal resistance and thermal capacitance of the filter. Thus, the purpose of indirectly obtaining the filter temperature is achieved by simulating the heating condition of the filter through the circuit.
滤波器温度模拟电路还包括电流镜电路，滤波器温度模拟电路通过电流镜电路与功率放大器401电连接，所述功率放大器401的输出端与滤波器402电连接，输入射频信号RFin经功率放大器401和滤波器402输出。The filter temperature simulation circuit also includes a current mirror circuit, which is electrically connected to the power amplifier 401 through the current mirror circuit. The output end of the power amplifier 401 is electrically connected to the filter 402, and the input radio frequency signal RFin is output through the power amplifier 401 and the filter 402.
在一些实施例中，电流镜电路还可以应用于保护电路中，图5是本公开实施例提供的保护电路及放大电路的结构示意图，保护电路至少包括滤波器模拟电路501、基准电压电路502、电流镜电路503和迟滞电路504。In some embodiments, the current mirror circuit can also be applied to the protection circuit. Figure 5 is a structural schematic diagram of the protection circuit and the amplifier circuit provided in the embodiment of the present disclosure. The protection circuit at least includes a filter analog circuit 501, a reference voltage circuit 502, a current mirror circuit 503 and a hysteresis circuit 504.
保护电路与功率放大器10电连接，功率放大器10与滤波器30电连接。保护电路至少包括滤波器模拟电路501、基准电压电路502、比较器COMP和电流镜电路503(即前述实施例中的电流镜电路)；比较器至少包括第一输入端1、第二输入端2和比较输出端out1。The protection circuit is electrically connected to the power amplifier 10, and the power amplifier 10 is electrically connected to the filter 30. The protection circuit at least includes a filter analog circuit 501, a reference voltage circuit 502, a comparator COMP and a current mirror circuit 503 (i.e., the current mirror circuit in the aforementioned embodiment); the comparator at least includes a first input terminal 1, a second input terminal 2 and a comparison output terminal out1.
在一些实施例中，滤波器模拟电路501与第一输入端1电连接，滤波器模拟电路501用于模拟滤波器30的电流，并输出与滤波器30温度相关的滤波器电压VSNS；基准电压电路502与第二输入端2电连接，基准电压电路502用于输出与环境温度相关的基准电压VREF；电流镜电路503分别与比较输出端out1、功率放大器10和滤波器模拟电路501电连接，电流镜电路503用于为功率放大器10提供第一输入电流IHBT，滤波器模拟电路501用于根据第一输入电流IHBT，获取用于模拟滤波器电流的第二输入电流IM；比较器COMP用于根据滤波器电压VSNS和基准电压VREF，控制电流镜电路503改变第一输入电流IHBT的大小，从而调节功率放大器的功率，以控制滤波器30的温度，其中，第二输入电流IM跟随IHBT变化。In some embodiments, the filter simulation circuit 501 is electrically connected to the first input terminal 1, and is used to simulate the current of the filter 30 and output a filter voltage V SNS related to the temperature of the filter 30; the reference voltage circuit 502 is electrically connected to the second input terminal 2, and is used to output a reference voltage V REF related to the ambient temperature; the current mirror circuit 503 is electrically connected to the comparison output terminal out1, the power amplifier 10 and the filter simulation circuit 501 respectively, and is used to provide a first input current I HBT for the power amplifier 10, and the filter simulation circuit 501 is used to obtain a second input current I M for simulating the filter current according to the first input current I HBT ; the comparator COMP is used to control the current mirror circuit 503 to change the size of the first input current I HBT according to the filter voltage V SNS and the reference voltage V REF , thereby adjusting the power of the power amplifier to control the temperature of the filter 30, wherein the second input current I M changes with I HBT .
在一些实施例中，滤波器模拟电路501具有临界温度；当滤波器模拟电路501的温度大于或等于临界温度时，电流镜电路用于限制第一输入电流IHBT和第二输入电流IM的电流值小于预设电流值，以限制功率放大器10和滤波器30的功率，以控制滤波器30的温度。 In some embodiments, the filter analog circuit 501 has a critical temperature; when the temperature of the filter analog circuit 501 is greater than or equal to the critical temperature, the current mirror circuit is used to limit the current values of the first input current I HBT and the second input current I M to be less than a preset current value to limit the power of the power amplifier 10 and the filter 30 to control the temperature of the filter 30.
在一些实施例中，当滤波器模拟电路501的温度大于或等于临界温度时，滤波器30电压大于基准电压。In some embodiments, when the temperature of the filter simulation circuit 501 is greater than or equal to a critical temperature, the voltage of the filter 30 is greater than a reference voltage.
本公开实施例通过对比与滤波器温度相关的滤波器电压和与环境温度相关的基准电压，改变流经滤波器的电流大小，调整功率放大器的功率输出，本公开根据功率和电流的线性关系，将电流和滤波器温度联系在一起，实现了对滤波器的温度监控，进而实现对滤波器的保护；且本公开直接对电信号进行采样，并利用滤波器的电阻间接监控滤波器温度，从而实现对功率模块进行保护，无需在滤波器中集成温度检测元件，既降低了成本，也减小了滤波器的尺寸。The embodiment of the present disclosure changes the current flowing through the filter and adjusts the power output of the power amplifier by comparing the filter voltage related to the filter temperature and the reference voltage related to the ambient temperature. The present disclosure links the current and the filter temperature together based on the linear relationship between power and current, thereby realizing temperature monitoring of the filter and further protecting the filter. The present disclosure directly samples the electrical signal and uses the resistance of the filter to indirectly monitor the filter temperature, thereby protecting the power module. There is no need to integrate a temperature detection element in the filter, which reduces the cost and the size of the filter.
接下来请继续参照图5，如图5所示，电流镜电路503至少包括控制晶体管MN1、第一电流源ILIMIT和电流镜单元。Next, please continue to refer to FIG. 5 . As shown in FIG. 5 , the current mirror circuit 503 at least includes a control transistor MN1 , a first current source I LIMIT and a current mirror unit.
在一些实施例中，电路还包括反相器inverter，反相器inverter分别与比较输出端out1和电流镜电路503电连接。In some embodiments, the circuit further includes an inverter, which is electrically connected to the comparison output terminal out1 and the current mirror circuit 503 respectively.
其中，控制晶体管MN1的第一端与电流镜单元电连接，控制晶体管MN1的第二端接地，控制晶体管MN1的第三端通过反相器与比较器COMP的输出端out1电连接，控制晶体管MN1用于调节第一输入电流IHBT的大小。第一电流源ILIMIT的正极分别与电流镜单元、控制晶体管MN1的第一端电连接，第一电流源ILIMIT的负极接地，第一电流源ILIMIT用于配合控制晶体管MN1调节第一输入电流IHBT和第二输入电流IM的大小。The first end of the control transistor MN1 is electrically connected to the current mirror unit, the second end of the control transistor MN1 is grounded, the third end of the control transistor MN1 is electrically connected to the output end out1 of the comparator COMP through an inverter, and the control transistor MN1 is used to adjust the magnitude of the first input current I HBT . The positive electrode of the first current source I LIMIT is electrically connected to the current mirror unit and the first end of the control transistor MN1 respectively, the negative electrode of the first current source I LIMIT is grounded, and the first current source I LIMIT is used to cooperate with the control transistor MN1 to adjust the magnitude of the first input current I HBT and the second input current IM .
在一些实施例中，如图5所示，电流镜电路503至少包括第一晶体管MP1、第二晶体管MP2。In some embodiments, as shown in FIG. 5 , the current mirror circuit 503 at least includes a first transistor MP1 and a second transistor MP2 .
在本公开实施例中，晶体管的第一端为晶体管的源极，晶体管的第二端为晶体管的漏极，晶体管的第三端为晶体管的栅极。其他实施例中，晶体管也可以为三极管等，此处不做限制。In the embodiment of the present disclosure, the first end of the transistor is the source of the transistor, the second end of the transistor is the drain of the transistor, and the third end of the transistor is the gate of the transistor. In other embodiments, the transistor may also be a triode, etc., which is not limited here.
在电流镜电路503的电流镜单元中，第一晶体管MP1和第二晶体管MP2的第一端与电源VDD电连接；第一晶体管MP1的第二端与控制晶体管MN1的第一端电连接，控制晶体管MN1的第二端接地，控制晶体管MN1的第三端通过反相器inverter与比较器COMP的比较输出端out1电连接；第一晶体管MP1的第三端分别与第一控制端口A、第二晶体管MP2的第三端、第一电流源ILIMIT的正极电连接；第二晶体管MP2的第二端和功率放大器10电连接，用于输出第一输入电流IHBT，其中，第一晶体管MP1、第二晶体管MP2形成第一电流镜电路，以使第一输入电流IHBT与第一晶体管MP1的输出电流成比例，从而通过调节第一晶体管MP1的输出电流对第一输入电流IHBT、第二输入电流I进行调节。In the current mirror unit of the current mirror circuit 503, the first ends of the first transistor MP1 and the second transistor MP2 are electrically connected to the power supply VDD; the second end of the first transistor MP1 is electrically connected to the first end of the control transistor MN1, the second end of the control transistor MN1 is grounded, and the third end of the control transistor MN1 is electrically connected to the comparison output end out1 of the comparator COMP through the inverter inverter; the third end of the first transistor MP1 is electrically connected to the first control port A, the third end of the second transistor MP2, and the positive electrode of the first current source I LIMIT respectively; the second end of the second transistor MP2 is electrically connected to the power amplifier 10 for outputting the first input current I HBT , wherein the first transistor MP1 and the second transistor MP2 form a first current mirror circuit so that the first input current I HBT is proportional to the output current of the first transistor MP1, so that the first input current I HBT and the second input current I are adjusted by adjusting the output current of the first transistor MP1.
具体地，当滤波器模拟电路501的温度大于或等于临界温度时，控制晶体管MN1关闭，第一晶体管MP1的电流被限制为第一电流源ILIMIT的电流，进而限制第一输入电流IHBT和第二输入电流IM的电流值。当滤波器模拟电路501的温度小于临界温度时，控制晶体管MN1开启，第一晶体管MP1的电流与为控制晶体管MN1的电流与ILIMIT之和。Specifically, when the temperature of the filter simulation circuit 501 is greater than or equal to the critical temperature, the control transistor MN1 is turned off, and the current of the first transistor MP1 is limited to the current of the first current source I LIMIT , thereby limiting the current values of the first input current I HBT and the second input current IM . When the temperature of the filter simulation circuit 501 is less than the critical temperature, the control transistor MN1 is turned on, and the current of the first transistor MP1 is the sum of the current of the control transistor MN1 and I LIMIT .
如图5所示，滤波器模拟电路501包括电流模拟模块及热阻模拟模块R1，其中，电流模拟模块与热阻模拟模块R1连接，热阻模拟模块R1用于模拟滤波器30的热阻。As shown in FIG. 5 , the filter simulation circuit 501 includes a current simulation module and a thermal resistance simulation module R1 , wherein the current simulation module is connected to the thermal resistance simulation module R1 , and the thermal resistance simulation module R1 is used to simulate the thermal resistance of the filter 30 .
一些实施例中，电流模拟模块包括第三晶体管MP3、第二电流源IQC。第三晶体管MP3的第一端与电源VDD电连接，第三晶体管MP3的第二端与热阻模拟模块电连接，第三晶体管MP3的第三端与电流镜电路的第一控制端口A电连接，第二输入电流IM的大小通过第三晶体管MP3的输出电流I3与第二电流源IQC确定，其中，第三晶体管MP3的输出电流I3与电流镜电路的第一输入电流IHBT成比例。 In some embodiments, the current simulation module includes a third transistor MP3 and a second current source I QC . A first end of the third transistor MP3 is electrically connected to a power supply VDD, a second end of the third transistor MP3 is electrically connected to the thermal resistance simulation module, a third end of the third transistor MP3 is electrically connected to a first control port A of a current mirror circuit, and a magnitude of the second input current IM is determined by an output current I3 of the third transistor MP3 and the second current source I QC , wherein the output current I3 of the third transistor MP3 is proportional to a first input current I HBT of the current mirror circuit.
一些实施例中，第三晶体管MP3的第一端与电源VDD电连接，第三晶体管MP3的第二端与热阻模拟模块R1电连接，第三晶体管MP3的第三端与第一控制端口A电连接。第一晶体管MP1与第三晶体管MP3形成第二电流镜电路，以控制第二晶体管MP2的电流IHBT与第三晶体管MP3的电流I3成比例。In some embodiments, a first terminal of the third transistor MP3 is electrically connected to a power source VDD, a second terminal of the third transistor MP3 is electrically connected to a thermal resistance simulation module R1, and a third terminal of the third transistor MP3 is electrically connected to a first control port A. The first transistor MP1 and the third transistor MP3 form a second current mirror circuit to control the current I HBT of the second transistor MP2 to be proportional to the current I 3 of the third transistor MP3.
一些实施例中，电流模拟模块还包括运算放大器OPMAP、第四晶体管MP4，如图5所示，图5是本公开实施例提供的滤波器模拟电路的结构示意图。运算放大器OPMAP包括第三输入端3、第四输入端4和运放输出端out2；电流镜电路503中的第二晶体管MP2的第二端和第三晶体管MP3的第二端分别与运算放大器OPAMP的第三输入端3和第四输入端4电连接，运算放大器控制第二晶体管MP2的第二端电压与第三晶体管MP3的第二端电压相同，即第二晶体管MP2与第三晶体管MP3的漏极电压相同。In some embodiments, the current simulation module further includes an operational amplifier OPMAP and a fourth transistor MP4, as shown in FIG5, which is a schematic diagram of the structure of the filter simulation circuit provided by an embodiment of the present disclosure. The operational amplifier OPMAP includes a third input terminal 3, a fourth input terminal 4 and an operational amplifier output terminal out2; the second end of the second transistor MP2 and the second end of the third transistor MP3 in the current mirror circuit 503 are electrically connected to the third input terminal 3 and the fourth input terminal 4 of the operational amplifier OPAMP, respectively, and the operational amplifier controls the second end voltage of the second transistor MP2 to be the same as the second end voltage of the third transistor MP3, that is, the drain voltage of the second transistor MP2 and the drain voltage of the third transistor MP3 are the same.
在一些实施例中，第二输入电流IM的大小通过第三晶体管MP3的输出电流I3与第二电流源IQC确定，其中，第三晶体管MP3的输出电流I3与第一输入电流IHBT成比例，第二电流源IQC为不受温度影响的基准电流，因此，第二输入电流IM的大小与第一输入电流IHBT的大小相关。In some embodiments, the magnitude of the second input current I M is determined by the output current I 3 of the third transistor MP3 and the second current source I QC , wherein the output current I 3 of the third transistor MP3 is proportional to the first input current I HBT , and the second current source I QC is a reference current that is not affected by temperature. Therefore, the magnitude of the second input current I M is related to the magnitude of the first input current I HBT .
在一些实施例中，运算放大器OPAMP的第三输入端3基于第二晶体管MP2的第二端与功率放大器10电连接，运算放大器OPAMP的第四输入端4与第二控制端口B电连接，运算放大器OPAMP的运放输出端out2与第三控制端口C电连接。In some embodiments, the third input terminal 3 of the operational amplifier OPAMP is electrically connected to the power amplifier 10 based on the second end of the second transistor MP2, the fourth input terminal 4 of the operational amplifier OPAMP is electrically connected to the second control port B, and the operational amplifier output terminal out2 of the operational amplifier OPAMP is electrically connected to the third control port C.
在本公开实施例中，第一控制端口A与滤波器模拟电路501中的第三晶体管MP3的第三端连接，第二控制端口B与滤波器模拟电路501中的第三晶体管MP3的第二端连接，第三控制端口C与滤波器模拟电路501中的第四晶体管MP4的第三端连接。In the embodiment of the present disclosure, the first control port A is connected to the third end of the third transistor MP3 in the filter simulation circuit 501, the second control port B is connected to the second end of the third transistor MP3 in the filter simulation circuit 501, and the third control port C is connected to the third end of the fourth transistor MP4 in the filter simulation circuit 501.
这里，第二晶体管MP2的第二端和第三晶体管MP3的第二端分别与运算放大器OPAMP的第三输入端3和第四输入端4电连接，运算放大器控制第二晶体管MP2的第二端电压与第三晶体管MP3的第二端电压相同，即第二晶体管MP2与第三晶体管MP3的漏极电压相同，基于第二晶体管MP2与第三晶体管MP3的栅极电压Vgate，使第二晶体管MP2和第三晶体管MP3均工作于线性区或饱和区。Here, the second end of the second transistor MP2 and the second end of the third transistor MP3 are electrically connected to the third input terminal 3 and the fourth input terminal 4 of the operational amplifier OPAMP, respectively. The operational amplifier controls the second end voltage of the second transistor MP2 to be the same as the second end voltage of the third transistor MP3, that is, the drain voltage of the second transistor MP2 and the third transistor MP3 are the same. Based on the gate voltage Vgate of the second transistor MP2 and the third transistor MP3, the second transistor MP2 and the third transistor MP3 both operate in the linear region or the saturation region.
这里，为了从功率放大器的HBT端口看向保护电路为低阻，场效应晶体管电流镜电路需要工作在线性区，双极晶体管电流镜需要工作在饱和区。因此，当第一晶体管、第二晶体管和第三晶体管为场效应晶体管时，电流镜电路503需要工作在线性区；当第一晶体管、第二晶体管和第三晶体管为双极晶体管时，电流镜电路503需要工作在饱和区。下述实施例不再对晶体管的具体类型和工作状态进行描述。Here, in order to see the protection circuit as low resistance from the HBT port of the power amplifier, the field effect transistor current mirror circuit needs to work in the linear region, and the bipolar transistor current mirror needs to work in the saturation region. Therefore, when the first transistor, the second transistor, and the third transistor are field effect transistors, the current mirror circuit 503 needs to work in the linear region; when the first transistor, the second transistor, and the third transistor are bipolar transistors, the current mirror circuit 503 needs to work in the saturation region. The following embodiments will no longer describe the specific type and working state of the transistor.
在一些实施例中，第一晶体管MP1的第二端用于接收第一电流源ILIMIT的输入电流，第二晶体管MP2的第二端根据输入电流镜像输出第一输入电流IHBT，第三晶体管MP3的第二端根据输入电流镜像输出第三晶体管MP3的输出电流I3，第一输入电流IHBT和第三晶体管MP3的输出电流I3与第一晶体管MP1的电流成镜像比例关系。In some embodiments, the second end of the first transistor MP1 is used to receive the input current of the first current source I LIMIT , the second end of the second transistor MP2 outputs the first input current I HBT according to the input current mirror, and the second end of the third transistor MP3 outputs the output current I 3 of the third transistor MP3 according to the input current mirror, and the first input current I HBT and the output current I 3 of the third transistor MP3 are in a mirror proportional relationship with the current of the first transistor MP1.
如图5所示，滤波器模拟电路501还包括模拟电容C1和转换电阻R2；模拟电容C1的一端分别与热阻模拟模块R1的一端和第一输入端1电连接，模拟电容C1的另一端接地；转换电阻R2的一端与热阻模拟模块R1的另一端电连接，转换电阻R2的另一端接地，转换电阻R2用于将电流转换为电压。As shown in Figure 5, the filter simulation circuit 501 also includes an analog capacitor C1 and a conversion resistor R2; one end of the analog capacitor C1 is electrically connected to one end of the thermal resistance simulation module R1 and the first input terminal 1 respectively, and the other end of the analog capacitor C1 is grounded; one end of the conversion resistor R2 is electrically connected to the other end of the thermal resistance simulation module R1, and the other end of the conversion resistor R2 is grounded. The conversion resistor R2 is used to convert current into voltage.
在一些实施例，功率放大器10至少包括放大晶体管Q，如图5所示，第三晶体管MP3的输出电流I3用于模拟放大晶体管Q的输出电流，第二电流源IQC输出的电流用于模拟放大晶体管Q的静态电流。滤波器模拟电路501用于根据输出电流、静态电流和热阻模拟模块R1，输出与滤波器温度相关的滤波器电压。这里，第三晶体管MP3的输出电流I3与第二电流源IQC的输出电流之间的差值为第二输出电流IM，第二输出电流IM 可以作为第四晶体管MP4的输出电流，第四晶体管MP4的输出电流用于模拟滤波器电流，即功率放大器流入滤波器的电流。In some embodiments, the power amplifier 10 includes at least an amplifying transistor Q. As shown in FIG5 , the output current I3 of the third transistor MP3 is used to simulate the output current of the amplifying transistor Q, and the current output by the second current source IQC is used to simulate the quiescent current of the amplifying transistor Q. The filter simulation circuit 501 is used to output a filter voltage related to the filter temperature according to the output current, the quiescent current and the thermal resistance simulation module R1. Here, the difference between the output current I3 of the third transistor MP3 and the output current of the second current source IQC is the second output current IM , and the second output current IM The output current of the fourth transistor MP4 can be used as the output current of the fourth transistor MP4. The output current of the fourth transistor MP4 is used to simulate the filter current, that is, the current flowing from the power amplifier into the filter.
在一些实施例中，热阻模拟模块R1用于模拟滤波器的热阻，第四晶体管MP4的输出电流流过热阻模拟模块R1后，输出与滤波器温度相关的滤波器电压VSNS。In some embodiments, the thermal resistance simulation module R1 is used to simulate the thermal resistance of the filter. After the output current of the fourth transistor MP4 flows through the thermal resistance simulation module R1 , a filter voltage V SNS related to the filter temperature is output.
在一些实施例中，如图5所示，基准电压电路502至少包括第三电流源IPTAT、第四电流源IR和分压电阻R3，其中，第三电流源IPTAT的正极与电源VDD电连接，第三电流源IPTAT的负极分别与第四电流源IR的正极、第二输入端2电连接，第四电流源IR的负极接地；其中，第三电流源IPTAT用于输出与环境温度成比例的电流，第四电流源IR为恒流源；分压电阻R3的一端分别与第三电流源IPTAT的负极、第四电流源IR的正极、第二输入端2电连接，另一端接地。In some embodiments, as shown in FIG5 , the reference voltage circuit 502 at least includes a third current source I PTAT , a fourth current source IR and a voltage divider resistor R3, wherein the positive electrode of the third current source I PTAT is electrically connected to the power supply VDD, the negative electrode of the third current source I PTAT is electrically connected to the positive electrode of the fourth current source IR and the second input terminal 2, respectively, and the negative electrode of the fourth current source IR is grounded; wherein the third current source IPTAT is used to output a current proportional to the ambient temperature, and the fourth current source IR is a constant current source; one end of the voltage divider resistor R3 is electrically connected to the negative electrode of the third current source I PTAT , the positive electrode of the fourth current source IR and the second input terminal 2, respectively, and the other end is grounded.
如图5所示，基准电压电路502还包括第五晶体管MP5、第六晶体管MP6。其中，第五晶体管MP5与第六晶体管MP6形成电流镜，第五晶体管MP5的第一端、第六晶体管MP6的第一端均与电源VDD电连接，第五晶体管MP5的第三端与第六晶体管MP6的第三端电连接，第五晶体管MP5的第二端与第二输入端2电连接，第六晶体管MP6的第二端与第六晶体管MP6的第三端、第三电流源IPTAT的负极电连接；分压电阻R3的一端通过第五晶体管MP5、第六晶体管MP6与第三电流源IPTAT的负极电连接。As shown in FIG5 , the reference voltage circuit 502 further includes a fifth transistor MP5 and a sixth transistor MP6. The fifth transistor MP5 and the sixth transistor MP6 form a current mirror, the first end of the fifth transistor MP5 and the first end of the sixth transistor MP6 are both electrically connected to the power supply VDD, the third end of the fifth transistor MP5 is electrically connected to the third end of the sixth transistor MP6, the second end of the fifth transistor MP5 is electrically connected to the second input terminal 2, the second end of the sixth transistor MP6 is electrically connected to the third end of the sixth transistor MP6 and the negative electrode of the third current source I PTAT ; one end of the voltage dividing resistor R3 is electrically connected to the negative electrode of the third current source I PTAT through the fifth transistor MP5 and the sixth transistor MP6.
在一些实施例中，如图5所示，基准电压电路502至少包括第五晶体管MP5、第六晶体管MP6、第三电流源IPTAT、第四电流源IR和分压电阻R3。第三电流源IPTAT的正极与电源VDD电连接，第三电流源IPTAT的负极分别与第四电流源IR的正极、第六晶体管MP6的第二端和第三端电连接，第四电流源IR的负极接地。第六晶体管MP6的第一端与电源VDD电连接，第六晶体管MP6的第三端与第五晶体管MP5的第三端电连接，第五晶体管MP5的第一端与电源VDD电连接，第五晶体管MP5的第二端分别与第二输入端和分压电阻R3的一端电连接，分压电阻R3的另一端接地。In some embodiments, as shown in FIG5 , the reference voltage circuit 502 at least includes a fifth transistor MP5, a sixth transistor MP6, a third current source I PTAT , a fourth current source IR and a voltage-dividing resistor R3. The positive electrode of the third current source I PTAT is electrically connected to the power supply VDD, the negative electrode of the third current source I PTAT is electrically connected to the positive electrode of the fourth current source IR , the second end and the third end of the sixth transistor MP6, respectively, and the negative electrode of the fourth current source IR is grounded. The first end of the sixth transistor MP6 is electrically connected to the power supply VDD, the third end of the sixth transistor MP6 is electrically connected to the third end of the fifth transistor MP5, the first end of the fifth transistor MP5 is electrically connected to the power supply VDD, the second end of the fifth transistor MP5 is electrically connected to the second input end and one end of the voltage-dividing resistor R3, respectively, and the other end of the voltage-dividing resistor R3 is grounded.
在一些实施例中，通过第三电流源IPTAT可以获取与环境温度成正比的电流，再通过不受温度影响的恒流源，即第四电流源IR，得到与环境温度成线性反比的电流给到第六晶体管MP6的漏极。这里，由于第三电流源IPTAT的负极与第四电流源IR的正极连接，而第四电流源IR为不受温度影响的恒流源，因此，第六晶体管MP6的漏极电流为第三电流源IPTAT与第四电流源IR的电流之差，因此，在第三电流源IPTAT获取与环境温度成正比的电流的情况下，第六晶体管MP6的漏极电流与环境温度成线性反比。In some embodiments, a current proportional to the ambient temperature can be obtained through the third current source I PTAT , and then a current linearly inversely proportional to the ambient temperature is obtained through a constant current source that is not affected by temperature, that is, a fourth current source IR , and is given to the drain of the sixth transistor MP6. Here, since the cathode of the third current source I PTAT is connected to the anode of the fourth current source IR , and the fourth current source IR is a constant current source that is not affected by temperature, the drain current of the sixth transistor MP6 is the difference between the currents of the third current source I PTAT and the fourth current source IR . Therefore, when the third current source I PTAT obtains a current proportional to the ambient temperature, the drain current of the sixth transistor MP6 is linearly inversely proportional to the ambient temperature.
在一些实施例中，第五晶体管MP5的第三端和第六晶体管MP6的第三端连接，第五晶体管MP5的第一端和第六晶体管MP6的第一端均与电源VDD电连接，因此，第五晶体管MP5和第六晶体管MP6构成电流镜电路，基于第六晶体管MP6的漏极电流，第五晶体管MP5的漏极输出第六晶体管MP6的漏极电流对应的镜像电流，该镜像电流与环境温度成线性反比。In some embodiments, the third end of the fifth transistor MP5 is connected to the third end of the sixth transistor MP6, and the first end of the fifth transistor MP5 and the first end of the sixth transistor MP6 are both electrically connected to the power supply VDD. Therefore, the fifth transistor MP5 and the sixth transistor MP6 constitute a current mirror circuit, and based on the drain current of the sixth transistor MP6, the drain of the fifth transistor MP5 outputs a mirror current corresponding to the drain current of the sixth transistor MP6, and the mirror current is linearly inversely proportional to the ambient temperature.
这里，通过分压电阻R3和第五晶体管MP5的漏极端输出的镜像电流，使得第五晶体管MP5的漏极端输出基准电压VREF，基准电压VREF随环境温度发生变化，这里可以是基准电压VREF与环境温度成反比。Here, the drain terminal of the fifth transistor MP5 outputs a reference voltage V REF through the voltage divider resistor R3 and the mirror current outputted from the drain terminal of the fifth transistor MP5 . The reference voltage V REF changes with the ambient temperature. Here, the reference voltage V REF may be inversely proportional to the ambient temperature.
在本公开实施例中，滤波器30的温度等于环境温度加上由于滤波器工作产生的热温度，当滤波器损坏的阈值温度固定时，环境温度越高时，由于工作产生的热温度的阈值就越低，因此本公开实施例通过形成一个与环境温度成反比的基准电压VREF与滤波器温度相关的滤波器电压VSNS进行比较，当环境温度越高，滤波器热温度的阈值越低，而此时基准电压VREF就越低。In the embodiment of the present disclosure, the temperature of the filter 30 is equal to the ambient temperature plus the heat temperature generated by the operation of the filter. When the threshold temperature of filter damage is fixed, the higher the ambient temperature, the lower the threshold of the heat temperature generated by the operation. Therefore, the embodiment of the present disclosure forms a reference voltage V REF that is inversely proportional to the ambient temperature and compares it with the filter voltage V SNS related to the filter temperature. When the ambient temperature is higher, the threshold of the filter heat temperature is lower, and at this time, the reference voltage V REF is lower.
在一些实施例中，滤波器具有临界温度，当滤波器温度达到临界温度并继续升高时， 基准电压VREF小于滤波器电压VSNS，比较器的比较输出端out1输出高电平，经反相器inverter转换后，给到控制晶体管MN1的栅极低电平，MN1截止，此时，第一晶体管MP1的电流被限定在第一电流源ILIMIT输出的电流Ilimit，则第二晶体管MP2镜像第一晶体管MP1后的第二晶体管MP2的漏极电流IHBT的最大值被限定在M*Ilimit，从而限制了功率放大器的电流，进一步限制了功率放大器的输出功率，从而限定了滤波器的功率，阻止滤波器温度超过临界温度，以实现滤波器的温度进行调节。In some embodiments, the filter has a critical temperature. When the filter temperature reaches the critical temperature and continues to rise, The reference voltage V REF is less than the filter voltage V SNS , and the comparison output terminal out1 of the comparator outputs a high level, which is converted by the inverter and given a low level to the gate of the control transistor MN1, and MN1 is turned off. At this time, the current of the first transistor MP1 is limited to the current I limit output by the first current source I LIMIT , and the maximum value of the drain current I HBT of the second transistor MP2 after the second transistor MP2 mirrors the first transistor MP1 is limited to M*I limit , thereby limiting the current of the power amplifier, further limiting the output power of the power amplifier, thereby limiting the power of the filter, preventing the filter temperature from exceeding the critical temperature, and realizing the temperature adjustment of the filter.
在一些实施例中，当滤波器温度小于临界温度时，第二晶体管的漏极电流IHBT较小，从而基准电压VREF大于滤波器电压，比较器的比较输出端out1输出低电平，经反相器inverter转换后，给到控制晶体管MN1的栅极为高电平，使得控制晶体管MN1导通，使得Vgate电压较低，MP2管工作在线性区，此时，控制晶体管MN1的电流也流过第一晶体管MP1，第一晶体管MP1的电流增加，镜像MP1的第二晶体管MP2的漏极电流IHBT不受限。In some embodiments, when the filter temperature is lower than the critical temperature, the drain current I HBT of the second transistor is small, so that the reference voltage V REF is greater than the filter voltage, and the comparison output terminal out1 of the comparator outputs a low level, which is converted by the inverter and given to the gate of the control transistor MN1 as a high level, so that the control transistor MN1 is turned on, so that the Vgate voltage is lower, and the MP2 tube works in the linear region. At this time, the current of the control transistor MN1 also flows through the first transistor MP1, the current of the first transistor MP1 increases, and the drain current I HBT of the second transistor MP2 of the mirror MP1 is not limited.
在一些实施例中，如图5所示，电路还包括迟滞电路504，迟滞电路504与基准电压电路502电连接；迟滞电路504至少包括并联的迟滞晶体管MN2和迟滞电阻R4。其中，迟滞晶体管MN2的第一端分别与分压电阻R3和迟滞电阻R4电连接，迟滞电阻R4的另一端接地，迟滞晶体管MN2的第二端接地，迟滞晶体管MN2的第三端与比较输出端out1电连接。In some embodiments, as shown in FIG5 , the circuit further includes a hysteresis circuit 504, which is electrically connected to the reference voltage circuit 502; the hysteresis circuit 504 at least includes a hysteresis transistor MN2 and a hysteresis resistor R4 connected in parallel. The first end of the hysteresis transistor MN2 is electrically connected to the voltage divider resistor R3 and the hysteresis resistor R4, respectively, the other end of the hysteresis resistor R4 is grounded, the second end of the hysteresis transistor MN2 is grounded, and the third end of the hysteresis transistor MN2 is electrically connected to the comparison output end out1.
这里，迟滞电路504用于根据滤波器电压VSNS和基准电压VREF，改变基准电压VREF的大小。这里，比较器COMP的比较输出端out1输出高电平后，第二晶体管MP2的漏极电流IHBT被限定，进而滤波器的功率被限定，此时，迟滞电路504由于比较输出端out1输出高电平，使得迟滞晶体管MN2导通，通过迟滞晶体管MN2和迟滞电阻R4使得基准电压VREF进一步降低，当滤波器的热温度降低到滤波器的热温度阈值后，滤波器温度小于滤波器的临界温度，此时基准电压VREF大于滤波器电压VSNS，比较输出端out1输出低电平，迟滞晶体管MN2截止，如此，可以防止因热振荡导致比较器输出逻辑电平的反复变换，提高了元器件的可靠性。Here, the hysteresis circuit 504 is used to change the size of the reference voltage V REF according to the filter voltage V SNS and the reference voltage V REF . Here, after the comparison output terminal out1 of the comparator COMP outputs a high level, the drain current IHBT of the second transistor MP2 is limited, and then the power of the filter is limited. At this time, the hysteresis circuit 504 outputs a high level due to the comparison output terminal out1 outputting a high level, so that the hysteresis transistor MN2 is turned on, and the reference voltage V REF is further reduced through the hysteresis transistor MN2 and the hysteresis resistor R4. When the thermal temperature of the filter is reduced to the thermal temperature threshold of the filter, the filter temperature is less than the critical temperature of the filter. At this time, the reference voltage V REF is greater than the filter voltage V SNS , the comparison output terminal out1 outputs a low level, and the hysteresis transistor MN2 is turned off. In this way, the repeated conversion of the comparator output logic level due to thermal oscillation can be prevented, and the reliability of components is improved.
本公开实施例再提供一种放大电路，如图5所示，放大电路至少包括功率放大器10，保护电路与功率放大器10电连接，功率放大器10与滤波器30电连接。其中，功率放大器10至少包括偏置电路101-1和放大晶体管Q。偏置电路101-1的一端与电流镜电路503中第二晶体管MP2的第二端电连接，即与电流镜电路503中第二晶体管MP2的漏极电连接，偏置电路101-1的另一端与放大晶体管Q的第三端(即基极)电连接；放大晶体管Q的发射极接地，放大晶体管Q的集电极与滤波器30电连接。The embodiment of the present disclosure further provides an amplifier circuit, as shown in FIG5 , the amplifier circuit at least includes a power amplifier 10, the protection circuit is electrically connected to the power amplifier 10, and the power amplifier 10 is electrically connected to the filter 30. The power amplifier 10 at least includes a bias circuit 101-1 and an amplifier transistor Q. One end of the bias circuit 101-1 is electrically connected to the second end of the second transistor MP2 in the current mirror circuit 503, that is, electrically connected to the drain of the second transistor MP2 in the current mirror circuit 503, and the other end of the bias circuit 101-1 is electrically connected to the third end (that is, the base) of the amplifier transistor Q; the emitter of the amplifier transistor Q is grounded, and the collector of the amplifier transistor Q is electrically connected to the filter 30.
在一些实施例中，第一输入电流IHBT用于为偏置电路101-1馈电；功率放大器10用于对第一输入电流IHBT进行放大，并将放大后的第一输入电流输入至滤波器30。In some embodiments, the first input current I HBT is used to feed the bias circuit 101 - 1 ; the power amplifier 10 is used to amplify the first input current I HBT and input the amplified first input current to the filter 30 .
在本公开实施例中，基准电压电路502中，通过第三电流源IPTAT和第四电流源IR获取与环境温度成线性反比的电流，将电流通过第五晶体管MP5和第六晶体管MP6形成的电流镜进行转换，再通过分压电阻R3和迟滞电阻R4将电流转换为电压，从而得到用于与滤波器热温度进行比较的基准电压VREF，基准电压VREF随温度变化，将基准电压VREF与滤波器电压VSNS通过比较器COMP进行比较，从而通过控制晶体管MN1对功率放大器10的电流IHBT进行调节。In the embodiment of the present disclosure, in the reference voltage circuit 502, a current that is linearly inversely proportional to the ambient temperature is obtained through the third current source I PTAT and the fourth current source IR , the current is converted through a current mirror formed by the fifth transistor MP5 and the sixth transistor MP6, and then the current is converted into a voltage through the voltage divider resistor R3 and the hysteresis resistor R4, thereby obtaining a reference voltage V REF for comparison with the filter thermal temperature, the reference voltage V REF changes with temperature, the reference voltage V REF is compared with the filter voltage V SNS through the comparator COMP, and the current I HBT of the power amplifier 10 is adjusted by controlling the transistor MN1.
在一些实施例中，当滤波器温度小于临界温度时，第二晶体管MP2漏极电流IHBT较小，从而滤波器电压VSNS小于基准电压VREF，因此控制晶体管MN1管的栅端电压为高电平，此时，Vgate电压较低，MP2管工作在线性区。当滤波器温度一旦达到临界温度并继续升高时，控制晶体管MN1管的栅端电压转换为低电平，MN1截止，第一晶体 管MP1的电流被限定在第一电流源ILIMIT输出的电流Ilimit，则第二晶体管MP2镜像第一晶体管MP1后的第二晶体管MP2的漏极电流IHBT的最大值被限定在M*Ilimit，从而限制了功率放大器的电流，进一步限制了功率放大器的输出功率，从而限定了滤波器的功率，阻止滤波器温度超过临界温度，以实现滤波器的温度进行调节。In some embodiments, when the filter temperature is lower than the critical temperature, the drain current I HBT of the second transistor MP2 is small, so that the filter voltage V SNS is lower than the reference voltage V REF , so the gate voltage of the control transistor MN1 is high. At this time, the Vgate voltage is low, and the MP2 operates in the linear region. Once the filter temperature reaches the critical temperature and continues to rise, the gate voltage of the control transistor MN1 is converted to a low level, MN1 is turned off, and the first transistor The current of the tube MP1 is limited to the current I limit output by the first current source I LIMIT , and the maximum value of the drain current I HBT of the second transistor MP2 after the second transistor MP2 mirrors the first transistor MP1 is limited to M*I limit , thereby limiting the current of the power amplifier, further limiting the output power of the power amplifier, thereby limiting the power of the filter, preventing the filter temperature from exceeding the critical temperature, and realizing the temperature adjustment of the filter.
接下来请参照图6和图7，图6是本公开实施例提供的滤波器的临界功率与环境温度的关系示意图，图7是本公开实施例提供的滤波器的临界温度与环境温度的关系示意图。滤波器临界功率(PTH)与环境温度(Ta)之间的关系如图6所示，滤波器临界温度(Tf0)与环境温度(Ta)之间的关系如图7所示，其中，在本公开提出的保护电路之前，相关技术中的滤波器临界功率PTH不随环境温度Ta的变化而变化，这会导致滤波器的临界温度Tf0随环境温度Ta的增加而线性增大，会造成滤波器因高温失效；而通过本公开实施例提供的保护电路优化后，滤波器临界功率PTH随环境温度Ta的变化而线性减小，使得滤波器的临界温度Tf0不随环境温度Ta的增加而变化，达到了优化效果。Next, please refer to Figures 6 and 7. Figure 6 is a schematic diagram of the relationship between the critical power and ambient temperature of the filter provided by the embodiment of the present disclosure, and Figure 7 is a schematic diagram of the relationship between the critical temperature and ambient temperature of the filter provided by the embodiment of the present disclosure. The relationship between the critical power (PTH) of the filter and the ambient temperature (Ta) is shown in Figure 6, and the relationship between the critical temperature (Tf0) of the filter and the ambient temperature (Ta) is shown in Figure 7, wherein, before the protection circuit proposed in the present disclosure, the critical power PTH of the filter in the related art does not change with the change of the ambient temperature Ta, which will cause the critical temperature Tf0 of the filter to increase linearly with the increase of the ambient temperature Ta, which will cause the filter to fail due to high temperature; and after the protection circuit provided by the embodiment of the present disclosure is optimized, the critical power PTH of the filter decreases linearly with the change of the ambient temperature Ta, so that the critical temperature Tf0 of the filter does not change with the increase of the ambient temperature Ta, and the optimization effect is achieved.
本公开实施例不仅根据环境温度自动调整了功率放大器最大功率输出，实现了对滤波器温度的自动追踪；还通过模拟滤波器的热阻，将功率和温度联系在一起，并利用功率和电流的线性关系，对功率放大器支路电流采样，实现对滤波器的温度监控，从而实现对滤波器更精准的保护。The disclosed embodiment not only automatically adjusts the maximum power output of the power amplifier according to the ambient temperature and realizes automatic tracking of the filter temperature; it also links power and temperature together by simulating the thermal resistance of the filter, and utilizes the linear relationship between power and current to sample the branch current of the power amplifier to realize temperature monitoring of the filter, thereby achieving more accurate protection of the filter.
以上所述，仅为本公开的实施例而已，并非用于限定本公开的保护范围。凡在本公开的精神和范围之内所作的任何修改、等同替换和改进等，均包含在本公开的保护范围之内。应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。The above is only an embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present disclosure are included in the scope of protection of the present disclosure. It should be understood that "one embodiment" or "one embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments.
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个***，或一些特征可以忽略，或不执行。It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method or device. In the absence of further restrictions, an element defined by the statement "comprises one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed.
以上所述，仅为本公开的实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。 The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (11)

  1. 一种电流镜电路，所述电流镜电路至少包括第一支路、第二支路、第三支路、控制电路和电流源；A current mirror circuit, the current mirror circuit at least comprising a first branch, a second branch, a third branch, a control circuit and a current source;
    所述第一支路的第一端和第二端均与所述电流源电连接，所述第一支路的第一端分别与所述第二支路的第一端和所述第三支路的第一端电连接；The first end and the second end of the first branch are both electrically connected to the current source, and the first end of the first branch is electrically connected to the first end of the second branch and the first end of the third branch respectively;
    所述第二支路的第二端和所述第三支路的第二端分别与所述控制电路电连接；The second end of the second branch and the second end of the third branch are electrically connected to the control circuit respectively;
    所述第一支路的第三端、所述第二支路的第三端和所述第三支路的第三端分别与电源电连接；The third end of the first branch, the third end of the second branch and the third end of the third branch are electrically connected to a power source respectively;
    所述第二支路和所述第三支路工作在线性区或饱和区，以使从所述第二支路的第三端看向所述电流镜电路为低阻。The second branch and the third branch operate in a linear region or a saturation region, so that a low resistance is seen from the third end of the second branch toward the current mirror circuit.
  2. 根据权利要求1所述的电路，所述控制电路，用于控制所述第二支路的第二端的电压与所述第三支路的第二端的电压相同，以使得工作在线性区或饱和区的所述第二支路和所述第三支路保持相同的状态以达到电流镜像复制。According to the circuit of claim 1, the control circuit is used to control the voltage of the second end of the second branch to be the same as the voltage of the second end of the third branch, so that the second branch and the third branch operating in the linear region or the saturation region maintain the same state to achieve current mirror replication.
  3. 根据权利要求1所述的电路，所述第一支路至少包括第一晶体管，第二支路至少包括第二晶体管，所述第三支路至少包括第三晶体管；The circuit according to claim 1, wherein the first branch comprises at least a first transistor, the second branch comprises at least a second transistor, and the third branch comprises at least a third transistor;
    所述第一晶体管的第一端分别与所述第二晶体管的第一端和所述第三晶体管的第一端电连接；The first end of the first transistor is electrically connected to the first end of the second transistor and the first end of the third transistor respectively;
    所述第一晶体管的第三端、所述第二晶体管的第三端和所述第三晶体管的第三端分别与电源电连接；The third end of the first transistor, the third end of the second transistor and the third end of the third transistor are electrically connected to a power supply respectively;
    其中，所述第一晶体管第一端与第三端之间的电压、所述第二晶体管第一端与第三端之间的电压和所述第三晶体管第一端与第三端之间的电压均相同。The voltage between the first terminal and the third terminal of the first transistor, the voltage between the first terminal and the third terminal of the second transistor, and the voltage between the first terminal and the third terminal of the third transistor are all the same.
  4. 根据权利要求3所述的电路，所述电流源，用于为所述第一晶体管的第二端提供输入电流；The circuit according to claim 3, wherein the current source is used to provide an input current to the second terminal of the first transistor;
    所述电流源还用于分别为所述第一晶体管的第一端、所述第二晶体管的第一端和所述第三晶体管的第一端提供偏置电流。The current source is further configured to provide bias currents for the first terminal of the first transistor, the first terminal of the second transistor, and the first terminal of the third transistor, respectively.
  5. 根据权利要求4所述的电路，所述控制电路至少包括运放电路；The circuit according to claim 4, wherein the control circuit comprises at least an operational amplifier circuit;
    所述运放电路，用于控制所述第二晶体管的第二端的电压和所述第三晶体管的第二端的电压相同，以控制所述第二晶体管和所述第三晶体管处于相同的状态；The operational amplifier circuit is used to control the voltage of the second end of the second transistor to be the same as the voltage of the second end of the third transistor, so as to control the second transistor and the third transistor to be in the same state;
    所述第二晶体管的第二端用于根据所述输入电流输出第一镜像电流，所述第三晶体管的第二端用于根据所述输入电流输出第二镜像电流；The second end of the second transistor is used to output a first mirror current according to the input current, and the second end of the third transistor is used to output a second mirror current according to the input current;
    其中，所述第一镜像电流与所述输入电流成第一镜像比例，所述第二镜像电流与所述输入电流成第二镜像比例。The first mirror current and the input current are in a first mirror ratio, and the second mirror current and the input current are in a second mirror ratio.
  6. 根据权利要求3所述的电路，所述电流镜电路与功率放大器电连接；The circuit according to claim 3, wherein the current mirror circuit is electrically connected to the power amplifier;
    所述电流镜电路通过所述第二晶体管的第二端与所述功率放大器电连接，为所述功率放大器提供偏置电流。The current mirror circuit is electrically connected to the power amplifier through the second end of the second transistor to provide a bias current for the power amplifier.
  7. 根据权利要求3所述的电路，所述控制电路至少包括运放电路；所述运放电路至少包括第一输入端和第二输入端；According to the circuit of claim 3, the control circuit at least comprises an operational amplifier circuit; the operational amplifier circuit at least comprises a first input terminal and a second input terminal;
    所述第二晶体管的第二端与所述第一输入端电连接，所述第三晶体管的第二端与所述第二输入端电连接，形成负反馈电路；其中，所述负反馈电路使所述第二晶体管的第二端的电压与所述第三晶体管的第二端的电压相同。The second end of the second transistor is electrically connected to the first input end, and the second end of the third transistor is electrically connected to the second input end, forming a negative feedback circuit; wherein the negative feedback circuit makes the voltage of the second end of the second transistor the same as the voltage of the second end of the third transistor.
  8. 根据权利要求3所述的电路，所述电流镜电路还包括控制晶体管；The circuit according to claim 3, wherein the current mirror circuit further comprises a control transistor;
    所述控制晶体管的第一端与控制电源电连接，所述控制晶体管的第二端接地，所述控制晶体管的第三端与所述第一晶体管的第二端电连接；所述控制晶体管用于对所述第 一晶体管的第二端的输入电流进行调节。The first end of the control transistor is electrically connected to the control power supply, the second end of the control transistor is grounded, and the third end of the control transistor is electrically connected to the second end of the first transistor; the control transistor is used to An input current is regulated at a second terminal of the transistor.
  9. 一种保护电路，所述保护电路包括权利要求1至8任一项所述的电流镜电路。A protection circuit, comprising the current mirror circuit according to any one of claims 1 to 8.
  10. 一种偏置电路，所述偏置电路包括权利要求1至8任一项所述的电流镜电路及偏置晶体管，所述电流镜电路的所述第二支路的输出端用于为所述偏置晶体管馈电。A bias circuit, comprising the current mirror circuit and a bias transistor as described in any one of claims 1 to 8, wherein the output end of the second branch of the current mirror circuit is used to feed the bias transistor.
  11. 一种电子设备，所述电子设备包括权利要求1至8任一项所述的电流镜电路。 An electronic device comprising the current mirror circuit according to any one of claims 1 to 8.
PCT/CN2024/070234 2022-12-31 2024-01-02 Current mirror circuit, protection circuit, bias circuit, and electronic device WO2024141108A1 (en)

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