WO2024125547A1 - 封装结构、电子设备和封装方法 - Google Patents

封装结构、电子设备和封装方法 Download PDF

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Publication number
WO2024125547A1
WO2024125547A1 PCT/CN2023/138395 CN2023138395W WO2024125547A1 WO 2024125547 A1 WO2024125547 A1 WO 2024125547A1 CN 2023138395 W CN2023138395 W CN 2023138395W WO 2024125547 A1 WO2024125547 A1 WO 2024125547A1
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WO
WIPO (PCT)
Prior art keywords
chip
packaging
metal ball
dielectric layer
electrically connected
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Application number
PCT/CN2023/138395
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English (en)
French (fr)
Inventor
金豆
Original Assignee
维沃移动通信有限公司
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Filing date
Publication date
Application filed by 维沃移动通信有限公司 filed Critical 维沃移动通信有限公司
Publication of WO2024125547A1 publication Critical patent/WO2024125547A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof

Definitions

  • the present application relates to the field of chip packaging technology, and in particular to a packaging structure, an electronic device and a packaging method.
  • the multiple chips when multiple chips are packaged, the multiple chips can be arranged in a vertical direction.
  • adjacent chips are interconnected through copper pillars, and multiple chips transmit data through the copper pillars.
  • the copper pillars need to occupy a certain vertical space, which makes the packaging structure thicker.
  • the present application aims to provide a packaging structure, an electronic device and a packaging method, which at least solve the problem of the large volume of the packaging structure.
  • an embodiment of the present application proposes a packaging structure, including a first packaging module and a second packaging module;
  • the first packaging module includes a first chip and a second chip, the first chip and the second chip are arranged along the thickness direction of the first chip, and the first chip is electrically connected to the second chip;
  • the second packaging module is arranged along the thickness direction with the first packaging module, the second packaging module includes a third chip and a fourth chip, the third chip and the fourth chip are arranged along the thickness direction, and the third chip and the fourth chip are electrically connected; the fourth chip is electrically connected to the first chip.
  • the present application embodiment provides an electronic device, including the package of the first aspect. structure.
  • an embodiment of the present application proposes a packaging method, which is used to package the packaging structure of the first aspect, and the packaging method includes: cutting a first wafer to obtain a first chip; arranging the first chip on a substrate; cutting a second wafer to obtain a second chip; bonding the second chip to the first chip to obtain a first packaging module; cutting a third wafer to obtain a third chip; bonding the third chip to a fourth chip on a fourth wafer; cutting the fourth wafer to obtain a second packaging module; arranging the first packaging module and the second packaging module in the thickness direction; and electrically connecting the first chip to the fourth chip.
  • the packaging structure provided in the present application includes a first packaging module and a second packaging module.
  • the first packaging module includes a first chip and a second chip
  • the second packaging module includes a third chip and a fourth chip.
  • the first chip and the second chip included in the first packaging module are bonded, and the third chip and the fourth chip included in the second packaging module are bonded. Then, the first packaging module and the second packaging module are connected, thereby modularizing the multiple chips in the packaging structure.
  • the first chip and the fourth chip located on both sides in the vertical direction can be connected to achieve electrical connection between the first packaging module and the second packaging module.
  • the electrical connection components between the first chip and the fourth chip can occupy the space where the second chip and the third chip are located, and there is no need to set up components for electrical connection between the second chip and the third chip, thereby reducing the occupation of the longitudinal space by the electrical connection components between the first packaging module and the second packaging module, reducing the thickness of the packaging module, and reducing the occupation of the longitudinal space by the packaging module, which is conducive to the thinness of the packaging module.
  • the electronic device provided in the present application includes the above-mentioned packaging structure, and the packaging method provided in the present application is used to manufacture the above-mentioned packaging structure. Therefore, the electronic device and packaging method provided in the present application have the beneficial effects of the above-mentioned packaging structure.
  • FIG1 is a schematic diagram of a packaging structure according to an embodiment of the present application.
  • FIG2 is a schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG3 is a second schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG4 is a third schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG5 is a second schematic diagram of a packaging structure according to an embodiment of the present application.
  • FIG6 is a fourth schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG7 is a fifth schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG8 is a sixth schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG9 is a seventh schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG10 is an eighth schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG11 is a ninth schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG12 is a tenth schematic diagram of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG13 is a schematic diagram eleven of a packaging process of a packaging structure according to an embodiment of the present application.
  • FIG. 14 is a flow chart of a packaging method according to an embodiment of the present application.
  • first or “second” in the specification and claims of this application may include one or more of the features explicitly or implicitly.
  • plural means two or more.
  • and/or in the specification and claims means at least one of the connected objects, and the character “/” generally means that the objects connected before and after are in an “or” relationship.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components.
  • the packaging structure includes a first packaging module 100 and a second packaging module 200;
  • the first packaging module 100 includes a first chip 110 and a second chip 120, the first chip 110 and the second chip 120 are arranged along the thickness direction of the first chip 110, and the first chip 110 is electrically connected to the second chip 120;
  • the second packaging module 200 is arranged along the thickness direction with the first packaging module 100, the second packaging module 200 includes a third chip 210 and a fourth chip 220, the third chip 210 and the fourth chip 220 are arranged along the thickness direction, and the third chip 210 and the fourth chip 220 are electrically connected;
  • the fourth chip 220 is electrically connected to the first chip 110.
  • the packaging structure includes a first packaging module 100 and a second packaging module 200.
  • the first packaging module 100 includes a first chip 110 and a second chip 120.
  • the second packaging module 200 includes a third chip 210 and a fourth chip 220.
  • the first chip 110 and the second chip 120 included in the first packaging module 100 are bonded, and the third chip 210 and the fourth chip 220 included in the second packaging module 200 are bonded.
  • the first packaging module 100 and the second packaging module 200 are connected, thereby modularizing the multiple chips in the packaging structure.
  • the first chip 110 and the fourth chip 220 located on both sides in the vertical direction can be connected to achieve electrical connection between the first packaging module 100 and the second packaging module 200. Since the electrical connection components between the first chip 110 and the fourth chip 220 can occupy the space where the second chip 120 and the third chip 210 are located when the first chip 110 and the fourth chip 220 are bonded, and there is no need to set up components for electrical connection between the second chip 120 and the third chip 210, thereby reducing the occupation of the longitudinal space by the electrical connection components between the first packaging module 100 and the second packaging module 200, reducing the thickness of the packaging module, and reducing the occupation of the longitudinal space by the packaging module, which is conducive to the thinness of the packaging module.
  • the first chip 110, the second chip 120, the third chip 210 and the fourth chip 220 are arranged in sequence.
  • the first chip 110, the second chip 120, the third chip 210 and the fourth chip 220 are arranged in the vertical direction, so that the signal transmission path between the chips is shorter and the transmission speed is faster, further improving the performance of the packaging module.
  • the packaging structure may further include a third packaging module, the third packaging module may include a fifth chip and a sixth chip, the fifth chip is electrically connected to the sixth chip, the sixth chip is electrically connected to the fourth chip 220 electrical connection.
  • the third packaging module may include a fifth chip and a sixth chip, the fifth chip is electrically connected to the sixth chip, the sixth chip is electrically connected to the fourth chip 220 electrical connection.
  • the packaging structure may further include a fourth packaging module or more packaging modules.
  • the first packaging module 100 may further include a seventh chip, which is electrically connected to the second chip 120 , and the first packaging module 100 may also include more chips.
  • the second packaging module 200 may also include other chips except the third chip 210 and the fourth chip 220 .
  • the second packaging module 200 includes three chips or four chips.
  • the first wafer 340 and the second wafer 342 are first cut to obtain the first chip 110 and the second chip 120, and the third wafer 344 is cut to obtain the third chip 210.
  • the third chip 210 is bonded to the fourth chip 220 in the wafer state, and after bonding, the fourth wafer 346 is cut to obtain the second packaging module 200.
  • the first chip 110 and the second chip 120 are then bonded to obtain the first packaging module 100, and then the first packaging module 100 is electrically connected to the second packaging module 200 to obtain the packaging structure.
  • the packaging structure also includes a first metal ball 302, a first side of the first metal ball 302 is connected to the first chip 110, and a second side is connected to the fourth chip 220, wherein the first side of the first metal ball 302 and the second side of the first metal ball 302 are two sides opposite to each other in the thickness direction.
  • the first chip 110 and the fourth chip 220 are connected via the first metal ball 302.
  • the first metal ball 302 can be mass-produced as a separate component. In the process of bonding the first chip 110 and the fourth chip 220, the first metal ball 302 can be fixed to the packaging structure, without the need to manufacture copper pillars and other components for electrical connection in the packaging structure through processes such as electroplating, thereby simplifying the packaging process of the packaging structure and reducing the difficulty of manufacturing the packaging structure. Furthermore, since the first metal ball 302 can be mass-produced separately, it does not need to occupy the processing time of the packaging structure, which speeds up the manufacturing speed of the packaging structure and improves the production efficiency of the packaging structure. The mass-produced first metal ball 302 can also reduce the material cost and process cost of the packaging structure.
  • the package structure further includes a first dielectric layer 304 and a first wiring layer 306; the first dielectric layer 304 is disposed between the first chip 110 and the second chip 120; the first wiring layer 306 is disposed on the first dielectric layer 304 and is connected to the first metal The ball 302 and the first chip 110 are electrically connected.
  • the first dielectric layer 304 is located between the first chip 110 and the second chip 120, the first wiring layer 306 is arranged on the first dielectric layer 304, the first wiring layer 306 is electrically connected to the first metal ball 302, and the first wiring layer 306 is electrically connected to the first chip 110, thereby realizing the electrical connection between the first metal ball 302 and the first chip 110, so that the first chip 110 can transmit data to the fourth chip 220 through the first metal ball 302.
  • a pad is provided on the first wiring layer 306 , and the first metal ball 302 is soldered to the pad of the first wiring layer 306 , thereby achieving connection between the first wiring layer 306 and the first metal ball 302 , and installation and positioning of the first wiring layer 306 on the first metal ball 302 .
  • the packaging structure also includes a first bump 308 and a second bump 310; the first bump 308 is arranged on a side of the first dielectric layer 304 close to the second chip 120 and is electrically connected to the first wiring layer 306; the second bump 310 is arranged on a side of the second chip 120 close to the first chip 110, is electrically connected to the second chip 120, and is in contact with the first bump 308.
  • the first bump 308 is disposed on a side of the first dielectric layer 304 close to the second chip 120, and is electrically connected to the first wiring layer 306, so that the first bump 308 is electrically connected to the first chip 110 through the first wiring layer 306.
  • the second bump 310 is disposed on a side of the second chip 120 close to the first chip 110, and is electrically connected to the second chip 120 and contacts the first bump 308, so as to achieve bonding between the first chip 110 and the second chip 120, and thus achieve signal transmission between the first chip 110 and the second chip 120.
  • first bump 308 and the second bump 310 may be micro bumps or copper pillars.
  • the package structure further includes a fifth bump 334 .
  • the fifth bump 334 is disposed on a side of the first chip 110 close to the first dielectric layer 304 and connected to the first wiring layer 306 .
  • An adhesive film 348 is further disposed on a side of the first chip 110 away from the first dielectric layer 304 , thereby facilitating bonding the first chip 110 to the substrate 338 to achieve wafer reconstruction.
  • the package structure further includes a fourth dielectric layer 336 , and the fourth dielectric layer 336 is disposed between the second bump 310 and the second chip 120 .
  • the package structure further includes a second metal ball 312, a second dielectric layer 314, a second wiring layer 316 and a third metal ball 318;
  • the metal ball 312 is arranged on the side of the first dielectric layer 304 close to the first chip 110 and is electrically connected to the first wiring layer 306;
  • the second dielectric layer 314 is arranged on the side of the first chip 110 away from the second chip 120;
  • the second wiring layer 316 is arranged on the second dielectric layer 314 and is electrically connected to the second metal ball 312;
  • the third metal ball 318 is arranged on the side of the second dielectric layer 314 away from the first chip 110 and is electrically connected to the second dielectric layer 314.
  • the second metal ball 312 is disposed on a side of the first dielectric layer 304 close to the first chip 110, and is electrically connected to the first wiring layer 306, so that the second metal ball 312 is electrically connected to the first chip 110 through the first wiring layer 306.
  • the second dielectric layer 314 is disposed on a side of the first chip 110 away from the second chip 120; the second wiring layer 316 is disposed on the second dielectric layer 314, and the second wiring layer 316 is electrically connected to the second metal ball 312, so that the second wiring layer 316 can be electrically connected to the first chip 110.
  • the third metal ball 318 is disposed on a side of the second dielectric layer 314 away from the first chip 110, and the third metal ball 318 is electrically connected to the second dielectric layer 314, so that the third metal ball 318 can be connected to the first chip 110, so that the first chip 110 can transmit data through the third metal ball 318.
  • third metal balls 318 which are arranged in an array on a side of the second dielectric layer 314 away from the first chip 110 to serve as pins of the packaging structure.
  • At least one of the first metal ball 302 , the second metal ball 312 , and the third metal ball 318 is a copper ball; or at least one of the first metal ball 302 , the second metal ball 312 , and the third metal ball 318 is a tin ball; or at least one of the first metal ball 302 , the second metal ball 312 , and the third metal ball 318 includes a copper core and a tin layer, and the tin layer covers the copper core.
  • the first metal ball 302, the second metal ball 312 or the third metal ball 318 can be a copper ball, a tin ball or a copper core ball.
  • the volume of the copper ball and the tin ball can be processed to a smaller size.
  • the copper core ball has a lower cost than the copper ball, and the copper core ball has better conductivity than the tin ball.
  • the packaging structure also includes a third dielectric layer 320 and a third wiring layer 322; the third dielectric layer 320 is arranged between the third chip 210 and the fourth chip 220; the third wiring layer 322 is arranged on the third dielectric layer 320, is electrically connected to the first metal ball 302, and is electrically connected to the fourth chip 220.
  • the third dielectric layer 320 is arranged between the third chip 210 and the fourth chip 220, and the third wiring layer 322 is arranged on the third dielectric layer 320.
  • the third wiring layer 322 is electrically connected to the first metal ball 302 and the fourth chip 220 at the same time, so that the fourth chip 220 can be electrically connected to the first chip 110 through the first metal ball 302, thereby realizing the bonding of the first chip 110 and the fourth chip 220.
  • the packaging structure also includes a third bump 324 and a fourth bump 326;
  • the third bump 324 is arranged on a side of the third chip 210 close to the fourth chip 220, and is electrically connected to the third chip 210;
  • the fourth bump 326 is arranged on a side of the third dielectric layer 320 close to the third chip 210, is electrically connected to the third wiring layer 322, and is in contact with the third bump 324.
  • the fourth bump 326 is disposed on a side of the third dielectric layer 320 close to the third chip 210 and is electrically connected to the third wiring layer 322, so that the fourth bump 326 is electrically connected to the fourth chip 220 through the third wiring layer 322.
  • the third bump 324 is disposed on a side of the third chip 210 close to the fourth chip 220 and is electrically connected to the third chip 210, and the third bump 324 is in contact with the fourth bump 326, so as to achieve bonding between the third chip 210 and the fourth chip 220, and further achieve signal transmission between the third chip 210 and the fourth chip 220.
  • the third bump 324 and the fourth bump 326 may be micro bumps or copper pillars.
  • the packaging structure further includes a packaging portion 328 , and the packaging portion 328 is coated on the first packaging module 100 and the second packaging module 200 .
  • the packaging portion 328 is coated on the first packaging module 100 and the second packaging module 200 to achieve packaging of the first packaging module 100 and the second packaging module 200. While achieving protection for the first packaging module 100 and the second packaging module 200, the heat dissipation rate of the first packaging module 100 and the second packaging module 200 is improved, the stability of the first packaging module 100 and the second packaging module 200 during operation is improved, and the service life of the first packaging module 100 and the second packaging module 200 is extended.
  • the packaging portion 328 can effectively protect the chip active area and prevent the chip active area from being bumped or damaged.
  • the packaging structure further includes a first colloid 330 and a second colloid 332 .
  • the first colloid 330 is filled in the first chip 110 and the second chip 120 .
  • the second colloid 332 is filled between the third chip 210 and the fourth chip 220 .
  • the first colloid 330 is filled between the first chip 110 and the second chip 120, and the second colloid 332 is filled between the third chip 210 and the fourth chip 220, so as to improve the packaging effect between the chips and avoid the packaging material being unable to be fully filled due to the small gap between the chips in the same packaging module.
  • the first glue 330 and the second glue 332 may be underfill glue.
  • the packaging structure provided by the present application can be packaged by the following packaging method.
  • the pads have been prepared on the substrate 338, and the pads are mainly used to fix the position of the first metal ball 302.
  • the fifth bumps 334 have been prepared on the first chip 110.
  • the first chip 110 has an adhesive film attached to the bottom and is fixed on the substrate 338 with the face facing upward.
  • wafer-level molding is performed, and after the molding compound is cured, grinding is performed to expose the surface of the first metal ball 302 and the fifth bump 334. Then, the first dielectric layer 304 and the first wiring layer 306 are prepared on the exposed surface, and the first wiring layer 306 realizes the interconnection between the first metal ball 302 and the first chip 110. Finally, the first bump 308 is prepared by electroplating process.
  • the second chip 120 faces downward and is bonded to the first chip 110 .
  • the first chip 110 and the second chip 120 are interconnected.
  • a first colloid 330 may be filled between the first chip 110 and the second chip 120 .
  • first metal balls 302 are arranged on the first wiring layer 306 .
  • the third chip 210 and the fourth chip 220 modules are bonded to the copper core ball.
  • the first chip 110, the second chip 120, the third chip 210 and the fourth chip 220 are interconnected.
  • the entire package body is encapsulated with a molding compound.
  • the package body is ground to thin the back substrate of the fourth chip 220 and remove the back plastic packaging material.
  • the substrate 338 is firstly removed by debonding, and then the first core is removed by grinding.
  • the back substrate of the chip 110 is removed, and the second metal ball 312 is exposed.
  • the third dielectric layer 320 and the third wiring layer 322 are prepared, and the third metal ball 318 is arranged. If the first chip 110 can still be thinned, the back substrate and the plastic packaging material of the fourth chip 220 can be removed again by grinding until the thickness meets the requirements. Finally, the package is cut into individual pieces by dicing.
  • the electronic device includes a packaging structure as described in any of the above embodiments, so the electronic device has all the beneficial effects of the packaging structure of any of the above embodiments.
  • the electronic device includes a mobile phone, a tablet computer, a laptop computer, a watch or a smart wristband.
  • the packaging method is used to package a packaging structure as in any of the above embodiments.
  • the packaging method includes:
  • Step 402 cutting the first wafer to obtain a first chip
  • Step 404 placing a first chip on a substrate
  • Step 406 cutting the second wafer to obtain a second chip
  • Step 408 bonding the second chip to the first chip to obtain a first packaging module
  • Step 410 cutting the third wafer to obtain a third chip
  • Step 412 bonding the third chip to the fourth chip on the fourth wafer
  • Step 414 cutting the fourth wafer to obtain a second packaging module
  • Step 416 arranging the first packaging module and the second packaging module in a thickness direction
  • Step 418 electrically connect the first chip to the fourth chip.
  • the first wafer and the second wafer are cut to obtain the first chip and the second chip, and the third wafer is cut to obtain the third chip.
  • the third chip is bonded to the fourth chip in the wafer state, and the fourth wafer is cut after bonding to obtain the second packaging module.
  • the first chip and the second chip are bonded to obtain the first packaging module, and then the first packaging module is electrically connected to the second packaging module to obtain the packaging structure.
  • the first chip and the fourth chip located on both sides in the vertical direction can be connected to each other, thereby realizing the electrical connection between the first package module and the second package module.
  • the electrical connection component between the first chip and the fourth chip can occupy the space where the second chip and the third chip are located, and There is no need to set up components for electrical connection between the second chip and the third chip, thereby reducing the longitudinal space occupied by the electrical connection components between the first packaging module and the second packaging module, reducing the thickness of the packaging module, and reducing the longitudinal space occupied by the packaging module, which is conducive to the lightweight and thinning of the packaging module.
  • the first chip When bonding the first packaging module, the first chip is attached to the substrate, and then the first wafer is reconstructed, so that the subsequent packaging process is all carried out in the wafer state, further improving the packaging efficiency of the packaging structure.
  • the substrate is a glass carrier.
  • the packaging method before arranging the first packaging module and the second packaging module in the thickness direction, the packaging method also includes: preparing a first dielectric layer on the first chip; preparing a first wiring layer on the first dielectric layer; arranging a first metal ball on the first wiring layer; preparing a third dielectric layer on the fourth chip; preparing a third wiring layer on the third dielectric layer; electrically connecting the first chip to the fourth chip includes connecting the third wiring layer to the first metal ball.
  • the first dielectric layer is located between the first chip and the second chip, the first wiring layer is arranged on the first dielectric layer, electrically connected to the first metal ball, and electrically connected to the first chip, thereby realizing the electrical connection between the first metal ball and the first chip;
  • the third dielectric layer is arranged between the third chip and the fourth chip, the third wiring layer is arranged on the third dielectric layer, and the third wiring layer is electrically connected to the first metal ball and the fourth chip at the same time, thereby allowing the fourth chip to be electrically connected to the first chip through the first metal ball, realizing the bonding of the first chip and the fourth chip, thereby allowing the first chip to transfer data to the fourth chip through the first metal ball.
  • the packaging method before bonding the second chip to the first chip, the packaging method further includes: arranging second metal balls on the substrate, the second metal balls being electrically connected to the first wiring layer.
  • the packaging method further includes: packaging the first packaging module with the second packaging module; separating the substrate from the first packaging module; preparing a second dielectric layer on the first packaging module; preparing a second wiring layer on the second dielectric layer, the second wiring layer being electrically connected to the second metal ball; arranging a third metal ball on the second dielectric layer, the third metal ball being electrically connected to the second wiring layer; grinding the packaged first packaging module and the second packaging module; and cutting the packaged first packaging module and the second packaging module to obtain a packaging structure.
  • a second metal ball is arranged on the substrate, and the second metal ball is electrically connected to the first wiring layer, so that the second metal ball can be pre-buried in the package structure after packaging.
  • the first dielectric layer is electrically connected to the first wiring layer on the side close to the first chip, so that the second metal ball is electrically connected to the first chip through the first wiring layer.
  • the second dielectric layer is arranged on the side of the first chip away from the second chip; the second wiring layer is arranged on the second dielectric layer, and the second wiring layer is electrically connected to the second metal ball, so that the second wiring layer can be electrically connected to the first chip.
  • the third metal ball is arranged on the side of the second dielectric layer away from the first chip, and the third metal ball is electrically connected to the second dielectric layer, so that the third metal ball can be connected to the first chip, so that the first chip can transmit data through the third metal ball.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

本申请公开了一种封装结构、电子设备和封装方法，封装结构，包括第一封装模组和第二封装模组；第一封装模组包括第一芯片和第二芯片，第一芯片和第二芯片沿第一芯片的厚度方向排列，且第一芯片与第二芯片电连接；第二封装模组与第一封装模组沿厚度方向排列，第二封装模组包括第三芯片和第四芯片，第三芯片和第四芯片沿厚度方向排列，且第三芯片和第四芯片电连接；第四芯片与第一芯片电连接。

Description

封装结构、电子设备和封装方法
交叉引用
本发明要求在2022年12月16日提交中国专利局、申请号为202211623125.0、发明名称为“封装结构、电子设备和封装方法”的中国专利申请的优先权，该申请的全部内容通过引用结合在本发明中。
技术领域
本申请涉及芯片封装技术领域，具体而言，涉及一种封装结构、电子设备和封装方法。
背景技术
相关技术中，多个芯片在进行封装时，多个芯片可沿垂直方向进行布置。在沿与芯片垂直的方向布置多个芯片时，相邻的芯片之间通过铜柱进行互联，多个芯片通过铜柱进行数据传输。但在该种芯片的封装结构中，铜柱需要占用一定纵向上的空间，进而使得封装结构的厚度较大。
发明内容
本申请旨在提供一种封装结构、电子设备和封装方法，至少解决封装结构的体积较大的问题。
为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请实施例提出了一种封装结构，包括第一封装模组和第二封装模组；第一封装模组包括第一芯片和第二芯片，第一芯片和第二芯片沿第一芯片的厚度方向排列，且第一芯片与第二芯片电连接；第二封装模组与第一封装模组沿厚度方向排列，第二封装模组包括第三芯片和第四芯片，第三芯片和第四芯片沿厚度方向排列，且第三芯片和第四芯片电连接；第四芯片与第一芯片电连接。
第二方面，本申请实施例提出了一种电子设备，包括第一方面的封装 结构。
第三方面，本申请实施例提出了一种封装方法，封装方法用于封装第一方面的封装结构，封装方法包括：切割第一晶圆，以得到第一芯片；将第一芯片布置于基板上；切割第二晶圆，以得到第二芯片；将第二芯片与第一芯片键合，以得到第一封装模组；切割第三晶圆，以得到第三芯片；将第三芯片与第四晶圆上的第四芯片键合；切割第四晶圆，以得到第二封装模组；将第一封装模组与第二封装模组厚度方向布置；将第一芯片与第四芯片电连接。
本申请所提供的封装结构包括第一封装模组和第二封装模组，第一封装模组包括第一芯片和第二芯片，第二封装模组包括第三芯片和第四芯片，第一封装模组包括的第一芯片和第二芯片进行键合，第二封装模组包括的第三芯片和第四芯片进行键合，然后再将第一封装模组和第二封装模组连接，进而将封装结构中的多个芯片进行模块化。
在将第一封装模组和第二封装模组进行连接时，可通过位于垂直方向上两侧的第一芯片和第四芯片进行连接，进而实现第一封装模组和第二封装模组的电连接。由于第一芯片与第四芯片在进行键合时，第一芯片和第四芯片之间的电连接部件可占用第二芯片和第三芯片所在的空间，并且在第二芯片与第三芯片之间无需再设置用于电连接的部件，进而减少了第一封装模组和第二封装模组之间的电连接部件对纵向空间的占用，降低封装模组的厚度，减小封装模组对纵向空间的占用，有利于封装模组的轻薄化。
本申请所提供的电子设备包括上述封装结构，本申请所提供的封装方法用于制造上述封装结构，因此本申请所提供的电子设备和封装方法就具备上述封装结构的有益效果。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1是根据本申请实施例的封装结构的示意图之一；
图2是根据本申请实施例的封装结构的封装过程的示意图之一；
图3是根据本申请实施例的封装结构的封装过程的示意图之二；
图4是根据本申请实施例的封装结构的封装过程的示意图之三；
图5是根据本申请实施例的封装结构的示意图之二；
图6是根据本申请实施例的封装结构的封装过程的示意图之四；
图7是根据本申请实施例的封装结构的封装过程的示意图之五；
图8是根据本申请实施例的封装结构的封装过程的示意图之六；
图9是根据本申请实施例的封装结构的封装过程的示意图之七；
图10是根据本申请实施例的封装结构的封装过程的示意图之八；
图11是根据本申请实施例的封装结构的封装过程的示意图之九；
图12是根据本申请实施例的封装结构的封装过程的示意图之十；
图13是根据本申请实施例的封装结构的封装过程的示意图之十一；
图14是根据本申请实施例的封装方法的流程图。
附图标记：
100第一封装模组，110第一芯片，120第二芯片，200第二封装模组，
210第三芯片，220第四芯片，302第一金属球，304第一介电层，306第一布线层，308第一凸块，310第二凸块，312第二金属球，314第二介电层，316第二布线层，318第三金属球，320第三介电层，322第三布线层，324第三凸块，326第四凸块，328封装部，330第一胶体，332第二胶体，334第五凸块，336第四介电层，338基板，340第一晶圆，342第二晶圆，344第三晶圆，346第四晶圆，348粘结膜。
具体实施方式
下面将详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
下面结合图1至图14描述根据本申请实施例的封装结构、电子设备和封装方法。
如图1所示，根据本申请一些实施例的封装结构，包括第一封装模组100和第二封装模组200；第一封装模组100包括第一芯片110和第二芯片120，第一芯片110和第二芯片120沿第一芯片110的厚度方向排列，且第一芯片110与第二芯片120电连接；第二封装模组200与第一封装模组100沿厚度方向排列，第二封装模组200包括第三芯片210和第四芯片220，第三芯片210和第四芯片220沿厚度方向排列，且第三芯片210和第四芯片220电连接；第四芯片220与第一芯片110电连接。
在该实施例中，封装结构包括第一封装模组100和第二封装模组200，第一封装模组100包括第一芯片110和第二芯片120，第二封装模组200包括第三芯片210和第四芯片220，第一封装模组100包括的第一芯片110和第二芯片120进行键合，第二封装模组200包括的第三芯片210和第四芯片220进行键合，然后再将第一封装模组100和第二封装模组200连接，进而将封装结构中的多个芯片进行模块化。
在将第一封装模组100和第二封装模组200进行连接时，可通过位于垂直方向上两侧的第一芯片110和第四芯片220进行连接，进而实现第一封装模组100和第二封装模组200的电连接。由于第一芯片110与第四芯片220在进行键合时，第一芯片110和第四芯片220之间的电连接部件可占用第二芯片120和第三芯片210所在的空间，并且在第二芯片120与第三芯片210之间无需再设置用于电连接的部件，进而减少了第一封装模组100和第二封装模组200之间的电连接部件对纵向空间的占用，降低封装模组的厚度，减小封装模组对纵向空间的占用，有利于封装模组的轻薄化。
具体地，在纵向上，第一芯片110、第二芯片120、第三芯片210和第四芯片220依次排列。第一芯片110、第二芯片120、第三芯片210和第四芯片220沿纵向布置，使得芯片之间信号传递的路径更短，传递速度更快，进一步提升封装模组的性能。
进一步地，封装结构还可包括第三封装模组，第三封装模组可包括第五芯片和第六芯片，第五芯片与第六芯片电连接，第六芯片与第四芯片 220电连接。
封装结构还可包括第四封装模组或更多的封装模组。
进一步地，第一封装模组100还可包括第七芯片，第七芯片与第二芯片120电连接，第一封装模组100也可包括更多的芯片。
第二封装模组200也可包括除第三芯片210和第四芯片220以外的其余芯片，例如第二封装模组200包括三个芯片或四个芯片。
具体地，如图2所示，在对封装结构进行封装时，先对第一晶圆340和第二晶圆342进行切割，以得到第一芯片110和第二芯片120，切割第三晶圆344得到第三芯片210。如图3所示，将第三芯片210与处于晶圆状态的第四芯片220进行键合，键合后对第四晶圆346进行切合，得到第二封装模组200。如图4所示，然后将第一芯片110和第二芯片120键合，得到第一封装模组100，再将第一封装模组100与第二封装模组200电连接，进而得到封装结构。
根据本申请的一些实施例，如图1和图5所示，封装结构还包括第一金属球302，第一金属球302的第一侧与第一芯片110连接，第二侧与第四芯片220连接，其中，第一金属球302的第一侧和第一金属球302的第二侧为在厚度方向上相背的两侧。
在该实施例中，第一芯片110和第四芯片220通过第一金属球302连接，第一金属球302可作为单独部件进行批量生产，在对第一芯片110和第四芯片220进行键合的过程中，将第一金属球302固定于封装结构上即可，无需通过电镀等工艺在封装结构内制造铜柱等用于电连接的部件，进而简化了封装结构的封装工艺，降低封装结构的制造难度。并且由于第一金属球302可单独进行批量生产，无需占用封装结构的加工时间，加快的封装结构的制造速度，提升了封装结构的生产效率。批量生产的第一金属球302还可降低封装结构的材料成本和工艺成本
根据本申请的一些实施例，如图1和图5所示，封装结构还包括第一介电层304和第一布线层306；第一介电层304设置于第一芯片110和第二芯片120之间；第一布线层306设置于第一介电层304上，与第一金属 球302及第一芯片110电连接。
在该实施例中，第一介电层304位于第一芯片110和第二芯片120之间，第一布线层306设置于第一介电层304上，第一布线层306与第一金属球302电连接，且第一布线层306与第一芯片110电连接，进而实现第一金属球302与第一芯片110的电连接，使得第一芯片110可通过第一金属球302向第四芯片220传递数据。
进一步地，第一布线层306上设置有焊盘，第一金属球302焊接于第一布线层306的焊盘上，进而实现第一布线层306与第一金属球302的连接，以及第一布线层306对第一金属球302的安装和定位。
根据本申请的一些实施例，如图1和图5所示，封装结构还包括第一凸块308和第二凸块310；第一凸块308设置于第一介电层304靠近第二芯片120的一侧，与第一布线层306电连接；第二凸块310设置于第二芯片120靠近第一芯片110的一侧，与第二芯片120电连接，且与第一凸块308相接触。
在该实施例中，第一凸块308设置于第一介电层304靠近第二芯片120的一侧，与第一布线层306电连接，进而使得第一凸块308通过第一布线层306与第一芯片110电连接。第二凸块310设置于第二芯片120靠近第一芯片110的一侧，与第二芯片120电连接，且与第一凸块308相接触，实现第一芯片110与第二芯片120的键合，进而实现第一芯片110与第二芯片120之间的信号传递。
进一步地，第一凸块308和第二凸块310可为微凸块，也可为铜柱。
进一步地，封装结构还包括第五凸块334，第五凸块334设置于第一芯片110靠近第一介电层304的一侧，且与第一布线层306连接。
第一芯片110远离第一介电层304的一侧还设置有粘结膜348，进而便于将第一芯片110粘接于基板338上，实现晶圆的重构。
进一步地，封装结构还包括第四介电层336，第四介电层336设置于第二凸块310与第二芯片120之间。
根据本申请的一些实施例，如图1和图5所示，封装结构还包括第二金属球312、第二介电层314、第二布线层316和第三金属球318；第二 金属球312设置于第一介电层304靠近第一芯片110的一侧，与第一布线层306电连接；第二介电层314设置于第一芯片110远离第二芯片120的一侧；第二布线层316设置于第二介电层314，与第二金属球312电连接；第三金属球318设置于第二介电层314远离第一芯片110的一侧，与第二介电层314电连接。
在该实施例中，第二金属球312设置于第一介电层304靠近第一芯片110的一侧，与第一布线层306电连接，使得第二金属球312通过第一布线层306与第一芯片110电连接。第二介电层314设置于第一芯片110远离第二芯片120的一侧；第二布线层316设置于第二介电层314，第二布线层316与第二金属球312电连接，进而使得第二布线层316能够与第一芯片110进行电连接。第三金属球318设置于第二介电层314远离第一芯片110的一侧，第三金属球318与第二介电层314电连接，使得第三金属球318能够与第一芯片110连接，进而使得第一芯片110可通过第三金属球318传递数据。
进一步地，第三金属球318的数量为多个，多个第三金属球318在第二介电层314远离第一芯片110的一侧呈阵列式排列，以作为封装结构的针脚。
根据本申请的一些实施例，如图1和图5所示，第一金属球302、第二金属球312和第三金属球318的至少一个为铜球；或第一金属球302、第二金属球312和第三金属球318的至少一个为锡球；或第一金属球302、第二金属球312和第三金属球318的至少一个包括铜球心和锡层，锡层包覆于铜球心。
在该实施例中，第一金属球302、第二金属球312或第三金属球318可为铜球，可为锡球，也可为铜核球。铜球和锡球的体积可加工至较小的尺寸，铜核球与铜球相比，成本更低，铜核球与锡球相比，导电性更好。
根据本申请的一些实施例，如图1和图5所示，封装结构还包括第三介电层320和第三布线层322；第三介电层320设置于第三芯片210和第四芯片220之间；第三布线层322设置于第三介电层320上，与第一金属球302电连接，与第四芯片220电连接。
在该实施例中，第三介电层320设置于第三芯片210和第四芯片220之间，第三布线层322设置于第三介电层320上，第三布线层322同时与第一金属球302和第四芯片220电连接，进而使得第四芯片220可通过第一金属球302与第一芯片110电连接，实现第一芯片110与第四芯片220的键合。
根据本申请的一些实施例，如图1和图5所示，封装结构还包括第三凸块324和第四凸块326；第三凸块324设置于第三芯片210靠近第四芯片220的一侧，与第三芯片210电连接；第四凸块326设置于第三介电层320靠近第三芯片210的一侧，与第三布线层322电连接，且与第三凸块324相接触。
在该实施例中，第四凸块326设置于第三介电层320靠近第三芯片210的一侧，与第三布线层322电连接，使得第四凸块326通过第三布线层322与第四芯片220电连接。第三凸块324设置于第三芯片210靠近第四芯片220的一侧，与第三芯片210电连接，且第三凸块324与第四凸块326相接触，实现第三芯片210与第四芯片220的键合，进而实现第三芯片210与第四芯片220之间信号的传递。
进一步地，第三凸块324和第四凸块326可为微凸块，也可为铜柱。
根据本申请的一些实施例，如图1和图5所示，封装结构还包括封装部328，封装部328包覆于第一封装模组100和第二封装模组200。
在该实施例中，封装部328包覆于第一封装模组100和第二封装模组200，实现对第一封装模组100和第二封装模组200的封装，在实现对第一封装模组100和第二封装模组200的保护的同时，提升第一封装模组100和第二封装模组200的散热速率，提升第一封装模组100和第二封装模组200在工作中的稳定性，延长第一封装模组100和第二封装模组200的使用寿命。
并且封装部328可以有效保护芯片有源区，防止芯片有源区磕碰或损坏。
根据本申请的一些实施例，如图5所示，封装结构还包括第一胶体330和第二胶体332；第一胶体330填充于第一芯片110与第二芯片120 之间；第二胶体332填充于第三芯片210与第四芯片220之间。
在该实施例中，第一胶体330填充于第一芯片110与第二芯片120之间，第二胶体332填充于第三芯片210与第四芯片220之间，提升芯片之间的封装效果，避免因同一封装模组的芯片之间的间隙较小而使得封装料无法充分填充。
第一胶体330和第二胶体332可为底部填充胶。
根据本申请的一些实施例，本申请所提供的封装结构可通过如下封装方法进行封装。
如图6所示，在布置第一金属球302和第一芯片110与第二芯片120键合前，基板338上已完成焊盘的制备，焊盘主要作用是用于第一金属球302的位置固定，第一芯片110上已完成第五凸块334制备。第一芯片110底部贴有粘接膜，面向上固定在基板338上。
如图7所示，进行晶圆级塑封，塑封料完成固化后进行磨片，磨片的目的是露出第一金属球302及第五凸块334表面。然后在其露出的表面制备第一介电层304和第一布线层306，第一布线层306实现第一金属球302和第一芯片110的互连。最后通过电镀工艺，制备第一凸块308。
如图8所示，第二芯片120面向下和第一芯片110进行键合，完成键合后，第一芯片110和第二芯片120实现互连。另外，可以选择在第一芯片110和第二芯片120之间填充第一胶体330。
如图9所示，在第一布线层306上布置第一金属球302。
如图10所示，将第三芯片210和第四芯片220模块和铜核球进行键合。此时，完成键合后，第一芯片110、第二芯片120、第三芯片210和第四芯片220实现互联。
如图11所示，使用塑封料对整个封装体进行塑封。
如图12所示，对封装体进行磨片，减薄第四芯片220背面衬底和去除背部塑封料。
如图13所示，先进行解键合去除基板338，然后进行磨片去除第一芯 片110背部衬底，并且露出第二金属球312。紧接着进行第三介电层320和第三布线层322制备，布置第三金属球318。如第一芯片110仍可减薄，可进行磨片再次去除第四芯片220背部衬底和塑封料，直至厚度满足要求。最后进行划片，将封装体切成单颗。
根据本申请一些实施例的电子设备，包括如上述任一实施例的封装结构，因此该电子设备具备上述任一实施例的封装结构的全部有益效果。
具体地，电子设备包括手机、平板电脑、笔记本电脑、手表或智能腕带。
根据本申请一些实施例的封装方法，封装方法用于封装如上述任一实施例的封装结构，如图14所示，封装方法包括：
步骤402，切割第一晶圆，以得到第一芯片；
步骤404，将第一芯片布置于基板上；
步骤406，切割第二晶圆，以得到第二芯片；
步骤408，将第二芯片与第一芯片键合，以得到第一封装模组；
步骤410，切割第三晶圆，以得到第三芯片；
步骤412，将第三芯片与第四晶圆上的第四芯片键合；
步骤414，切割第四晶圆，以得到第二封装模组；
步骤416，将第一封装模组与第二封装模组厚度方向布置；
步骤418，将第一芯片与第四芯片电连接。
在该实施例中，先对第一晶圆和第二晶圆进行切割，以得到第一芯片和第二芯片，切割第三晶圆得到第三芯片。将第三芯片与处于晶圆状态的第四芯片进行键合，键合后对第四晶圆进行切合，得到第二封装模组。然后将第一芯片和第二芯片键合，得到第一封装模组，再将第一封装模组与第二封装模组电连接，进而得到封装结构。
在将第一封装模组和第二封装模组进行连接时，可通过位于垂直方向上两侧的第一芯片和第四芯片进行连接，进而实现第一封装模组和第二封装模组的电连接。由于第一芯片与第四芯片在进行键合时，第一芯片和第四芯片之间的电连接部件可占用第二芯片和第三芯片所在的空间，并且在 第二芯片与第三芯片之间无需再设置用于电连接的部件，进而减少了第一封装模组和第二封装模组之间的电连接部件对纵向空间的占用，降低封装模组的厚度，减小封装模组对纵向空间的占用，有利于封装模组的轻薄化。
在对第一封装模组进行键合时，将第一晶片贴合于基板上，进而重构第一晶圆，使得后续的封装过程全部在晶圆状态下进行，进一步提升封装结构的封装效率。
进一步地，基板为玻璃载体。
根据本申请的一些实施例，在将第一封装模组与第二封装模组厚度方向布置之前，封装方法还包括：在第一芯片上制备第一介电层；在第一介电层上制备第一布线层；在第一布线层上布置第一金属球；在第四芯片上制备第三介电层；在第三介电层上制备第三布线层；将第一芯片与第四芯片电连接包括将第三布线层与第一金属球连接。
在该实施例中，第一介电层位于第一芯片和第二芯片之间，第一布线层设置于第一介电层上，与第一金属球电连接，与第一芯片电连接，进而实现第一金属球与第一芯片的电连接；第三介电层设置于第三芯片和第四芯片之间，第三布线层设置于第三介电层上，第三布线层同时与第一金属球和第四芯片电连接，进而使得第四芯片可通过第一金属球与第一芯片电连接，实现第一芯片与第四芯片的键合，进而使得第一芯片可通过第一金属球向第四芯片传递数据。
根据本申请的一些实施例，在将第二芯片与第一芯片键合之前，封装方法还包括：在基板上布置第二金属球，二金属球与第一布线层电连接。
在将第一芯片与第四芯片电连接之后，封装方法还包括：将第一封装模组与第二封装模组封装；将基板与第一封装模组分离；在第一封装模组上制备第二介电层；在第二介电层上制备第二布线层，第二布线层与第二金属球电连接；在第二介电层上布置第三金属球，第三金属球与第二布线层电连接；磨削封装后的第一封装模组与第二封装模组；切割封后的第一封装模组与第二封装模组，以得到封装结构。
在该实施例中，在基板上布置第二金属球，二金属球与第一布线层电连接，使得第二金属球能够预埋于封装后的封装结构内。第二金属球设置 于第一介电层靠近第一芯片的一侧，与第一布线层电连接，使得第二金属球通过第一布线层与第一芯片电连接。第二介电层设置于第一芯片远离第二芯片的一侧；第二布线层设置于第二介电层，第二布线层与第二金属球电连接，进而使得第二布线层能够与第一芯片进行电连接。第三金属球设置于第二介电层远离第一芯片的一侧，第三金属球与第二介电层电连接，使得第三金属球能够与第一芯片连接，进而使得第一芯片可通过第三金属球传递数据。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
尽管已经示出和描述了本申请的实施例，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (14)

  1. 一种封装结构，包括：
    第一封装模组，所述第一封装模组包括第一芯片和第二芯片，所述第一芯片和所述第二芯片沿所述第一芯片的厚度方向排列，且所述第一芯片与所述第二芯片电连接；
    第二封装模组，所述第二封装模组与所述第一封装模组沿所述厚度方向排列，所述第二封装模组包括第三芯片和第四芯片，所述第三芯片和所述第四芯片沿所述厚度方向排列，且所述第三芯片和所述第四芯片电连接；
    所述第四芯片与所述第一芯片电连接。
  2. 根据权利要求1所述的封装结构，其中，还包括：
    第一金属球，所述第一金属球的第一侧与所述第一芯片连接，第二侧与所述第四芯片连接；
    其中，所述第一金属球的第一侧和所述第一金属球的第二侧为在所述厚度方向上相背的两侧。
  3. 根据权利要求2所述的封装结构，其中，还包括：
    第一介电层，所述第一介电层设置于所述第一芯片和所述第二芯片之间；
    第一布线层，所述第一布线层设置于所述第一介电层上，与所述第一金属球及所述第一芯片电连接。
  4. 根据权利要求3所述的封装结构，其中，还包括：
    第一凸块，所述第一凸块设置于所述第一介电层靠近所述第二芯片的一侧，与所述第一布线层电连接；
    第二凸块，所述第二凸块设置于所述第二芯片靠近所述第一芯片的一侧，与所述第二芯片电连接，且与所述第一凸块相接触。
  5. 根据权利要求3所述的封装结构，其中，还包括：
    第二金属球，所述第二金属球设置于所述第一介电层靠近所述第一芯片的一侧，与所述第一布线层电连接；
    第二介电层，所述第二介电层设置于所述第一芯片远离所述第二芯片的一侧；
    第二布线层，所述第二布线层设置于所述第二介电层，与所述第二金属球电连接；
    第三金属球，所述第三金属球设置于所述第二介电层远离所述第一芯片的一侧，与所述第二介电层电连接。
  6. 根据权利要求5所述的封装结构，其中，所述第一金属球、所述第二金属球和所述第三金属球的至少一个为铜球；或
    所述第一金属球、所述第二金属球和所述第三金属球的至少一个为锡球；或
    所述第一金属球、所述第二金属球和所述第三金属球的至少一个包括铜球心和锡层，所述锡层包覆于所述铜球心。
  7. 根据权利要求2所述的封装结构，其中，还包括：
    第三介电层，所述第三介电层设置于所述第三芯片和所述第四芯片之间；
    第三布线层，所述第三布线层设置于所述第三介电层上，与所述第一金属球电连接，与所述第四芯片电连接。
  8. 根据权利要求7所述的封装结构，其中，还包括：
    第三凸块，所述第三凸块设置于所述第三芯片靠近所述第四芯片的一侧，与所述第三芯片电连接；
    第四凸块，所述第四凸块设置于所述第三介电层靠近所述第三芯片的一侧，与所述第三布线层电连接，且与所述第三凸块相接触。
  9. 根据权利要求1至8中任一项所述的封装结构，其中，还包括：
    封装部，所述封装部包覆于所述第一封装模组和所述第二封装模组。
  10. 根据权利要求1至8中任一项所述的封装结构，其中，还包括：
    第一胶体，所述第一胶体填充于所述第一芯片与所述第二芯片之间；
    第二胶体，所述第二胶体填充于所述第三芯片与所述第四芯片之间。
  11. 一种电子设备，包括如权利要求1至10中任一项所述的封装结构。
  12. 一种封装方法，所述封装方法用于封装如权利要求1至10中任一项所述的封装结构，所述封装方法包括：
    切割第一晶圆，以得到所述第一芯片；
    将所述第一芯片布置于基板上；
    切割第二晶圆，以得到所述第二芯片；
    将所述第二芯片与所述第一芯片键合，以得到所述第一封装模组；
    切割第三晶圆，以得到所述第三芯片；
    将所述第三芯片与第四晶圆上的所述第四芯片键合；
    切割所述第四晶圆，以得到所述第二封装模组；
    将所述第一封装模组与所述第二封装模组所述厚度方向布置；
    将所述第一芯片与所述第四芯片电连接。
  13. 根据权利要求12所述的封装方法，其中，在所述将所述第一封装模组与所述第二封装模组所述厚度方向布置之前，所述封装方法还包括：
    在所述第一芯片上制备第一介电层；
    在所述第一介电层上制备第一布线层；
    在所述第一布线层上布置第一金属球；
    在所述第四芯片上制备第三介电层；
    在所述第三介电层上制备第三布线层；
    所述将所述第一芯片与所述第四芯片电连接包括将所述第三布线层与所述第一金属球连接。
  14. 根据权利要求13所述的封装方法，其中，在所述将所述第二芯片与所述第一芯片键合之前，所述封装方法还包括：
    在所述基板上布置第二金属球，所述二金属球与所述第一布线层电连接；
    在所述将所述第一芯片与所述第四芯片电连接之后，所述封装方法还包括：
    将所述第一封装模组与所述第二封装模组封装；
    将所述基板与所述第一封装模组分离；
    在所述第一封装模组上制备第二介电层；
    在所述第二介电层上制备第二布线层，所述第二布线层与第二金属球电连接；
    在所述第二介电层上布置第三金属球，所述第三金属球与所述第二布线层电连接；
    磨削封装后的所述第一封装模组与所述第二封装模组；
    切割封后的所述第一封装模组与所述第二封装模组，以得到所述封装结构。
PCT/CN2023/138395 2022-12-16 2023-12-13 封装结构、电子设备和封装方法 WO2024125547A1 (zh)

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