WO2024118642A1

WO2024118642A1 - Manufacturable gallium containing electronic devices

Info

Publication number: WO2024118642A1
Application number: PCT/US2023/081408
Authority: WO
Inventors: James W. Raring; Nicholas J. Pfister
Original assignee: Kyocera Sld Laser, Inc.
Priority date: 2022-11-30
Filing date: 2023-11-28
Publication date: 2024-06-06

Abstract

Electronic devices are formed on donor substrates and transferred to carrier substrates using bonding regions on the electronic devices and bonding the bonding regions to a carrier substrate. The transfer process may include forming anchors and removing sacrificial regions.

Description

MANUFACTURABLE GALLIUM CONTAINING ELECTRONIC DEVICES

BACKGROUND

[0001] Devices based on wide bandgap III-V semiconductor materials such as gallium nitride (GaN) play a major role in our modem world. Examples of such semiconductor devices include light emitting devices such as light emitting diodes and laser diodes, electronic devices such as Schottky diodes, p-n diodes, bipolar junction transistors, field effect transistors, metal-oxide-semiconductor field-effect transistors, insulated gate bipolar transistors, high electron mobility transistors, and heterojunction bipolar transistors to name a few, along with light absorbing devices such as solar cells.

[0002] Semiconductor power electronic devices are a key class of semiconductor devices that hugely affect the world we live in. Power electronic devices may be used as switches or as amplifiers. The first gallium nitride metal semiconductor field-effect transistors (GaN MESFET) were experimentally demonstrated in 1993 and they are being actively developed. Other devices include p-n junction diodes, Schottky diodes, field effect transistors (FET), junction field effect transistors (JFET), insulated gate bipolar transistors (IGBT), heterojunction bipolar transistors (HBT), and high electron mobility transistors (HEMT). Such devices can be deployed in many applications such as in automobiles, hybrid electric automobiles, cell phones, iphones, ipads, computers, and others.

[0003] In 2010 the first enhancement mode gallium nitride transistors became generally available. These devices were designed to replace power MOSFETs in applications where switching speed or power conversion efficiency is critical. These transistors, also called eGaN FETs, are built by growing a thin layer of GaN on top of a standard silicon wafer. This allows the eGaN FETs to maintain costs similar to silicon power MOSFETs, but with the superior electrical performance GaN.

SUMMARY

[0004] Embodiments of the invention provide electronic semiconductor devices based on high quality gallium and nitrogen containing epitaxial materials that are pseudomorphically grown on native gallium and nitrogen containing substrates such as GaN substrates or foreign substrates. By using, as an example, a selective etch process such as a photo electrochemical (PEC) etch combined with a bonding process, at least a portion of an epitaxial material is transferred to a carrier wafer. Subsequently, the carrier wafer with the bonded epitaxial material may be subjected to subsequent processing steps to form semiconductor devices including electronic devices such as diode or transistor devices, Schottky diodes, p-n diodes, transistors, field effect transistors, bipolar junction transistors, high electron mobility transistors, or solar cell devices. In other embodiments the semiconductor devices may be fully or partially formed in the epitaxial material before transfer to the carrier wafer or to an integrated circuit. In other embodiments, different types of semiconductor devices are configured on a common carrier using the selective bonding and etching process to form an integrated device. What follows is a general description of the typical configuration and fabrication of some exemplary electronic devices.

[0005] The carrier wafer is designed to receive the electronic devices. The carrier wafer may be comprised of an interconnect network configured to enable addressability of the electronic devices. Any relevant interconnect schemes, configurations, and/or processes could be taken from existing technologies and applied to the present invention.

[0006] The present invention enables a highly manufacturable and cost-efficient process for producing electronic devices not readily possible with prior art. Specifically, the current invention allows for a wafer level transfer process from a donor wafer to a common carrier wafer forming the electronic device. Since it is a wafer level process, thousands, tens of thousands, or hundreds of thousands of electronic devices can be transferred in one process step (depending on wafer size and pitch) and hence avoiding one-by-one pick and place techniques. This advantage can enable high throughput for low cost and high alignment tolerances for tight packing of the electronic devices. Moreover, since it is a selective transfer process from the donor to the carrier and the pitch of the electronic devices from the donor wafer to the carrier wafer can be expanded, a much higher density of electronic devices can be formed on single device type donor wafers than the final density of that single device type as expanded on the carrier wafer. For example, a donor wafer may be prepared with a device pitch of X. At the transfer step to the first carrier wafer, only 1/3 of the electronic devices may be transferred to the carrier wafer at a pitch of X/3, such that the resulting donor wafer has a repeating array different electronic devices spaced from each other by X but spaced from their next nearest neighbor with the same device type by X/3. The same sequence can be performed on a second and a third carrier wafer or on a second and third location on the first carrier wafer if the carrier wafer is larger than the donor wafer. This die expansion or transferring at a larger pitch enables an increased use of epitaxial and substrate area of the donor wafer.

[0007] In an example, the present invention provides a method for manufacturing gallium and nitrogen containing semiconductor devices with low cost and/or improved performance. The method includes providing a gallium and nitrogen containing substrate or a foreign substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising a sacrificial release region and a specific layer stack of high-quality epitaxial material designed for the semiconductor device to be fabricated in. For example, in a Schottky diode power electronic device the layer stack may comprise at least a nominally undoped or intrinsic gallium and nitrogen containing layer and a least an n-type gallium and nitrogen containing layer. In yet another example, in a p-n diode power electronic device the layer stack may comprise at least a nominally undoped or intrinsic gallium and nitrogen containing layer, a least an n-type gallium and nitrogen containing layer, and at least a p-type gallium and nitrogen containing layer. In yet another example, in a high electron mobility transistor (HEMT) power electronic device the layer stack may comprise at least two layers with different bandgaps such as GaN and AlGaN to form a 2- dimensional electron gap at the interface between the two layers with different bandgaps. The method includes patterning and then etching the epitaxial material to form a plurality of mesa regions corresponding to dice, each of the dice corresponding to at least one semiconductor device, such as an electronic device, a power electronic device, a solar cell device, or a combination thereof characterized by a first pitch between a pair of dice, the first pitch being larger than, equal to, or less than a design width. As used herein, the term mesa region or mesa is used to describe the patterned epitaxial material on the gallium and nitrogen containing substrate or the foreign substrate and prepared for transfer to the carrier wafer. The mesa region can be any shape or form including a rectangular shape, a square shape, a triangular shape, a circular shape, an elliptical shape, a polyhedron shape, or other shape. The term mesa shall not limit the scope of the present invention.

[0008] The method includes transferring each of the plurality of dice to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being less than, equal to, or larger than the first pitch corresponding to the design width. The method includes singulating the carrier wafer into a plurality of semiconductor devices on carrier chips.

[0009] In various embodiments the carrier wafer can be larger in diameter than the gallium and nitrogen containing substrate or the foreign substrate. For example, the gallium and nitrogen containing substrate can be a 2” round substrate or a smaller GaN substrate and the carrier wafer can be a 4”, 6”, 8”, or 12” round or other size/shaped silicon substrate, sapphire substrate, glass substrate, glass ceramics substrate, quartz substrate, high purity fused silica substrate, silicon carbide substrate, aluminum nitride substrate, germanium substrate, aluminum oxynitride substrate, gallium arsenide substrate, diamond substrate, gallium nitride substrate, indium phosphide substrate, flexible member, circuit board member, silicon wafer with CMOS circuitry, silicon on insulator (SOI) substrate, or gallium nitride on silicon substrate. After the plurality of devices are transferred from the gallium and nitrogen containing substrate, the substrate can be prepared for re-use.

[0010] In an example, the present semiconductor device die configured with carrier, which can serve as a submount, can be packaged into a module without any further liftoff process or the like. The process is efficient and uses conventional process technology. Depending upon the embodiment, these and other benefits may be achieved.

[0011] In accordance with an embodiment, a partially completed semiconductor device includes a plurality of electronic devices arranged in an array overlying a surface region of a donor substrate, adjacent ones of the plurality of electronic devices in the array separated by a first pitch, each of the plurality of electronic devices comprising a sacrificial region overlying the surface region of the donor substrate and gallium containing device layers of epitaxial material overlying the sacrificial region, the epitaxial material comprises at least an intrinsic- type or unintentionally doped gallium containing region or at least an n-type gallium containing region or at least a p-type gallium containing region or at least a combination of one or more of the intrinsic-type or unintentionally doped gallium containing region, the n- type gallium containing region, or the p-type gallium containing region; bonding regions overlying a first portion of the plurality of electronic devices, each of the bonding regions comprising a metal contact configured to provide electrical coupling with at least one of the gallium containing device layers, wherein a surface region of a second portion of the bonding regions contact and are bonded to a surface region of contact regions on a carrier substrate to form bonded electronic devices, the contact regions on the carrier substrate configured to provide electrical coupling to corresponding electronic devices; and anchors extending between each of the plurality of electronic devices and the donor substrate. The bonded electronic devices on the donor substrate are configured to be releasable by selectively removing at least part of the sacrificial regions to transfer the second portion of the plurality of electronic devices to the carrier substrate, wherein the anchors are configured to mechanically support the plurality of electronic devices after removal of at least part of the sacrificial regions, and wherein adjacent pairs of the bonded electronic devices are configured with a second pitch on the carrier substrate that is equal to or greater than the first pitch.

[0012] In an embodiment, the gallium containing device layers comprise gallium and nitrogen or gallium and arsenic.

[0013] In another embodiment, the electronic devices comprise at least one of Schottky diode devices, p-n diode devices, bipolar junction transistor (BJT) devices, field-effect transistor (FET) devices, metal-oxide-semiconductor field-effect transistor (MOSFET) devices, junction field effect transistor (JFET) devices, enhancement mode junction field effect transistor (eJFET) devices, metal-semiconductor FET (MESFET) devices, high- electron-mobility transistor (HEMT) devices, insulated gate bipolar transistor (IGBT) devices, or heterojunction bipolar transistor (HBT) devices, metal-insulator semiconductor barrier Schottky rectifier devices, static induction transistor (SIT) devices, current apertured vertical electron transistor (CAVET) devices, and wherein the electronic devices comprise at least one of trench type devices, normally-on type devices, normally-off type devices, p-type devices, n-type devices, or combinations thereof.

[0014] In another embodiment, the carrier substrate is selected from silicon substrate, a sapphire substrate, an aluminum nitride substrate, a silicon nitride substrate, a silicon carbide substrate, a glass substrate, a group V semiconductor substrate, a III-V semiconductor substrate, a II- VI semiconductor substrate, a glass substrate, a glass ceramic substrate, a quartz substrate, a high purity fused silica substrate, a silicon carbide substrate, an aluminum nitride substrate, a germanium substrate, an aluminum oxynitride substrate, a gallium arsenide substrate, a diamond substrate, a synthetic diamond substrate, a gallium nitride substrate, an indium phosphide substrate, a flexible member, a circuit board member, a CMOS substrate, a silicon substrate with CMOS circuitry, a silicon on insulator (SOI) substrate, or a gallium nitride on silicon substrate. [0015] In another embodiment, the donor substrate is selected from a gallium nitride substrate, a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium oxide substrate, a spinel substrate, a lanthanum aluminate substrate, a magnesium oxide substrate, or a template type substrate.

[0016] In another embodiment, the sacrificial regions include GaN, InGaN, AlInGaN, AlGaN, AlGaAs, AllnP, InGaAs, InAlAs, Ge, silicon, or silicon oxide.

[0017] In yet another embodiment, the plurality of electronic devices include one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a current spreading region, a drift region, an insulation region, an edge termination region, an emitter region, a base region, a collector region, a gate region, a source region, a drain region, an isolation region, or a passivation region either alone or in any combination.

[0018] In accordance with another embodiment, a donor substrate includes a plurality of electronic devices arranged in an array overlaying a surface region of the donor substrate, adjacent ones of the plurality of electronic devices in the array separated by a first pitch that is less than a design width, each of the plurality of electronic devices including: gallium containing device layers of epitaxial material, the epitaxial material comprising at least an intrinsic-type or unintentionally doped gallium containing region or at least an n-type gallium containing region or at least a p-type gallium containing region or at least a combination of one or more of the intrinsic-type or unintentionally doped gallium containing region, the n- type gallium containing region, or the p-type gallium containing region; a sacrificial region configured to be selectively removed to allow transfer of at least a portion of the plurality of electronic devices to one or more carrier substrates; anchors extending between each of the plurality of electronic devices and the donor substrate, the anchors configured to mechanically support the plurality of electronic devices after removal of at least part of the sacrificial regions; and one or more metal contact regions overlying the gallium containing device layers so that the gallium containing device layers are between the sacrificial region and the one or more metal contact regions, the one or more metal contact regions configured to provide an electrical coupling with at least one of the gallium containing device layers, a surface region of at least one of the one or more metal contact regions configured to contact and bond to a surface region of metal contact regions on the one or more carrier substrates. [0019] In an embodiment, the sacrificial region is disposed between the gallium containing device layers and the surface region of the donor substrate.

[0020] In another embodiment, the gallium containing device layers comprise gallium and nitrogen or gallium and arsenic.

[0021] In another embodiment, the electronic devices comprise at least one of Schottky diode devices, p-n diode devices, bipolar junction transistor (BJT) devices, field-effect transistor (FET) devices, metal-oxide-semiconductor field-effect transistor (MOSFET) devices, junction field effect transistor (JFET) devices, enhancement mode junction field effect transistor (eJFET) devices, metal-semiconductor FET (MESFET) devices, high- electron-mobility transistor (HEMT) devices, insulated gate bipolar transistor (IGBT) devices, or heterojunction bipolar transistor (HBT) devices, metal-insulator semiconductor barrier Schottky rectifier devices, static induction transistor (SIT) devices, current apertured vertical electron transistor (CAVET) devices, and wherein the electronic devices comprise at least one of trench type devices, normally-on type devices, normally-off type devices, p-type devices, n-type devices, or combinations thereof.

[0022] In another embodiment, the donor substrate is selected from a gallium nitride substrate, a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium oxide substrate, a spinel substrate, a lanthanum aluminate substrate, a magnesium oxide substrate, or a template type substrate.

[0023] In another embodiment, the sacrificial region includes GaN, InGaN, AlInGaN, AlGaN, AlGaAs, AllnP, InGaAs, InAlAs, Ge, silicon, or silicon oxide.

[0024] In yet another embodiment, the plurality of electronic devices include one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a current spreading region, a drift region, an insulation region, an edge termination region, an emitter region, a base region, a collector region, a gate region, a source region, a drain region, an isolation region, or a passivation region either alone or in any combination.

[0025] In accordance with another embodiment, a carrier substrate configured with circuitry for distributing electronic signals or current includes a plurality of electronic devices arranged in an array overlaying a surface region of the carrier substrate, wherein each of a first portion of the plurality of electronic devices include: gallium containing device layers of epitaxial material, the epitaxial material comprising at least an intrinsic-type or unintentionally doped gallium containing region or at least an n-type gallium containing region or at least a p-type gallium containing region or at least a combination of one or more of the intrinsic-type or unintentionally doped gallium containing region, the n-type gallium containing region, or the p-type gallium containing region; and one or more contact regions overlying the surface region of the carrier substrate, a surface region of the one or more contact regions contacting and bonded to a surface region of one or more metal contact regions of each electronic device, the one or more metal contact regions configured to provide an electrical coupling with at least one of the gallium containing device layers; and wherein each of a second portion of the plurality of electronic devices are different types of electronic devices than the first portion of the plurality of electronic devices.

[0026] In an embodiment, the second portion of the plurality of electronic devices include at least one of other gallium nitride based electronic devices, silicon based electronic devices, or gallium arsenic based electronic devices.

[0027] In another embodiment, the gallium containing device layers comprise gallium and nitrogen or gallium and arsenic.

[0028] In another embodiment, the electronic devices comprise at least one of Schottky diode devices, p-n diode devices, bipolar junction transistor (BJT) devices, field-effect transistor (FET) devices, metal-oxide-semiconductor field-effect transistor (MOSFET) devices, junction field effect transistor (JFET) devices, enhancement mode junction field effect transistor (eJFET) devices, metal-semiconductor FET (MESFET) devices, high- electron-mobility transistor (HEMT) devices, insulated gate bipolar transistor (IGBT) devices, or heterojunction bipolar transistor (HBT) devices, metal-insulator semiconductor barrier Schottky rectifier devices, static induction transistor (SIT) devices, current apertured vertical electron transistor (CAVET) devices, and wherein the electronic devices comprise at least one of trench type devices, normally-on type devices, normally-off type devices, p-type devices, n-type devices, or combinations thereof.

[0029] In another embodiment, the carrier substrate is selected from silicon substrate, a sapphire substrate, an aluminum nitride substrate, a silicon nitride substrate, a silicon carbide substrate, a glass substrate, a group V semiconductor substrate, a III-V semiconductor substrate, a II- VI semiconductor substrate, a glass substrate, a glass ceramic substrate, a quartz substrate, a high purity fused silica substrate, a silicon carbide substrate, an aluminum nitride substrate, a germanium substrate, an aluminum oxynitride substrate, a gallium arsenide substrate, a diamond substrate, a synthetic diamond substrate, a gallium nitride substrate, an indium phosphide substrate, a flexible member, a circuit board member, a CMOS substrate, a silicon substrate with CMOS circuitry, a silicon on insulator (SOI) substrate, or a gallium nitride on silicon substrate.

[0030] In yet another embodiment, the plurality of electronic devices include one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a current spreading region, a drift region, an insulation region, an edge termination region, an emitter region, a base region, a collector region, a gate region, a source region, a drain region, an isolation region, or a passivation region either alone or in any combination.

[0031] In accordance with another embodiment, a partially completed semiconductor device includes a plurality of electronic devices arranged in an array overlying a surface region of a donor substrate, adjacent ones of the plurality of electronic devices in the array separated by a first pitch, each of the plurality of electronic devices comprising a sacrificial region overlying the surface region of the donor substrate and gallium containing device layers of epitaxial material overlying the sacrificial region, the epitaxial material comprises at least an intrinsic-type or unintentionally doped gallium containing region or at least an n-type gallium containing region or at least a p-type gallium containing region or at least a combination of one or more of the intrinsic-type or unintentionally doped gallium containing region, the n-type gallium containing region, or the p-type gallium containing region; bonding regions overlying a first portion of the plurality of electronic devices, wherein a surface region of a second portion of the bonding regions contact and are bonded to a surface region of contact regions on a carrier substrate to form bonded electronic devices; and anchors extending between each of the plurality of electronic devices and the donor substrate. The bonded electronic devices on the donor substrate are configured to be releasable by selectively removing at least part of the sacrificial regions using a wet etch to transfer the second portion of the plurality of electronic devices to the carrier substrate, wherein the anchors are configured to mechanically support the plurality of electronic devices after removal of at least part of the sacrificial regions, and wherein adjacent pairs of the bonded electronic devices are configured with a second pitch on the carrier substrate that is equal to or greater than the first pitch. [0032] In an example, the present invention enables the integration of different semiconductor devices onto a common carrier for integration to increase functionality of the resulting semiconductor chip formed on the carrier wafer.

[0033] The present invention achieves these benefits and others in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A is a simplified side view of a selective area bonding process in an example of the present invention.

[0035] Figures 1B-1G are simplified side views of a bonding processes using an intermediate substrate in examples of the present invention.

[0036] Figure 2A is a simplified schematic of an epitaxial structure of a Schottky diode power device according to an example of the present invention.

[0037] Figure 2B is a simplified schematic cross-section of a structure of a Schottky diode power device on a carrier wafer according to an example of the present invention.

[0038] Figure 2C is a simplified schematic of an epitaxial structure of a Schottky barrier diode device according to an example of the present invention.

[0039] Figure 2D is a simplified schematic cross-section of a structure of a Schottky barrier diode device on a carrier wafer according to an example of the present invention.

[0040] Figures 2E and 2F are simplified schematic cross-sections of structures of Schottky barrier diode devices formed according to examples of methods of the invention.

[0041] Figures 2G and 2H are simplified schematic cross-sections of structures of metalinsulator-semiconductor barrier Schottky rectifier devices formed according to examples of methods of the invention.

[0042] Figures 21 and 2J are simplified schematic cross-sections of structures of metalinsulator-semiconductor barrier Schottky rectifier devices formed according to examples of methods of the invention. [0043] Figure 3 A is a simplified schematic of an epitaxial structure of a p-n diode power device according to an example of the present invention.

[0044] Figure 3B is a simplified schematic cross-section of a structure of a p-n diode power device on a carrier wafer according to an example of the present invention.

[0045] Figure 3C is a simplified schematic of an epitaxial structure of a p-n diode power device according to an example of the present invention.

[0046] Figure 3D is a simplified schematic cross-section of a structure of a p-n diode power device on a carrier wafer according to an example of the present invention.

[0047] Figures 3E to 3 V illustrate methods by which various electronic devices are formed on a gallium and nitrogen containing or foreign wafer and transferred to a carrier wafer according to examples of the present invention.

[0048] Figure 4A is a simplified example of a conventional HEMT device formed epitaxially on a foreign substrate according to an example of the present invention.

[0049] Figure 4B is a simplified schematic of an epitaxial structure of a HEMT device formed on a gallium and nitrogen containing substrate or a foreign substrate according to an example of the present invention.

[0050] Figure 4C is a simplified schematic of an epitaxial structure of a HEMT device formed on a foreign substrate according to an example of the present invention.

[0051] Figure 4D is a simplified schematic cross-section of a structure of a HEMT/HFET device on a carrier wafer according to an example of the present invention.

[0052] Figure 4E is a simplified schematic cross-section of a structure of a HEMT/HFET device on a carrier wafer according to an example of the present invention.

[0053] Figure 4F is a simplified schematic cross-section of a structure of an insulated HEMT/MIS-HEMT device on a carrier wafer according to an example of the present invention.

[0054] Figures 4G and 4H illustrate a method by which a HEMT device is formed on a gallium and nitrogen containing or foreign wafer and transferred to a carrier wafer according to examples of the present invention. [0055] Figure 41 is a simplified schematic of an epitaxial structure of a HEMT device grown on a gallium and nitrogen containing substrate or a foreign substrate according to an example of the present invention.

[0056] Figure 4J is a simplified schematic of an epitaxial structure of a HEMT device grown on a foreign substrate according to an example of the present invention.

[0057] Figure 4K is a simplified schematic cross-section of a structure of a HEMT device on a carrier wafer according to an example of the present invention.

[0058] Figure 4L is a simplified schematic cross-section of a structure of a HEMT device on a carrier wafer according to an example of the present invention.

[0059] Figure 4M is a simplified schematic cross-section of a structure of a HEMT device on a carrier wafer according to an example of the present invention.

[0060] Figure 4N is a simplified schematic cross-section of a structure of a recessed gate HEMT device on a carrier wafer according to an example of the present invention.

[0061] Figures 40 and 4P illustrate a method by which a HEMT device is formed on a gallium and nitrogen containing or foreign wafer and transferred to a carrier wafer according to examples of the present invention.

[0062] Figure 4Q is a simplified schematic cross-section of a structure of a GIT device on a carrier wafer according to an example of the present invention.

[0063] Figure 4R is a simplified schematic of an epitaxial structure of a HEMT device on a gallium and nitrogen containing substrate or a foreign substrate according to an example of the present invention.

[0064] Figure 4S is a simplified schematic of an epitaxial structure of a HEMT device on a foreign substrate according to an example of the present invention.

[0065] Figure 4T is a simplified schematic cross-section of a structure of a plurality of HEMT devices formed on a gallium and nitrogen containing or foreign substrate according to an example of the present invention.

[0066] Figure 4U is a simplified schematic cross-section of a structure of a plurality of HEMT devices selectively bonded to multiple carrier wafers or printed circuit boards according to an example of the present invention. [0067] Figure 5A is a simplified cross-section schematic example of preparation of Schottky diode epitaxial device layers for die expanded transfer according to an embodiment of this invention.

[0068] Figure 5B is a simplified cross-sectional schematic example of selective bonding of Schottky diode epitaxial device layers for die expansion according to an embodiment of this invention.

[0069] Figure 5C is an example top-view schematic of conventional Schottky diode device.

[0070] Figure 5D is an example cross-sectional view of a conventional Schottky diode device.

[0071] Figure 5E is an example cross-sectional view of Schottky diode device according to this invention.

[0072] Figure 5F is an example top-view schematic of conventional HEMT device.

[0073] Figure 5G is an example cross-sectional view of a conventional HEMT device.

[0074] Figure 5H is an example cross-sectional view of HEMT device according to this invention.

[0075] Figure 6A is a simplified schematic example of electronic device integration onto a common carrier wafer according to this invention.

[0076] Figure 6B is a simplified schematic example of electronic device integration onto a common carrier wafer according to this invention.

[0077] Figure 6C is a simplified schematic example of electronic device integration onto a carrier wafer configured with device functionality according to this invention.

[0078] Figure 6D is a simplified schematic cross-section of electronics devices integrated onto a high thermal conductivity substrate according to this invention.

[0079] Figure 6E is a simplified schematic cross-section of a structure of electronic device integration on a carrier wafer according to this invention.

[0080] Figure 6F is a simplified schematic cross-section of a structure of different electronic devices connected to a carrier wafer according to this invention. [0081] Figures 6G and 6H illustrate a method by which a GaAs electronic device is formed and integrated with another electronic device on a carrier wafer according to this invention.

[0082] Figure 7A illustrates an example of an integrated circuit formed with transferred GaN devices according to some embodiments.

[0083] Figure 7B illustrates an example of an integrated circuit formed with transferred GaN devices according to some embodiments.

[0084] Figure 7C illustrates an example of an integrated circuit formed with transferred GaN devices according to some embodiments.

[0085] Figure 7D illustrates an example of an integrated circuit formed with transferred GaN devices using an intermediate substrate according to some embodiments.

[0086] Figure 7E illustrates an example of an integrated circuit formed with a top-side contact process on an intermediate carrier according to some embodiments.

[0087] Figure 7F illustrates an example of heterogeneous integration of III-IV electronic devices on CMOS substrates according to some embodiments.

[0088] Figure 7G illustrates an example of integrating gallium and nitrogen containing electronic devices with CMOS circuitry according to some embodiments.

[0089] Figure 7H illustrates an example of gallium and nitrogen containing electronic devices on diamond substrates according to some embodiments.

[0090] Figure 71 illustrates an example of gallium and nitrogen containing electronic devices with improved thermal performance according to some embodiments.

DETAILED DESCRIPTION

[0091] Embodiments of the invention provide methods for fabricating semiconductor devices based on gallium and nitrogen containing epitaxial materials grown on bulk gallium and nitrogen containing substrates or foreign substrates. Typically, these devices are fabricated using an epitaxial deposition on a gallium and nitrogen containing substrate or a foreign substrate followed by processing steps on the epitaxial substrate and overlying epitaxial material. In some embodiments, for the fabrication of devices such as electronic or power electronic devices, the gallium and nitrogen containing epitaxial materials could be provided by heteroepitaxial growth on a substrate that is not gallium nitride. These heteroepitaxial substrates may include sapphire, SiC, gallium oxide, spinel, lanthanum aluminate, magnesium oxide, and silicon among others. By using a selective etch process, such as a photoelectrochemical (PEC) etch, combined with a bonding process, at least a portion of the epitaxial material can be transferred to one or more carrier wafers. Subsequently, the carrier wafer with the bonded epitaxial material is subjected to processing steps to form semiconductor devices including electronic devices such as Schottky diodes, p- n diodes, transistors, field effect transistors, bipolar junction transistors, high electron mobility transistors, solar cell devices, and the like. In other embodiments, the semiconductor devices are fully or partially formed in the epitaxial material before transfer to the carrier wafer or to an integrated circuit. In other embodiments, different types of semiconductor devices are configured on a common carrier using the selective bonding and etching process to form an integrated device or integrated circuit. In some embodiments the carrier wafer may include electrical circuitry and additional circuit elements such as transistors, resistors, capacitors, and/or inductors. What follows is a general description of the typical configuration and fabrication of some of these devices.

[0092] The invention involves a semiconductor device wafer composed of one or more sacrificial layers and one or more device layers overlying the surface region of a substrate wafer. The substrate wafer comprises a bulk gallium and nitrogen containing material such as GaN but can be others.

[0093] Of course, in some embodiments for the fabrication of electronic devices, the gallium and nitrogen containing epitaxial materials could be provided by heteroepitaxial growth on a substrate that is not gallium nitride. These heteroepitaxial substrates may include sapphire, SiC, gallium oxide, spinel, lanthanum aluminate, magnesium oxide, and silicon among others. In a preferred embodiment, the gallium and nitrogen containing epitaxial materials are deposited on sapphire or SiC due to their relatively low cost and ability to achieve relatively low defectivity and low strain epitaxial films. In an embodiment, the gallium and nitrogen containing epitaxial materials are deposited on silicon wafers due to the low cost of silicon wafers and availability of large area silicon wafers; i.e. wafers having greater than 150 mm diameter.

[0094] Another advantage offered by the present invention is the ability to access either the Ga-face or the N-face of the gallium and nitrogen containing epitaxial device layers for device fabrication and contact formation. For example, if the epitaxial layers are grown on a Ga-face substrate the epitaxial layers will be formed terminating with a Ga-face surface. After the epitaxy is transferred to the carrier wafer for process the N-face will be exposed for process. The N-face may provide an advantage to the device such as an improved contact property or an improved behavior for the semiconductor layers. In the case where it is desirable to do the device fabrication with the Ga-face on the surface, semiconductor process steps may be performed on the epitaxial wafers prior to transfer to the carrier wafer. The order of the epitaxial stack can be arranged to provide the most benefit to the device.

[0095] Following the growth of the epitaxial layers on the bulk gallium and nitrogen containing substrate or the foreign substrate, the semiconductor device layers are separated from the substrate by a selective wet etching process such as a PEC etch configured to selectively remove the sacrificial layers and enable release of the device layers to one or more carrier wafers. In one embodiment, a bonding material is deposited on the surface overlying the semiconductor device layers. A bonding material is also deposited either as a blanket coating or patterned on a carrier wafer. Standard lithographic processes are used to selectively mask the semiconductor device layers. The wafer is then subjected to an etch process such as dry etch or wet etch processes to define via structures that expose the one or more sacrificial layers on the sidewall of the mesa structure. As used herein, the term mesa region or mesa may be used to describe the patterned epitaxial material on the gallium and nitrogen containing substrate or the foreign substrate and prepared for transfer to the carrier wafer. The mesa region can be any shape or form including a rectangular shape, a square shape, a triangular shape, a circular shape, an elliptical shape, a polyhedron shape, or other shape. The term mesa shall not limit the scope of the present invention.

[0096] Following the definition of the mesa, a selective etch process is used to fully or partially remove the one or more sacrificial layers while leaving the semiconductor device layers intact. The resulting structure comprises undercut mesas comprised of epitaxial device layers. The undercut mesas correspond to dice from which semiconductor devices are or will be formed on. In some embodiments a protective passivation layer can be employed on the sidewall of the mesa regions to prevent the device layers from being exposed to the selective etch. In other embodiments a protective passivation is not needed because the device layers are not sensitive to the selective etch or measures are taken to prevent etching of sensitive layers such as shorting the anode and cathode. The undercut mesas corresponding to the dice are then transferred to the carrier wafer using a bonding technique wherein the bonding material overlying the semiconductor device layers is joined with the bonding material on the carrier wafer. The resulting structure is a carrier wafer comprising gallium and nitrogen containing epitaxial device layers overlying the bonding region.

[0097] In an embodiment, the PEC etching is deployed as the selective etch to remove the one or more sacrificial layers. PEC is a photo-assisted wet etch technique that can be used to etch GaN and its alloys. The process involves an above-band-gap excitation source and an electrochemical cell formed by the semiconductor and the electrolyte solution. In this case, the exposed (Al,In,Ga)N material surface acts as the anode, while a metal pad deposited on the semiconductor acts as the cathode. The above-band-gap light source generates electronhole pairs in the semiconductor. Electrons are extracted from the semiconductor via the cathode while holes diffuse to the surface of material to form an oxide. Since the diffusion of holes to the surface requires the band bending at the surface to favor a collection of holes, PEC etching typically works only for n-type material although some methods have been developed for etching p-type material. The oxide is then dissolved by the electrolyte resulting in wet etching of the semiconductor. Different types of electrolytes including HC1, KOH, and HNO3 have been shown to be effective in PEC etching of GaN and its alloys. The etch selectivity and etch rate can be optimized by selecting a favorable electrolyte. It is also possible to generate an external bias between the semiconductor and the cathode to assist with the PEC etching process.

[0098] Figure 1 A is a schematic representation of the die expansion process with selective area bonding according to the present invention. A device wafer is prepared for bonding in accordance with an embodiment of this invention. The wafer consists of a substrate 106, buffer layers 103, the fully removed sacrificial layer 109, the device layers 102, the bonding media 101, the cathode metal utilized in the PEC etch removal of the sacrificial layer and the anchor material 104. The mesa regions formed in the gallium and nitrogen containing epitaxial wafer form dice of epitaxial material and release layers defined through processing. Individual epitaxial material die are formed at first pitch. A carrier wafer is prepared consisting of the carrier wafer 107 and bond pads 108 at second pitch. The substrate is aligned to the carrier wafer such that a subset of the mesa on the gallium and nitrogen containing or foreign substrate with a first pitch align with a subset of bond pads on the carrier at a second pitch. Since the first pitch is greater than the second pitch and the mesas will comprise device die, the basis for die expansion is established. The bonding process is carried out and upon separation of the substrate from the carrier wafer the subset of mesas are selectively transferred to the carrier. The process is then repeated with a second set of mesas and bond pads on the carrier wafer until the carrier wafer is populated fully by epitaxial mesas. The gallium and nitrogen containing epitaxy substrate can now optionally be prepared for reuse.

[0099] In the example depicted in Figure 1 A, one quarter of the epitaxial die are transferred in this first selective bond step, leaving three quarters on the epitaxy wafer. The selective area bonding step is then repeated to transfer the second quarter, third quarter, and fourth quarter of the epitaxial die to the patterned carrier wafer. This selective area bond may be repeated any number of times and is not limited to the four steps depicted in Figure 1 A. The result is an array of epitaxial die on the carrier wafer with a wider die pitch than the original die pitch on the epitaxy wafer. The die pitch on the epitaxial wafer will be referred to as pitch 1, and the die pitch on the carrier wafer will be referred to as pitch 2, where pitch 2 is greater than pitch 1.

[0100] In one embodiment the bonding between the carrier wafer and the gallium and nitrogen containing or foreign substrate with epitaxial layers is performed between bonding layers that have been applied to the carrier and the gallium and nitrogen containing or foreign substrate with epitaxial layers. The bonding layers can be a variety of bonding pairs including metal-metal, oxide-oxide, soldering alloys, photoresists, polymers, wax, etc. Only epitaxial die which are in contact with a bond bad on the carrier wafer will bond. Sub-micron alignment tolerances are possible on commercial die bonders. The epitaxy wafer is then pulled away, breaking the epitaxy material at a weakened epitaxial release layer such that the desired epitaxial layers remain on the carrier wafer. Herein, a ‘selective area bonding step’ is defined as a single iteration of this process.

[0101] In one embodiment, the carrier wafer is patterned in such a way that only selected mesas come in contact with the metallic bond pads on the carrier wafer. When the epitaxy substrate is pulled away the bonded mesas break off at the weakened sacrificial region, while the un-bonded mesas remain attached to the epitaxy substrate. This selective area bonding process can then be repeated to transfer the remaining mesas in the desired configuration. This process can be repeated through any number of iterations and is not limited to the two iterations depicted in Figure 1 A. The carrier wafer can be of any size, including but not limited to about 2 inch, 3 inch, 4 inch, 6 inch, 8 inch, and 12 inch. After all desired mesas have been transferred, a second bandgap selective PEC etch can be optionally used to remove any remaining sacrificial region material to yield smooth surfaces. At this point standard semiconductor device processes can be carried out on the carrier wafer. Another embodiment of the invention incorporates the fabrication of device components on the dense epitaxy wafers before the selective area bonding steps.

[0102] In an example, the present invention provides a method for increasing the number of gallium and nitrogen containing semiconductor devices which can be fabricated from a given epitaxial surface area; where the gallium and nitrogen containing epitaxial layers overlay gallium and nitrogen containing or foreign substrates. The gallium and nitrogen containing epitaxial material is patterned into die with a first die pitch; the die from the gallium and nitrogen containing epitaxial material with a first pitch is transferred to a carrier wafer to form a second die pitch on the carrier wafer; the second die pitch is larger than the first die pitch.

[0103] In an example, each epitaxial device die is an etched mesa with a pitch of between about 1 pm and about 100 pm wide or between about 100 micron and about 500 microns wide or between about 500 micron and about 3000 microns wide and between about 100 and about 3000 pm long. In an example, the second die pitch on the carrier wafer is between about 100 microns and about 200 microns or between about 200 microns and about 1000 microns or between about 1000 microns and about 3000 microns. In an example, the second die pitch on the carrier wafer is between about 2 times and about 50 times larger than the die pitch on the epitaxy wafer. In an example, electronic devices are fabricated on the carrier wafer before epitaxial transfer. In an example, the semiconductor devices contain GaN, AIN, InN, InGaN, AlGaN, InAlN, and/or InAlGaN. In an example, the gallium and nitrogen containing material are grown on a polar, nonpolar, or semipolar plane. In an example, one or multiple semiconductor devices are fabricated on each die of epitaxial material. In an example, device components, which do not require epitaxy material, are placed in the space between epitaxy die.

[0104] In one embodiment, device dice are transferred to a carrier wafer such that the distance between die is expanded in both the transverse as well as lateral directions. This can be achieved by spacing bond pads on the carrier wafer with larger pitches than the spacing of device die on the substrate.

[0105] In another embodiment of the invention, device dice from a plurality of epitaxial wafers are transferred to the carrier wafer such that each design width on the carrier wafer contains dice from a plurality of epitaxial wafers. When transferring die at close spacings from multiple epitaxial wafers, it is important for the un-transferred die on the epitaxial wafer to not inadvertently contact and bond to die already transferred to the carrier wafer. To achieve this, die from a first epitaxial wafer are transferred to a carrier wafer using the methods described above. A second set of bond pads are then deposited on the carrier wafer and are made with a thickness such that the bonding surface of the second pads is higher than the top surface of the first set of transferred die. This is done to provide adequate clearance for bonding of the die from the second epitaxial wafer. A second substrate transfer a second set of die to the carrier. Finally, the semiconductor devices are fabricated and passivation layers are deposited followed by electrical contact layers that allow each dice to be individually driven. The die transferred from the first and second substrates are spaced at a pitch which is smaller than the second pitch of the carrier wafer. This process can be extended to transfer of die from any number of substrates, and to the transfer of any number of devices per dice from each substrate.

[0106] In some embodiments, multiple semiconductor device die are transferred to a single carrier wafer and placed within close proximity to each other. Dice in close proximity are preferably within one millimeter of each other, but could be other distances from each other.

[0107] In another embodiment of the invention, individual PEC undercut etches are used after each selective bonding step for etching away the sacrificial release layer of only bonded mesas. Which epitaxial die get undercut is controlled by only etching down to expose the sacrificial layer of mesas which are to be removed on the current selective bonding step. The advantage of this embodiment is that only a very coarse control of PEC etch rates is required. This comes at the cost of additional processing steps and geometry constraints.

[0108] By enabling the gallium and nitrogen containing epitaxial layer dice to be transferred to the carrier wafer at a larger pitch, the expensive gallium and nitrogen containing or foreign substrate and epitaxial device layers can be more efficiently utilized. Additionally, a larger area will be required on the carrier wafer than the area of the gallium and nitrogen containing or foreign substrate. For example, in a fixed expansion configuration, a carrier wafer with 4 times larger area will be required to receive all of the transferred device dice. This is powerful feature for GaN devices formed on GaN substrates since currently bulk GaN substrates are commercially available in 2” diameter with recent announcements of 4” diameter sampling. These wafer diameters are relatively small compared to the well-established silicon substrate technology, which are currently available at diameters up to 12”. For example, a 12” substrate has 36 times the substrate area of a 2” GaN substrate and 9 times the substrate area of a 4” GaN substrate, which are not yet available in high volume. This drastically larger area enables device processing with orders of magnitude more device dies per wafer to provide massive reductions in manufacturing costs.

[0109] Figures 1B-1G are simplified side views of a bonding process using an intermediate substrate in an example of the present invention. When the intermediate substrate bonding process is used, die are transferred from a donor substrate, such as an epitaxial wafer, to an intermediate substrate member, and are subsequently transferred from the intermediate substrate member to the carrier wafer, instead of being transferred directly from the donor substrate to the carrier wafer. In this embodiment, an intermediate member and pick and place member, such as a pedestal collet, can be used to eliminate bonding interference issues associated with bonding multiple die from different donor wafers to a carrier wafer. In this approach, after the sacrificial release layer is removed, the die are weakly bond to the donor substrate. The donor wafer is pressed into an intermediate member which, for example, has a pressure sensitive adhesive tape or coating applied to the surface that adheres to each individual die and has an adhesion force strong enough to break the anchors on the donor wafer as the donor wafer and intermediate member are pulled apart. This process may provide a mass transfer of the die from the donor wafer to the intermediate member.

[0110] Substrates with low flatness and total thickness variation (TTV) may be used for the intermediate member. These include, but are not limited to, silicon substrates, sapphire substrates, glass substrates, and the like. In some instances, an ultraviolet (UV) release layer or laser-based release layer can be used with substrates of an appropriate transparency.

[OHl] A wide variety of materials can be used for the adhesive layer. As an example, a double-sided thermal release tape may be directly applied to the intermediate member and be used as the temporary adhesive layer. These tapes are traditionally used in many areas of semiconductor processing and have very good thickness and thickness variation control. In addition, the initial adhesive strength of the tape can be tuned to overcome the failure strength of the anchors on the donor wafer to facilitate transfer from the donor wafer to the intermediate member. Upon heating, the adhesive strength drops so the transferred die can be removed in subsequent transfer steps. In addition to thermal release tapes, a double-sided UV release tape may be used in some embodiments. Similar to the thermal release tape, the adhesion strength of the UV release tape can be reduced to facilitate transfer from the intermediate member. Instead of using heat, the UV release tape is activated by exposing the tape to UV light to reduce the adhesion strength. When using UV release tape, a transparent substrate may be used so the tape can be exposed through the substrate. In other embodiments, the transferred die may be coupled to the intermediate member by a vacuum, van der waals forces, chemical bonds, and the like.

[0112] After the die are transferred to the intermediate member, the adhesion strength of the adhesion layer is reduced to enable subsequent pickup with, for example, a die attach collet. A pedestal style die attach collet may be used to selectively align and pick up die from the intermediate member. The pedestal feature is designed to avoid X, Y, and Z clearance issues with existing die from previous transfers or existing topography of the carrier wafers. In addition, these collets can be designed to pick up many die at one time allowing massive parallel die transfer to a receiving carrier substrate. After pickup from the intermediate member, the die are aligned and bonded to the carrier wafer. The pickup collets can be made of typical materials used in a variety of high temperature die attach processes. This process is repeated until all the die from the intermediate member are transferred to the carrier wafer.

[0113] Figures 1B-1G provide an example of how this approach may be used to transfer die from multiple donor wafers for an electronic device. Initially, epitaxial device layers are grown on each donor wafer. The donor wafers then go through device processing. Figure IB is a cross-sectional illustration of an intermediate substrate member having an adhesion layer thereon. There intermediate substrate member may comprise any of the materials of any of the substrates discussed herein, and/or may comprise another material. The adhesion layer on the intermediate substrate member may comprise any adhesive material known to those of skill in the art. In some embodiments, the adhesion layer comprises a UV or thermal release film.

[0114] Figure 1C is a cross-sectional illustration of the intermediate substrate member having die attached thereto. For example, the die may be formed on the donor substrate using processing steps and methods discussed herein and/or otherwise known to those of skill in the art. The die may be attached to the donor substrate by anchors connected to the donor substrate and to the die. To transfer the die from the donor substrate to the intermediate substrate member, the donor substrate may be manipulated so as to cause the interface regions on the die to contact the adhesion layer on the intermediate substrate member. In some embodiments, causing the interface regions to contact the adhesion layer causes the interface regions to adhere to the adhesion layer with sufficient adhesion force. In some embodiments, while the interface regions contact the adhesion layer, the adhesion layer is activated, for example using UV radiation, heat, or by another method to cause the interface regions to adhere to the adhesion layer with sufficient adhesion force. Once the interface regions are adhered to the intermediate member with sufficient adhesion force, the donor substrate is removed. Because the adhesion force by which the interface regions adhered to the adhesion layer is sufficient, removing the donor substrate causes the anchors to mechanically fail, releasing the die from the donor substrate.

[0115] Figure ID is a cross-sectional illustration of the intermediate substrate member having die attached thereto and a pick and place member configured to remove die from the intermediate substrate member. The pick and place member may, for example, be part of a pick and place tool understood by those of skill in the art. To remove die from the intermediate substrate member, the pick and place member causes a particular die to be fixed thereto using, for example, mechanical, pneumatic, and/or electrostatic forces. Once a particular die is fixed to the pick and place member, the pick and place member is moved so as to cause the die fixed to the pick and place member to separate from the intermediate substrate member.

[0116] Figure IE is a cross-sectional illustration of the pick and place member placing the die fixed thereto onto a carrier wafer. The pick and place member is moved so as to align the interface region of the die fixed thereto with a particular target bond pad, for example, previously formed on the carrier wafer. To transfer the die from the pick and place tool to the carrier wafer, the pick and place member is moved so as to cause the interface (or bonding) region of the die attached thereto to contact the target bond pad. In some embodiments, causing the interface regions to contact the target bond pad causes the interface regions to adhere to the target bond pad. In some embodiments, while the interface region contacts the target bond pad, the connection is formed, for example, using UV radiation, heat, or by another method to cause the interface regions to adhere to the target bond pad. For example, heat may be applied so as to cause a metal of the interface region to melt with a metal of the target bond pad. Once the interface region is fixed to the target bond pad, the pick and place member is caused to release the die.

[0117] Figures IF and 1G are cross-sectional illustrations of the pick and place member placing additional die on the carrier wafer. In the illustrated embodiment, the additional die are different from the die illustrated in figure IE. In the illustrated embodiment, the die illustrated in figure IE comprises a first electronic device, the die attached to the carrier wafer in figure IF comprises a second electronic device, and the die attached to the carrier wafer in figure 1G comprises a third electronic device. In some embodiments, the electronic devices may be the same or different types of electronic devices.

[0118] In the present invention a wide range of power electronic and transistor devices can be formed. Examples of such devices include Schottky diode devices, p-n diode devices, bipolar junction transistor (BJT), field-effect transistor (FET), metal-oxide-semiconductor field (MOSFET), junction field effect transistor (JFET), metal-semiconductor FETs (MESFETs), high-electron-mobility transistors (HEMT), insulated gate bipolar transistors (IGBT), heterojunction bipolar transistors (HBT), and others. In one embodiment, the semiconductor device layers are epitaxially grown on a bulk polar GaN substrate. In another embodiment, the semiconductor device layers are epitaxially grown on bulk nonpolar or semipolar GaN substrate, The devices may be processed to form contacts on the N-face and the Ga-face to provide performance enhancements and the layer structures may be ordered to provide an advantage over what is possible using conventional device fabrication technologies.

[0119] One embodiment of a GaN power device fabricated using this invention is a Schottky diode, which is a two terminal majority carrier device with a low forward voltage drop and a very fast switching action. When current flows through the Schottky diode device there is a small voltage drop across the diode terminals. An ideal Schottky diode should have characteristics such as high breakdown voltage, low leakage current, low forward voltage drop, low on-state resistance, and fast recovery. The keys characteristics for the fabrication of ideal Schottky diodes are the selection of a semiconductor material with optimum intrinsic properties, high crystal quality of the semiconductor layers, high quality intrinsic layer as a drift region with desired thickness, proper device structure and design, good edge termination, rectifying Schottky contact, low contact resistance for the ohmic contact, and high conductivity from the ohmic contacts to the intrinsic drift region. In GaN the majority carrier is most typically electrons, or n-type, but it can be p-type. As used herein, the term intrinsic or intrinsic region is used to describe a semiconductor material with very low doping or carrier concentration. The intrinsic region can be formed by growing epitaxial materials that are not intentionally doped (NID), unintentionally doped (UID), or may be intentionally doped to compensate the unintentional background doping to reduce the carrier concentration. The intrinsic region is typically configured as an insulating region, a semiinsulating region, or a drift region.

[0120] The three primary or typical device geometries for Schottky diodes are lateral, semivertical mesa, and vertical. The earliest GaN Schottky type diodes were lateral type, which suffer from very poor lateral conductivity. The semi-vertical structure comprises a mesa etched in GaN that is typically grown on a foreign substrate. A Schottky contact is made on top of the mesa and ohmic contacts are made on the etched region surrounding the mesa. These structures were improved over the lateral structures but were still limited by lateral conductivity of the epi layers connecting the ohmically contacted material to the intrinsic material. With the advent of native bulk GaN substrates truly vertical Schottky diodes were enabled. By forming epitaxial intrinsic layers on top of highly doped GaN substrates and forming the ohmic contact to the substrate and the Schottky contacts to the intrinsic layers extremely high performance Schottky diodes were realized. This invention enables a truly vertical Schottky diode without the need for a substrate in the final device by using a highly conductive metal region to laterally conduct to the ohmic contact in one configuration or laterally conduct to the Schottky contact region in an alternative configuration. Since the metal layers are highly conductive and can be made several microns thick (1-15 microns or more) the lateral conductivity will be extremely high and even improved over the conductivity in conventional vertical Schottky diodes, which include the resistance of the substrate.

[0121] In a typical embodiment, a metal-semiconductor junction is formed between a metal and a semiconductor, creating a Schottky barrier on the anode side of the device. Typical metals used for the Schottky barrier are molybdenum, platinum, palladium, nickel, gold, chromium, tungsten, but can be others. The metal region forming the Schottky barrier can be comprised of a metal stack comprising multiple layers including additional metals such as gold. The semiconductor layers forming the Schottky barrier are typically comprised of a gallium and nitrogen containing material such as GaN with very low conductivity (intrinsic region or drift) that is either unintentionally doped or may be intentionally doped with a species to compensate the unintentional background doping to achieve a low conductivity. These regions may be comprised of one or more layers, wherein the layers are comprised of GaN or other gallium and nitrogen containing alloys. These layers typically need to have carrier concentrations of less than about 1E17 cm-3, less than about 6E16 cm-3, less than about 3E16 cm-3, or less than about 1E16 cm-3. The thickness of this region is typically between 0.5 um and 10 um, or about 10 um and 30 um, or about 30 um and 60 um. Sometimes referred to as the standoff region or the drift region, the thickness and conductivity of this intrinsic region sets the resistivity of the device, which will determine power dissipation and maximum current density of the device. The thicker and less conductive this region, the larger the breakdown voltage or critical field of the device.

[0122] In this embodiment, the cathode side of the device is typically formed with an ohmic metal contact to a semiconductor layer. Typical metals used to form the ohmic contact include titanium or aluminum, but could be others. The ohmic metal contact region is often comprised of a metal stack that may include additional metals such as gold, nickel, palladium, or platinum. The ohmic contact is made to a semiconductor contact layer such as an n-type gallium and nitrogen containing material such as GaN. In one example the n-type GaN layer is doped with an n-type dopant such as silicon at a doping level between 5E17 and 1E20 cm'³. The n-type contact layer may have a thickness between about 25 nm and 100 nm, or about 100 nm to about 1000 nm, or about 1000 nm to about 3000 nm.

[0123] In one embodiment of this invention, a Schottky diode epitaxial structure is grown on a bulk gallium and nitrogen containing substrate or a foreign substrate. The growth is comprised of an epitaxial technique such as metal organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a combination. As shown in Figure 2A, the epitaxial structure would comprise a buffer layer grown on top of the substrate. The buffer layer could be comprised of GaN or n-type GaN. Overlying the buffer layer is a sacrificial region as described in this invention. Overlying the sacrificial region are the Schottky diode device layers comprising an n-type contact layer such as n-type GaN and a nominally unintentionally doped or intrinsic region comprised of gallium and nitrogen containing material such as GaN overlying the n-type contact region. In one embodiment the n-contact layer is comprised n-type GaN with a thickness of between 10 nm and 100 nm or 100 nm and 3000 nm. In this embodiment the n-type GaN may be silicon doped GaN with a doping level of greater than 5E17 cm-3 or less than about 1E20 cm-3. In one embodiment the intrinsic region or drift region is comprised of a thickness of 1 um to about 10 um or about 10 um to about 30 um or about 30 um to about 60 um and is comprised of unintentionally doped GaN with a total carrier concentration of less than 1E17 cm-3, less than 5E16 cm-3, less than 2E16 cm-3, or less than 8E15 cm-3. In another embodiment, the intrinsic region is comprised of an intentional dopant intended to compensate the unintentional background dopants to reduce the total carrier concentration and reduce the conductivity. In one embodiment of this invention the epitaxial layers are formed by MOCVD. In another embodiment the sacrificial region and n-type contact layers are formed by MOCVD and the intrinsic region is formed by HVPE where growth rates are much higher so it is more economical to grow very thick layers.

[0124] In one embodiment, a vertical Schottky diode device structure is formed from the epitaxial structure in Figure 2A to result in a device structure as shown in Figure 2B. In this embodiment, the epitaxial device material is prepared for transfer by forming a mesa region by etching the epitaxial material to a depth at or below the sacrificial region. The etching process can be a dry etching process such as a reactive ion etch (RIE), an inductively coupled plasma (ICP) etch, a chemical assisted ion beam etch (CAIBE), or other. Typical gases used in the etching process may include Cl and/or BC13. Alternatively, the mesa could be defined through a wet etch process. The wet etch process may be selective and designed to terminate on the sacrificial region. In this embodiment, a Schottky diode contact is formed on top of epitaxial region on the intrinsic GaN material, which can be done either before or after the mesa is defined. The metal for the Schottky diode contact may be selected, for example, from one of or a combination of molybdenum, platinum, palladium, nickel, gold, chromium, tungsten, or others. Overlying the Schottky contact is a bonding region, which in some embodiments may be, for example, an n-type contact of the Schottky diode comprised of a metal such as Al, Ti, or the like. The metal may be the same metal as used for the Schottky contact, or in an embodiment, additional layers of metal would be deposited over the Schottky contact metal. In one embodiment, this metal would be a gold metal to form a goldgold bond. Metal depositions can be performed by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others, and annealing steps may be used to improve the contact quality. In some embodiments electroplating may be used to deposit a thick layer of a conductive metal such as gold to promote higher conductivity or coverage.

[0125] In addition to preparing the epitaxial device layers for transfer step with the formation of the mesa structures with Schottky contacts and comprising bonding regions, the carrier wafer would be prepared for the transfer process. The carrier wafer could be selected from silicon, silicon carbide, sapphire, aluminum nitride, or others. In preparation for the transfer process, bonding regions would be formed on the carrier wafer, which in some embodiments may serve as, for example, an n-electrode or bond pad of the electronic device. In one embodiment the bonding region is a metal bonding region and is comprised of at least gold. Metal deposition can be performed by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others, and annealing steps may be used to improve the contact quality. In some embodiments electroplating may be used to deposit a thick layer of a conductive metal such as gold to promote high lateral conductivity. The transfer process would comprise a PEC etch to selectively remove the sacrificial release material followed by a bonding step to selectively transfer the epitaxial material to the carrier wafer and release the substrate. In this embodiment the bonding region is configured from a metal layer region comprising metal layers such as gold. The total thickness of this metal bonding region is a critical design aspect since it will be required to laterally conduct all of the device current from bonding pads positioned adjacent to the mesa to the Schottky barrier contact. Once bonded, with the substrate released the remainder of the device process would be performed to the epitaxial device material on carrier wafer. The subsequent processing steps would include forming the n-type ohmic contact with the exposed n-type contact layer on the top of the transferred mesa. The n-type ohmic contact would comprise a metal to allow for a good ohmic contact such as titanium or aluminum. In many embodiments a metal stack would be deposited with more than one layers wherein the ohmic contact layer is in contact with the n-type GaN layer and metals such as gold and/or nickel are configured in the stack overlying the ohmic contact layer. The ohmic metal deposition can be performed by conventional methods such as electron beam deposition, sputtering, or thermal evaporation, and annealing steps may be used to improve the contact quality.

[0126] Additional processing steps to form the completed Schottky diode device could include photolithography, deposition of dielectric passivation regions such as silicon dioxide or silicon nitride. Dry or wet etching or lift off of the dielectric may be necessary to form a patterned region. Additionally, larger bond pad regions may be formed to make the device addressable by electrical power sources. The bond pads would be connected to the Schottky metal contact and/or the ohmic metal contact and may be configured to be partially or fully formed on the carrier wafer surrounding the epitaxial device material. Additionally, edge termination regions may be formed in the device. Edge termination is one of the key technologies for fabricating high voltage Schottky diodes, which functions to reduce the peak electric field along the Schottky contact edge and enhance the breakdown voltage. Several methods are used for edge termination including, but not limited to mesa, guard rings, field plates and high resistivity region by ion implantation can be used to reduce the chance of premature breakdown. [0127] In an alternative embodiment of this invention, a Schottky diode epitaxial structure is grown on a bulk GaN substrate. The growth is comprised of an epitaxial technique such as metal organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a combination. As shown in Figure 2C, the epitaxial structure in this embodiment would comprise a buffer layer grown on top of the substrate. The buffer layer could be comprised of GaN or n-type GaN. Overlying the buffer layer is a sacrificial region as described in this invention. Overlying the sacrificial region are the Schottky diode device layers comprising a nominally unintentionally doped or intrinsic region comprised of gallium and nitrogen containing material such as GaN and an n-type contact layer such as n- type GaN overlying the nominally unintentionally doped or intrinsic region. In one embodiment the intrinsic or drift region or drift region is comprised of a thickness of 1 um to about 10 um or about 10 um to about 30 um or about 30 um to about 60 um and is comprised of unintentionally doped GaN with a total carrier concentration of less than 1E17 cm-3, less than 5E16 cm-3, less than 2E16 cm-3, or less than 8E15 cm-3. In another embodiment, the intrinsic region is comprised of an intentional dopant intended to compensate the unintentional background dopants to reduce the total carrier concentration and reduce the conductivity. In one embodiment the n-contact layer is comprised n-type GaN with a thickness of between 10 nm and 100 nm or 100 nm and 3000 nm. In this embodiment the n- type GaN may be silicon doped GaN with a doping level of greater than 5E17 cm-3 or less than about 1E20 cm-3. In one embodiment of this invention the epitaxial layers are formed by MOCVD. In another embodiment the sacrificial region and n-type contact layers are formed by MOCVD and the intrinsic region is formed by HVPE where growth rates are much higher so it is more economical to grow very thick layers.

[0128] In an alternative embodiment of a vertical Schottky diode device structure according to this invention the epitaxial structure in Figure 2C is fabricated to result in a device structure as shown in Figure 2D. In this embodiment, the epitaxial device material is prepared for transfer by forming a mesa region by etching the epitaxial material to a depth at or below the sacrificial region. The etching process can be a dry etching process such as a reactive ion etch (RIE), an inductively coupled plasma (ICP) etch, a chemical assisted ion beam etch (CAIBE), or other. Typical gases used in the etching process may include Cl and/or BC13. Alternatively, the mesa could be defined through a wet etch process. The wet etch process may be selective and designed to terminate on the sacrificial region. In this embodiment an n- type ohmic contact is formed on top of epitaxial region on the n-type GaN contact layer, which can be done either before or after the mesa is defined. The n-type ohmic contact would comprise a metal to allow for a good ohmic contact such as titanium or aluminum. In many embodiments a metal stack would be deposited with more than one layers wherein the ohmic contact layer is in contact with the n-type GaN layer and metals such as gold and/or nickel are configured in the stack overlying the ohmic contact layer. Metal depositions can be performed by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others. In some embodiments electroplating may be used to deposit a thick layer of a conductive metal such as gold to promote higher conductivity or coverage. In addition to preparing the epitaxial device layers for transfer step with the formation of the mesa structures with Schottky contacts and comprising bonding regions, the carrier wafer would be prepared for the transfer process. Overlying or part of the ohmic contact is a bonding region comprised of a metal. The metal may be the same metal as used for the ohmic contact layer, or in an embodiment, additional layers of metal would be deposited over the ohmic contact metal to form a metal layer stack. In one embodiment, this metal would be comprised of at least a gold metal to form a gold-gold bond.

[0129] In addition to preparing the epitaxial device layers for transfer step with the formation of the mesa structures with ohmic contacts and comprising bonding regions, the carrier wafer would be prepared for the transfer process. The carrier wafer could be selected from silicon, silicon carbide, sapphire, aluminum nitride, or others. In preparation for the transfer process, bonding regions would be formed on the carrier wafer, which in some embodiments may serve as, for example, an n-electrode or bond pad of the electronic device. In one embodiment the bonding region is a metal bonding region and is comprised of at least gold. Metal deposition can be performed by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others, and annealing steps may be used to improve the contact quality. In some embodiments electroplating may be used to deposit a thick layer of a conductive metal such as gold to promote high lateral conductivity. The transfer process may comprise a PEC etch to selectively remove the sacrificial release material followed by a bonding step to selectively transfer the epitaxial material to the carrier wafer and release the substrate. In this embodiment the bonding region is configured from a metal layer region comprising metal layers such as gold. The total thickness of this metal bonding region is a critical design aspect since it will be required to laterally conduct all of the device current from bonding pads positioned adjacent to the mesa to the ohmic contact in contact with the n-type contact layer. Once bonded, with the substrate released the remainder of the device process would be performed to the epitaxial device material on carrier wafer. Depending on the embodiment, subsequent processing steps may include forming the Schottky barrier contact with an exposed portion of the intrinsic or nominally undoped layer on the top of the transferred mesa. The Schottky barrier metal contact would be selected from one of or a combination of molybdenum, platinum, palladium, nickel, gold, chromium, tungsten, or others. Metal depositions can be performed by conventional methods such as electron beam deposition, sputtering, or thermal evaporation.

[0130] Additional processing steps to form the completed Schottky diode device could include photolithography, deposition of dielectric passivation regions such as silicon dioxide or silicon nitride. Dry or wet etching or lift off of the dielectric may be necessary to form patterned regions. Additionally, larger bond pad regions may be formed to make the device addressable by electrical power sources. The bond pads would be connected to the Schottky metal contact and/or the ohmic metal contact and may be configured to be partially or fully formed on the carrier wafer surrounding the epitaxial device material. Additionally, edge termination regions may be formed in the device. Edge termination is one of the key technologies for fabricating high voltage Schottky diodes, which functions to reduce the peak electric field along the Schottky contact edge and enhance the breakdown voltage. Several methods are used for edge termination including, but not limited to mesa, guard rings, field plates and high resistivity region by ion implantation can be used to reduce the chance of premature breakdown. A final device structure of this embodiment including edge termination regions is shown in Figure 2D.

[0131] In another embodiment of this invention, a p-n diode power electronic device can be fabricated. A p-n diode power device is a two terminal semiconductor diode based upon the p-n junction wherein the diode conducts current in only one direction, and it is made by joining a p-type semiconducting layer to an n-type semiconducting layer. Under a forward bias current flows with a small resistance and in reverse bias little or no current is able to flow until the diode reaches breakdown. Semiconductor p-n diodes have multiple uses including rectification of alternating current to direct current, detection of radio signals, emitting light and detecting light.

[0132] An ideal p-n diode should have characteristics such as high breakdown voltage, low leakage current, low forward voltage drop, low on-state resistance, and fast recovery. The key properties to form ideal p-n diodes are the selection of a semiconductor material with optimum intrinsic properties, semiconductor crystal quality with very low defect density, high quality intrinsic layer as drift region with desired thickness, a good ohmic n-contact for low n-type contact resistance for, a good ohmic p-contact for low p-type contact resistance; highly conductive n-type and p-type semiconductor layers sandwiching the intrinsic drift region, proper device structure and design, and good edge termination.

[0133] Two typical device geometries for p-n diodes are semi -vertical mesa and vertical. The GaN-based semi-vertical mesa structure typically comprises a mesa structure formed with an etching process into gallium and nitrogen containing material such as GaN. The epitaxial structure can be grown on either native GaN or foreign substrates such as silicon or sapphire. In one example an ohmic metal contact is made to a p-type semiconductor on the top of the mesa and an ohmic metal contact to an n-type semiconductor is made in the region surrounding the mesa. This performance can be limited in the semi-vertical mesa structure by the lateral conductivity of the n-type epi layers connecting n-type ohmic contact to the mesa region where current will flow vertically. With the introduction of native bulk GaN substrates truly vertical p-n diodes were enabled. By forming epitaxial intrinsic drift layers overly a highly doped GaN substrates, forming a p-type gallium and nitrogen containing layer such as p-type GaN overlying the intrinsic layer, and forming ohmic contacts to both the p-type region overlying the intrinsic region and the highly doped n-type substrates high performance truly vertical p-n diodes were realized. In this invention enables a truly vertical p-n diode device without the need for a substrate in the final device by using a highly conductive metal region to laterally conduct to the n-type contact in one configuration or laterally conduct to the p-type contact region in an alternative configuration. Since the metal layers such as gold are highly conductive and can be made several microns thick (1-10 microns or more) the lateral conductivity will be extremely high and even improved over the conductivity in conventional vertical Schottky diodes, which include the resistance of the substrate.

[0134] In a typical embodiment, a gallium and nitrogen containing semiconductor material intrinsic or unintentionally doped drift region is sandwiched between a p-type semiconductor gallium and nitrogen containing semiconductor such as GaN and n-type semiconductor gallium and nitrogen containing semiconductor such as GaN. A metal-semiconductor contact is formed between a metal and a p-type semiconductor such as p-GaN and a metalsemiconductor contact is formed between a metal and an n-type semiconductor such as n- type GaN. Typical metals used for a high-quality p-type contacts are palladium, platinum, nickel, or nickel-gold, but can be others. The metal region forming the Schottky barrier can be comprised of a metal stack comprising multiple layers including additional metals such as gold. The semiconductor unintentionally doped drift region or intrinsic region comprised of a gallium and nitrogen containing material such as GaN with very low conductivity is either unintentionally doped or may be intentionally doped with a species to compensate the unintentional background doping to achieve a low conductivity. These drift regions may be comprised of one or more layers, wherein the layers are comprised of GaN or other gallium and nitrogen containing alloys. These drift layers typically need to have carrier concentrations of less than about 1E17 cm-3, less than about 6E16 cm-3, less than about 3E16 cm-3, or less than about 1E16 cm-3. The thickness of this region is typically between 0.5 um and 10 um, or about 10 um and 30 um, or about 30 um and 60 um. The thicker and less conductive this region, the larger the breakdown voltage or critical field of the device.

[0135] Figures 2E and 2F illustrate a method by which the Schottky device is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0136] Figure 2E is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 2E(a), the Schottky device is partially formed on the gallium and nitrogen containing substrate or a foreign substrate, and as illustrated in figure 2E(b), the device is further processed to form edge termination and a Schottky contact, for example comprising a Schottky metal, such as platinum, nickel and/or palladium. The edge termination and the Schottky contact are formed using techniques discussed herein and/or otherwise known to those of skill in the art.

[0137] Figure 2F is a simplified schematic cross-section of the device of figure 2E after transfer to a carrier wafer according to an example of the present invention. The device may be attached to a Schottky contact electrode, which has been previously formed on the carrier wafer. The device may be additionally processed after being attached to the carrier wafer. In this example, after the device is attached to the carrier wafer, an n-type contact is formed on the exposed n+ GaN contact layer. The n-type contact may be formed using a metal such as aluminum and/or titanium using processes known to those of skill in the art, and/or discussed herein. The n-type contact may then be electrically connected with other contacts formed on the carrier wafer or formed on devices on the carrier wafer, for example using wire interconnects, wire bonding, or other methods. [0138] Trench structures may be used in GaN vertical devices. For example, they may be used in trench metal-insulator-semiconductor barrier Schottky rectifiers, where they shield the high electric field at the Schottky contact. The addition of the trench enhances reverse blocking characteristics of the GaN Schottky rectifier by increasing breakdown voltage and reducing leakage current at high reverse biases.

[0139] Trench structures can also be used in other vertical GaN power devices such as current aperture vertical electron transistors and MOSFETs. Normally-off GaN transistors also benefit from the addition of trenches. The current-aperture vertical electron transistor is a normally-on device that combines the high conductivity of a two-dimensional electron gas channel at the AlGaN/GaN heterojunction with the improved field distribution of a vertical structure. Normally-off operation is possible by switching to a trenched semi-polar gate. Using a trench with the vertical GaN MOSFET combines normally-off operation with low on-resistance.

[0140] Figures 2G and 2H illustrate a method by which the device, a metal-insulator- semiconductor barrier Schottky rectifier, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0141] Figure 2G is a simplified schematic cross-section of a vertical metal-insulator semiconductor barrier Schottky rectifier according to an example of the present invention. The rectifier is formed on a gallium and nitrogen containing substrate or a foreign substrate using techniques discussed herein and/or otherwise known to those of skill in the art.

[0142] Figure 2H is a simplified schematic cross-section of the rectifier illustrated in figure 2G attached to a carrier wafer according to an example of the present invention. The rectifier is attached to a bond pad which may serve as a cathode electrode comprising a metal, such as aluminum or titanium, where the cathode has been previously formed on the carrier wafer. The rectifier may be additionally processed after being attached to the carrier wafer. In this example, the exposed GaN drift layer is etched to form trenches, which are subsequently processed so as to have a dielectric layer formed therein, as illustrated. The dielectric layer may comprise any dielectric material, such as those discussed herein, or otherwise known to those of skill in the art. The processing may also include forming an anode contact in the trenches. The material of the anode contact may for example, be a metal or another conductor, such as those discussed herein, or otherwise known to those of skill in the art. As understood by those of skill in the art, the trenches enhance the reverse current blocking characteristics of the rectifier, reduce the leakage current at high reverse biases, and increase or double the breakdown voltage reverse biased.

[0143] Figures 21 and 2J illustrate a method by which the device, a metal-insulator- semiconductor barrier Schottky rectifier, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0144] Figure 21 is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 21(a), the device is partially formed on the gallium and nitrogen containing substrate or a foreign substrate, and as illustrated in figure 21(b), the device is further processed to form trenches with dielectric layers and an anode contact, for example, using materials and techniques discussed elsewhere herein and/or otherwise known to those of skill in the art.

[0145] Figure 2J is a simplified schematic cross-section of the device of figure 21 transferred to a carrier wafer according to an example of the present invention. The device is attached to a bonding pad, which may serve as an anode electrode of the metal-insulator- semiconductor barrier Schottky rectifier device, comprising a metal, such as aluminum or titanium, where the anode electrode has been previously formed on the carrier wafer. The device may be additionally processed after being attached to the carrier wafer. In this example, after the device is attached to the carrier wafer, a cathode n-type contact is formed on the exposed n+ GaN contact layer. The cathode contact may be formed using a metal such as aluminum and/or titanium according to processes known to those of skill in the art and/or discussed herein. The cathode contact may then be electrically connected with other contacts formed on the carrier wafer or formed on devices on the carrier wafer, for example using wire interconnects, wire bonding, or other methods.

[0146] In one embodiment of this invention, a p-n diode epitaxial structure is grown on a bulk gallium and nitrogen containing substrate such as GaN or a foreign substrate. The growth is comprised of an epitaxial technique such as metal organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a combination. As shown in Figure 3 A, the epitaxial structure would comprise a buffer layer grown on top of the GaN substrate. The buffer layer could be comprised of GaN or n-type GaN. Overlying the buffer layer is a sacrificial region as described in this invention. Overlying the sacrificial region are the p-n diode device layers comprising an n-type contact layer such as n-type GaN, a nominally unintentionally doped drift region or intrinsic region comprised of gallium and nitrogen containing material such as GaN overlying the n-type contact region, and an p-type contact layer such as p-type GaN overlying the nominally unintentionally doped drift region or intrinsic region comprised of gallium and nitrogen containing material. In one embodiment the n-contact layer is comprised n-type GaN with a thickness of between 10 nm and 100 nm or 100 nm and 3000 nm. In one embodiment the n- type GaN may be silicon doped GaN with a doping level of greater than 5E17 cm-3 or less than about 1E20 cm-3. In one embodiment the intrinsic region or drift region is comprised of a thickness of 1 um to about 10 um or about 10 um to about 30 um or about 30 um to about 60 um and is comprised of unintentionally doped GaN with a total carrier concentration of less than 1E17 cm-3, less than 5E16 cm-3, less than 2E16 cm-3, or less than 8E15 cm-3. In another embodiment, the intrinsic region is comprised of an intentional dopant intended to compensate the unintentional background dopants to reduce the total carrier concentration and reduce the conductivity. In one embodiment the p-contact layer is comprised p-type GaN with a thickness of between 10 nm and 100 nm or 100 nm and 3000 nm. In one embodiment the p-type GaN may be magnesium doped GaN with a doping level of greater than 5E17 cm- 3 or less than about 1E20 cm-3. In one embodiment of this invention the epitaxial layers are formed by MOCVD. In another embodiment the sacrificial region and n-type contact layers are formed by MOCVD and the intrinsic region is formed by HVPE where growth rates are much higher so it is more economical to grow very thick layers.

[0147] In one embodiment, a vertical p-n diode device structure is formed from the epitaxial structure in Figure 3 A to result in a device structure as shown in Figure 3B. In this embodiment, the epitaxial device material is prepared for transfer by forming a mesa region by etching the epitaxial material to a depth at or below the sacrificial region. The etching process can be a dry etching process such as a reactive ion etch (RIE), an inductively coupled plasma (ICP) etch, a chemical assisted ion beam etch (CAIBE), or other. Typical gases used in the etching process may include Cl and/or BC13. Alternatively, the mesa could be defined through a wet etch process. The wet etch process may be selective and designed to terminate on the sacrificial region. In this embodiment, an ohmic contact is formed on top of epitaxial region on the p-type gallium and nitrogen containing material, which can be done either before or after the mesa is defined. The metal for the ohmic contact would be selected, for example, from one of or a combination of platinum, palladium, nickel, nickel-gold, gold, or others. Overlying the p-type contact is a bonding region comprised of a metal, which in some embodiments may be, for example, an p-type contact of the p-n diode device comprised of a metal such as Al, Ti, or the like. The metal may be the same metal as used for the ohmic p- type contact, or in an embodiment, additional layers of metal may be deposited over the p- type contact metal. In one embodiment, this metal would be a gold metal to form a gold-gold bond. Metal depositions can be performed by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others, and annealing steps may be used to enhance the contact properties. In some embodiments electroplating may be used to deposit a thick layer of a conductive metal such as gold to promote higher conductivity or coverage.

[0148] In addition to preparing the epitaxial device layers for the transfer step with the formation of the mesa structures with p-type contacts and comprising bonding regions, the carrier wafer would be prepared for the transfer process. The carrier wafer could be selected from silicon, silicon carbide, sapphire, aluminum nitride, or others. In preparation for the transfer process, bonding regions would be formed on the carrier wafer, which in some embodiments may serve as, for example, an p-electrode or bond pad of the electronic device. In one embodiment the bonding region is a metal bonding region and is comprised of at least gold. Metal deposition can be performed by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others, and annealing steps may be used to improve the contact quality. In some embodiments electroplating may be used to deposit a thick layer of a conductive metal such as gold to promote high lateral conductivity. The transfer process would comprise a PEC etch to selectively remove the sacrificial release material followed by a bonding step to selectively transfer the epitaxial material to the carrier wafer and release the substrate. In this embodiment the bonding region is configured from a metal layer region comprising metal layers such as gold. The total thickness of this metal bonding region is a critical design aspect since it will be required to laterally conduct all of the device current from bonding pads positioned adjacent to the mesa to the p-type contact. Once bonded, with the substrate released the remainder of the device process would be performed to the epitaxial device material on the carrier wafer. The subsequent processing steps would include forming the n-type ohmic contact with the exposed n-type semiconductor contact layer on the top of the transferred mesa. The n-type contact would comprise a metal to allow for a good ohmic contact such as titanium or aluminum. In many embodiments a metal stack would be deposited with more than one layers wherein the n-type contact layer is in contact with the n-type GaN layer and metals such as gold, nicker, platinum, or palladium are configured in the stack overlying the n-type contact layer. The n-type metal deposition can be performed by conventional methods such as electron beam deposition, sputtering, or thermal evaporation, and annealing steps may be used to improve the contact quality.

[0149] Additional processing steps to form the completed p-n diode device could include photolithography, deposition of dielectric passivation regions such as silicon dioxide or silicon nitride. Dry or wet etching or lift off of the dielectric may be necessary to form a patterned region. Additionally, larger bond pad regions may be formed to make the device addressable by electrical power sources. The bond pads would be connected to the p-type contact metal and/or the n-type contact metal and may be configured to be partially or fully formed on the carrier wafer surrounding the epitaxial device material. Additionally, edge termination regions may be formed in the device. Edge termination is one of the key technologies for fabricating high voltage diodes, which functions to reduce the peak electric field along the contact edge and enhance the breakdown voltage. Several methods are used for edge termination including, but not limited to mesa, guard rings, field plates and high resistivity region by ion implantation can be used to reduce the chance of premature breakdown.

[0150] In an alternative embodiment of this invention, a p-n diode epitaxial structure is grown on a bulk gallium and nitrogen containing substrate such as GaN or a foreign substrate. The growth is comprised of an epitaxial technique such as metal organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a combination. The epitaxial structure according to this embodiment, as shown in Figure 3C, comprises a buffer layer grown on top of the GaN substrate. The buffer layer could be comprised of GaN or n-type GaN. Overlying the buffer layer is a sacrificial region as described in this invention. Overlying the sacrificial region are the p-n diode device layers comprising an p-type contact layer such as p-type GaN, a nominally unintentionally doped drift region or intrinsic region comprised of gallium and nitrogen containing material such as GaN overlying the p-type contact region, and an n-type contact layer such as n-type GaN overlying the nominally unintentionally doped drift region or intrinsic region comprised of gallium and nitrogen containing material. In one embodiment the p-contact layer is comprised p-type GaN with a thickness of between 10 nm and 100 nm or 100 nm and 3000 nm. In one embodiment the p-type GaN may be magnesium doped GaN with a doping level of greater than 5E17 cm-3 or less than about 1E20 cm-3. In one embodiment the intrinsic region or drift region is comprised of a thickness of 1 um to about 10 um or about 10 um to about 30 um or about 30 um to about 60 um and is comprised of unintentionally doped GaN with a total carrier concentration of less than 1E17 cm-3, less than 5E16 cm-3, less than 2E16 cm-3, or less than 8E15 cm-3. In another embodiment, the intrinsic region is comprised of an intentional dopant intended to compensate the unintentional background dopants to reduce the total carrier concentration and reduce the conductivity. In one embodiment the n-contact layer is comprised n-type GaN with a thickness of between 10 nm and 100 nm or 100 nm and 3000 nm. In one embodiment the n-type GaN may be silicon doped GaN with a doping level of greater than 5E17 cm-3 or less than about 1E20 cm-3. In one embodiment of this invention the epitaxial layers are formed by MOCVD. In another embodiment the sacrificial region and n-type contact layers are formed by MOCVD and the intrinsic region is formed by HVPE where growth rates are much higher so it is more economical to grow very thick layers.

[0151] In this embodiment, a vertical p-n diode device structure is formed from the epitaxial structure in Figure 3C to result in a device structure as shown in Figure 3D. In this embodiment, the epitaxial device material is prepared for transfer by forming a mesa region by etching the epitaxial material to a depth at or below the sacrificial region. The etching process can be a dry etching process such as a reactive ion etch (RIE), an inductively coupled plasma (ICP) etch, a chemical assisted ion beam etch (CAIBE), or other. Typical gases used in the etching process may include Cl and/or BC13. Alternatively, the mesa could be defined through a wet etch process. The wet etch process may be selective and designed to terminate on the sacrificial region. In this embodiment, an ohmic contact is formed on top of epitaxial region on the n-type gallium and nitrogen containing material, which can be done either before or after the mesa is defined. The metal for the ohmic contact would be selected, for example, from one of or a combination of aluminum, titanium, platinum, palladium, nickel, nickel-gold, gold, or others. Overlying the n-type contact is a bonding region comprised of a metal, which in some embodiments may be, for example, an n-type contact of the p-n diode device comprised of a metal such as Al, Ti, or the like. The metal may be the same metal as used for the ohmic n-type contact, or in an embodiment, additional layers of metal may be deposited over the n-type contact metal. In one embodiment, this metal would be a gold metal to form a gold-gold bond. Metal depositions can be performed by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others, and annealing steps may be performed. In some embodiments electroplating may be used to deposit a thick layer of a conductive metal such as gold to promote higher conductivity or coverage. [0152] In addition to preparing the epitaxial device layers for the transfer step with the formation of the mesa structures with n-type contacts and comprising bonding regions, the carrier wafer would be prepared for the transfer process. The carrier wafer could be selected from silicon, silicon carbide, sapphire, aluminum nitride, or others. In preparation for the transfer process, bonding regions would be formed on the carrier wafer, which in some embodiments may serve as, for example, an n-electrode or bond pad of the electronic device. In one embodiment the bonding region is a metal bonding region and is comprised of at least gold. Metal deposition can be performed by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others, and annealing steps may be used to improve the contact quality. In some embodiments electroplating may be used to deposit a thick layer of a conductive metal such as gold to promote high lateral conductivity. The transfer process would comprise a PEC etch to selectively remove the sacrificial release material followed by a bonding step to selectively transfer the epitaxial material to the carrier wafer and release the substrate. In this embodiment the bonding region is configured from a metal layer region comprising metal layers such as gold. The total thickness of this metal bonding region is a critical design aspect since it will be required to laterally conduct all of the device current from bonding pads positioned adjacent to the mesa to the n-type contact. Once bonded, with the substrate released the remainder of the device process would be performed to the epitaxial device material on the carrier wafer. The subsequent processing steps would include forming the p-type ohmic contact with the exposed p-type semiconductor contact layer on the top of the transferred mesa. The p-type ohmic contact would comprise a metal to allow for a good ohmic contact such as platinum, palladium, nickel, nickel-gold, or a combination thereof. In many embodiments a metal stack would be deposited with more than one layers wherein the ohmic contact layer is in contact with the n-type GaN layer and metals such as gold, nickel, platinum, or palladium are configured in the stack overlying the contact layer. The p-type contact metal deposition can be performed by conventional methods such as electron beam deposition, sputtering, or thermal evaporation, and annealing steps may be used to improve the contact quality.

[0153] Additional processing steps to form the completed p-n diode device could include photolithography, deposition of dielectric passivation regions such as silicon dioxide or silicon nitride. Dry or wet etching or lift off of the dielectric may be necessary to form a patterned region. Additionally, larger bond pad regions may be formed to make the device addressable by electrical power sources. The bond pads would be connected to the p-type contact metal and/or the n-type contact metal and may be configured to be partially or fully formed on the carrier wafer surrounding the epitaxial device material. Additionally, edge termination regions may be formed in the device. Edge termination is one of the key technologies for fabricating high voltage diodes, which functions to reduce the peak electric field along the contact edge and enhance the breakdown voltage. Several methods are used for edge termination including, but not limited to mesa, guard rings, field plates and high resistivity region by ion implantation can be used to reduce the chance of premature breakdown.

[0154] Figures 3E and 3F illustrate a method by which the p-n diode device is formed and partially processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0155] Figure 3E is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated, in figure 3E(a), the device is partially formed on the substrate, and as illustrated in figure 3E(b), the device is further processed to form edge termination and a p-type contact, for example comprising a metal, such as platinum, nickel and/or palladium. The edge termination and p-type contact are formed using techniques discussed herein and/or otherwise known to those of skill in the art.

[0156] Figure 3F is a simplified schematic cross-section of the device of figure 3E after transfer to a carrier wafer according to an example of the present invention. The device is attached to a contact electrode, which has been previously formed on the carrier wafer. The device may be additionally processed after being attached to the carrier wafer. In this example, after the device is attached to the carrier wafer, an n-type contact is formed on the exposed n+ GaN contact layer. The n-type contact may be formed using a metal such as aluminum and/or titanium using processes known to those of skill in the art and/or discussed herein. The n-type contact may then be electrically connected with other contacts formed on the carrier wafer or formed on devices on the carrier wafer, for example using wire interconnects, wire bonding, or other methods.

[0157] Figures 3G and 3H illustrate a method by which the device, a vertical SITs device, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0158] Figure 3G is a simplified schematic cross-section of a vertical SITs device according to an example of the present invention. The device is formed on a gallium and nitrogen containing substrate or a foreign substrate using techniques discussed herein and/or otherwise known to those of skill in the art.

[0159] Figure 3H is a simplified schematic cross-section of the device illustrated in figure 3G after transfer to a carrier wafer according to an example of the present invention. The device may be attached to a bonding pad that serves as a drain contact comprising, for example, a metal, such as aluminum or titanium, where the drain contact has been previously formed on the carrier wafer. The device may be additionally processed after being attached to the carrier wafer. In this example, the exposed n+ GaN contact layer and the GaN drift layer are etched to form recess regions where gate contact layers are formed as illustrated. The gate contact layers may comprise any conductive material, such as those discussed herein or otherwise known to those of skill in the art. The further processing may also include forming a source contact on the n+ GaN contact layer. The material of the source contact may for example, be a metal or another conductor, such as those discussed herein or otherwise known to those of skill in the art.

[0160] Figures 31 and 3 J illustrate a method by which the device, a vertical SITs device, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0161] Figure 31 is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 31(a), the device is partially formed on the substrate, and as illustrated in figure 31(b), the device is further processed by etching the exposed n+ GaN contact layer and the GaN drift layer to form the recess regions where gate contact layers are formed as illustrated. The gate contact layers may comprise any conductive material, such as those discussed herein or otherwise known to those of skill in the art. The further processing may also include forming a source contact on the n+ GaN contact layer. The material of the source contact may, for example, be a metal or another conductor, such as those discussed herein or otherwise known to those of skill in the art.

[0162] Figure 3 J is a simplified schematic cross-section of the device of figure 31 transferred to a carrier wafer according to an example of the present invention. The device is attached to source and gate electrodes comprising a metal, such as aluminum or titanium, where the source and gate electrodes have been previously formed on the carrier wafer. The device may be additionally processed after being attached to the carrier wafer. In this example, after the device is attached to the carrier wafer, a drain contact is formed on the exposed n+ GaN contact layer. The drain contact may be formed using a metal such as aluminum and/or titanium using processes known to those of skill in the art and/or discussed herein. The drain contact may then be electrically connected with other contacts formed on the carrier wafer or formed on devices on the carrier wafer, for example using wire interconnects, wire bonding, or other methods.

[0163] Figures 3K and 3L illustrate a method by which the device, a vertical CAVET device, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0164] Figure 3K is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 3K(a), the device is partially formed on the substrate. In addition, as illustrated in figure 3K(b), the device is further processed to form current blocking layers as illustrated. The current blocking layers may be formed using, for example, an ion implant process, a selective p-GaN growth process, or another process, such as those discussed herein or otherwise known to those of skill in the art. As illustrated in figure 3K(c), the further processing also includes forming a second GaN drift layer and an n+ GaN layer over the previously formed GaN drift layer and the current blocking layers. The second GaN drift layer and the n+ GaN layer may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art.

[0165] Figure 3L is a simplified schematic cross-section of the device of figure 3K transferred to a carrier wafer according to an example of the present invention. The device is attached to a bonding pad, which may serve as a drain electrode comprising, for example, a metal, such as aluminum or titanium, where the drain electrode has been previously formed on the carrier wafer. The device may be additionally processed after being attached to the carrier wafer. In this example, the exposed p+ GaN layer, the AlGaN layer, and the GaN drift layer are etched to form recesses where source contact layers are formed as illustrated. The source contact layers may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art. The further processing may also include forming a gate contact on the p+ GaN contact layer. The gate contact may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art. [0166] Figures 3M and 3N illustrate a method by which the device, a vertical CAVET device, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0167] Figure 3M is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 3M(a), the device is partially formed on the substrate. In addition, as illustrated in figure 3M(b), the device is further processed to form current blocking layers as illustrated. The current blocking layers may be formed using, for example, an ion implant process, a selective p-GaN growth process, or another process, such as those discussed herein or otherwise known to those of skill in the art. As illustrated in figure 3M(c,) the further processing also includes forming a second GaN drift layer, an Al GaN layer, and a p+ GaN layer over the previously formed GaN drift layer and the current blocking layers. The second GaN drift layer, the AlGaN layer, and the p+ GaN layer may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art.

[0168] As illustrated in figure 3N(a), the further processing also includes etching the exposed p+ GaN layer, the AlGaN layer, and the GaN drift layer to form recesses where source contact layers are formed as illustrated. The source contact layers may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art. The further processing also includes forming a gate contact on the p+ GaN contact layer. The gate contact may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art.

[0169] Figure 3N(b) is a simplified schematic cross-section of the device of figures 3M and 3N(a) transferred to a carrier wafer according to an example of the present invention. The device is attached to gate and source electrodes comprising, for example, a metal, such as aluminum or titanium, where the gate and source electrodes have been previously formed on the carrier wafer. The device may be additionally processed after being attached to the carrier wafer. In this example, a drain electrode bond pad is formed on the n+ GaN layer. The drain electrode may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art.

[0170] Figures 30 and 3P illustrate a method by which the device, a vertical MOSFET device, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer. [0171] Figure 30 is a simplified schematic cross-section of a structure of a device according to an example of the present invention. The device is formed on a gallium and nitrogen containing substrate or a foreign substrate using materials and processes such as those discussed herein or otherwise known to those of skill in the art.

[0172] Figure 3P is a simplified schematic cross-section of the device of figure 30 after transfer to a carrier wafer according to an example of the present invention. The device may be attached to bonding pad that serves as a drain electrode comprising, for example, a metal, such as aluminum or titanium, where the drain electrode has been previously formed on the carrier wafer. The device may be additionally processed after being attached to the carrier wafer. In this example, the exposed n+ GaN layer, the p+ GaN layer, and the GaN drift layer are etched to form a trench where a dielectric layer and a gate contact are formed therein as illustrated. The dielectric layer and the gate contact may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art. The further processing may also include forming source contacts on the n+ GaN layer. The source contacts may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art.

[0173] Figures 3Q and 3R illustrate a method by which the device, a vertical MOSFET device, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0174] Figure 3Q is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 3Q(a), the device is partially formed on the substrate, and as illustrated in figure 3Q(b), the device is further processed by etching the exposed n+ GaN layer, the p+ GaN layer, and the GaN drift layer to form a trench where a dielectric layer and a gate contact are formed therein as illustrated. The dielectric layer and the gate contact may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art. The processing also includes forming source contacts on the n+ GaN layer. The source contacts may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art.

[0175] Figure 3R is a simplified schematic cross-section of the device of figure 3Q after transfer to a carrier wafer according to an example of the present invention. The device may be attached to gate and source electrodes comprising, for example, a metal, such as aluminum or titanium, where the gate and source electrodes have been previously formed on the carrier wafer. The device maybe additionally processed after being attached to the carrier wafer. In this example, the additional processing includes forming a drain contact on the n+ GaN contact layer. The drain contact may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art. Similar processing could be used for a FIN MOSFET (FINFET) or other electronic devices.

[0176] Figures 3S and 3T illustrate a method by which the device, a trench CAVET device, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0177] Figure 3S is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 3S(a), the device is partially formed on the substrate. In addition, as illustrated in Figure 3S(b), the device is further processed such that the exposed p GaN layer is etched to form a trench. In addition, as illustrated in figure 3S(c), the device is further processed such that a GaN layer, an AlGaN layer, and a dielectric layer are formed as illustrated. The GaN layer, the AlGaN layer, and the dielectric layer may be formed using materials and processes such as those discussed herein or otherwise known to those of skill in the art.

[0178] In addition, as illustrated in Figure 3T(a), the further processing also includes etching the dielectric layer, the AlGaN layer, and the second GaN drift layer to form recesses where source contacts are formed. As illustrated, the further processing also includes forming a gate contact on the dielectric layer. The source contacts and the gate contact may be formed using materials and processes such as those discussed herein or otherwise known to those of skill in the art.

[0179] Figure 3T(b) is a simplified schematic cross-section of the device of figure 3S and 3T(a) after transfer to a carrier wafer according to an example of the present invention. The device is attached to gate and source electrodes comprising, for example, a metal, such as aluminum or titanium, where the gate and source electrodes have been previously formed on the carrier wafer. The device is additionally processed after being attached to the carrier wafer. In this example, the additional processing includes forming a drain electrode bond pad on the n+ GaN contact layer. The drain electrode bond pad may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art. [0180] Figures 3U and 3 V illustrate a method by which the device, a vertical enhancement mode junction field effect transistor (eJFET) device, is formed and partially or fully processed while attached to the gallium and nitrogen containing or foreign wafer, and by which the device is transferred to the carrier wafer.

[0181] Figure 3U is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 3U(a), the device is partially formed on the substrate. In addition, as illustrated in Figure 3U(b), the device is further processed such that the exposed GaN drift layer is etched to form recesses. In addition, as illustrated in figure 3U(c), the device is further processed such that pGaN layers and junction termination JTE are formed. The pGaN layers and the junction termination may be formed using materials and processes such as those discussed herein or otherwise known to those of skill in the art.

[0182] Furthermore, as illustrated in Figure 3 V(a), the device is further processed to form source and gate contacts. The source and gate contacts may be formed using materials and processes such as those discussed herein or otherwise known to those of skill in the art.

[0183] Figure 3 V(b) is a simplified schematic cross-section of the device of figure 3U and 3 V(a) after transfer to a carrier wafer according to an example of the present invention. The device may be attached to gate and source electrodes comprising, for example, a metal, such as aluminum or titanium, where the gate and source electrodes have been previously formed on the carrier wafer. The device is additionally processed after being attached to the carrier wafer. In this example, the additional processing includes forming a drain contact on the GaN drift layer. The drain contact may be formed using materials and processes, such as those discussed herein or otherwise known to those of skill in the art.

[0184] Another embodiment of a GaN power device fabricated according to this invention is a high electron mobility transistor device (HEMT), which is a three terminal device comprised of a source, a gate, and a drain. The HEMT is a heterostructure field-effect transistor (FET) based on a heterojunction which consists of at least two different semiconducting materials such as GaN and Al GaN brought into contact with each other to form an interface, typically using epitaxial growth. Due to the different band gaps of the semiconductor materials and their relative alignment to each other, band discontinuities form at the interface. By choosing proper materials and compositions of the semiconductor materials, the conduction band offset can form a triangular shaped potential well confining electrons in the horizontal direction. Within the well the electrons can only move in a two- dimensional plane parallel to the heterointerface and are therefore referred to as a two- dimensional electron gas (2DEG). Since the HEMT is a field effect transistor (FET) formed with a heterostructure it is also known as an (HFET) or modulation-doped FET (MODFET). The advantages of the HEMT include its high carrier concentration and its higher electron mobility due to reduced ionized impurity scattering. The combination of high carrier concentration and high electron mobility results in a high current density and a low channel resistance, which are especially important for high frequency operation and power switching applications.

[0185] GaN HEMTs have attracted attention due to their high-power performance. HEMT transistors are able to operate at higher frequencies than ordinary transistors, up to millimeter wave frequencies, and are used in high-frequency products such as cell phones, satellite television receivers, voltage converters, and radar equipment.

[0186] GaN power transistors are typically formed as planar HEMT devices, where the conductive transistor channel is a 2DEG formed at the interface between a high bandgap layer such as AlGaN, AIN, or InAlGaN, and a lower bandgap layer such as GaN or InGaN. Source and drain contacts are formed to the 2DEG, while a gate is formed over the higher bandgap layer such as AlGaN. Imperfections in the crystalline epitaxial structure that create traps or other defects can limit performance such as compressing the gain and other nonlinear effects. Forming a very high-quality epitaxial material free from defects and excessive impurities is critical to the device performance. Efforts to form higher quality epi-layers in AlGaN/GaN HEMTs have resulted in significant improvement of the large-signal characteristics. This first step of device formation comprises forming the epitaxial layer structure on a substrate. The lack of large area, low cost GaN substrates has historically necessitated heteroepitaxy on compatible substrates, commonly sapphire, silicon carbide, or silicon, but can be others such as aluminum nitride. The epitaxial layers may be either grown entirely by MBE or MOCVD or on a resistive GaN buffer grown by vapor phase epitaxy.

[0187] Heteroepitaxy on such severely lattice-mismatched substrates makes the nucleation layer and buffer one of the most critical aspects of the growth. With sapphire as a substrate, the nucleation layer typically consists of GaN or AIN. Overlying the buffer layer is typically an insulating GaN layer with a thickness ranging from about 0.5 um to about 5 um or about 5 um to 10 um. The insulating layer can be an intrinsic region, a not intentionally doped region (NID) an unintentionally doped region (UID), or a region intentionally doped to compensate the unwanted background dopants and increase the resistance. Typical carrier concentrations in this insulating layer would be less than about 1E17 cm-3, less than about 5E17 cm-3, or less than about 1E16 cm-3. Overlying the insulating GaN layer is the AlGaN electron supply region. The AlGaN electron supply region may be comprised of an AlGaN layer doped with silicon at a concentration of between 5E17 cm-3 and 1E20 cm-3 with a thickness ranging from 5 nm to about 100 nm. In some embodiments no doping is used or a modulation doped is implemented. In some embodiments the AlGaN supply region is comprised of multiple layers including an undoped AlGaN spacer layer ranging in thickness from 1 nm to about 15 nm overlying the GaN insulating layer, the n-type doped AlGaN layer with a thickness ranging from 5 nm to 100 nm overlying the AlGaN spacer layer, and an undoped AlGaN barrier layer with a thickness ranging 5 nm to 100 nm overlying the n-type doped AlGaN layer. The AlGaN supply region may be comprised of a substantially uniform AlGaN composition or a graded or non-uniform AlGaN composition. In some embodiments the AlGaN composition will range from 5% to 15% AIN, or about 15% to about 30% AIN, or about 30% to about 50% AIN. The composition of the AlGaN electron supply region is a critical design parameter as it can influence the carrier concentration. In some embodiments, a GaN cap or n-type GaN layer may be formed over the AlGaN electron supply region.

[0188] An example of a conventional HEMT device grown on a foreign substrate is shown in Figure 4A. Following the formation of the AlGaN and GaN epitaxial layers, device fabrication of a typical AlGaN/GaN HEMT as shown in Figure 4A may initiate with the definition of the active device area. This can be either be defined through a patterning and etching of a mesa process or an implantation process. In the more typical etching embodiment, wet or dry etching techniques can be deployed wherein C12 or BC13 are common gases used in etching by RIE, ICP, or CAIBE methods of etching. Next, the source and drain ohmic contacts are formed. In one embodiment the source and drain contacts are made by partially etching the AlGaN region in the source and drain regions and depositing the ohmic contact metals. In another embodiment the source and drain contacts are formed directly to the AlGaN surface region. In yet another embodiment the source and drain contacts are made by etching through the AlGaN region and into the insulating GaN region to form an ohmic contact directly with the 2DEG. In yet another embodiment, the source and drain contacts are formed on an n-type GaN or NID GaN layer overlying the AlGaN region. The source and drain contact metallization is often followed by an annealing step to improve the contact characteristics. An example ohmic contact may be Ti/Al/Ni/Au, but it could be others such as Al/Ni/Au, a Ta-based ohmic contact, or others. The gate metal is typically defined by a deposition and lift-off process of a metal such as Ni/Au, but could be others such as Pt, Pd, or Au. The deposition method can be electron beam deposition, sputtering, thermal evaporation, or other techniques. In many of the early GaN transistors, this gate electrode was formed as a Schottky contact to the top surface. By applying negative voltage to this contact, the Schottky barrier becomes reverse biased and the electrons underneath are depleted. Therefore, in order to turn this device OFF, a negative voltage relative to both drain and source electrodes is needed. This type of transistor is called a depletion mode, or d-mode, HFET. Dielectric passivation layers are formed on the device to electrically isolate certain features, protect certain regions, and to eliminate dispersion between the large signal alternating current (AC) and the direct current (DC) characteristics of the HEMT.

[0189] In the example conventional HEMT device in Figure 4A, as with any power FET, there are gate, source, and a drain electrodes. The source and drain electrodes form an ohmic contact with the underlying 2DEG. This creates a short-circuit between the source and the drain until the 2DEG is depleted and the semi-insulating GaN crystal can block the flow of current. The gate electrode is placed on top of the Al GaN layer functioning to deplete the 2DEG. In some embodiments, the gate electrode is formed as a Schottky contact to the top surface. By applying negative voltage to this contact, the Schottky barrier becomes reverse biased and the electrons underneath are depleted. Therefore, in order to turn this device OFF, a negative voltage relative to both drain and source electrodes is needed. This type of transistor is called a depletion mode, or d-mode, HFET and is a normally ON device. Embodiments for normally OFF devices are possible in the present invention.

[0190] In one embodiment according to this invention, a HEMT epitaxial device structure is grown on a bulk gallium and nitrogen containing substrate such as GaN or on a foreign substrate. The growth is comprised of an epitaxial technique such as metal organic vapor deposition (MOCVD) or molecular beam epitaxy (MBE), but can be other techniques. As shown in Figure 4B, the epitaxial structure would comprise a buffer layer grown on top of the GaN substrate. The buffer layer could be comprised of GaN or n-type GaN. Overlying the buffer layer is a sacrificial region as described in this invention. Overlying the sacrificial region are the HEMT device layers comprising a higher bandgap material such as AlGaN electron supply region overlying the sacrificial region and an intrinsic region or nominally UID or NID insulating gallium and nitrogen containing material such as GaN overlying the higher bandgap region. The AlGaN electron supply region may be comprised of an AlGaN layer doped with silicon at a concentration of between 1E18 cm-3 and 1E20 cm-3 with a thickness ranging from about 5 nm to about 100 nm. In some embodiments no doping is used or a modulation doping is implemented. The AlGaN supply region may be comprised of multiple layers including an undoped AlGaN spacer layer ranging in thickness from 1 nm to about 15 nm, an n-type doped AlGaN layer with a thickness ranging from 5 nm to 100 nm, and an undoped AlGaN barrier layer with a thickness ranging 5 nm to 100 nm. The AlGaN supply region may be comprised of a substantially uniform AlGaN composition or a graded or non-uniform AlGaN composition. In some embodiments the AlGaN composition will range from 5% to 15% AIN, or about 15% to about 30% AIN, or about 30% to about 50% AIN. The insulating layer is comprised of GaN and may be an NID, UTD, or an intentionally doped region to compensate the unwanted background dopants and increase the resistance and create the insulating property. The insulating region would comprise a thickness ranging from about 0.5 um to about 5 um or about 5 um to 10 um with a typical carrier concentrations of less than about 1E17 cm-3, less than about 5E16 cm-3, or less than about 1E16 cm-3, or less than about 5E15 cm-3. In other embodiments the high bandgap layer may be comprised of AIN.

[0191] In one embodiment according to this invention, the epitaxial device material, such as that shown in Figure 4B, is prepared for transfer by forming a mesa region by etching the epitaxial material to a depth at or below the sacrificial region. The etching process can be a dry etching process such as a reactive ion etch (RIE), an inductively coupled plasma (ICP) etch, a chemical assisted ion beam etch (CAIBE), or other. Typical gases used in the etching process may include Cl and/or BC13. Alternatively, the mesa could be defined through a wet etch process. The wet etch process may be selective and designed to terminate on the sacrificial region. A bonding region is formed overlying the mesa region. The bonding region may be comprised of a metal, a dielectric, an oxide, or from a semiconductor layer overlying the GaN insulating layer. In some embodiments it is desirable to use an insulating bonding region to isolate the device and minimize parasitic capacitance of the final device. Examples of insulating bond regions would oxide bonding regions, dielectric bonding regions, glass bonding regions, or polymer bonding regions, or other.

[0192] In addition to preparing the epitaxial device layers for the transfer step with the formation of the mesa structures and bonding regions, the carrier wafer is prepared for the transfer process. The carrier wafer could be selected from silicon, silicon carbide, sapphire, aluminum nitride, or others. In a preferred embodiment the carrier wafer would be insulating or semi-insulating and would be selected from sapphire, silicon carbide, or aluminum nitride. In preparation for the transfer process, bonding regions may be formed on the carrier wafer. The bonding region could be comprised of metal, dielectric, oxide, semiconductor, glass, polymer, or other, or a combination thereof. In an embodiment, the bonding region would be similar to the bonding region on the top of the mesa structures such that the bond interface would be comprised of a like-like material, such as oxide-oxide, semiconductorsemiconductor, or metal-metal. In the case of oxide or dielectrics, depositions may be performed with chemical vapor deposition processes, sputtering processes, electron beam deposition processes, or other processes. For metal interfaces, the material can be deposited by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others. In an alternative embodiment the bonding region is comprised of two dissimilar materials such as semiconductor-glass, oxide-glass, semiconductor-polymer, or other. The transfer process would comprise a PEC etch to selectively remove the sacrificial release material followed by a bonding step to selectively transfer the epitaxial material to the carrier wafer and release the substrate. The bonding may be selected from a thermocompression bonding, a diffusion bonding, or other. Once bonded, with the substrate released the remainder of the device process would be performed to the epitaxial device material on the carrier wafer.

[0193] In one embodiment according to this invention, the epitaxial device material, such as that shown in Figure 4C, is prepared for transfer by forming a mesa region by etching the epitaxial material to a depth at or below the sacrificial region. As shown in Figure 4C, the epitaxial structure comprises a GaN buffer layer grown on top of a foreign substrate, comprising, for example, a material other than GaN, such as SiC, Si, sapphire, or another material. The benefits of transferring the devices from the foreign substrate to a carrier wafer include improved thermal properties when the carrier wafer is made from materials such as diamond or silicon carbide, integration of GaN electronic components into circuits including CMOS circuits, forming GaN based ICs, etc.

[0194] In some embodiments, an optional nucleation or buffer layer may be formed on the foreign substrate. For example, materials having lattice structures compatible with the GaN buffer layer, and in some embodiments, compatible with the foreign substrate, may be used so that the lattice structure of the buffer layer is sufficiently free of defects. These and other layers may be used in electronic devices that are formed and transferred to carrier wafers in accordance with embodiments described herein.

[0195] The subsequent processing steps determine the final device structure of the HEMT device. Simplified example HEMT device structures that could be fabricated from the epitaxial structure in Figure 4B or 4C according to this invention are shown in Figures 4D- 4F. In both device structures the process includes forming an isolation structure for the active device area by etching a mesa or by ion implantation, or in an embodiment, the transferred epitaxial mesa would provide the isolation for the active device area. In the embodiment shown in Figure 4D, the source and drain contacts are made to the surface of the exposed AlGaN region. In the embodiment according to Figure 4E, the source and drain contacts are made after etching either into the AlGaN layer or through the AlGaN to directly contact the insulating layer. In one embodiment, the source and drain contacts would be comprised of Ti/Al/Ni/Au, but could be others such as Al/Ni/Au, a Ta-based ohmic contact, or others. The source and drain contact metallization is often followed by an annealing step to improve the contact characteristics. Next, the gate metal is defined. In one embodiment the gate is formed by a lift-off process of a metal such as Ni/Au, but could be others such as Pt, Pd, or Au. The deposition method can be electron beam deposition, sputtering, thermal evaporation, or other techniques. Dielectric passivation layers such as silicon nitride are formed on the device to electrically isolate certain features, protect certain regions, and to eliminate dispersion between the large signal AC and the DC characteristics of the HEMT.

[0196] In an embodiment of this invention a gate insulator is implemented by placing an insulating material such as a dielectric or oxide between the semiconductor material and the gate electrode. In this metal-insulator-semiconductor high-electron-mobility transistor (MIS- HEMT) device several insulator materials can be used including SiO2, SiNx, A12O3, AIN, HfO2, ZrO2, La2O3, and Ta2O5. A gate insulator is not needed for RF devices but may be required for power devices to suppress the gate leakage current and current collapse. An example of a MIS-HEMT device according to one embodiment of this invention is shown in Figure 4F.

[0197] Figures 4G and 4H illustrate a method by which the device, a HEMT device, is formed and processed while attached to the gallium and nitrogen containing or foreign wafer, comprising, for example, Silicon, Sapphire, or Silicon Carbide. [0198] Figure 4G is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 4G(a), the device is partially formed on the substrate. In addition, as illustrated in figure 4G(b), the device is further processed by etching the AlGaN layer and forming source, drain, and gate contacts as illustrated. The source, drain, and gate contacts may be formed using materials and processes such as those discussed herein or otherwise known to those of skill in the art.

[0199] Figure 4H is a simplified schematic cross-section of the device of figures 4G after transfer to a carrier wafer according to an example of the present invention. The device is attached to drain, gate, and source electrodes comprising, for example, a metal, such as aluminum or titanium, where the drain, gate, and source electrodes have been previously formed on the carrier wafer.

[0200] In another HEMT device embodiment according to the present invention, the epitaxial device stack includes a GaN, AlGaN, or INGaN cap layer between the sacrificial region and the AlGaN region, as shown in Figure 41. The epitaxial structure also comprises a GaN buffer layer grown on top of a gallium and nitrogen containing or foreign substrate, comprising, for example, GaN. The GaN, AlGaN, or INGaN cap layer is formed with materials and process such as those discussed herein or otherwise known to those of skill in the art.

[0201] In another HEMT device embodiment according to the present invention the epitaxial device stack includes a GaN, AlGaN, or INGaN cap layer between the sacrificial region and the AlGaN region. The GaN, AlGaN, or INGaN cap layer is formed with materials and process such as those discussed herein or otherwise known to those of skill in the art. As shown in the example of Figure 4J, the epitaxial structure comprises a GaN buffer layer grown on top of a foreign substrate, comprising, for example, a material other than GaN, such as SiC, Si, sapphire, or another material. The benefits of transferring the HEMT devices to a carrier wafer include improved thermal properties when the carrier wafer is made from materials such as diamond or silicon carbide, integration of GaN electronic components into circuits including CMOS circuits, forming GaN based ICs, etc.

[0202] In some embodiments, a nucleation or buffer layer is formed on the foreign substrate. For example, materials having lattice structures compatible with the GaN buffer layer, and in some embodiments compatible with the foreign substrate, may be used so that the lattice structure of the buffer layer is sufficiently free of defects. [0203] The GaN buffer layer could be comprised of GaN or n-type GaN. Overlying the GaN buffer layer is a sacrificial region as described in this invention. Overlying the sacrificial region are the HEMT device layers comprising a cap layer, a higher bandgap material such as AlGaN electron supply region overlying the sacrificial region and an intrinsic region or nominally UID or NID insulating gallium and nitrogen containing material such as GaN overlying the higher bandgap region. In one embodiment the cap layer is a GaN cap layer comprised of UID or NID GaN to create an insulating region. In an alternative embodiment the cap layer is a GaN cap layer comprised of an n-type GaN to create a conductive region. In an alternative embodiment the cap layer is an AlGaN cap layer, which can be a p-type or n- type AlGaN. In an alternative embodiment the cap layer is an InGaN cap layer, which can be a p-type or n-type InGaN. The AlGaN electron supply region may be comprised of an AlGaN layer doped with silicon at a concentration of between 5E17 cm-3 and 1E20 cm-3 with a thickness ranging from about 5 nm to about 100 nm. In some embodiments no doping is used or a modulation doping is implemented. The AlGaN supply region may be comprised of multiple layers including an undoped AlGaN spacer layer ranging in thickness from 1 nm to about 15 nm, an n-type doped AlGaN layer with a thickness ranging from 5 nm to 100 nm, and an undoped AlGaN barrier layer with a thickness ranging 5 nm to 100 nm. The AlGaN supply region may be comprised of a substantially uniform AlGaN composition or a graded or non-uniform AlGaN composition. In some embodiments the AlGaN composition will range from 5% to 15% AIN, or about 15% to about 30% AIN, or about 30% to about 50% AIN. The insulating layer is comprised of GaN and may be an NID, UID, or an intentionally doped region to compensate the unwanted background dopants and increase the resistance and create the insulating property. The insulating region would comprise a thickness ranging from about 0.5 um to about 5 um or about 5 um to 10 um with a typical carrier concentrations of less than about 1E17 cm-3, less than about 5E16 cm-3, or less than about 1E16 cm-3, or less than about 5E15 cm-3.

[0204] In one embodiment according to this invention, the epitaxial device material, such as that shown in Figure 4J, is prepared for transfer by forming a mesa region by etching the epitaxial material to a depth at or below the sacrificial region. The etching process can be a dry etching process such as a RIE, ICP etch, CAIBE, or other. Typical gases used in the etching process may include Cl and/or BC13. Alternatively, the mesa could be defined through a wet etch process. The wet etch process may be selective and designed to terminate on the sacrificial region. A bonding region is formed overlying the mesa region. The bonding region may be comprised of a metal, a dielectric, an oxide, or from a semiconductor layer overlying the GaN insulating layer. In some embodiments it is desirable to use an insulating bonding region to isolate the device and minimize parasitic capacitance of the final device. In this embodiment the carrier wafer is prepared for the transfer process. The carrier wafer could be selected from silicon, silicon carbide, sapphire, aluminum nitride, or others. In a preferred embodiment the carrier wafer would be insulating or semi-insulating and would be selected from sapphire, silicon carbide, or aluminum nitride. In preparation for the transfer process, bonding regions may be formed on the carrier wafer. The bonding region could be comprised of metal, dielectric, oxide, semiconductor, glass, polymer, or other, or a combination thereof. In one embodiment, the bonding region would be similar to the bonding region on the top of the mesa structures such that the bond interface would be comprised of a like-like material, such as oxide-oxide, semiconductor-semiconductor, or metal-metal. In an alternative embodiment the bonding region is comprised of two dissimilar materials such as semiconductor-glass, oxide-glass, semiconductor-polymer, or other.

[0205] Subsequent processing steps determine the final device structure of the HEMT device. Simplified example HEMT device structures that could be fabricated from the epitaxial structure in Figures 41 or 4J according to this invention are shown in Figure 4K, Figure 4L, Figure 4M, Figure 4N, and Figure 4Q. In all device structures the process may include forming an isolation structure for the active device area by etching a mesa or by ion implantation, or in an embodiment the transferred epitaxial mesa may provide the isolation for the active device area. In the embodiment shown in Figure 4K the cap layer is an n-type GaN cap layer. In this embodiment the source and drain contacts are made to the surface of the exposed n-type GaN cap layer overlying the AlGaN region to form good ohmic contacts, while the gate contact is made to the AlGaN region. In the embodiment according to Figure 4L, the cap layer is an n-type GaN cap layer. In this embodiment the source and drain contacts are made after etching through the n-GaN cap layer to contact the AlGaN region, while the gate contact is made to the n-type GaN cap layer. In yet another embodiment according to Figure 4M, the cap layer is a UID or NID GaN cap layer. In this embodiment the source and drain contacts are made to a UID or NID GaN cap layer and an insulator material is placed between gate and the GaN cap layer. In one embodiment, the source and drain contacts would be comprised of Ti/Al/Ni/Au, but could be others such as Al/Ni/Au, a Tabased ohmic contact, or others. The source and drain contact metallization is often followed by an annealing step to improve the contact characteristics. Next, the gate metal is defined. In one embodiment the gate is formed by a lift-off process of a metal such as Ni/Au, but could be others such as Pt, Pd, or Au. The deposition method can be electron beam deposition, sputtering, thermal evaporation, or other techniques. Dielectric passivation layers such as silicon nitride are formed on the device to electrically isolate certain features, protect certain regions, and to eliminate dispersion between the large signal AC and the DC characteristics of the HEMT.

[0206] In a conventional HEMT, the device is normally ON, but applying a bias to the gate electrode depletes electrons in the channel below to prohibit current flow and turn the device OFF. Normally OFF devices are desirable for several applications. For example, a normally- off device operation is required to simplify the inverter circuit for electric or hybrid electric vehicles. Normally-off operation in GaN HEMT can be achieved by several methods, although they face limitations and tradeoffs. The most widely used method is by gate recess etching.

[0207] This can be performed by ICP plasma to remove the Al GaN layer on top of the GaN channel layer. The reduction of AlGaN thickness results in a lower polarization-induced 2DEG density. A recessed gate HEMT device according to one embodiment of this invention is show in Figure 4N as an example. In this embodiment the cap layer is a GaN cap layer. In this embodiment the source and drain contacts are made to the GaN cap layer. An etch is performed to etch into the AlGaN region in the gate region. A passivation layer or insulating layer is applied in the etched region and the gate electrode is formed.

[0208] Another HEMT device enabling normally OFF operation is the gate injection transistor (GIT) device. In this device a p-type GaN, InGaN, or AlGaN layer is placed between the gate electrode and the AlGaN supply region. In the example of p-type AlGaN, the GIT structure is normally-off because a p-AlGaN layer raises the potential at the AlGaN/GaN interface channel above the Fermi level. This could also be understood as a natural depletion of mobile electrons on the n-side due to the built-in p-n junction. By applying a positive gate bias, the channel begins to accumulate 2DEG as the quantum well reaches the Fermi level, thereby turning the device on.

[0209] Figures 40 and 4P illustrate a method by which the device, a HEMT device, is formed and processed while attached to the gallium and nitrogen containing or foreign wafer, comprising, for example, Silicon, Sapphire, or Silicon Carbide. [0210] Figure 40 is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 40(a), the device is partially formed on the substrate. In addition, as illustrated in figure 40(b), the device is further processed to etch the cap layer and the AlGaN layer to form a trench. The device is further processed to form source and drain contacts, and to form a gate dielectric and a gate contact, as illustrated. The source and drain contacts, the dielectric layer, and the gate contact may be formed using a process such as those discussed herein or otherwise known to those of skill in the art.

[0211] Figure 4P is a simplified schematic cross-section of the device of figures 40 attached to a carrier wafer according to an example of the present invention. The device is attached to drain, gate, and source electrodes comprising, for example, a metal, such as aluminum or titanium, where the drain, gate, and source electrodes have been previously formed on the carrier wafer. The drain, gate, and source electrodes may be formed using materials and processes such as those discussed herein or otherwise known to those of skill in the art.

[0212] A GIT device according to one embodiment of the present invention is show in Figure 4Q as an example. In this embodiment the cap layer is a p-type AlGaN cap layer. In this embodiment the source and drain contacts are made to the AlGaN supply layer after etching through the p-type AlGaN cap layer. The gate contact is made to the p-type AlGaN cap region between the source and the drain.

[0213] In alternative embodiment according to this invention, HEMT epitaxial device layers would be grown on the gallium and nitrogen containing or foreign substrate in a reverse order compared to Figure 4B and Figure 4J. That is, overlying the sacrificial region, first the lower bandgap intrinsic region or nominally UID or NID insulating gallium and nitrogen containing material such as GaN is formed. Overlying the insulating region, the higher bandgap region such as AlGaN is formed. An example of this embodiment according to the present invention is shown in Figure 4R. Of course, this is just one example, and the structure could include additional features such as a cap layer overlying the AlGaN region. The cap layer could be comprised of UID, n-type, or p-type GaN, AlGaN, or InGaN. The HEMT power devices would then be fabricated on the gallium and nitrogen containing substrate such as GaN or on the foreign substrate. In the process, source, drain, and gate electrodes would be applied, and sufficient insulating and passivating layers would be configured on the devices according to the descriptions provided in earlier examples. Mesas would be formed using an etching process to expose the sacrificial region. The etching process can be a dry etching process such as RIE, ICP etch, a CAIBE, or other. Typical gases used in the etching process may include Cl and/or BC13. Alternatively, the mesa could be defined through a wet etch process. The wet etch process may be selective and designed to terminate on the sacrificial region. Following the mesa formation process the sacrificial region would be fully or partially removed using a selective etch process such as PEC etching. In an embodiment, anchor regions would be formed to mechanically support the HEMT device mesas and hold them in place with sacrificial region removed prior to the bonding step. The anchor regions could be formed from a semiconductor material, a metal material, an oxide, or a dielectric. Bonding regions would be formed configured to bond the HEMT devices to a carrier wafer. In an embodiment the bonding regions would be metal regions overlying the source, drain, and gate electrodes, but can be others.

[0214] In one embodiment according to this invention, the epitaxial device material, such as that shown in Figure 4S, is prepared for transfer by forming a mesa region by etching the epitaxial material to a depth at or below the sacrificial region. As shown in Figure 4S, the epitaxial structure comprises a GaN buffer layer grown on top of a foreign substrate, comprising, for example, a material other than GaN, such as SiC, Si, sapphire, or another material. The benefits of transferring the HEMT devices to a carrier wafer include improved thermal properties when the carrier wafer is made from materials such as diamond or silicon carbide, integration of GaN electronic components into circuits including CMOS circuits, forming GaN based ICs, etc.

[0215] In some embodiments, a nucleation or buffer layer is formed on the foreign substrate. For example, materials having lattice structures compatible with the GaN buffer layer and, in some embodiments, compatible with the foreign substrate, may be used so that the lattice structure of the buffer layer is sufficiently free of defects.

[0216] Figure 4T shows an example of an array of HEMT devices prepared for transfer to a carrier wafer according to this invention. As illustrated in figure 4T, the substrate may comprise GaN or may be a foreign substrate, comprising, for example, a material other than GaN, such as SiC, Si, sapphire, or another material. In some embodiments, a nucleation or buffer layer is formed on the foreign substrate. For example, materials having lattice structures compatible with the GaN buffer layer and, in some embodiments, compatible with the foreign substrate, may be used so that the lattice structure of the buffer layer is sufficiently free of defects.

[0217] In addition to preparing the HEMT devices for the transfer step with the fabrication of the device structures including forming the source, gate, and drain regions along with applying the necessary passivation layers, formation of the mesa structures, anchor structures, and bonding regions, along with selectively etching the sacrificial region, the carrier wafer is prepared for the transfer process. The carrier wafer could be selected from silicon, silicon carbide, sapphire, aluminum nitride, or others. In one embodiment the carrier wafer would be insulating or semi-insulating and would be selected from sapphire, silicon carbide, or aluminum nitride. In another embodiment the carrier wafer would be configured from silicon and comprise electronic devices formed from a complementary metal-oxide-semiconductor (CMOS) process. In another embodiment the power devices would be transferred directly to a printed circuit board. In preparation for the transfer process, bonding regions may be formed on the carrier wafer. In a preferred embodiment, the bonding regions would be comprised of metal and be configured to bond to the source, gate, and drain metal bond regions. The metal regions on the carrier may be comprised of a material such as gold, platinum, titanium, palladium, copper, aluminum, or a combination thereof. The metal material can be deposited by conventional methods such as electron beam deposition, sputtering, thermal evaporation, or others such as electroplating.

[0218] The bonding may be selected from a thermocompression bonding, a diffusion bonding, or other. Once bonded and the substrate released, the remainder of the device processing would be performed to the epitaxial device material on the carrier wafer. In one configuration, bond pad regions to access the source, gate, and drain would be formed substantially on the carrier wafer. In another configuration, electrical interconnects would be used to connect the GaN power devices to other devices on the carrier wafer such as CMOS devices integrated within the carrier or other devices transferred to the carrier wafer according to this invention. Figure 4U shows an example of selective bonding wherein the bond interface regions from the GaN wafers comprising the HEMT devices are bonded to the bond region on a carrier wafer or a printed circuit board. As illustrated in figure 4U, the carrier wafer may comprise GaN or may be a foreign substrate, comprising, for example, a material other than GaN, such as SiC, Si, sapphire, or another material. In some embodiments, a nucleation or buffer layer is formed on the foreign substrate. For example, materials having lattice structures compatible with the GaN buffer layer and, in some embodiments, compatible with the foreign substrate, may be used so that the lattice structure of the buffer layer is sufficiently free of defects. By selective bonding, one or more HEMT devices can be transferred to multiple carrier wafers or printed circuit boards. An advantage to this device structure is the lack of conduction layers below the insulating GaN region.

[0219] As in any of the gallium and nitrogen containing semiconductor devices according to this invention, the die expansion process can be applied to electronic devices such as Schottky diode devices, p-n diode devices, HEMT devices, FET devices, heterojunction bipolar transistor, or any other transistor devices. As an example, a cross-sectional schematic process flow illustrating the semiconductor epitaxial device layers of a Schottky diode device in preparation for die expansion is shown in Figure 5A. As described in this invention, after deposition of the device layers over the sacrificial region, mesa regions are defined at a first pitch. Before or after the mesa regions are defined, the ohmic contact is formed to the n-type contact layer and a bonding region is formed overlying the mesa. The sacrificial region is then selectively etched using a selective etching process such as PEC etching. The etch can be a full etch wherein the entirety of the sacrificial region is removed or wherein the sacrificial region is partially removed such that a portion remains unetched. The unetched sacrificial region could function as an anchor region, providing mechanical support to the epitaxial layers to hold them in place prior to the bonding steps. As previously described, other materials can be used for anchor features such as metal regions, dielectric regions, oxide regions, or other. As illustrated in figure 5A, the substrate may comprise GaN or may be a foreign substrate, comprising, for example, a material other than GaN, such as SiC, Si, sapphire, or another material. In some embodiments, a nucleation or buffer layer is formed on the foreign substrate. For example, materials having lattice structures compatible with the GaN buffer layer and, in some embodiments, compatible with the foreign substrate, may be used so that the lattice structure of the buffer layer is sufficiently free of defects.

[0220] Figure 5B is an example illustration of the selective bonding process to a carrier wafer wherein the mesa on the substrate comprised of the Schottky diode device layers are transferred to the carrier wafer in a sequential fashion according to a second pitch that is greater than the pitch that the mesa was formed at on the substrate. After bonding to the carrier wafer, the remaining steps are performed for the fabrication of the Schottky diode device. As illustrated, the substrate may comprise GaN or may be a foreign substrate, comprising, for example, a material other than GaN, such as SiC, Si, sapphire, or another material. In some embodiments, a nucleation or buffer layer is formed on the foreign substrate. For example, materials having lattice structures compatible with the GaN buffer layer and, in some embodiments, compatible with the foreign substrate, may be used so that the lattice structure of the buffer layer is sufficiently free of defects.

[0221] The value of such die expansion applied to electronic devices could be enormous through the greatly increased utilization of the epi area. The origin of this large value creation is that typical GaN based power devices have a very small “active” area relative to the total chip area required for the device. This is due to the fact that the electrodes or bond pads that are used to connect the “active” device area to external or on-chip power sources often require factors of 5 or more area than the active devices themselves require. As an example, a top-view schematic of an example conventional Schottky diode device is shown in Figure 5C. According to Figure 5C, the device is comprised by a total area depicted by 100. Within the total area 100 of the device, the active area 101 is depicted with the dashed line. As shown, the active area wherein Schottky diode function is generated where the Schottky contact electrode 102 and the ohmic contact electrode 103 actually connects to the active area 101 is much smaller than the area 100 configured to provide sufficient area for the full Schottky contact electrode 102 and the ohmic contact electrode 103.

[0222] A cross section of the conventional Schottky diode device shown in Figure 5C is shown in Figure 5D. According to Figure 5D, epitaxial layers are formed on the substrate 200, which may be selected from silicon, silicon carbide, sapphire, or other. The epitaxial layers are configured with a nucleation layer 201 overlying the substrate 200, an n-contact layer and/or conduction region 202 overlying the nucleation region 201, and an intrinsic, UID, or NID drift region 203 overlying the n-contact layer region 202. In this example, a mesa region is formed to define the active area. In some embodiments the mesa is formed using an etching process wherein the etch destructively removes the epitaxial semiconductor material and terminates at or near the substrate. On top of the active area mesa the Schottky diode contact is made with a Schottky diode contact electrode 204 to the drift region 203 in the active area. In this embodiment, the Schottky contact electrode is primarily positioned overlying the substrate wherein the semiconductor was destructively etched. In typical configurations, insulating layers such as dielectrics or oxides would be positioned between the mesa and the electrode and/or between the substrate and the electrode. On the side of the active area wherein the semiconductor layers have been exposed to leave a portion of the n- contact layer region 202 exposed, the ohmic n-contact and n-contact electrode 205 is formed. In this conventional embodiment, the ohmic n-contact electrode is primarily positioned overlying the n-contact and lateral conduction regions and/or overlying the substrate wherein the semiconductor was etched to the substrate. In typical configurations, insulating layers such as dielectrics or oxides would be positioned between the mesa and the electrode and/or between the substrate and the electrode.

[0223] A cross section of a Schottky diode device according to this invention is shown in Figure 5E. According to Figure 5E, the Schottky diode device layer mesa has been transferred from a native gallium and nitrogen containing or foreign substrate to a carrier wafer 300. In this embodiment, the transferred mesa region substantially defines the active area of the device. Overlying the carrier wafer 300 is the bond region 301, overlying the bond region 301 is the intrinsic, or UID, or NID drift region 302, and overlying the drift region 302 is the n-contact layer region 303. In this embodiment the bond region 301 is formed from a highly conductive metal configured with the designed thickness and conductivity to enable a high current operation with minimal resistance and hence, enable a vertical Schottky diode device. According to the present invention, the Schottky contact electrode is overlying the metallic bond region to form an electrical contact. In some embodiments a thick electrode metal is formed over the metallic bond region to enable probing or wirebonding. In another embodiment, the bond region metal on the carrier wafer is the electrode region. Overlying the n-contact layer region 303 is the ohmic n-contact electrode 305, which extends off the mesa and onto the carrier wafer. In typical configurations, insulating layers such as dielectrics or oxides would be positioned between the mesa and the electrode and/or between the carrier wafer and the electrode. An aspect of this invention embodiment is the transferred epitaxial material that was initially formed on a bulk GaN substrate is only occupying the “active” area where it is needed and a vast majority of the electrode metal is contained on the carrier wafer. This is a drastic improvement in the use of epitaxy material and epitaxial substrate area since in conventional methods the electrodes occupy regions wherein the epitaxial material is present or was present prior to using a destructive removal process such as etching. In the present invention for forming a Schottky diode device, very little of the gallium and nitrogen containing epitaxial material is wasted.

[0224] In an alternative example of die expansion for semiconductor power electronic devices, a top-view schematic of an example conventional HEMT device is shown in Figure 5F. According to Figure 5F, the device is comprised by a total area depicted by 400. Within the total area 400 of the device, the active area 401 is depicted with the dashed line. As shown, the HEMT function is generated where the source electrode 402, gate electrode 403, and drain electrode 404 actually connect to the active area 401 is much smaller than the area 400 configured to provide sufficient area for the full area of the source contact electrode 402, gate contact electrode 403, drain contact electrode 404.

[0225] A cross section of the conventional HEMT diode device shown in Figure 5F is shown in Figure 5G. According to Figure 5G, epitaxial layers are formed on the substrate 500, which may be selected from silicon, silicon carbide, sapphire, or other. The epitaxial layers are configured with a nucleation layer 501 overlying the substrate 500, a low bandgap region 502 such as GaN that is typically, UID, or NID overlying the nucleation layer 501, and a high bandgap region 503 such as AlGaN overlying the low bandgap region 502. In this example, a mesa region is formed to define the active area. In some embodiments the mesa is formed using an etching process wherein the etch destructively removes the epitaxial semiconductor material and terminates at or near the substrate. On top of the active area mesa the source contact is made with a source contact electrode 504, a gate contact is made with a gate contact electrode 505, and drain contact is made with the drain contact electrode 506. In this embodiment, the source, gate, and drain contact electrodes are primarily positioned overlying the substrate wherein the semiconductor was destructively etched. In typical configurations, insulating layers such as dielectrics or oxides would be positioned between the mesa and the electrode and/or between the substrate and the electrode.

[0226] A cross section of a HEMT device according to this invention is shown in Figure 5H. According to Figure 5H, the HEMT diode device layer mesa has been transferred from a native gallium and nitrogen containing or foreign substrate to a carrier wafer 600. In this embodiment, the transferred mesa region substantially defines the active area of the device. Overlying the carrier wafer 600 within the active area is the bond region 601, the lower bandgap material such as GaN region 602 overlying the bond region 601, and the higher bandgap region 603 overlying the lower bandgap region 602. In this embodiment the bond region 601 may be formed from an insulating region such as an oxide material. In alternative embodiments it may be formed by a metal. On top of the active area mesa the source contact is made with a source contact electrode 604, a gate contact is made with a gate contact electrode 605, and drain contact is made with the drain contact electrode 606. In this embodiment, the source, gate, and drain contact electrodes are primarily positioned overlying the carrier wafer. In typical configurations, insulating layers such as dielectrics or oxides would be positioned between the mesa and the electrode and/or between the substrate and the electrode. An aspect of this invention embodiment is the transferred epitaxial material that was initially formed on a bulk GaN substrate is only primarily occupying the “active” area where it is needed to generate the HEMT function and a vast majority of the electrode metal that is required for making electrical connections is contained on the carrier wafer. This is a drastic improvement in the use of epitaxy material and epitaxial substrate area since in conventional methods the electrodes occupy regions wherein the epitaxial material is present or was present prior to using a destructive removal process such as etching. In the present invention for forming a HEMT device, very little of the gallium and nitrogen containing epitaxial material is wasted.

[0227] One feature of the present invention is the ability to fabricate devices with increased functionality by transferring various semiconductor components to a common carrier wafer to form an integrated semiconductor device. There are many applications where it would be advantageous to have various semiconductor components on a common carrier wafer to form an integrated device. One example is the integration of various electronic power devices. For example, GaN power devices such as MOSFETs, HEMTs, and MOS-Channel HEMTs (MOSCHEMTs) have shown outstanding performance. Thus, integration of GaN power devices such as HEMTs can reduce the cost, size, and efficiency of solid state systems. Another emerging application is in LI-FI, which is a bidirectional, high speed and fully networked wireless communications, like WI-FI, using visible light. Since LI-FI requires driver circuitry to modulate the light output of the LED devices, merging electronic devices onto the same chip as the LED would be advantageous.

[0228] Figure 6A is an example of a MOSFET device integrated with a HEMT device and Schottky diode device. The integrated devices in Figure 6A are merely an example of integration using the present invention. According to some embodiments of this invention, any configuration and any number of semiconductor devices can be integrated onto a common substrate. In some embodiments, the common substrate comprises a carrier wafer, an IC wafer, a CMOS circuit, or another substrate, and in some embodiments, the common substrate comprises semiconductor devices such as silicon devices. In the embodiment shown in Figure 6A, a HEMT device is fabricated on a substrate, which could be on a native GaN substrate or a foreign substrate. The HEMT device is comprised of a sacrificial region underlying the HEMT device layers. Mesas are formed using an etching process and the sacrificial region is selectively etched. In an embodiment, anchor structures or regions are formed to maintain the structural integrity of the HEMT device layers to hold them in place. Following the formation of the bond region overlying the mesa region, the HEMT structure is transferred to a carrier wafer. Similar process steps are employed to transfer the previously formed or partially formed Schottky device layers and the previously formed or partially formed MOSFET device layers to the common substrate. The HEMT, Schottky diode and MOSFET device layers may then be further processed into their respective devices. A simplified schematic of the resulting structure is shown in Figure 6A. In other embodiments, one or more of the electronic devices may be formed and transferred in a top-down configuration rather than the bottom-down configuration shown in this example.

[0229] In another embodiment of integrating a MOSFET device with a HEMT device, the HEMT device is processed on the gallium and nitrogen substrate such as GaN or on another substrate. The gate, source, and drain regions are formed along with all of the passive regions. The HEMT device is then transferred to the common substrate such that the gate, source, and drain regions form metal bonds to the common substrate. In one embodiment, the MOSFET epitaxial layers are transferred to the common substrate and then the MOSFET device is formed using process steps understood by those of skill in the art and/or discussed herein. In some embodiments, processing steps are performed on the MOSFET epitaxial layers on the gallium and nitrogen containing substrate or other carrier wafer.

[0230] In an embodiment, another device is integrated with a HEMT device, such as that shown in figure 6B. The HEMT device may be processed on the gallium and nitrogen substrate such as GaN or on another substrate. The gate, source, and drain regions are formed along with the passive regions. The HEMT device is then transferred to the common substrate such that the gate, source, and drain regions form metal bonds to the common substrate. In one embodiment, epitaxial layers of the other device are transferred to the common substrate and then the other device is formed using process steps understood by those of skill in the art and/or discussed herein. In some embodiments, processing steps are performed on the epitaxial layers of the other device on the gallium and nitrogen containing substrate or on another substrate. In some embodiments, the other device comprises one or more GaAs based electronic devices such as GaAs based transistors, SiC based electronic devices, Si based electronic devices, GaN based devices, or any other kinds of electronic devices.

[0231] In yet another embodiment of semiconductor device integration according to this invention, a gallium and nitrogen semiconductor device or epitaxial layer structure is transferred to a common substrate comprising semiconductor devices. An example of this embodiment is transferring an electronic device to a silicon wafer with CMOS circuitry configured as the driver for the electronic device. In another example of this embodiment, one or more GaN based HEMT devices (and/or other GaN devices) are bonded to a silicon substrate comprising silicon MOSFET devices (not shown). In some embodiments, different types of HEMT devices are bonded to the silicon substrate. For example, by cascading a high-voltage, normally-on GaN device and a low-voltage silicon MOSFET device, a normally OFF high-power device can be formed. This approach can provide a simple and low-cost method to deliver a normally-off GaN device. A simplified schematic of the device is shown in Figure 6C. For example, in some embodiments, the one or more GaN based HEMT devices (and/or other GaN devices) are grown on GaN, silicon, sapphire, or silicon carbide and then lifted off and transferred to a select common substrate. The electronic devices may be vertical devices or lateral devices and may be oriented with drain, source, gate upward or downward contacting electrodes on the carrier wafer, or a combination of orientations. In one embodiment, a D-mode GaN HEMT is integrated with a low-voltage e- mode Si MOSFET.

[0232] In yet another embodiment of semiconductor device integration according to this invention, a gallium and nitrogen semiconductor device or epitaxial layer structure is transferred to a common high thermal conductivity substrate comprising, for example, at least one of diamond, silicon carbide, and another semiconductor material. This approach can enable superior heat extraction over that which the devices could achieve on their native growth substrates and/or can enable higher performance switching and device operation. For example, GaN HEMTs could be grown on silicon or sapphire and then lifted off and transferred to a select carrier wafer. A possible additional benefit is that if the GaN HEMTs are lifted off of silicon and transferred to a select carrier of a different material, higher HEMT breakdown voltages may be achieved due to removal of the silicon substrate. In some embodiments, different types of HEMT devices are bonded to the select carrier. The electronic devices may be vertical devices or lateral devices and may be oriented with drain, source, gate upward or downward contacting electrodes on the carrier wafer, or a combination of orientations. A simplified schematic of the device is shown in Figure 6D.

[0233] Devices with n-type channels with negatively charged carriers (electrons) provide normally-off characteristics. This allows lower power consumption and fail-safe features. Devices with p-channels may enable complementary IC designs that reduce power loss in logic control systems.

[0234] P-type gates in AlGaN/GaN heterostructure field-effect transistors (HFETs) provide normally-off operation and low channel resistance by injecting holes from the gate.

[0235] In yet another embodiment of semiconductor device integration according to this invention, a gallium and nitrogen semiconductor device or epitaxial layer structure is transferred to a common substrate. For example, diverse types of electronic devices can be integrated together to form different circuit architectures or functions. This diversity includes lateral devices, vertical devices, GaN devices, GaAs devices, Si devices, other types of devices, normally-on devices, normally-off devices, trench devices, p-type devices, n-type devices. A simplified schematic of this type of device is shown in Figure 6E, which illustrates integration of a p-type transistor and an n-type transistor on the same substrate. Another simplified schematic of this type of device is shown in Figure 6F, which illustrates integration of a normally-on CAVET device with a normally-off trench MOSFET device on the same substrate. As illustrated in these examples, any combination of different electronic devices may be transferred to the same carrier wafer in accordance with the embodiments described herein.

[0236] Figures 6G and 6H illustrate a method by which the device, a GaAs electronic device, or an electronic device of another material, is formed and processed while attached to another substrate, comprising, for example, gallium and nitrogen, Silicon, Sapphire, or Silicon Carbide, where the carrier wafer has a normally-off trench MOSFET (or any other electronic device) connected thereto.

[0237] Figure 6G is a simplified schematic cross-section of a structure of a device according to an example of the present invention. As illustrated in figure 6G(a), the device is partially formed on a GaAs or other material substrate. In addition, as illustrated in the example of figure 6G(b), the device is a HEMT device, and is further processed to etch the n+ GaAs and n+ AlGaAs layers. The device is also further processed to form source, gate, and drain contacts on the GaAs substrate as illustrated. The source, gate, and drain contacts may be formed using materials and processes such as those discussed herein or otherwise known to those of skill in the art. In other embodiments, the device includes one or more bipolar junction transistors (BJTs), MOSFETs, enhancement-mode MOSFETs, heterojunction bipolar transistors (HBTs), metal-semiconductor FETs (MESFETs), high electron mobility transistors (HEMTs), pHEMTs, laterally diffused MOS (LDMOS), JFETs, Schottky diodes, p-n diodes, and/or other types of devices.

[0238] Figure 6H is a simplified schematic cross-section of the device of Figure 6G attached to a carrier wafer according to an example of the present invention, where the carrier wafer has a normally-off trench MOSFET device thereon. In this embodiment, the carrier wafer may be an IC wafer, a CMOS circuit, or another wafer, such as any of the wafers or carrier wafers or substrates discussed herein or otherwise known to those of skill in the art. The device is attached to drain, gate, and source electrodes comprising, for example, a metal, such as aluminum or titanium, where the drain, gate, and source electrodes have been previously formed on the carrier wafer.

[0239] Figure 7A is an example of an integrated circuit formed with transferred GaN devices according to some embodiments. In the illustrated example, GaN power transistors are integrated with a semiconductor on insulator (SOI) CMOS driver chip onto an inexpensive package substrate (Si, glass, ceramic, etc.). These embodiments enable a very small, very thin integrated voltage regulator, such as a buck converter, or the like. These embodiments leverage the transfer process, for example, to simultaneously mechanically bond and generate electrical interconnects. The interconnection distance between transistors and gate driver is very short, which significantly reduces parasitic and switching loss, and reduces electrical and thermal resistance to support high current density. The interconnects and passives (inductors, capacitors, etc.) may be fabricated on the package substrate such that they do not take up real estate on the more expensive III-V substrate.

[0240] Embodiments of the present invention can use various schemes for electrical interconnect between the transferred device and the carrier or host wafer. In one embodiment, electrical interconnect can be formed only on the topside of the transferred device. To form an electrical interconnect between the topside of the transferred device and the carrier wafer, complimentary bonding metal pads are formed on both surfaces using typical metals such as: Au, Cu, In, Al, etc. In addition, metal oxides such as indium tin oxide can also be bonded together using thermocompression bonding. As described previously, this transfer processes may leverage thermocompression bonding between the metallization of the donor wafer device and the metallization of the carrier wafer. As a result, the bond forms an electrical interconnect between the donor wafer metallization and carrier wafer metallization. This bonding scheme can easily be integrated into back-end CMOS processes. For example, electrical vias can be terminated at the final overglass (passivation) layer of a CMOS carrier wafer. The complimentary bonding pads can be deposited on top of the electrical vias to form contact between the transferred device and CMOS circuitry. This embodiment eliminates the need to form electrical interconnects post transfer which minimizes process complexity and cost.

[0241] In another embodiment, a transferred device can have both topside and backside contacts. After the device is transferred to the carrier wafer forming a topside contact, an additional contact can be generated on the backside of the donor wafer device. This process typically involves depositing and patterning a backside metal contact with the appropriate metallization on the transferred devices. After the contact metallization process, a passivation layer is deposited on the transferred devices and carrier wafer for electrical isolation. Various dielectric films can be used such as oxides, nitrides, or organic dielectrics such as polyimide, BCB, parylene, etc. After passivation, openings are generated in the passivation layer and electrical contacts can be formed between the transferred devices and carrier wafer using various interconnect schemes. In one embodiment, a standard redistribution layer (RDL) interconnect can be used because the transferred device thickness is very thin. In another embodiment, wirebonds can be used to connect the device backside contact to the carrier wafer contacts.

[0242] In another embodiment, electrical interconnects can be formed only on the backside of the transferred device. This can be accomplished by integrating an electrically insulating layer between the bonding metal and the device or the bonding metal and the carrier wafer. This allows the device to be transferred, but the bond is primarily used for mechanical purposes due to the electrical isolation layer. At this point, a backside electrical interconnect can be formed as described previously.

[0243] In another embodiment, a multi-layer interconnect approach can be used to enable three-dimensional, monolithic integration of stacked devices. For example, a first layer of devices can be transferred to the carrier substate with various interconnect designs such as those described previously. A dielectric layer can be used to isolate and generate a new planar surface on top of the transferred devices. This can be accomplished by depositing traditional dielectric thin films (oxides, nitrides, etc.) followed by subsequent chemical mechanical polishing to planarize the thin film. Organic based dielectrics can also be used which are designed to self-level and also generate planar surfaces. After the devices are encapsulated and the dielectric layer planarized, vias can be etched and filled with metal interconnects to electrically connect the devices. Bonding pads can be defined on top of the vias to generate pads for the next level of transferred devices. At this stage, this approach can be repeated multiple times to build 3D, monolithic device structures with several layers of transferred devices. This device stacking approach can reduce interconnect distances between devices and enable 3D heterogeneous integration of different device technologies.

[0244] This transfer technology can be used to attach devices on the top and bottom surfaces of the carrier wafer. In one embodiment, the carrier wafer can consist of an interposer substrate. The interposer has through substrate vias that electrically connect both top and bottom surfaces to support 2.5D packaging approaches. Devices can be transferred and electrically interconnected on the top surface of the interposer and can be connected to devices that are transferred to the bottom by through substrate vias. The interposer substrate can be fabricated on various substrates including silicon, glass, glass/ceramic, ceramics, etc.

[0245] Figure 7B illustrates an example of an integrated circuit formed with transferred GaN devices according to some embodiments. The illustrated examples include one IC having electrodes electrically connecting the transferred devices to the substrate which are only on the sides of the transferred devices facing the substrate. The illustrated examples also include one IC having electrodes electrically connecting the transferred devices to the substrate which are both on the sides of the transferred devices facing the substrate and on the sides of the transferred devices not facing the substrate or opposite the substrate.

[0246] Figure 7C illustrates examples of an integrated circuit formed with transferred devices according to some embodiments. In the illustrated example, a package substrate comprising, for example, Si, glass, a ceramic, or another material is populated with die from each of an n-type GaN HEMT wafer, a p-type GaN HEMT wafer, and an SOI CMOS wafer. Because the package substrate has interconnects and passive components, such as inductors, capacitors, and resistors previously formed thereon, no or little processing is required after the die are transferred from the various wafers.

[0247] Figure 7D illustrates an example of an integrated circuit formed with transferred devices according to some embodiments. In the illustrated example, a device wafer having die formed thereon and attached thereto with anchors, for example, is pressed into an intermediate substrate which has a pressure sensitive adhesive tape or other coating applied to a surface that adheres to each individual die. The adhesion force is strong enough to break the anchors attaching the die to the device wafer when the device wafer and intermediate carrier wafer are pulled apart. This process results in a mass transfer of the die to the intermediate substrate. A pedestal style chuck may be used to selectively align and pick up die from the intermediate substrate. The pedestal chuck may be controlled and maneuvered around existing topography and/or previously placed die. The chuck may be designed to pick up many die at one time allowing massive parallel die transfer to a destination substrate. This process can be repeated multiple times with different device types, for example, from different device wafers so that multiple device types are placed on a single destination substrate.

[0248] Figure 7E illustrates an example of an integrated circuit formed with transferred GaN devices according to some embodiments. In the illustrated example, the IC substrate has transferred GaN devices having top-side contacts. Accordingly, electrodes electrically connect the transferred devices to the substrate on sides of the transferred devices not facing the substrate or opposite the substrate. In the illustrated example, the devices on the donor wafer are passivated and channels are formed in the passivation to allow etching of the sacrificial release layer. In addition, the devices may be mass transferred from the donor wafer to an intermediate carrier wafer that has an adhesion layer strong enough to break device anchors. Bonding pads are deposited and patterned on the devices. Additional processing can also be done at this step. The devices are bonded and transferred to a package substrate, interposer, IC wafer, or the like. In some embodiments, at least some of the bonds form a back side electrode. In some embodiments, one or more of the bonds form mechanical connections and do not make electrical connections.

[0249] Some embodiments bond the topside of a device to a carrier wafer. This results in a “flipped” device architecture that can be preferential in some applications. However, there can be other applications that require the orientation of device architecture to be preserved during the transfer process. Figure 7E describes a process flow that enables the device orientation to be preserved during the transfer process. The initial part of this transfer process uses the same release process as described earlier. The devices are processed on the donor wafer and optionally passivated. The passivation layer may be used as for protection during the sacrificial release layer etch and may form anchors to the substrate to secure the devices on the donor wafer after the sacrificial release layer is removed. The sacrificial release layer is etched and the devices are mass transferred from the donor wafer to an intermediate carrier wafer that has a temporary adhesion layer to secure the devices for further processing. This results in the topside of the device bonded down to the intermediate carrier wafer and the backside of the devices are exposed. Further processing can be performed on the backside of the devices before the next transfer process. A metal bonding layer is patterned and deposited on the exposed backside. This metal layer can be used as a backside electrode, or it can be used as a bonding layer only. The devices may be thermocompression bonded to an alternate substrate which has complimentary metal pads. This substrate can be a package substrate, interposer substrate, integrated circuit (IC) wafer, or other substrates depending on application. The devices are now bonded to an alternate substrate with the initial device orientation preserved. Additional passivation steps and topside electrode formation steps may be used to form a topside contact. Additional processing besides electrodes can also be performed on the topside of the device. In addition, further processing can be performed on the substrate to create passives (inductor, resistors, capacitors, interconnects, bond pads, etc). Additional transfer processes can be performed to attach other devices to the substrate.

[0250] Figure 7F illustrates an example of an integrated circuit formed with GaN devices transferred to a CMOS substrate according to some embodiments. In the illustrated example, III-V device die are mass transferred to the CMOS substrate. In addition, the device die are repeatedly placed across the CMOS substrate forming bonds which are both electrical and mechanical. Densely spaced die on the III-V wafer can be “re-pitched” (expanded) onto the CMOS substrate for highly efficient use of the III-V wafer. Multiple device types from different source wafers can be transferred enabling heterogenous integration of III-V devices with CMOS technologies. The transfer process generates robust metallic bonds that are compatible with CMOS BEOL (Back end of line) interconnect formation processing.

[0251] Figure 7G illustrates an example of an integrated circuit formed with transferred GaN devices according to some embodiments. In the illustrated example, the GaN devices are directly bonded to CMOS driver circuitry previously formed on a semiconductor wafer comprising, for example, silicon. For example, GaN HEMTs may be integrated with CMOS drivers for power conversion circuits, such as buck converters and the like. As a result, GaN HEMT devices are used for superior switching speed and improved efficiency, and the transfer process enables direct bonding of the GaN HEMTs to the CMOS driver circuitry to greatly minimize interconnect parasitics for faster and more power efficient operation. These embodiments also eliminate substrate related HEMT leakage paths because the HEMT devices do not share a common semiconductor substrate. In addition, these embodiments result in a smaller footprint because the HEMT devices are transferred directly on top of the CMOS circuitry. As illustrated, the GaN HEMT devices are transferred to the CMOS wafer, which has previously formed interconnect structures thereon in a CMOS BEOL process, and the contacts of the GaN HEMT devices electrically and mechanically connect to the previously formed interconnect.

[0252] Figure 7H illustrates an example of an integrated circuit formed with GaN devices transferred to a highly thermal conductive substrate according to some embodiments. In the illustrated example, the GaN devices are bonded to a diamond substrate. In alternative embodiments, the GaN devices are bonded to a substrate of another highly thermal conductive material, such as SiC, AIN, Al ON, or another material. The illustrated transfer process is “device first” which enables full or partial processing of the GaN devices on another substrate prior to transfer. In some embodiments, the GaN device processing is completely decoupled from the device to substrate attachment process. Accordingly, there is no need to grow a diamond substrate onto a GaN on Si or SiC device wafer. Therefore, the design and processing options are increased, and single crystal diamond substrates with high or ultra-high thermal conductivity may be used.

[0253] Figure 71 illustrates benefits of an integrated circuit formed with GaN devices transferred to a highly thermal conductive substrate according to some embodiments. In the illustrated example, the GaN devices are bonded to a diamond substrate. In alternative embodiments, the GaN devices are bonded to a substrate of another highly thermal conductive material, such as SiC, AIN, Al ON, or another material. The benefits include improved thermal performance of, for example, power and/or RF devices. Because the GaN power transistors are bonded to a high thermal conductivity diamond substrate, junction temperatures of the GaN devices are reduced, and output power is improved and/or device sizes may be reduced. The transfer process may use metallic bonding for low thermal resistance of the bonds. The metallic bonds also form an electrical interconnect, so no additional processing is necessary to electrically attach the chips post transfer. In addition, the die are inverted, reducing thermal path from device heat generation sources to the diamond substrate.

[0254] In some embodiments, an optional nucleation or buffer layer may be formed on the foreign substrate. For example, materials having lattice structures compatible with a GaN buffer layer, and in some embodiments, compatible with a foreign substrate, may be used so that the lattice structure of the buffer layer is sufficiently free of defects. These and other layers may be used in electronic devices that are formed and transferred to carrier wafers in accordance with embodiments described herein.

[0255] Transfer of electronic devices or materials and their subsequent heterogeneous integration is an attractive strategy to realize high performance and low-cost circuits for a wide variety of new applications. Additionally, new device configurations can be achieved that could not otherwise be realized. To enable transfer, the device may be designed with an integrated sacrificial release layer that can be selectively etched while minimizing impact to the device structure and anchor system previously described. There are many different device technologies and materials systems that can benefit from this integration approach leveraging electronic device transfer.

[0256] In some embodiments, gallium and nitrogen containing devices grown on silicon substrates can be transferred to alternate substrates for performance improvements. In this example, the release layer may be a (111) Si substrate used to grow the epitaxial gallium and nitrogen containing buffer and devices layers. Anisotropic silicon etchants such as KOH and TMAH can be used to laterally etch the (110) planes. The (110) planes etch faster than the (111) plane so the etchant laterally undercuts the gallium and nitrogen containing device releasing it from the silicon substrate. For this instance, the anchor structures may be fabricated from a material such as silicon nitride so that they are not etched during the release process and can withstand the subsequent bonding process (e.g., thermocompression bonding).

[0257] In other embodiments, CMOS or MEM’s devices grown on silicon-on-insulator wafers (SOI) wafers can also be transferred to alternate substrates. In an example, the release layer may be the buried oxide layer of the SOI wafer. HF and/or other fluorine containing etch chemistries can be used due to the high selectivity of the oxide and silicon layers. Silicon can be used in some embodiments as an etch resistant anchor material.

[0258] In another embodiment, gallium and arsenic containing devices can integrate various sacrificial release layers in the epitaxially grown layers to enable electronic device transfer. There are multiple release layers that can be used with this material system. For example, Al(Ga)As layers can be etched with HF -based solutions due to the high selectivity between GaAs and AlAs. An alternative release layer for GaAs is A10.5In0.5P, which can be etched using hydrochloric acid (HC1) with high selectivity to GaAs. There are also applications that leverage Ge as a release layer integrated into the GaAs-based epitaxially design. The device can be released by using gas phase lateral etching of the Ge layer with XeF2.

[0259] In other embodiments, InP-based devices can be transferred by integrating InGaAs and InAlAs sacrificial release layers into the epitaxial layer stack. These layers are readily etched with a low temperature FeC13 etchant that has a high selectivity to InP.

[0260] Integrated circuits using transferred electronic devices in accordance with embodiments described herein include power management integrated circuits that integrate, for example, GaN power transistors with CMOS gate drivers for high performance buck power stage for high efficiency power conversion, RF front end integrated circuits that integrate, for example, GaN power amplifiers with RF SOI switches and InP low noise amplifiers for higher performance RF front end for 5G+ applications, and power electronics integrated circuits that integrate, for example, GaN HEMT’s and IGBT’s for high efficiency invertors for electric vehicles.

[0261] As used herein, the terms GaN substrate and gallium containing substrate are associated with Group Ill-nitride based materials including GaN, InGaN, AlGaN, or other Group III containing alloys or compositions that are used as starting materials. Such starting materials include polar GaN substrates (i.e., substrate where the largest area surface is nominally an (h k 1) plane wherein h=k=0, and 1 is non-zero), non-polar GaN substrates (i.e., substrate material where the largest area surface is oriented at an angle ranging from about 80-100 degrees from the polar orientation described above towards an (h k 1) plane wherein 1=0, and at least one of h and k is non-zero) or semi-polar GaN substrates (i.e., substrate material where the largest area surface is oriented at an angle ranging from about +0.1 to 80 degrees or 110-179.9 degrees from the polar orientation described above towards an (h k 1) plane wherein 1=0, and at least one of h and k is non-zero).

[0262] The methods, structures, and configurations discussed above are examples. Various configurations may omit, substitute, or add various procedures or features as appropriate. For instance, in alternative configurations, the methods may be performed in an order different from that described, and/or various features may be added, omitted, and/or combined. Also, features described with respect to certain configurations may be combined in various other configurations. Different aspects and elements of the configurations may be combined in a similar manner. Also, technology evolves and thus many of the elements are examples and do not limit the scope of the disclosure or claims. [0263] While certain features of the embodiments of the disclosure have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the embodiments of the disclosure. Unless stated otherwise, terms such as “first" and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

WHAT IS CLAIMED IS:

1. A partially completed semiconductor device, comprising: a plurality of electronic devices arranged in an array overlying a surface region of a donor substrate, adjacent ones of the plurality of electronic devices in the array separated by a first pitch, each of the plurality of electronic devices comprising a sacrificial region overlying the surface region of the donor substrate and gallium containing device layers of epitaxial material overlying the sacrificial region, the epitaxial material comprises at least an intrinsic-type or unintentionally doped gallium containing region or at least an n-type gallium containing region or at least a p-type gallium containing region or at least a combination of one or more of the intrinsic-type or unintentionally doped gallium containing region, the n- type gallium containing region, or the p-type gallium containing region; bonding regions overlying a first portion of the plurality of electronic devices, each of the bonding regions comprising a metal contact configured to provide electrical coupling with at least one of the gallium containing device layers, wherein a surface region of a second portion of the bonding regions contact and are bonded to a surface region of contact regions on a carrier substrate to form bonded electronic devices, the contact regions on the carrier substrate configured to provide electrical coupling to corresponding electronic devices; and anchors extending between each of the plurality of electronic devices and the donor substrate; wherein the bonded electronic devices on the donor substrate are configured to be releasable by selectively removing at least part of the sacrificial regions to transfer the second portion of the plurality of electronic devices to the carrier substrate, wherein the anchors are configured to mechanically support the plurality of electronic devices after removal of at least part of the sacrificial regions, and wherein adjacent pairs of the bonded electronic devices are configured with a second pitch on the carrier substrate that is equal to or greater than the first pitch.

2. The partially completed semiconductor device of claim 1 wherein the gallium containing device layers comprise gallium and nitrogen or gallium and arsenic.

3. The partially completed semiconductor device of claim 1 wherein the electronic devices comprise at least one of Schottky diode devices, p-n diode devices, bipolar junction transistor (BJT) devices, field-effect transistor (FET) devices, metal-oxide- semiconductor field-effect transistor (MOSFET) devices, junction field effect transistor (JFET) devices, enhancement mode junction field effect transistor (eJFET) devices, metalsemiconductor FET (MESFET) devices, high-electron-mobility transistor (HEMT) devices, insulated gate bipolar transistor (IGBT) devices, or heterojunction bipolar transistor (HBT) devices, metal-insulator semiconductor barrier Schottky rectifier devices, static induction transistor (SIT) devices, current apertured vertical electron transistor (CAVET) devices, and wherein the electronic devices comprise at least one of trench type devices, normally-on type devices, normally-off type devices, p-type devices, n-type devices, or combinations thereof.

4. The partially completed semiconductor device of claim 1 wherein the carrier substrate is selected from silicon substrate, a sapphire substrate, an aluminum nitride substrate, a silicon nitride substrate, a silicon carbide substrate, a glass substrate, a group V semiconductor substrate, a III-V semiconductor substrate, a II- VI semiconductor substrate, a glass substrate, a glass ceramic substrate, a quartz substrate, a high purity fused silica substrate, a silicon carbide substrate, an aluminum nitride substrate, a germanium substrate, an aluminum oxynitride substrate, a gallium arsenide substrate, a diamond substrate, a synthetic diamond substrate, a gallium nitride substrate, an indium phosphide substrate, a flexible member, a circuit board member, a CMOS substrate, a silicon substrate with CMOS circuitry, a silicon on insulator (SOI) substrate, or a gallium nitride on silicon substrate.

5. The partially completed semiconductor device of claim 1 wherein the donor substrate is selected from a gallium nitride substrate, a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium oxide substrate, a spinel substrate, a lanthanum aluminate substrate, a magnesium oxide substrate, or a template type substrate.

6. The partially completed semiconductor device of claim 1 wherein the sacrificial regions include GaN, InGaN, AlInGaN, AlGaN, AlGaAs, AllnP, InGaAs, InAlAs, Ge, silicon, or silicon oxide.

7. The partially completed semiconductor device of claim 1 wherein the plurality of electronic devices include one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a current spreading region, a drift region, an insulation region, an edge termination region, an emitter region, a base region, a collector region, a gate region, a source region, a drain region, an isolation region, or a passivation region either alone or in any combination.

8. A donor substrate, comprising: a plurality of electronic devices arranged in an array overlaying a surface region of the donor substrate, adjacent ones of the plurality of electronic devices in the array separated by a first pitch that is less than a design width, each of the plurality of electronic devices including: gallium containing device layers of epitaxial material, the epitaxial material comprising at least an intrinsic-type or unintentionally doped gallium containing region or at least an n-type gallium containing region or at least a p-type gallium containing region or at least a combination of one or more of the intrinsic- type or unintentionally doped gallium containing region, the n-type gallium containing region, or the p-type gallium containing region; a sacrificial region configured to be selectively removed to allow transfer of at least a portion of the plurality of electronic devices to one or more carrier substrates; anchors extending between each of the plurality of electronic devices and the donor substrate, the anchors configured to mechanically support the plurality of electronic devices after removal of at least part of the sacrificial regions; and one or more metal contact regions overlying the gallium containing device layers so that the gallium containing device layers are between the sacrificial region and the one or more metal contact regions, the one or more metal contact regions configured to provide an electrical coupling with at least one of the gallium containing device layers, a surface region of at least one of the one or more metal contact regions configured to contact and bond to a surface region of metal contact regions on the one or more carrier substrates.

9. The donor substrate of claim 8 wherein the sacrificial region is disposed between the gallium containing device layers and the surface region of the donor substrate.

10. The donor substrate of claim 8 wherein the gallium containing device layers comprise gallium and nitrogen or gallium and arsenic.

11. The donor substrate of claim 8 wherein the electronic devices comprise at least one of Schottky diode devices, p-n diode devices, bipolar junction transistor (BJT) devices, field-effect transistor (FET) devices, metal-oxide-semiconductor field-effect transistor (MOSFET) devices, junction field effect transistor (JFET) devices, enhancement mode junction field effect transistor (eJFET) devices, metal-semiconductor FET (MESFET) devices, high-electron-mobility transistor (HEMT) devices, insulated gate bipolar transistor (IGBT) devices, or heterojunction bipolar transistor (HBT) devices, metal-insulator semiconductor barrier Schottky rectifier devices, static induction transistor (SIT) devices, current apertured vertical electron transistor (CAVET) devices, and wherein the electronic devices comprise at least one of trench type devices, normally-on type devices, normally-off type devices, p-type devices, n-type devices, or combinations thereof.

12. The donor substrate of claim 8 wherein the donor substrate is selected from a gallium nitride substrate, a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium oxide substrate, a spinel substrate, a lanthanum aluminate substrate, a magnesium oxide substrate, or a template type substrate.

13. The donor substrate of claim 8 wherein the sacrificial region includes GaN, InGaN, AlInGaN, AlGaN, AlGaAs, AllnP, InGaAs, InAlAs, Ge, silicon, or silicon oxide.

14. The donor substrate of claim 8 wherein the plurality of electronic devices include one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a current spreading region, a drift region, an insulation region, an edge termination region, an emitter region, a base region, a collector region, a gate region, a source region, a drain region, an isolation region, or a passivation region either alone or in any combination.

15. A carrier substrate configured with circuitry for distributing electronic signals or current, comprising: a plurality of electronic devices arranged in an array overlaying a surface region of the carrier substrate, wherein each of a first portion of the plurality of electronic devices include: gallium containing device layers of epitaxial material, the epitaxial material comprising at least an intrinsic-type or unintentionally doped gallium containing region or at least an n-type gallium containing region or at least a p-type gallium containing region or at least a combination of one or more of the intrinsic- type or unintentionally doped gallium containing region, the n-type gallium containing region, or the p-type gallium containing region; and one or more contact regions overlying the surface region of the carrier substrate, a surface region of the one or more contact regions contacting and bonded to a surface region of one or more metal contact regions of each electronic device, the one or more metal contact regions configured to provide an electrical coupling with at least one of the gallium containing device layers; and wherein each of a second portion of the plurality of electronic devices are different types of electronic devices than the first portion of the plurality of electronic devices.

16. The carrier substrate of claim 15 wherein the second portion of the plurality of electronic devices include at least one of other gallium nitride based electronic devices, silicon based electronic devices, or gallium arsenic based electronic devices.

17. The carrier substrate of claim 15 wherein the gallium containing device layers comprise gallium and nitrogen or gallium and arsenic.

18. The carrier substrate of claim 15 wherein the electronic devices comprise at least one of Schottky diode devices, p-n diode devices, bipolar junction transistor (BJT) devices, field-effect transistor (FET) devices, metal-oxide-semiconductor field-effect transistor (MOSFET) devices, junction field effect transistor (JFET) devices, enhancement mode junction field effect transistor (eJFET) devices, metal-semiconductor FET (MESFET) devices, high-electron-mobility transistor (HEMT) devices, insulated gate bipolar transistor (IGBT) devices, or heterojunction bipolar transistor (HBT) devices, metal-insulator semiconductor barrier Schottky rectifier devices, static induction transistor (SIT) devices, current apertured vertical electron transistor (CAVET) devices, and wherein the electronic devices comprise at least one of trench type devices, normally-on type devices, normally-off type devices, p-type devices, n-type devices, or combinations thereof.

19. The carrier substrate of claim 15 wherein the carrier substrate is selected from silicon substrate, a sapphire substrate, an aluminum nitride substrate, a silicon nitride substrate, a silicon carbide substrate, a glass substrate, a group V semiconductor substrate, a III-V semiconductor substrate, a II- VI semiconductor substrate, a glass substrate, a glass ceramic substrate, a quartz substrate, a high purity fused silica substrate, a silicon carbide substrate, an aluminum nitride substrate, a germanium substrate, an aluminum oxynitride substrate, a gallium arsenide substrate, a diamond substrate, a synthetic diamond substrate, a gallium nitride substrate, an indium phosphide substrate, a flexible member, a circuit board member, a CMOS substrate, a silicon substrate with CMOS circuitry, a silicon on insulator (SOI) substrate, or a gallium nitride on silicon substrate.

20. The carrier substrate of claim 15 wherein the plurality of electronic devices include one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a current spreading region, a drift region, an insulation region, an edge termination region, an emitter region, a base region, a collector region, a gate region, a source region, a drain region, an isolation region, or a passivation region either alone or in any combination.