WO2024108893A1 - 一种上下电时序控制电路 - Google Patents

一种上下电时序控制电路 Download PDF

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Publication number
WO2024108893A1
WO2024108893A1 PCT/CN2023/090600 CN2023090600W WO2024108893A1 WO 2024108893 A1 WO2024108893 A1 WO 2024108893A1 CN 2023090600 W CN2023090600 W CN 2023090600W WO 2024108893 A1 WO2024108893 A1 WO 2024108893A1
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Prior art keywords
voltage
power
circuit
resistor
control circuit
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PCT/CN2023/090600
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English (en)
French (fr)
Inventor
许赵哲
张航
刘晓锋
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普罗斯通信技术（苏州）有限公司
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Publication of WO2024108893A1 publication Critical patent/WO2024108893A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the invention relates to the technical field of mobile communications, and in particular to a power-on and power-off timing control circuit capable of controlling the power-on and power-off timing of a power amplifier.
  • gallium nitride (GaN) power amplifiers have emerged. Due to their unique advantages, they are used in more and more communication products.
  • gallium nitride power amplifiers have strict requirements on the timing of gate voltage Vg and drain voltage Vd when powering on and off. When powering on, the gate is required to be powered on first, and then the drain is powered on after stabilization; when powering off, the drain is required to be powered off first, and the gate is powered off when the voltage reaches the safe level.
  • the object of the present invention is to provide a power-on and power-off timing control circuit, which does not require software and a single-chip microcomputer to perform power-on and power-off timing control and has the advantages of simple structure and low cost.
  • an embodiment of the present invention provides a power-on and power-off timing control circuit for controlling the power-on and power-off timing of a power amplifier
  • the power-on and power-off timing control circuit comprises a switch circuit for controlling whether a first voltage converter inputs a voltage to a drain of the power amplifier, a voltage discharge circuit for controlling whether the voltage of the drain of the power amplifier is discharged to the ground according to a control signal output by a second voltage converter, and a timing control circuit for controlling the delayed opening of the switch circuit according to a control signal output by the second voltage converter, wherein the drain of the power amplifier is connected to the voltage output end of the first voltage converter through the switch circuit, and the gate is connected to the voltage output end of the second voltage converter; the voltage discharge circuit is connected between the drain of the power amplifier and the control signal output end of the second voltage converter, and the timing control circuit is connected between the switch circuit and the control signal output end of the second voltage converter.
  • the switching circuit includes a first switching transistor, which is connected between the voltage output terminal of the first voltage converter and the drain of the power amplifier, and the gate of the first switching transistor is connected to the timing control circuit.
  • the voltage discharge circuit includes:
  • a second switch transistor a gate of which is connected to the control signal output terminal of the second voltage converter
  • the load is discharged and connected to the drain of the power amplifier through the second switch transistor while being grounded.
  • the voltage discharge circuit further includes:
  • a first voltage stabilizing circuit wherein the gate of the second switch transistor is connected to a control signal output terminal of a second voltage converter through the first voltage stabilizing circuit.
  • the first voltage stabilizing circuit includes a first voltage stabilizing diode and a current limiting resistor
  • the gate of the second switching transistor is connected to the control signal output end of the second voltage converter through the current limiting resistor
  • the cathode of the first voltage stabilizing diode is connected between the current limiting resistor and the gate of the second switching transistor
  • the anode is grounded.
  • the discharge load includes a resistor, or
  • the timing control circuit includes a first voltage divider circuit, a second voltage divider circuit, a third voltage divider circuit, a second voltage stabilizing circuit, a triode and a third switch transistor, wherein:
  • the base of the triode is connected to the voltage output end of the first voltage converter and the control signal output end of the second voltage converter respectively through the first voltage divider circuit, the first electrode is connected to the voltage output end of the first voltage converter through the second voltage divider circuit to form a first connection point, and the second electrode is grounded;
  • the gate of the third switch transistor is connected to the second voltage divider circuit, the first electrode is connected between the first connection point and the switch circuit to form a second connection point, and the second electrode is grounded through the third voltage divider circuit;
  • An input end of the second voltage stabilizing circuit is connected to the third voltage dividing circuit, and an opposite end is connected between the second connection point and the switch circuit.
  • the first voltage divider circuit includes a third resistor and a fourth resistor connected in series, and a connection point formed by connecting the third resistor and the fourth resistor is connected to the control signal output terminal of the second voltage converter.
  • the second voltage divider circuit includes a first resistor and a second resistor connected in series, and a connection point formed by connecting the first resistor and the second resistor is connected to the gate of the third switch transistor.
  • the third voltage-dividing circuit includes a fifth resistor and a sixth resistor connected in series, and a connection point formed by connecting the fifth resistor and the sixth resistor is connected to a switch circuit.
  • the second voltage stabilizing circuit includes a second voltage stabilizing diode, the cathode of the second voltage stabilizing diode is connected between the second connection point and the switching circuit, and the anode is connected between the connection point formed by the fifth resistor and the sixth resistor and the fifth resistor.
  • the voltage output end of the second voltage converter is connected to the gate of the power amplifier through a filter capacitor and an analog load, one end of the analog load is connected to the voltage output end of the second voltage converter to form a third connection point, and the opposite end is grounded, one end of the filter capacitor is connected between the third connection point and the voltage output end of the second voltage converter, and the opposite end is grounded.
  • the simulated load comprises a resistor, or
  • the power amplifier is a gallium nitride power amplifier.
  • the power-on and power-off timing control circuit according to the embodiment of the present invention is composed of simple circuit components, which can adjust the power-on timing and power-off timing of the power amplifier to meet the timing requirements of power-on and power-off, ensure its stable operation, and do not need to be controlled by a single-chip microcomputer and software to achieve the power-on and power-off timing adjustment of the power amplifier. It has the advantages of simple structure and low cost.
  • FIG1 is a timing diagram of power on and off of a GaN power amplifier
  • FIG2 is a block diagram of a power-on and power-off timing control circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a power-on and power-off timing control circuit according to an embodiment of the present invention.
  • FIG4 is a power-on timing diagram of a gallium nitride power amplifier according to an embodiment of the present invention.
  • FIG. 5 is a power-down timing diagram of a gallium nitride power amplifier according to an embodiment of the present invention.
  • a power-on and power-off timing control circuit can adjust the power-on timing and power-off timing of the power amplifier to meet the timing requirements of power-on and power-off, and ensure its stable operation.
  • the power amplifier here includes but is not limited to a gallium nitride power amplifier. As long as the power-on timing and power-off timing of the power amplifier meet the following requirements, the power-on and power-off timing control circuit described in the present invention can be applied.
  • the power-on timing and power-off timing meet: when powered on, the gate of the power amplifier is powered on before the drain; when powered off, the drain of the power amplifier is powered off before the gate.
  • the power-on and power-off timing of the gallium nitride power amplifier can be seen in FIG1.
  • the -9.5V voltage required by the gate is powered on first, and then a 50V voltage is output to the drain after stabilization; when powered off, the 50V voltage of the drain is powered off first, and the -9.5V voltage of the gate is disconnected when the safety voltage reaches within 10V.
  • the power-on and power-off timing control circuit includes a switch circuit 10, a voltage discharge circuit 20 and a timing control circuit 30.
  • the drain Vd of the gallium nitride power amplifier a is connected to the voltage output end of the first voltage converter b through the switch circuit 10, and the gate Vg is connected to the voltage output end of the second voltage converter c.
  • the first voltage converter is a universal 50v voltage converter
  • the second voltage converter is a universal -9.5v voltage converter.
  • the switch circuit is used to control whether the first voltage converter can input voltage to the drain of the gallium nitride power amplifier.
  • the first voltage converter When it is turned on (that is, the voltage transmission path between the first voltage converter and the drain of the gallium nitride power amplifier is conductive), the first voltage converter can input a corresponding voltage to the drain. When it is turned off (the voltage transmission path between the first voltage converter and the drain of the gallium nitride power amplifier is not conductive), the first voltage converter cannot input a corresponding voltage to the drain. For example, when the switch circuit is turned on, the first voltage converter can input a 50v voltage to the drain, and when it is turned off, the first voltage converter cannot input a corresponding 50v voltage to the drain.
  • the voltage discharge circuit is connected between the drain of the GaN power amplifier and the control signal output terminal of the second voltage converter, and is used to control whether the voltage of the drain of the GaN power amplifier is grounded and discharged according to the control signal output by the second voltage converter.
  • the switch circuit When the switch circuit is turned on at the same time, the voltage of the drain of the GaN power amplifier can be grounded and discharged to accelerate the voltage discharge at the moment when the switch circuit is turned off; when the switch circuit is turned off, it cannot ground the voltage of the drain of the GaN power amplifier and discharge it.
  • the timing control circuit is connected between the switch circuit and the control signal output terminal of the second voltage converter, and is used for controlling the switch circuit to be turned on or off according to the control signal output by the second voltage converter.
  • the second voltage converter when powered on, the second voltage converter inputs a -9V voltage to the gate of the GaN power amplifier through the voltage output terminal.
  • the second voltage converter inputs a control signal to the timing control circuit and the voltage discharge circuit through the control signal output terminal.
  • the timing control circuit controls the switch circuit to delay opening according to the control signal, so that the 50V voltage output by the first voltage converter reaches the drain of the GaN power amplifier at a certain interval, and the voltage discharge circuit is in a closed state according to the control signal, and the voltage of the drain of the GaN power amplifier cannot be discharged to the ground.
  • the gate of the GaN power amplifier is powered on before the drain.
  • the second voltage converter When power is turned off, the second voltage converter inputs a control signal to the timing control circuit and the voltage discharge circuit through the control signal output terminal.
  • the timing control circuit controls the switch circuit to close according to the control signal, and the voltage discharge circuit is turned on according to the control signal.
  • the voltage of the drain of the gallium nitride power amplifier can then be discharged to the ground.
  • the drain of the gallium nitride power amplifier is preferably powered off before the gate.
  • the switch circuit includes a first switch transistor Q1, which has a first electrode, a second electrode and a gate, wherein the first electrode is connected to the first voltage converter, the second electrode is connected to the drain of the gallium nitride power amplifier, and the gate is connected to the timing control circuit.
  • the first switch transistor Q1 is preferably a P-type MOS tube, preferably a P-type MOS tube of model IXTA52P10P, whose source is connected to the first voltage converter, and the drain is connected to the drain of the gallium nitride power amplifier.
  • the voltage discharge circuit includes a second switch transistor Q2 and a discharge load.
  • the second switch transistor Q2 has a first electrode, a second electrode and a gate, wherein the first electrode is connected to the drain Vd of the gallium nitride power amplifier, the second electrode is grounded through the discharge load, and the gate is connected to the control signal output end of the second voltage converter.
  • the second switch transistor Q2 is an N-type MOS tube, preferably an N-type MOS tube of model IRF540NS, wherein the drain is connected to the drain of the gallium nitride power amplifier, and the source is grounded through the discharge load.
  • the discharge load includes one or more resistors.
  • the discharge load includes multiple resistors, the multiple resistors are connected in parallel.
  • the multiple resistors can also be connected in series.
  • the discharge load includes four resistors, namely resistors R8, R9, R10, and R11, and the four resistors are connected in parallel. The number of resistors in the discharge load can be selected according to actual needs to achieve the required resistance value.
  • the voltage discharge circuit also includes a first voltage stabilizing circuit, and the gate of the second switching transistor Q2 is connected to the control signal output end of the second voltage converter through the first voltage stabilizing circuit.
  • the first voltage stabilizing circuit includes a first voltage stabilizing diode Z2 and a current limiting resistor R7, and the gate of the second switching transistor Q2 is connected to the control signal output end of the second voltage converter through the current limiting resistor R7.
  • the cathode of the first voltage stabilizing diode Z2 is connected between the current limiting resistor R7 and the gate of the second switching transistor Q2, and the anode is grounded.
  • the first voltage stabilizing diode Z2 is a 12V voltage stabilizing diode
  • the preferred voltage stabilizing diode is a PDZ12B voltage stabilizing diode.
  • the timing control circuit 30 includes a first voltage divider circuit 31, a second voltage divider circuit 32, a third voltage divider circuit 33, a second voltage stabilizing circuit 34, a transistor Q5 and a third switch transistor Q9.
  • the transistor Q5 has a base,
  • the first electrode and the second electrode, the transistor Q5 here is an NPN transistor, preferably an NPN transistor of model UMT2222A, the first electrode of which is the collector, and the second electrode is the emitter.
  • the third switch transistor Q9 has a gate, a first electrode, and a second electrode, the third switch transistor Q9 here is a P-type MOS transistor, preferably a P-type MOS transistor of model NDS352AP, the first electrode of which is the source, and the second electrode is the drain.
  • the base of the transistor Q5 is respectively connected to the voltage output end of the first voltage converter b and the control signal output end of the second voltage converter c through the first voltage divider circuit 31, the first electrode is connected to the voltage output end of the first voltage converter b through the second voltage divider circuit 32 to form a first connection point A, and the second electrode is grounded; the gate of the third switching transistor Q9 is connected to the second voltage divider circuit 32, the first electrode is connected between the first connection point A and the switch circuit 10 to form a second connection point B, and the second electrode is grounded through the third voltage divider circuit 33; the input end of the second voltage stabilizing circuit is connected to the third voltage divider circuit, and the opposite end is connected between the second connection point B and the switch circuit 10.
  • the first voltage divider circuit 31 includes a third resistor R3 and a fourth resistor R4, the third resistor R3 and the fourth resistor R4 are connected in series, and the base of the transistor Q5 is connected to the voltage output end of the first voltage converter through the third resistor R3 and the fourth resistor R4 connected in series, and at the same time, the connection point of the third resistor R3 and the fourth resistor R4 is also connected to the control signal output end of the second voltage converter c.
  • the second voltage divider circuit 32 includes a first resistor R1 and a second resistor R2, the first resistor R1 and the second resistor R2 are connected in series, and the first electrode of the transistor Q5 is connected to the voltage output end of the first voltage converter b through the first resistor R1 and the second resistor R2 connected in series to form a first connection point A, and the second electrode is grounded.
  • the connection point between the first resistor R1 and the second resistor R2 is also connected to the gate of the third switching transistor Q9.
  • the third voltage divider circuit 33 includes a fifth resistor R5 and a sixth resistor R6, which are connected in series, and a first electrode of the third switching transistor Q9 is connected between the first connection point A and the first electrode of the second switching transistor Q1 to form a second connection point B, and the second electrode is grounded through the fifth resistor R5 and the sixth resistor R6 connected in series.
  • the connection point formed by the fifth resistor R5 and the sixth resistor R6 is also connected to the gate of the second switching transistor Q1.
  • the second voltage stabilizing circuit 34 includes a second voltage stabilizing diode Z1 , and an anode of the second voltage stabilizing diode Z1 is connected between a connection point formed by connecting the fifth resistor R5 and the sixth resistor R6 and the fifth resistor R5 .
  • the timing control circuit adopts the above circuit structure and can control the switch circuit to open or close according to the control signal output by the second voltage converter.
  • the second voltage regulator diode Z1 is a 12V voltage regulator diode, preferably a voltage regulator diode of model PDZ12B.
  • the voltage output end of the second voltage converter is connected to the gate Vg of the gallium nitride power amplifier through the filter capacitor C3 and the simulated load RL.
  • one end of the simulated load RL is connected to the voltage output end of the second voltage converter to form a third connection point C, and the opposite end is grounded.
  • the simulated load RL can be used to simulate a load current of a certain value, such as simulating a load current of 10mA.
  • the simulated load RL has a resistor, or multiple resistors connected in series, or multiple resistors connected in parallel, which can be selected according to actual needs; one end of the filter capacitor C3 is connected between the third connection point C and the voltage output end of the second voltage converter, and the opposite end is grounded. In this embodiment, the filter capacitor C3 and the simulated load RL share the same ground.
  • the first voltage converter and the second voltage converter When powered on, the first voltage converter and the second voltage converter are powered on normally, and there is no order in which they are powered on.
  • the second voltage converter outputs a -9.5V voltage to the gate of the GaN power amplifier through its voltage output terminal, and the first voltage converter outputs a 50V voltage through its voltage output terminal.
  • the 50V voltage cannot reach the GaN power amplifier, and it is necessary to wait for the timing control circuit to control it to turn on so that the 50V voltage can be output to the drain of the GaN power amplifier.
  • the timing control circuit turns on the first switch transistor Q1 according to the control signal output by the second voltage converter.
  • the control signal is the Ready signal of the second voltage converter, which is an open-drain output and is Ready when low, that is, when the output -9.5V voltage is within the 5% standard voltage range, the Ready signal is pulled low by the conversion power supply, as shown in FIG4 , and a low-level Ready signal is formed in about 1ms.
  • the transistor Q5 When the control signal is low, the transistor Q5 is in the cut-off state, and at this time, the Vgs voltage of the third switch transistor Q9 is 0V, so that the third switch transistor Q9 is in the cut-off state, which in turn causes the 50V voltage of the gate of the first switch transistor Q1 to be turned off, and further through the second voltage regulator diode, the Vgs voltage of the first switch transistor Q1 is 12V, and the first switch transistor Q1 is turned on. After the first switch transistor is turned on, the 50V voltage can be output to the drain of the gallium nitride power amplifier. Through the above process, the purpose of the gate priority power-on of the gallium nitride power amplifier is achieved.
  • the Ready signal When the power is turned off, when the voltage output by the second voltage converter exceeds 5%, that is, when the voltage is turned off from -9.5V to about -9V, the Ready signal returns to the pull-up high level, as shown in Figure 5.
  • the Ready signal is turned off in about 2ms, and then it returns to a high level signal.
  • the high level signal causes the transistor Q5 to turn on. After the transistor Q5 is turned on, the voltage difference of the Vgs of the third switch transistor Q3 exceeds -10V through the voltage division of the first resistor and the second resistor, so that the third switch transistor Q3 is turned on.
  • the gate voltage and the source voltage of the first switch transistor Q1 are the same, which causes the first switch transistor to turn off, so that the 50V voltage cannot be input to the drain of the gallium nitride power amplifier.
  • the Ready signal returns to the pull-up high level, and the second switch transistor Q2 is turned on, that is, the voltage discharge circuit is turned on, so that the voltage of the drain of the gallium nitride power amplifier is grounded and discharged.
  • the power-on and power-off timing control circuit described in the present invention is composed of simple circuit components and can adjust the power-on timing and power-off timing of the power amplifier so that it meets the timing requirements of power-on and power-off and ensures its stable operation. It does not need to control the power-on and power-off timing of the power amplifier through a single-chip microcomputer and software, and has the advantages of simple structure and low cost.

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Abstract

本发明是关于一种上下电时序控制电路，属于移动通信技术领域。其包括开关电路、电压泄放电路和时序控制电路。功率放大器的漏极通过开关电路连接第一电压转换器，栅极连接第二电压转换器；电压泄放电路连接于功率放大器的漏极和第二电压转换器之间，时序控制电路连接于开关电路和第二电压转换器之间。在上电时，时序控制电路控制开关电路延迟开启，而电压泄放电路关闭，以使功率放大器的栅极先于漏极上电；在下电时，时序控制电路控制开关电路关闭，而电压泄放电路开启，以使功率放大器的漏极先于栅极下电。该上下电时序控制电路无需通过单片机和软件来调节功率放大器的上下电时序，具有结构简单、成本低的优点。

Description

一种上下电时序控制电路
本发明要求2022年11月22日向中国专利局提交的、申请号为202223103573.6、发明名称为“一种上下电时序控制电路”的中国专利申请的优先权，该申请的全部内容通过引用结合在本文中。
技术领域
本发明关于移动通信技术领域，特别是关于一种可控制功率放大器上下电时序的上下电时序控制电路。
背景技术
在移动通信领域中，射频功率放大器被广泛应用，其是无线发射机的核心部件，其用于使无线信号具备足够的发射功率向外辐射。随着半导体材料工艺的不断进步，氮化镓(GaN)功率放大器应运而生，因其特有的优势，其被越来越多的通信产品使用。氮化镓功率放大器在实际应用时，其在上电和下电时，对栅极电压Vg和漏极电压Vd的时序有着严格的要求，在上电时要求栅极优先上电，稳定后再对漏极上电；在下电时要求漏极优先下电，达到安全电压以内时，再对栅极下电。然而，目前针对有上述上下电时序要求的功率放大器进行上下电时序控制时，通常采用软件和单片机来实现，此种控制方案具有成本高，控制复杂等缺陷。
公开于该背景技术部分的信息仅仅旨在增加对本发明的总体背景的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域一般技术人员所公知的现有。
发明内容
本发明的目的在于提供一种上下电时序控制电路，无需采用软件和单片机进行上下电时序控制，具有结构简单、成本低的优点。
为实现上述目的，本发明的实施例提供了一种上下电时序控制电路，用于控制功率放大器的上下电时序，所述上下电时序控制电路包括用于控制第一电压转换器是否向功率放大器的漏极输入电压的开关电路、用于根据第二电压转换器输出的控制信号控制功率放大器的漏极的电压是否接地泄放的电压泄放电路，以及用于根据第二电压转换器输出的控制信号控制开关电路延迟开启的时序控制电路，所述功率放大器的漏极通过所述开关电路连接第一电压转换器的电压输出端，栅极连接第二电压转换器的电压输出端；所述电压泄放电路连接于所述功率放大器的漏极和第二电压转换器的控制信号输出端之间，所述时序控制电路连接于所述开关电路和第二电压转换器的控制信号输出端之间。
在本发明的一个或多个实施方式中，所述开关电路包括第一开关晶体管，所述第一开关晶体管连接于所述第一电压转换器的电压输出端和功率放大器的漏极之间，且所述第一开关晶体管的栅极连接所述时序控制电路。
在本发明的一个或多个实施方式中，所述电压泄放电路包括：
第二开关晶体管，其栅极连接第二电压转换器的控制信号输出端；
泄放负载，接地的同时通过所述第二开关晶体管连接功率放大器的漏极。
在本发明的一个或多个实施方式中，所述电压泄放电路还包括：
第一稳压电路，所述第二开关晶体管的栅极通过所述第一稳压电路连接第二电压转换器的控制信号输出端。
在本发明的一个或多个实施方式中，所述第一稳压电路包括第一稳压二极管和限流电阻，第二开关晶体管的栅极通过限流电阻连接第二电压转换器的控制信号输出端，第一稳压二极管的负极连接于限流电阻和第二开关晶体管的栅极之间，正极接地。
在本发明的一个或多个实施方式中，所述泄放负载包括一个电阻，或者
多个串联连接的电阻，或者
多个并联连接的电阻。
在本发明的一个或多个实施方式中，所述时序控制电路包括第一分压电路、第二分压电路、第三分压电路、第二稳压电路、三极管和第三开关晶体管，其中，
所述三极管的基极通过第一分压电路分别连接第一电压转换器的电压输出端和第二电压转换器的控制信号输出端，第一电极通过第二分压电路连接第一电压转换器的电压输出端，形成第一连接点，第二电极接地；
第三开关晶体管的栅极连接所述第二分压电路，第一电极连接于所述第一连接点和开关电路之间，形成第二连接点，第二电极通过第三分压电路接地；
第二稳压电路的输入端连接第三分压电路，相对端连接于所述第二连接点和开关电路之间。
在本发明的一个或多个实施方式中，所述第一分压电路包括串联连接的第三电阻和第四电阻，所述第三电阻和第四电路连接形成的连接点连接所述第二电压转换器的控制信号输出端。
在本发明的一个或多个实施方式中，所述第二分压电路包括串联连接的第一电阻和第二电阻，所述第一电阻和第二电阻连接形成的连接点与第三开关晶体管的栅极连接。
在本发明的一个或多个实施方式中，所述第三分压电路包括串联连接的第五电阻和第六电阻，所述第五电阻和第六电阻连接形成的连接点连接开关电路。
在本发明的一个或多个实施方式中，所述第二稳压电路包括第二稳压二极管，所述第二稳压二极管的负极连接于第二连接点和开关电路之间，正极连接于第五电阻和第六电阻连接形成的连接点与第五电阻之间。
在本发明的一个或多个实施方式中，所述第二电压转换器的电压输出端通过滤波电容和模拟负载连接功率放大器的栅极，所述模拟负载的一端接第二电压转换器的电压输出端，形成第三连接点，相对端接地，滤波电容的一端连接于第三连接点和第二电压转换器的电压输出端之间，相对端接地。
在本发明的一个或多个实施方式中，所述模拟负载包括一个电阻，或者
多个串联连接的电阻，或者
多个并联连接的电阻。
在本发明的一个或多个实施方式中，所述功率放大器为氮化镓功率放大器。
与现有技术相比，根据本发明实施方式的上下电时序控制电路，其由简单的电路元器件组成，能够对功率放大器的上电时序和下电时序进行调节，以使其满足上电和下电时的时序需求，确保其稳定工作，无需通过单片机和软件的控制来实现功率放大器的上下电时序调节，具有结构简单、成本低的优点。
附图说明
图1是氮化镓功率放大器上下电时序图；
图2是根据本发明一实施方式的上下电时序控制电路结构框图；
图3是根据本发明一实施方式的上下电时序控制电路原理图；
图4是根据本发明一实施方式的氮化镓功率放大器上电时序图；
图5是根据本发明一实施方式的氮化镓功率放大器下电时序图。
具体实施方式
下面结合附图，对本发明的具体实施方式进行详细描述，但应当理解本发明的保护范围并不受具体实施方式的限制。
除非另有其它明确表示，否则在整个说明书和权利要求书中，术语“包括”或其变换如“包含”或“包括有”等等将被理解为包括所陈述的元件或组成部分，而并未排除其它元件或其它组成部分。
如图1至图5所示，根据本发明优选实施方式的一种上下电时序控制电路，能够对功率放大器的上电时序和下电时序进行调节，以使其满足上电和下电时的时序需求，确保其稳定工作。这里的功率放大器包括但不限于氮化镓功率放大器，只要功率放大器的上电时序和下电时序满足如下要求即可适用本发明所述的上下电时序控制电路。上电时序和下电时序满足：上电时，功率放大器的栅极优先于漏极上电；下电时，功率放大器的漏极优先于栅极下电。
以下以氮化镓功率放大器为例，对所述上下电时序控制电路进行详细地说明，该氮化镓功率放大器的上下电时序可参见图1所示，上电时，栅极所需的-9.5V电压优先上电，稳定后再向漏极输出50V电压；下电时，漏极的50V电压优先下电，达到安全电压10v以内时再断开栅极的-9.5v电压。
具体地，如图2所示，上下电时序控制电路包括开关电路10、电压泄放电路20和时序控制电路30。其中，氮化镓功率放大器a的漏极Vd通过开关电路10连接第一电压转换器b的电压输出端，栅极Vg连接第二电压转换器c的电压输出端，第一电压转换器为通用型50v电压转换器，第二电压转换器为通用型-9.5v电压转换器。该开关电路用于控制第一电压转换器是否可向氮化镓功率放大器的漏极输入电压，其在开启时(即第一电压转换器与氮化镓功率放大器的漏极的电压传输路径导通)第一电压转换器可向漏极输入相应电压，在关闭时(第一电压转换器与氮化镓功率放大器的漏极的电压传输路径未导通)第一电压转换器无法向漏极输入相应电压，如开关电路在开启时第一电压转换器可向漏极输入50v电压，在关闭时第一电压转换器无法向漏极输入相应50v电压。
电压泄放电路连接于氮化镓功率放大器的漏极和第二电压转换器的控制信号输出端之间，其用于根据第二电压转换器输出的控制信号控制氮化镓功率放大器的漏极的电压是否接地泄放。其在开关电路关闭的同时开启，可将氮化镓功率放大器的漏极的电压接地泄放，以加速开关电路关闭瞬间的电压泄放；其在关闭时，其无法将氮化镓功率放大器的漏极的电压接地泄放。
时序控制电路连接于开关电路和第二电压转换器的控制信号输出端之间，其用于根据第二电压转换器输出的控制信号控制开关电路开启或者关闭。
实施时，在上电时，第二电压转换器通过电压输出端向氮化镓功率放大器的栅极输入-9v电压。与此同时，第二电压转换器通过控制信号输出端向时序控制电路和电压泄放电路输入控制信号，时序控制电路根据该控制信号控制开关电路延迟开启，使第一电压转换器输出的50v电压间隔一定时间到达氮化镓功率放大器的漏极，而电压泄放电路根据该控制信号处于关闭状态，氮化镓功率放大器的漏极的电压无法接地泄放。最终实现了氮化镓功率放大器的栅极优先于漏极上电。
在下电时，第二电压转换器通过控制信号输出端向时序控制电路和电压泄放电路输入控制信号，时序控制电路根据该控制信号控制开关电路关闭，电压泄放电路依据所述控制信号开启，氮化镓功率放大器的漏极的电压进而可接地泄放。最终实现了氮化镓功率放大器的漏极优选于栅极下电。
如图3所示，开关电路包括第一开关晶体管Q1，具有第一电极、第二电极及栅极，其中，第一电极连接第一电压转换器，第二电极连接氮化镓功率放大器的漏极，栅极连接时序控制电路。本实施例中，第一开关晶体管Q1优选P型MOS管，优选型号为IXTA52P10P的P型MOS管，其源极连接第一电压转换器，漏极连接氮化镓功率放大器的漏极。
如图3所示，电压泄放电路包括第二开关晶体管Q2和泄放负载。其中，第二开关晶体管Q2具有第一电极、第二电极及栅极，其第一电极连接氮化镓功率放大器的漏极Vd，第二电极通过泄放负载接地，栅极连接第二电压转换器的控制信号输出端。本实施例中，第二开关晶体管Q2为N型MOS管，优选型号为IRF540NS的N型MOS管，其漏极连接氮化镓功率放大器的漏极，源极通过泄放负载接地。
进一步地，泄放负载包括一个或多个电阻。当泄放负载包括多个电阻时，多个电阻并联连接，当然，多个电阻也可串联连接。如图3所示，泄放负载包括四个电阻，分别为电阻R8、R9、R10、R11，四个电阻并联连接。泄放负载中电阻的数量可根据实际需求进行选择，以达到所需的阻值。
进一步地，电压泄放电路还包括第一稳压电路，第二开关晶体管Q2的栅极通过第一稳压电路连接第二电压转换器的控制信号输出端。本实施例中，第一稳压电路包括第一稳压二极管Z2和限流电阻R7，第二开关晶体管Q2的栅极通过限流电阻R7连接第二电压转换器的控制信号输出端，第一稳压二极管Z2的负极连接于限流电阻R7和第二开关晶体管Q2的栅极之间，正极接地。本实施例中，第一稳压二极管Z2为12V稳压二极管，优选型号为PDZ12B的稳压二极管。
如图3所示，时序控制电路30包括第一分压电路31、第二分压电路32、第三分压电路33、第二稳压电路34、三极管Q5和第三开关晶体管Q9。其中，三极管Q5具有基极、 第一电极和第二电极，这里的三极管Q5为NPN型三极管，优选型号为UMT2222A的NPN型三极管，其第一电极为集电极，第二电极为发射极。第三开关晶体管Q9具有栅极、第一电极和第二电极，这里的第三开关晶体管Q9为P型MOS管，优选型号为NDS352AP的P型MOS管，其第一电极为源极，第二电极为漏极。
进一步地，三极管Q5的基极通过第一分压电路31分别连接第一电压转换器b的电压输出端和第二电压转换器c的控制信号输出端，第一电极通过第二分压电路32连接第一电压转换器b的电压输出端，形成第一连接点A，第二电极接地；第三开关晶体管Q9的栅极连接所述第二分压电路32，第一电极连接于所述第一连接点A和开关电路10之间，形成第二连接点B，第二电极通过第三分压电路33接地；第二稳压电路的输入端连接第三分压电路，相对端连接于所述第二连接点B和开关电路10之间。
如图3所示，具体地，第一分压电路31包括第三电阻R3和第四电阻R4，第三电阻R3和第四电阻R4串联连接，并且三极管Q5的基极通过串联连接后的第三电阻R3和第四电阻R4连接第一电压转换器的电压输出端，同时，第三电阻R3和第四电阻R4的连接点还连接第二电压转换器c的控制信号输出端。
第二分压电路32包括第一电阻R1和第二电阻R2，第一电阻R1和第二电阻R2串联连接，并且三极管Q5的第一电极通过串联连接后的第一电阻R1和第二电阻R2连接第一电压转换器b的电压输出端，形成第一连接点A，第二电极接地，同时，第一电阻R1和第二电阻R2的连接点还连接第三开关晶体管Q9的栅极。
第三分压电路33包括第五电阻R5和第六电阻R6，第五电阻R5和第六电阻R6串联连接，并且第三开关晶体管Q9的第一电极连接于第一连接点A和第二开关晶体管Q1的第一电极之间，形成第二连接点B，第二电极通过串联连接后的第五电阻R5和第六电阻R6接地，同时，第五电阻R5与第六电阻R6连接形成的连接点还连接第二开关晶体管Q1的栅极。
第二稳压电路34包括第二稳压二极管Z1，第二稳压二极管Z1的正极连接于第五电阻R5和第六电阻R6连接形成的连接点与第五电阻R5之间。
时序控制电路采用上述电路结构，可根据第二电压转换器输出的控制信号控制开关电路开启或者关闭。本实施例中，第二稳压二极管Z1为12V稳压二极管，优选型号为PDZ12B的稳压二极管。
如图3所示，本实施例中，第二电压转换器的电压输出端通过滤波电容C3和模拟负载RL连接氮化镓功率放大器的栅极Vg。其中，模拟负载RL的一端接第二电压转换器的电压输出端，形成第三连接点C，相对端接地，模拟负载RL可用于模拟一定数值的负载电流，如模拟10mA的负载电流，模拟负载RL一个电阻，或者多个串联连接的电阻，或者多个并联连接的电阻，可根据实际需求进行选择；滤波电容C3的一端连接于第三连接点C和第二电压转换器的电压输出端之间，相对端接地。在本实施例中，滤波电容C3与模拟负载RL共地。
以下结合图3～5所示，对图3所示的上下电时序控制电路的工作原理进行详细地说明：
在上电时，第一电压转换器和第二电压转换器正常上电，两者上电无先后顺序。其中，第二电压转换器通过其电压输出端输出-9.5V电压至氮化镓功率放大器的栅极，第一电压转换器通过其电压输出端输出50V电压，而由于第一开关晶体管Q1的存在，该50V电压无法到达氮化镓功率放大器，需等待时序控制电路控制其开启，以便于50V电压可输出至氮化镓功率放大器的漏极。
进一步地，时序控制电路依据第二电压转化器输出的控制信号来开启第一开关晶体管Q1。该控制信号为第二电压转换器的Ready信号，其为开漏输出，低电平时为Ready，也即当输出-9.5V电压在5％标准电压范围内时，Ready信号被转换电源拉低，如图4所示，在约1ms左右，形成了低电平的Ready信号。控制信号为低电平时三极管Q5处于截止状态，此时第三开关晶体管Q9的Vgs电压为0V，使得第三开关晶体管Q9处于截止状态，进而导致第一开关晶体管Q1栅极的50V电压随之关断，进一步通过第二稳压二极管，使得第一开关晶体管Q1的Vgs电压为12V，第一开关晶体管Q1导通，第一开关晶体管导通后，该50V电压可输出至氮化镓功率放大器的漏极。通过上述过程，实现了氮化镓功率放大器的栅极优先上电的目的。
在下电时，当第二电压转换器输出的电压下电幅度超过5％时，即-9.5V下电到-9V左右时，Ready信号恢复上拉高电平，如图5所示，约在2ms左右Ready信号关闭，此时恢复为高电平信号。而高电平信号导致三极管Q5导通。三极管Q5导通后，通过第一电阻和第二电阻的分压，使得第三开关晶体管Q3的Vgs电压差超过-10V，因而第三开关晶体管Q3导通。在第三开关晶体管Q3导通后，在第五电阻的作用下，第一开关晶体管Q1的栅极电压和源极电压相同，进而导致第一开关晶体管关断，使得50V电压无法输入至氮化镓功率放大器的漏极。与此同时，Ready信号恢复上拉高电平，第二开关晶体管Q2导通，即电压泄放电路开启，使得氮化镓功率放大器的漏极的电压接地泄放。通过上述过程，实现了氮化镓功率放大器的漏极优先下电的目的。
本发明所述的上下电时序控制电路，其由简单的电路元器件组成，能够对功率放大器的上电时序和下电时序进行调节，以使其满足上电和下电时的时序需求，确保其稳定工作，无需通过单片机和软件的控制来实现功率放大器的上下电时序调节，具有结构简单、成本低的优点。
前述对本实用新型的具体示例性实施方案的描述是为了说明和例证的目的。这些描述并非想将本实用新型限定为所公开的精确形式，并且很显然，根据上述教导，可以进行很多改变和变化。对示例性实施例进行选择和描述的目的在于解释本实用新型的特定原理及其实际应用，从而使得本领域的技术人员能够实现并利用本实用新型的各种不同的示例性实施方案以及各种不同的选择和改变。本实用新型的范围意在由权利要求书及其等同形式所限定。

Claims (14)

  1. 一种上下电时序控制电路，用于控制功率放大器的上下电时序，其特征在于，包括开关电路、电压泄放电路及时序控制电路，其中，
    所述功率放大器的漏极通过所述开关电路连接第一电压转换器的电压输出端，栅极连接第二电压转换器的电压输出端，所述开关电路用于控制第一电压转换器是否向功率放大器的漏极输入电压；
    所述电压泄放电路连接于所述功率放大器的漏极和第二电压转换器的控制信号输出端之间，所述电压泄放电路用于根据第二电压转换器输出的控制信号控制功率放大器的漏极的电压是否接地泄放；
    所述时序控制电路连接于所述开关电路和第二电压转换器的控制信号输出端之间，所述时序控制电路用于根据第二电压转换器输出的控制信号控制开关电路延迟开启。
  2. 如权利要求1所述的上下电时序控制电路，其特征在于，所述开关电路包括第一开关晶体管，所述第一开关晶体管连接于所述第一电压转换器的电压输出端和功率放大器的漏极之间，且所述第一开关晶体管的栅极连接所述时序控制电路。
  3. 如权利要求1所述的上下电时序控制电路，其特征在于，所述电压泄放电路包括：
    第二开关晶体管，其栅极连接第二电压转换器的控制信号输出端；
    泄放负载，接地的同时通过所述第二开关晶体管连接功率放大器的漏极。
  4. 如权利要求3所述的上下电时序控制电路，其特征在于，所述电压泄放电路还包括：
    第一稳压电路，所述第二开关晶体管的栅极通过所述第一稳压电路连接第二电压转换器的控制信号输出端。
  5. 如权利要求4所述的上下电时序控制电路，其特征在于，所述第一稳压电路包括第一稳压二极管和限流电阻，第二开关晶体管的栅极通过限流电阻连接第二电压转换器的控制信号输出端，第一稳压二极管的负极连接于限流电阻和第二开关晶体管的栅极之间，正极接地。
  6. 如权利要求3所述的上下电时序控制电路，其特征在于，所述泄放负载包括一个电阻，或者
    多个串联连接的电阻，或者
    多个并联连接的电阻。
  7. 如权利要求1所述的上下电时序控制电路，其特征在于，所述时序控制电路包括第一分压电路、第二分压电路、第三分压电路、第二稳压电路、三极管和第三开关晶体管，其中，
    所述三极管的基极通过第一分压电路分别连接第一电压转换器的电压输出端和第二电压转换器的控制信号输出端，第一电极通过第二分压电路连接第一电压转换器的电压输出端，形成第一连接点，第二电极接地；
    第三开关晶体管的栅极连接所述第二分压电路，第一电极连接于所述第一连接点和开关电路之间，形成第二连接点，第二电极通过第三分压电路接地；
    第二稳压电路的输入端连接第三分压电路，相对端连接于所述第二连接点和开关电路之间。
  8. 如权利要求7所述的上下电时序控制电路，其特征在于，所述第一分压电路包括串联连接的第三电阻和第四电阻，所述第三电阻和第四电路的连接点连接所述第二电压转换器的控制信号输出端。
  9. 如权利要求7所述的上下电时序控制电路，其特征在于，所述第二分压电路包括串联连接的第一电阻和第二电阻，所述第一电阻和第二电阻连接形成的连接点与第三开关晶体管的栅极连接。
  10. 如权利要求7所述的上下电时序控制电路，其特征在于，所述第三分压电路包括串联连接的第五电阻和第六电阻，所述第五电阻和第六电阻连接形成的连接点连接开关电路。
  11. 如权利要求10所述的上下电时序控制电路，其特征在于，所述第二稳压电路包括第二稳压二极管，所述第二稳压二极管的负极连接于第二连接点和开关电路之间，正极连接于第五电阻和第六电阻连接形成的连接点与第五电阻之间。
  12. 如权利要求1所述的上下电时序控制电路，其特征在于，所述第二电压转换器的电压输出端通过滤波电容和模拟负载连接功率放大器的栅极，所述模拟负载的一端接第二电压转换器的电压输出端，形成第三连接点，相对端接地，滤波电容的一端连接于第三连接点和第二电压转换器的电压输出端之间，相对端接地。
  13. 如权利要求12所述的上下电时序控制电路，其特征在于，所述模拟负载包括一个电阻，或者
    多个串联连接的电阻，或者
    多个并联连接的电阻。
  14. 如权利要求1所述的上下电时序控制电路，其特征在于，所述功率放大器为氮化镓功率放大器。
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