WO2024105872A1 - Power conversion device and flying object - Google Patents

Power conversion device and flying object Download PDF

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Publication number
WO2024105872A1
WO2024105872A1 PCT/JP2022/042815 JP2022042815W WO2024105872A1 WO 2024105872 A1 WO2024105872 A1 WO 2024105872A1 JP 2022042815 W JP2022042815 W JP 2022042815W WO 2024105872 A1 WO2024105872 A1 WO 2024105872A1
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WIPO (PCT)
Prior art keywords
semiconductor switching
inverter
sub
switching element
power conversion
Prior art date
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PCT/JP2022/042815
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French (fr)
Japanese (ja)
Inventor
悠輔 城内
良太 朝倉
賢司 藤原
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三菱電機株式会社
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Priority to PCT/JP2022/042815 priority Critical patent/WO2024105872A1/en
Publication of WO2024105872A1 publication Critical patent/WO2024105872A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/49—Combination of the output voltage waveforms of a plurality of converters

Definitions

  • This application relates to a power conversion device and a flying object equipped with the same.
  • the power conversion device used in the electric aircraft is required to be lightweight and reliable. For example, if the loss of the semiconductor device constituting the power conversion device is uneven, heat is generated locally, and if a failure occurs, reliability is impaired.
  • a cooling fan or heat sink is used to increase the cooling capacity of the part where local heat is generated in order to increase reliability, the weight of the device increases and the fuel efficiency of the aircraft decreases. Therefore, it is required to reduce the weight of the cooling fan or cooling heat sink while ensuring reliability by dispersing the semiconductor loss generated in the power conversion device. In this way, not only the reliability of the power conversion device but also its weight reduction is required for the electric aircraft. And, it can be seen that the challenge in reducing the weight of the cooling fan or cooling heat sink is to equalize the semiconductor loss constituting the power conversion device.
  • the applicant has disclosed a power conversion device that includes a three-phase main inverter and three single-phase sub-inverters connected to each phase of the main inverter, in which the semiconductor switching elements that make up the sub-inverters are PWM-controlled using a level-shifted carrier wave (see, for example, Patent Document 1).
  • the purpose of this application is to reduce the unevenness of losses in each semiconductor switching element that makes up the sub-inverter, to reduce the weight of the cooling fan or heat sink, and to reduce the risk of failure.
  • the power conversion device disclosed in the present application includes a main inverter having a capacitor with a neutral point between a positive terminal to which a positive DC potential is applied and a negative terminal to which a negative DC potential is applied, and capable of outputting at least the potential of the positive terminal, the potential of the negative terminal, and the potential of the neutral point; a sub-inverter connected to the output of the main inverter, having a plurality of semiconductor switching elements and an intermediate capacitor, and adjusting the voltage of the intermediate capacitor to the output voltage of the main inverter; and a control unit that controls the main inverter and the sub-inverter, the control unit controlling the sub-inverter by PWM control and controlling the voltage output by the sub-inverter, the control unit controlling the semiconductor switching elements of the plurality of semiconductor switching elements of the sub-inverter so that the losses of the respective semiconductor switching elements are equal.
  • the present application provides a power conversion device that can reduce the unevenness of losses in the semiconductor switching elements that make up the sub-inverter, reduce the weight of the cooling fan or heat sink, and reduce the risk of failure.
  • FIG. 1 is a schematic block diagram showing a configuration of a power conversion device according to a first embodiment.
  • 1 is a circuit diagram showing a configuration of a power conversion device according to a first embodiment.
  • 2 is a diagram showing a configuration of a semiconductor switching element used in the power conversion device according to the first embodiment;
  • 4A, 4B, and 4C are diagrams showing an example of voltage output command values for each inverter of the power conversion device according to the first embodiment.
  • 4 is a diagram showing gate drive signals for each semiconductor switching element of a main inverter of the power conversion device according to the first embodiment.
  • FIG. 11 is a diagram showing the operation of a sub-inverter of a power conversion device according to a comparative example.
  • FIG. 4 is a diagram showing the operation of a sub-inverter of the power conversion device according to the first embodiment.
  • FIG. 10 is a diagram showing current and voltage waveforms of a sub-inverter of a power conversion device according to a comparative example.
  • FIG. 1 is a diagram showing current and voltage waveforms of the output of a power conversion device according to a comparative example.
  • 3 is a diagram showing current and voltage waveforms of a sub-inverter of the power conversion device according to the first embodiment.
  • FIG. 2 is a diagram showing current and voltage waveforms of the output of the power conversion device according to the first embodiment.
  • 10 is a diagram showing an example of the operation of a sub-inverter of a power conversion device according to a comparative example.
  • FIG. 11 is a diagram showing another example of the operation of the sub-inverter of the power conversion device according to the comparative example.
  • 4 is a diagram showing an example of the operation of a sub-inverter of the power conversion device according to the first embodiment.
  • FIG. 10 is a diagram showing another example of the operation of the sub-inverter of the power conversion device according to embodiment 1.
  • FIG. 13 is a diagram for explaining an example of a switching pattern of a sub-inverter of a power conversion device according to embodiment 2.
  • FIG. FIG. 11 is a diagram showing an example of a switching pattern of a sub-inverter of a power conversion device according to the second embodiment. 13 is a diagram showing a transition of a current path due to the switching pattern of FIG.
  • FIG. FIG. 11 is a diagram showing another example of a switching pattern of the sub-inverter of the power conversion device according to the second embodiment.
  • 15 is a diagram showing a transition of a current path due to the switching pattern of FIG. 14 in the sub-inverter of the power conversion device according to the second embodiment.
  • FIG. FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment.
  • 17 is a diagram showing a transition of a current path due to the switching pattern of FIG. 16 in the sub-inverter of the power conversion device according to the second embodiment.
  • FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment.
  • 19 is a diagram showing a transition of a current path due to the switching pattern of FIG. 18 in the sub-inverter of the power conversion device according to the second embodiment.
  • FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment.
  • 21 is a diagram showing a transition of a current path due to the switching pattern of FIG. 20 in the sub-inverter of the power conversion device according to the second embodiment.
  • FIG. FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment.
  • FIG. 23 is a diagram showing a transition of a current path due to the switching pattern of FIG. 22 in the sub-inverter of the power conversion device according to the second embodiment.
  • FIG. FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment.
  • 25 is a diagram showing a transition of a current path due to the switching pattern of FIG. 24 in the sub-inverter of the power conversion device according to the second embodiment.
  • FIG. FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment.
  • 27 is a diagram showing a transition of a current path due to the switching pattern of FIG.
  • FIG. 13A and 13B are diagrams illustrating examples of switching patterns when a sub-inverter of a power conversion device according to a second embodiment generates a positive voltage and when a sub-inverter generates a negative voltage.
  • 29A, 29B, and 29C are diagrams for explaining current paths when the sub-inverter of the power conversion device according to embodiment 2 generates a positive voltage.
  • 30A, 30B, and 30C are diagrams illustrating current paths when the sub-inverter of the power conversion device according to embodiment 2 generates a negative voltage.
  • FIG. 11 is a block diagram showing the configuration of a flying object according to a third embodiment.
  • Fig. 1 is a schematic configuration diagram showing an example of a power conversion system using a power conversion device 3 according to the first embodiment.
  • the power conversion device 3 is connected in series between a DC source 1 and a load 4, and a DC link capacitor 2 is connected in parallel between the DC source 1 and the power conversion device 3.
  • the power conversion device 3 includes an inverter, which is a power conversion unit that converts power from the DC source 1 into a predetermined power and outputs it to the load 4, and a control unit that controls the inverter.
  • a DC/AC inverter will be described as an example of the inverter.
  • FIG. 2 is a circuit diagram showing an example of the configuration of the power conversion device 3.
  • the DC/AC inverter 30 shown in FIG. 1 is a DC/AC inverter and includes a main inverter 9, which is a three-phase three-level inverter, and a sub-inverter 12, which is a single-phase inverter connected in series to the outputs of each phase of the main inverter 9.
  • the semiconductor switching elements Q1 to Q12 constituting the main inverter 9 have a structure in which, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is connected to a diode in inverse parallel.
  • the semiconductor switching elements Q13 to Q24 constituting the sub-inverter 12 also have a structure in which, for example, a MOSFET is connected to a diode in inverse parallel.
  • the semiconductor switching elements Q1 to Q12 constituting the main inverter 9 and the semiconductor switching elements Q13 to Q24 constituting the sub-inverter 12 are all semiconductor switching elements made of wide band gap semiconductor materials. Details will be described later, but since the semiconductor switching elements Q13 to Q24 constituting the sub-inverter 12 perform high-speed switching, semiconductor switching elements made of wide band gap semiconductor materials are particularly preferable.
  • FIG. 3 shows an example of the configuration of the semiconductor switching elements applied to the semiconductor switching elements Q1 to Q12 constituting the main inverter 9 and the semiconductor switching elements Q13 to Q24 constituting the sub-inverter 12, and is composed of a MOSFET 15 having a drain terminal D, a gate terminal G, and a source terminal S, and a diode 16 connected in reverse parallel to the MOSFET 15.
  • the MOSFET 15 may be a Si-MOSFET or a wide band gap semiconductor material, such as a SiC-MOSFET.
  • the diode 16 may be a Si-diode or a wide band gap semiconductor material, such as a SiC-diode.
  • a semiconductor switching element made of a wide band gap semiconductor material is preferable.
  • a temperature sensor 102 for detecting the temperature of each semiconductor switching element may be provided.
  • the main inverter 9 is configured with a P-side capacitor 5 and an N-side capacitor 6 connected in series between the positive terminal to which the positive potential of the DC source 1 is applied and the negative terminal to which the negative potential of the DC source 1 is applied, semiconductor switching elements Q1 to Q4 connected in series, semiconductor switching elements Q5 to Q8 connected in series, and semiconductor switching elements Q9 to Q12 connected in series, all connected in parallel to the DC link capacitor 2.
  • connection point E (also called the neutral point) between the P-side capacitor 5 and the N-side capacitor 6 is connected to a connection point Eu between the anode terminal of diode D1 and the cathode terminal of diode D2, a connection point Ev between the anode terminal of diode D3 and the cathode terminal of diode D4, and a connection point Ew between the anode terminal of diode D5 and the cathode terminal of diode D6.
  • the cathode terminal of diode D1 is connected to the connection point Ku between semiconductor switching element Q1 and semiconductor switching element Q2, the cathode terminal of diode D3 is connected to the connection point Kv between semiconductor switching element Q5 and semiconductor switching element Q6, and the cathode terminal of diode D5 is connected to the connection point Kw between semiconductor switching element Q9 and semiconductor switching element Q10.
  • the anode terminal of diode D2 is connected to the connection point Au between semiconductor switching element Q3 and semiconductor switching element Q4, the anode terminal of diode D4 is connected to the connection point Av between semiconductor switching element Q7 and semiconductor switching element Q8, and the anode terminal of diode D6 is connected to the connection point Aw between semiconductor switching element Q11 and semiconductor switching element Q12.
  • connection point u between semiconductor switching element Q2 and semiconductor switching element Q3, connection point v between semiconductor switching element Q6 and semiconductor switching element Q7, and connection point w between semiconductor switching element Q10 and semiconductor switching element Q11 are each connected to the sub-inverter 12.
  • the semiconductor switching elements Q1 to Q4 connected in series form the U-phase leg
  • the semiconductor switching elements Q5 to Q8 connected in series form the V-phase leg
  • the semiconductor switching elements Q9 to Q12 connected in series form the W-phase leg.
  • the main inverter 9 is configured to be able to output at least three levels of potential in each phase: the potential of the positive DC terminal, the potential of the negative DC terminal, and the potential of the neutral point.
  • the sub-inverter 12 includes a U-phase inverter, a V-phase inverter, and a W-phase inverter, each of which is composed of a bridge circuit of four semiconductor switching elements corresponding to each phase.
  • the U-phase inverter is configured with semiconductor switching elements Q13 and Q14 connected in series, semiconductor switching elements Q15 and Q16 connected in series, and intermediate capacitor 10u connected in parallel.
  • the V-phase inverter is configured with semiconductor switching elements Q17 and Q18 connected in series, semiconductor switching elements Q19 and Q20 connected in series, and intermediate capacitor 10v connected in parallel.
  • the W-phase inverter is configured with semiconductor switching elements Q21 and Q22 connected in series, semiconductor switching elements Q23 and Q24 connected in series, and intermediate capacitor 10w connected in parallel.
  • connection point U between semiconductor switching element Q13 and semiconductor switching element Q14 is connected to connection point u of the main inverter 9
  • the connection point V between semiconductor switching element Q17 and semiconductor switching element Q18 is connected to connection point v of the main inverter 9
  • the connection point W between semiconductor switching element Q21 and semiconductor switching element Q22 is connected to connection point w of the main inverter 9.
  • connection point Uo between semiconductor switching element Q15 and semiconductor switching element Q16, the connection point Vo between semiconductor switching element Q19 and semiconductor switching element Q20, and the connection point Wo between semiconductor switching element Q23 and semiconductor switching element Q24 are each connected to load 4.
  • the control unit 19 receives sensor signals from sensors such as a current sensor 101, a voltage sensor (not shown), or a temperature sensor 102 provided in the main inverter 9 and the sub-inverter 12, and outputs gate drive signals to the semiconductor switching elements Q1 to Q24 provided in the main inverter 9 and the sub-inverter 12, controlling them to convert to a specified power.
  • sensors such as a current sensor 101, a voltage sensor (not shown), or a temperature sensor 102 provided in the main inverter 9 and the sub-inverter 12, and outputs gate drive signals to the semiconductor switching elements Q1 to Q24 provided in the main inverter 9 and the sub-inverter 12, controlling them to convert to a specified power.
  • Figures 4A to 4C are diagrams for explaining the output voltage command values of the main inverter 9 and the sub-inverter 12 in one cycle of the U phase AC output.
  • Figure 4A is a diagram showing the target output voltage command value from the inverter 3.
  • the target output waveform is a sine wave as shown in the figure.
  • Figure 4B is a diagram showing the output voltage command value of the main inverter 9, and in one cycle of the AC output, the output waveform is a square wave with one positive and one negative pulse.
  • Figure 4C shows the waveform of the output voltage command value of the sub-inverter 12, which is the waveform of the difference between the output voltage command value of Figure 4A and the output voltage command value of the main inverter 9 in Figure 4B.
  • the output of the inverter 30 is generated by adding or subtracting the voltage of the intermediate capacitor of the sub-inverter 12 to or from the output of the main inverter 9.
  • the main inverter 9 and the sub-inverter 12 output voltages according to the output voltage command values of their respective predetermined waveforms in response to gate drive signals from the control unit 19.
  • the main inverter 9 generates a positive and negative single-pulse waveform by low-frequency switching operation
  • the sub-inverter 12 generates multiple pulse-shaped voltage waveforms by PWM (Pulse Width Modulation) control so as to output a voltage of the output voltage command value.
  • PWM Pulse Width Modulation
  • the maximum value of the output voltage command value of the sub-inverter 12 is smaller than 1, for example, 0.5.
  • the output voltage of the sub-inverter 12 is the voltage of the intermediate capacitor 10u.
  • the voltage of each intermediate capacitor of the sub-inverter 12 is set to be smaller than the voltage of the P-side capacitor 5 and the N-side capacitor 6, which are the input capacitors of the main inverter 9.
  • FIG. 4C for example, if it is set to 1/2 (1/4 of the voltage of DC source 1), a stable waveform with fewer harmonic components can be output in the PWM operation of sub-inverter 12.
  • the control unit 19 calculates gate drive signals using sensor signals from current or voltage sensors provided in the main inverter 9 and sub-inverter 12 so as to maintain the relationship of the capacitor voltage ratios, and outputs the signals to each of the semiconductor switching elements Q1 to Q24.
  • the main inverter 9 generates a one-pulse waveform by low-frequency switching operation at a high DC voltage
  • the sub-inverter 12 performs high-speed switching operation at a low DC voltage.
  • Figure 5 shows ideal gate drive signals that are output to each semiconductor switching element to output a voltage waveform corresponding to the output voltage command value of the U-phase of the main inverter 9.
  • the output voltage command value of the main inverter 9 and the waveforms of the gate drive signals for driving the semiconductor switching elements Q1 to Q4 that make up the U-phase leg of the main inverter 9 are shown.
  • the semiconductor switching elements Q1 to Q4 are switched on and off once per AC output period.
  • the voltage applied between the drain and source of the semiconductor switching element becomes the voltage value of the input capacitor P-side capacitor 5 or N-side capacitor 6 while the gate drive signal is off (i.e. 0), and the voltage value becomes 0 while the gate drive signal is on (i.e. 1) (actually, the voltage drop due to internal factors is applied).
  • FIG. 6A is a diagram showing gate drive signals output to semiconductor switching elements for outputting a voltage waveform corresponding to the output voltage command value of the U-phase sub-inverter 12 according to the PWM control method described in Patent Document 1 as a comparative example.
  • the output voltage command value and carrier wave of the sub-inverter 12 and the waveforms of each gate drive signal for driving the semiconductor switching elements Q13 to Q16 constituting the U-phase inverter of the sub-inverter 12 are shown.
  • PWM control is performed using a level shift modulation method for two carrier waves, carrier wave A and carrier wave B.
  • the level shift modulation method is a method in which a DC offset is evenly added to the maximum amplitude of the carrier wave to (the number of levels - 1) carrier waves, and the output voltage command value and each carrier wave are compared.
  • the number of levels means the number of levels of voltage values that can be output.
  • the number of levels of the sub-inverter is 3.
  • Semiconductor switching element Q13 also referred to as first semiconductor switching element Q13
  • semiconductor switching element Q14 also referred to as second semiconductor switching element Q14
  • semiconductor switching element Q15 also referred to as third semiconductor switching element Q15
  • semiconductor switching element Q16 also referred to as fourth semiconductor switching element Q16
  • the semiconductor switching elements that make up the PWM-operated sub-inverter 12 switch many times, it is sufficient to use semiconductor switching elements that are suitable for high frequency driving such as SiC-MOSFETs with small switching losses.
  • the voltage applied between the drain and source of the semiconductor switching elements becomes the voltage value of intermediate capacitor 10u during the period when the gate drive signal is off (i.e.
  • semiconductor switching elements Q13 to Q16 each have a different switching conduction time, which means that different losses occur in each of the semiconductor switching elements that make up the sub-inverter, which can lead to localized heat generation. This is undesirable as it can reduce the lifespan of the device or increase the weight due to the strengthening of the heat sink.
  • FIG. 6B is a diagram explaining the operation of the sub-inverter in the U-phase of the power conversion device according to the first embodiment.
  • the losses (switching loss and conduction loss) occurring in the semiconductor switching elements constituting the sub-inverter are distributed to each semiconductor switching element.
  • the output voltage command value and carrier wave of the sub-inverter 12 and the waveforms of each gate drive signal for driving the semiconductor switching elements Q13 to Q16 constituting the inverter of the U-phase of the sub-inverter 12 are shown.
  • PWM control is performed using a phase shift modulation method.
  • Phase shift modulation is a method in which the phases of (number of levels - 1) carrier waves are shifted evenly and the voltage command value and the carrier wave are compared.
  • Semiconductor switching elements Q13 to Q16 are switched on and off multiple times per AC output cycle.
  • the switching elements that make up the PWM-operated sub-inverter 12 switch many times, so semiconductor switching elements suitable for high-frequency driving, such as SiC-MOSFETs with small switching losses, can be used.
  • the voltage applied between the drain and source of the semiconductor switching elements becomes the voltage value of the intermediate capacitor 10u while the gate drive signal is off (i.e., 0), and the voltage value becomes 0 while the gate drive signal is on (i.e., 1) (in reality, the voltage drop due to internal factors is applied).
  • each intermediate capacitor of the sub-inverter 12 is set to be smaller than the voltage of the P-side capacitor 5 and N-side capacitor 6, which are the input capacitors of the main inverter 9, for example to 1/2, the voltage applied to the semiconductor switching elements that make up the sub-inverter 12 will be 1/2 of the voltage applied to the semiconductor switching elements that make up the main inverter 9. These can be applied to other power conversion devices as well as three-phase power conversion devices.
  • the semiconductor switching elements Q13 to Q16 each have approximately the same switching conduction time, and the losses generated in each of the semiconductor switching elements constituting the sub-inverter are approximately the same. Therefore, compared to the comparative example, there is no risk of localized heat generation, and the cooling fan or heat sink can be made lighter and the risk of failure can be reduced.
  • FIG. 7A and 7B are diagrams showing an example of output waveforms when the gate drive signals of FIG. 5 and FIG. 6A according to a comparative example are applied to the semiconductor switching elements Q1 to Q4 and the semiconductor switching elements Q13 to Q16 of FIG. 2. That is, the diagrams show the operation of the comparative example.
  • FIG. 7A and 7B are diagrams showing an example of output waveforms when the gate drive signals of FIG. 5 and FIG. 6A according to a comparative example are applied to the semiconductor switching elements Q1 to Q4 and the semiconductor switching elements Q13 to Q16 of FIG. 2. That is, the diagrams show the operation of the comparative example.
  • FIG. 1 the diagrams showing an example of output waveforms when the gate drive signals of FIG. 5 and FIG. 6A according to a comparative example are applied to the semiconductor switching elements Q1 to Q4 and the semiconductor switching elements Q13 to Q16 of FIG. 2. That is, the diagrams show the operation of the comparative example.
  • the drain currents of the semiconductor switching elements Q13 and Q14 constituting the sub-inverter 12 The drain-source voltage of the semiconductor switching element Q13 constituting the sub-inverter 12, The drain-source voltage of the semiconductor switching element Q14 constituting the sub-inverter 12, The drain currents of the semiconductor switching elements Q15 and Q16 constituting the sub-inverter 12, The drain-source voltage of the semiconductor switching element Q15 constituting the sub-inverter 12, The drain-source voltage of the semiconductor switching element Q16 constituting the sub-inverter 12, This is the waveform.
  • phase currents output by the inverter 30 (main inverter 9+sub-inverter 12) are shown in order from the top.
  • Each line voltage output by the inverter 30, 1 is a waveform of each phase voltage output by the inverter 30.
  • the drain current waveform of each semiconductor switching element shows that the conduction time of Q14 and Q16 is longer than that of Q13 and Q15. This causes conduction loss according to the proportion of the conduction time, so the elements Q14 and Q16 generate more heat than Q13 and Q15, leading to a shorter lifespan of the elements.
  • the timing when it changes from 0V to 500V is called turn-off, and the timing when it changes from 500V to 0V is called turn-on, and switching loss occurs at turn-off and turn-on.
  • the number of turn-ons and turn-offs of Q13 to Q16 is almost equal, so there is almost no bias in switching loss. Since the loss generated by semiconductor switching elements is mainly the sum of switching loss and conduction loss (strictly speaking, it also includes recovery loss of the body diode), the loss generated by Q13 and Q15 is larger than that of Q14 and Q16, which is not desirable.
  • FIG. 8A and 8B show examples of output waveforms when the gate drive signals of FIG. 5 and FIG. 6B according to the first embodiment are applied to the semiconductor switching elements Q1 to Q4 and the semiconductor switching elements Q13 to Q16 of FIG. 2. That is, it is a diagram showing the operation of the power conversion device according to the first embodiment.
  • FIG. 8A and 8B show examples of output waveforms when the gate drive signals of FIG. 5 and FIG. 6B according to the first embodiment are applied to the semiconductor switching elements Q1 to Q4 and the semiconductor switching elements Q13 to Q16 of FIG. 2. That is, it is a diagram showing the operation of the power conversion device according to the first embodiment.
  • FIG. 8A and 8B show examples of output waveforms when the gate drive signals of FIG. 5 and FIG. 6B according to the first embodiment are applied to the semiconductor switching elements Q1 to Q4 and the semiconductor switching elements Q13 to Q16 of FIG. 2. That is, it is a diagram showing the operation of the power conversion device according to the first embodiment. In FIG.
  • the drain currents of the semiconductor switching elements Q13 and Q14 constituting the sub-inverter 12 The drain-source voltage of the semiconductor switching element Q13 constituting the sub-inverter 12, The drain-source voltage of the semiconductor switching element Q14 constituting the sub-inverter 12, The drain currents of the semiconductor switching elements Q15 and Q16 constituting the sub-inverter 12, The drain-source voltage of the semiconductor switching element Q15 constituting the sub-inverter 12, The drain-source voltage of the semiconductor switching element Q16 constituting the sub-inverter 12,
  • phase currents output by the inverter 30 are shown in order from the top.
  • Each line voltage output by the inverter 30, 4 shows the waveforms of the phase voltages output by the inverter 30.
  • the drain current waveforms of each semiconductor switching element show that the conduction times of Q13 to Q16 are almost equal, so there is almost no bias in conduction loss.
  • the drain-source voltage waveforms of each semiconductor switching element show that the timing when the voltage changes from 0V to 500V is called turn-off, and the timing when the voltage changes from 500V to 0V is called turn-on, and switching losses occur at the time of turn-off and turn-on.
  • the number of times Q13 to Q16 are turned on and off is almost equal, so there is almost no bias in switching losses. In other words, the losses generated by semiconductor switching elements Q13 to Q16 can be distributed almost equally.
  • phase currents, line voltages, and phase voltages in the comparative example and embodiment 1 do not differ significantly.
  • the loss of each semiconductor switching element constituting the sub-inverter is controlled so as to be distributed, thereby reducing localized loss bias, and reducing the weight of the cooling fan or heat sink and the risk of failure. In other words, it is possible to provide a power conversion device with improved reliability without increasing weight.
  • the power conversion device of this embodiment 1 can maintain a high loss distribution effect even during load fluctuation.
  • FIG. 9A shows the output voltage waveform and gate drive signal waveforms for Q13 to Q16 when the rotation speed of the load motor is controlled to 10,000 rpm using the same modulation method as in FIG. 6A, which is a comparative example.
  • 1 on the vertical axis indicates that each semiconductor switching element is on, i.e., conducting.
  • the gate drive signal waveforms of each semiconductor switching element show that Q13 and Q15 have a conduction time ratio (conduction ratio) of 18% per cycle, while Q14 and Q16 have a conduction ratio of 82%, resulting in a bias. This causes conduction loss according to the ratio of conduction time, and so the elements Q14 and Q16 generate more heat than Q13 and Q15, leading to a shortened lifespan of the elements.
  • Figure 9B shows the output voltage waveform and gate drive signal waveforms for Q13 to Q16 when the load motor speed is controlled to 8000 rpm using the same modulation method as Figure 6A (comparison example).
  • the gate drive signal waveforms for each semiconductor switching element show a bias in the conduction rate of Q13, 26%, Q14, 74%, Q15, 21%, and Q16, 79%.
  • the proportion of conduction time for Q14 and Q16 and Q13 and Q15 tends to be mitigated, but the elements Q14 and Q16 generate about three times as much heat as Q13 and Q15, leading to a shortened lifespan of the elements.
  • Fig. 10A shows the output waveform and the gate drive signal waveforms of Q13 to Q16 when the load motor speed is controlled to 10,000 rpm using the same modulation method as Fig. 6B, i.e., the modulation method of embodiment 1. From the gate drive signal waveforms of each semiconductor switching element, it can be seen that the conduction rate of each of the semiconductor switching elements Q13 to Q16 is 50%, and the losses are distributed.
  • FIG. 10B shows the output waveform and the gate drive signal waveforms of Q13 to Q16 when the rotation speed of the load motor is controlled to 8000 rpm using the same modulation method as in FIG. 6B, i.e., the modulation method of embodiment 1.
  • the gate drive signal waveforms of each semiconductor switching element show that the conduction rate of Q13 is 51%, the conduction rate of Q14 is 49%, the conduction rate of Q15 is 50%, and the conduction rate of Q16 is 50%.
  • the conduction rates of Q13 and Q14 change slightly, and the amount of heat generated by semiconductor switching element Q13 increases slightly, but it can be seen that the loss is distributed significantly compared to the comparative example shown in FIG. 9B.
  • the power conversion device controls the losses of the semiconductor switching elements of the sub-inverter 12, which has multiple semiconductor switching elements controlled by PWM control, to be equal. This reduces uneven heat generation among the semiconductor switching elements, and provides a power conversion device that can reduce the weight of the cooling fan or heat sink and the risk of failure.
  • Embodiment 2 a technology is described in which there are multiple switching patterns in which the sub-inverter 12 outputs the same voltage, each of which has a different conduction loss in each semiconductor switching element, and by selecting a switching pattern, it is possible to equalize the losses in the semiconductor switching elements.
  • Figure 11 shows the switching pattern of the sub-inverter 12.
  • the symbols are "+”, “zero up”, “zero down”, and “-”.
  • “+” means that the output voltage of the sub-inverter 12 is positive
  • “zero up” means that the current passes through the semiconductor switching elements Q13 and Q15 and the output voltage of the sub-inverter 12 is zero
  • “zero down” means that the current passes through the semiconductor switching elements Q14 and Q16 and the output voltage of the sub-inverter 12 is zero
  • “-” means that the output voltage of the sub-inverter 12 is negative.
  • Vsub means the voltage output by the sub-inverter.
  • Vcap is the voltage of the intermediate capacitor
  • the sub-inverter 12 outputs (generates) a voltage of +Vcap or -Vcap by switching the semiconductor switching elements on and off.
  • FIG. 12 shows a switching pattern, which is the transition of the on/off state of each semiconductor switching element Q13 to Q16 when current I>0 (the direction flowing to the load is positive) switching from “+” shown in FIG. 11 to "zero up,” and FIG. 13 shows the transition of the current path on the circuit diagram.
  • FIG. 14 shows the switching pattern when the sub-inverter is controlled to switch from “+” to "zero down” when current I>0
  • FIG. 15 shows the transition of the current path. Note that in FIG. 12 and FIG. 14, "OFF (D conduction)" indicates that the gate drive signal is off and current flows through the diode of the semiconductor switching element. This is the same below.
  • Dead time is a period during which the upper and lower switches are not turned on at the same time when switching on and off, in order to prevent a short circuit between the upper and lower arms. It is well known that dead time is used when operating a power conversion device in real equipment, so it will not be explained in detail.
  • Q13 and Q15 are made conductive, generating zero voltage. At this time, conduction loss occurs in Q13 and Q15.
  • Q14 and Q16 are made conductive, generating zero voltage. At this time, conduction loss occurs in Q14 and Q16.
  • the switching pattern in Fig. 12 and the switching pattern in Fig. 14 both output the same voltage.
  • the combination of semiconductor switching elements that are conductive i.e., the switching pattern, can be selected, making it possible to distribute the conduction loss.
  • the loss of Q13 is high among the semiconductor switching elements Q13 to Q16, the loss of Q13 can be suppressed by selecting the switching pattern in Fig. 14, which does not make Q13 conductive.
  • the loss of the semiconductor switching element can be determined from the temperature by placing a temperature sensor 102 directly under the element as shown in Fig. 3.
  • each semiconductor switching element is grasped depending on the temperature, and if there is a variation in temperature, the current path of the semiconductor switching element when the output voltage of the sub-inverter 12 becomes zero is changed, the on time of the semiconductor switching element with a high temperature is shortened, and control is performed in a direction to reduce the bias in loss. Making the temperature equal means that there is no bias in loss.
  • Figure 3 shows an example in which one semiconductor switching element is one module, it is also possible to use a structure in which, for example, Q13 and Q14 are one module, and Q15 and Q16 are one module, with a temperature sensor located directly under each semiconductor switching element of each module.
  • FIG. 16 the switching pattern when switching from "-" shown in FIG. 11 to "zero DOWN" when current I>0 (the direction flowing through the load is positive) is shown in FIG. 16, and the transition of the current path is shown in FIG. 17. Also, the switching pattern when switching from "-" to "zero UP” when current I>0 (the direction flowing through the load is positive) is shown in FIG. 18, and the transition of the current path is shown in FIG. 19.
  • Q14 and Q16 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q14 and Q16.
  • Q13 and Q15 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q13 and Q15.
  • FIG. 20 shows the switching pattern when switching from "+” shown in FIG. 11 to "zero UP" when current I ⁇ 0 (the direction flowing through the load is positive), and FIG. 21 shows the transition of the current path.
  • FIG. 22 shows the switching pattern when switching from "+” to "zero DOWN” when current I ⁇ 0 (the direction flowing through the load is positive), and FIG. 23 shows the transition of the current path.
  • Q13 and Q15 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q13 and Q15.
  • Q14 and Q16 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q14 and Q16.
  • FIG. 20 and FIG. 22 referring to FIG. 21 and FIG. 23, it can be seen that the voltage output is the same in both cases.
  • FIG. 24 the switching pattern when switching from "-" shown in FIG. 11 to "zero UP" when current I ⁇ 0 (the direction flowing through the load is positive) is shown in FIG. 24, and the transition of the current path is shown in FIG. 25.
  • FIG. 26 the switching pattern when switching from "-" to "zero DOWN" when current I ⁇ 0 (the direction flowing through the load is positive) is shown in FIG. 26, and the transition of the current path is shown in FIG. 27.
  • Q13 and Q15 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q13 and Q15.
  • Q14 and Q16 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q14 and Q16.
  • FIG. 24 and FIG. 26 by referring to FIG. 25 and FIG. 27, it can be seen that the voltage output is the same in both cases.
  • the switching pattern of the semiconductor switching elements when generating zero voltage in sub-inverter 12 can be selected, and the conduction time can be controlled by Q13 and Q15, and Q14 and Q16.
  • FIG. 28 shows the switching pattern of the sub-inverter for controlling the conduction time of Q13 and Q16, Q14 and Q15 when the sub-inverter 12 generates a positive voltage and a negative voltage.
  • the symbol “+” indicates that the sub-inverter 12 generates a positive voltage
  • "-" indicates that the sub-inverter generates a negative voltage.
  • Q14 and Q15 are made conductive.
  • a positive voltage can also be generated by turning off all of Q13 to Q16 when current I ⁇ 0. Therefore, when Q14 and Q15 are made conductive to generate a positive voltage, Q14 and Q15 can be turned off to continue generating a positive voltage, so that the conduction time of Q14 and Q15 can be controlled.
  • the average conduction time can be controlled by selecting the switching pattern, i.e., the current path, when generating a positive voltage.
  • Figures 30A and 30B show the current paths for generating "-", i.e., a negative voltage
  • Figure 30C shows the current path for generating a negative voltage when current I>0 (the direction flowing through the load is positive).
  • Q13 and Q16 are made conductive.
  • a negative voltage can also be generated by turning off all of Q13 to 16 when current I>0. Therefore, when Q13 and Q16 are made conductive to generate a negative voltage, Q13 and Q16 can be turned off to continue generating a negative voltage, so the conductive time of Q13 and Q16 can be controlled.
  • the average conductive time can be controlled by selecting the switching pattern, i.e., the current path, when generating a negative voltage.
  • the conduction time can be controlled by Q13 and Q16, and Q14 and Q15.
  • the semiconductor loss can be controlled to be distributed, reducing the bias in localized loss and reducing the weight of the cooling fan or heat sink and the risk of failure. In other words, it is possible to provide a power conversion device that improves reliability without increasing weight.
  • Embodiment 3 is an embodiment of a flying object including the power conversion device according to embodiment 1 or embodiment 2.
  • the flying object of this embodiment is, for example, an airplane, a helicopter, a drone, a flying car, or the like.
  • FIG. 31 is a schematic block diagram of a flying object 100 according to embodiment 3.
  • the flying object 100 is equipped with the power conversion device described in embodiment 1 or embodiment 2.
  • the flying object 100 is equipped with a propulsion power system 60 including a power source 63, a power source (DC power source) 1 connected to the power source 63, a DC/DC converter 50 connected to the power source 1 and equipped with a step-down chopper circuit for converting to a predetermined voltage, an inverter 30 that converts the DC power stepped down by the DC/DC converter 50 into AC power, a load 61 to which power is supplied from the inverter 30, and a control unit 62 that controls the DC/DC converter 50 and the inverter 30.
  • the load 61 is a propulsion load for obtaining propulsive force, such as an electric motor.
  • the inverter of the power conversion device according to embodiment 1 or embodiment 2 is used as the inverter 30 mounted on the flying object 100.
  • Devices mounted on flying objects such as aircraft that fly in the sky are required to be lightweight and reliable.
  • a power conversion device equipped with an inverter 30 in which the losses of the sub-inverters described in embodiment 1 or embodiment 2 are distributed is mounted on the propulsion power system 60. This makes it possible to reduce the weight of the cooling fan or cooling heat sink, suppressing increases in weight and cost, and also suppressing localized heat generation, improving reliability.
  • Embodiment 4 is an embodiment of a flying object including the power conversion device according to embodiment 1 or embodiment 2.
  • the flying object of this embodiment is, for example, an airplane, a helicopter, a drone, a flying car, or the like.
  • FIG. 32 is a schematic block diagram of a flying object 100 according to embodiment 4.
  • the flying object 100 is equipped with the power conversion device described in embodiment 1 or embodiment 2.
  • the flying object 100 is equipped with, as its equipment power system 70, a power source 74, an AC/DC converter 72 connected to the power source 74 and converting AC power to DC power, a DC source 1 connected to the AC/DC converter 72, a DC/DC converter 50 connected to the DC source 1 and equipped with a step-down chopper circuit for converting to a predetermined voltage, an inverter 30 that converts the DC power stepped down by the DC/DC converter 50 into AC power, a load 71 to which power is supplied from the inverter 30, and a control unit 73 that controls the DC/DC converter 50, the inverter 30, and the AC/DC converter 72.
  • the load 71 is an equipment load, and refers to, for example, an electric motor used to drive an air conditioner, an engine starter, and an auxiliary power device.
  • the inverter of the power conversion device according to embodiment 1 or embodiment 2 is used as inverter 30 of equipment power system 70 mounted on flying object 100.
  • Lightweight and reliable devices are required for mounting on flying objects that fly in the sky, such as flying objects represented by aircraft.
  • the control unit 19 shown in FIG. 2 specifically includes, as shown in FIG. 33, an arithmetic processing device 191 such as a CPU (Central Processing Unit), a storage device 192 for exchanging data with the arithmetic processing device 191, and an input/output interface 193 for inputting and outputting signals between the arithmetic processing device 191 and the outside.
  • the arithmetic processing device 191 may include an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and various signal processing circuits.
  • ASIC Application Specific Integrated Circuit
  • IC Integrated Circuit
  • DSP Digital Signal Processor
  • FPGA Field Programmable Gate Array
  • multiple arithmetic processing devices 191 of the same type or different types may be provided, and each process may be shared and executed.
  • the storage device 192 includes a RAM (Random Access Memory) configured to be able to read and write data from the arithmetic processing device 191, a ROM (Read Only Memory) configured to be able to read data from the arithmetic processing device 191, and the like.
  • the input/output interface 193 is composed of, for example, each voltage detection means provided in the main inverter 9 and the sub-inverter 12, an A/D converter that inputs sensor signals output from the current sensor 101, the temperature sensor 102, etc., to the arithmetic processing device 191, a drive circuit for outputting drive signals to each semiconductor switching element, etc.

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Abstract

This power conversion device comprises: a main inverter (9) that can output voltages having at least three levels; a sub-inverter (12) that is connected to the output of the main inverter (9), has a plurality of semiconductor switching elements (Q13, Q14, Q15, Q16) and an intermediate capacitor (10U), and adjusts the voltage of the intermediate capacitor (10U) to the output voltage of the main inverter (9); and a control unit (19) that controls the main inverter (9) and the sub-inverter (12). The control unit (19) performs a PWM control so that the losses of the plurality of semiconductor switching elements (Q13, Q14, Q15, Q16) of the sub-inverter (12) become equal.

Description

電力変換装置、および飛行物体Power conversion device and flying object
　本願は、電力変換装置、およびそれを備えた飛行物体に関するものである。 This application relates to a power conversion device and a flying object equipped with the same.
　近年、環境問題の観点で、航空機に関してＣＯ２削減の動きから電動化への開発が進められている。電動航空機で用いる電力変換装置では、軽量化、信頼性が求められる。例えば電力変換装置を構成する半導体デバイスの損失の偏りが生じると局所的に発熱し、故障が発生してしまうと信頼性を損ねる。また、信頼性を上げるために局所発熱が発生した部分の冷却能力を高めるために冷却ファンあるいはヒートシンクを用いると、装置の重量が重くなり、航空機の燃費が低下する。そのため、電力変換装置で発生する半導体損失の分散により、信頼性を確保しつつ、冷却ファンあるいは冷却ヒートシンクの重量を低減することが求められる。このように、電動航空機では電力変換装置の信頼性のみならず、軽量化が求められる。そして、冷却ファンあるいは冷却ヒートシンクの軽量化には、電力変換装置を構成する半導体損失を均等化することが課題であることがわかる。 In recent years, from the viewpoint of environmental issues, the development of electric aircraft has been promoted due to the movement to reduce CO2 emissions. The power conversion device used in the electric aircraft is required to be lightweight and reliable. For example, if the loss of the semiconductor device constituting the power conversion device is uneven, heat is generated locally, and if a failure occurs, reliability is impaired. In addition, if a cooling fan or heat sink is used to increase the cooling capacity of the part where local heat is generated in order to increase reliability, the weight of the device increases and the fuel efficiency of the aircraft decreases. Therefore, it is required to reduce the weight of the cooling fan or cooling heat sink while ensuring reliability by dispersing the semiconductor loss generated in the power conversion device. In this way, not only the reliability of the power conversion device but also its weight reduction is required for the electric aircraft. And, it can be seen that the challenge in reducing the weight of the cooling fan or cooling heat sink is to equalize the semiconductor loss constituting the power conversion device.
　これに対し、出願人は、３相のメインインバータとメインインバータのそれぞれの相に接続された３つの単相のサブインバータとを備えた電力変換装置において、サブインバータを構成する半導体スイッチング素子をレベルシフトのキャリア波を用いてＰＷＭ制御する電力変換装置を開示している（例えば、特許文献１参照）。 In response to this, the applicant has disclosed a power conversion device that includes a three-phase main inverter and three single-phase sub-inverters connected to each phase of the main inverter, in which the semiconductor switching elements that make up the sub-inverters are PWM-controlled using a level-shifted carrier wave (see, for example, Patent Document 1).
国際公開第ＷＯ２０２０－２６１３８４号International Publication No. WO2020-261384
　特許文献１に記載のサブインバータを構成する半導体スイッチング素子のＰＷＭ制御では、指令値によってサブインバータを構成するそれぞれの半導体スイッチング素子のスイッチング回数および導通時間に差が生じ、損失のばらつきが発生する。それぞれの半導体に損失のばらつきが生じると、発熱が多い半導体スイッチング素子に対する冷却能力を高める冷却ファンあるいはヒートシンクを用いる必要があり、装置の重量が重くなる。よって、冷却装置の負荷を軽減し、冷却装置の小型化、軽量化のために、それぞれの半導体の損失を均等化することが求められる。 In the PWM control of the semiconductor switching elements that make up the sub-inverter described in Patent Document 1, differences in the number of switching times and conduction time of each semiconductor switching element that makes up the sub-inverter occur depending on the command value, resulting in variation in loss. When variation in loss occurs in each semiconductor, it becomes necessary to use a cooling fan or heat sink to increase the cooling capacity of the semiconductor switching elements that generate a lot of heat, which increases the weight of the device. Therefore, it is necessary to equalize the loss of each semiconductor in order to reduce the load on the cooling device and make it smaller and lighter.
　本願では、サブインバータを構成するそれぞれの半導体スイッチング素子の損失の偏りを減らし、冷却ファンあるいはヒートシンクの軽量化および故障のリスクを低減することを目的とする。 The purpose of this application is to reduce the unevenness of losses in each semiconductor switching element that makes up the sub-inverter, to reduce the weight of the cooling fan or heat sink, and to reduce the risk of failure.
　本願に開示される電力変換装置は、直流のプラス電位が印加されるプラス端子と、直流のマイナス電位が印加されるマイナス端子との間に中性点を有するコンデンサを備え、少なくとも、前記プラス端子の電位と前記マイナス端子の電位と、前記中性点の電位とを出力可能なメインインバータと、前記メインインバータの出力に接続され、複数の半導体スイッチング素子と中間コンデンサとを有し、前記中間コンデンサの電圧を前記メインインバータの出力電圧に加減するサブインバータと、前記メインインバータおよび前記サブインバータを制御する制御部と、を備え、前記制御部は、前記サブインバータをＰＷＭ制御により制御し、前記サブインバータが出力する電圧を制御する電力変換装置において、前記制御部は、前記サブインバータの前記複数の半導体スイッチング素子の各半導体スイッチング素子の損失が均等になるよう制御するものである。 The power conversion device disclosed in the present application includes a main inverter having a capacitor with a neutral point between a positive terminal to which a positive DC potential is applied and a negative terminal to which a negative DC potential is applied, and capable of outputting at least the potential of the positive terminal, the potential of the negative terminal, and the potential of the neutral point; a sub-inverter connected to the output of the main inverter, having a plurality of semiconductor switching elements and an intermediate capacitor, and adjusting the voltage of the intermediate capacitor to the output voltage of the main inverter; and a control unit that controls the main inverter and the sub-inverter, the control unit controlling the sub-inverter by PWM control and controlling the voltage output by the sub-inverter, the control unit controlling the semiconductor switching elements of the plurality of semiconductor switching elements of the sub-inverter so that the losses of the respective semiconductor switching elements are equal.
　本願によれば、サブインバータを構成するそれぞれの半導体スイッチング素子の損失の偏りを減らし、冷却ファンまたはヒートシンクの軽量化および故障のリスクを低減できる電力変換装置を提供することができる。 The present application provides a power conversion device that can reduce the unevenness of losses in the semiconductor switching elements that make up the sub-inverter, reduce the weight of the cooling fan or heat sink, and reduce the risk of failure.
実施の形態１による電力変換装置の構成を示す概略ブロック図である。1 is a schematic block diagram showing a configuration of a power conversion device according to a first embodiment. 実施の形態１による電力変換装置の構成を示す回路図である。1 is a circuit diagram showing a configuration of a power conversion device according to a first embodiment. 実施の形態１による電力変換装置に用いる半導体スイッチング素子の構成を示す図である。2 is a diagram showing a configuration of a semiconductor switching element used in the power conversion device according to the first embodiment; 図４Ａ、図４Ｂ、および図４Ｃは、実施の形態１による電力変換装置の各インバータの電圧出力指令値の一例を示す線図である。4A, 4B, and 4C are diagrams showing an example of voltage output command values for each inverter of the power conversion device according to the first embodiment. 実施の形態１による電力変換装置のメインインバータの各半導体スイッチング素子のゲート駆動信号を示す線図である。4 is a diagram showing gate drive signals for each semiconductor switching element of a main inverter of the power conversion device according to the first embodiment. FIG. 比較例による電力変換装置のサブインバータの動作を示す線図である。11 is a diagram showing the operation of a sub-inverter of a power conversion device according to a comparative example. FIG. 実施の形態１による電力変換装置のサブインバータの動作を示す線図である。4 is a diagram showing the operation of a sub-inverter of the power conversion device according to the first embodiment. FIG. 比較例による電力変換装置のサブインバータの電流および電圧波形を示す線図である。10 is a diagram showing current and voltage waveforms of a sub-inverter of a power conversion device according to a comparative example. FIG. 比較例による電力変換装置の出力の電流および電圧波形を示す線図である。1 is a diagram showing current and voltage waveforms of the output of a power conversion device according to a comparative example. 実施の形態１による電力変換装置のサブインバータの電流および電圧波形を示す線図である。3 is a diagram showing current and voltage waveforms of a sub-inverter of the power conversion device according to the first embodiment. FIG. 実施の形態１による電力変換装置の出力の電流および電圧波形を示す線図である。2 is a diagram showing current and voltage waveforms of the output of the power conversion device according to the first embodiment. 比較例による電力変換装置のサブインバータの動作の一例を示す線図である。10 is a diagram showing an example of the operation of a sub-inverter of a power conversion device according to a comparative example. FIG. 比較例による電力変換装置のサブインバータの動作の別の例を示す線図である。FIG. 11 is a diagram showing another example of the operation of the sub-inverter of the power conversion device according to the comparative example. 実施の形態１による電力変換装置のサブインバータの動作の一例を示す線図である。4 is a diagram showing an example of the operation of a sub-inverter of the power conversion device according to the first embodiment. FIG. 実施の形態１による電力変換装置のサブインバータの動作の別の例を示す線図である。10 is a diagram showing another example of the operation of the sub-inverter of the power conversion device according to embodiment 1. FIG. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンの一例を説明する図である。13 is a diagram for explaining an example of a switching pattern of a sub-inverter of a power conversion device according to embodiment 2. FIG. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンの一例を示す図である。FIG. 11 is a diagram showing an example of a switching pattern of a sub-inverter of a power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータの図１２のスイッチングパターンによる電流経路の遷移を示す図である。13 is a diagram showing a transition of a current path due to the switching pattern of FIG. 12 in the sub-inverter of the power conversion device according to the second embodiment. FIG. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンの別の例を示す図である。FIG. 11 is a diagram showing another example of a switching pattern of the sub-inverter of the power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータの図１４のスイッチングパターンによる電流経路の遷移を示す図である。15 is a diagram showing a transition of a current path due to the switching pattern of FIG. 14 in the sub-inverter of the power conversion device according to the second embodiment. FIG. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンのさらに別の例を示す図である。FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータの図１６のスイッチングパターンによる電流経路の遷移を示す図である。17 is a diagram showing a transition of a current path due to the switching pattern of FIG. 16 in the sub-inverter of the power conversion device according to the second embodiment. FIG. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンのさらに別の例を示す図である。FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータの図１８のスイッチングパターンによる電流経路の遷移を示す図である。19 is a diagram showing a transition of a current path due to the switching pattern of FIG. 18 in the sub-inverter of the power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンのさらに別の例を示す図である。FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータの図２０のスイッチングパターンによる電流経路の遷移を示す図である。21 is a diagram showing a transition of a current path due to the switching pattern of FIG. 20 in the sub-inverter of the power conversion device according to the second embodiment. FIG. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンのさらに別の例を示す図である。FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータの図２２のスイッチングパターンによる電流経路の遷移を示す図である。23 is a diagram showing a transition of a current path due to the switching pattern of FIG. 22 in the sub-inverter of the power conversion device according to the second embodiment. FIG. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンのさらに別の例を示す図である。FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータの図２４のスイッチングパターンによる電流経路の遷移を示す図である。25 is a diagram showing a transition of a current path due to the switching pattern of FIG. 24 in the sub-inverter of the power conversion device according to the second embodiment. FIG. 実施の形態２による電力変換装置のサブインバータのスイッチングパターンのさらに別の例を示す図である。FIG. 11 is a diagram showing yet another example of the switching pattern of the sub-inverter of the power conversion device according to the second embodiment. 実施の形態２による電力変換装置のサブインバータの図２６のスイッチングパターンによる電流経路の遷移を示す図である。27 is a diagram showing a transition of a current path due to the switching pattern of FIG. 26 in the sub-inverter of the power conversion device according to the second embodiment. FIG. 実施の形態２による電力変換装置のサブインバータのプラス電圧生成時、およびマイナス電圧生成時のスイッチングパターンの例を説明する図である。13A and 13B are diagrams illustrating examples of switching patterns when a sub-inverter of a power conversion device according to a second embodiment generates a positive voltage and when a sub-inverter generates a negative voltage. 図２９Ａ、図２９Ｂ、図２９Ｃは、実施の形態２による電力変換装置のサブインバータのプラス電圧生成時の電流経路を説明する図である。29A, 29B, and 29C are diagrams for explaining current paths when the sub-inverter of the power conversion device according to embodiment 2 generates a positive voltage. 図３０Ａ、図３０Ｂ、図３０Ｃは、実施の形態２による電力変換装置のサブインバータのマイナス電圧生成時の電流経路を説明する図である。30A, 30B, and 30C are diagrams illustrating current paths when the sub-inverter of the power conversion device according to embodiment 2 generates a negative voltage. 実施の形態３による飛行物体の構成を示すブロック図である。FIG. 11 is a block diagram showing the configuration of a flying object according to a third embodiment. 実施の形態４による飛行物体の構成を示すブロック図である。FIG. 13 is a block diagram showing the configuration of a flying object according to a fourth embodiment. 本願の電力変換装置の制御部の構成の一例を示すブロック図である。2 is a block diagram showing an example of a configuration of a control unit of a power conversion device according to the present application; FIG.
実施の形態１．
　以下、実施の形態１に係る電力変換装置について図を用いて説明する。図１は、実施の形態１に係る電力変換装置３を用いた電力変換システムの一例を示す概略構成図である。図１において、直流源１と負荷４との間に、電力変換装置３が直列に接続され、直流源１と電力変換装置３との間にＤＣリンクコンデンサ２が並列に接続されている。電力変換装置３は、直流源１からの電力を所定の電力に変換して負荷４に出力する電力変換部であるインバータと、インバータを制御する制御部とを具備する。なお、本実施の形態１においてはインバータとして、ＤＣ／ＡＣインバータを例に説明する。 Embodiment 1.
The power conversion device according to the first embodiment will be described below with reference to the drawings. Fig. 1 is a schematic configuration diagram showing an example of a power conversion system using a power conversion device 3 according to the first embodiment. In Fig. 1, the power conversion device 3 is connected in series between a DC source 1 and a load 4, and a DC link capacitor 2 is connected in parallel between the DC source 1 and the power conversion device 3. The power conversion device 3 includes an inverter, which is a power conversion unit that converts power from the DC source 1 into a predetermined power and outputs it to the load 4, and a control unit that controls the inverter. In the first embodiment, a DC/AC inverter will be described as an example of the inverter.
　図２は、電力変換装置３の構成の一例を示す回路図である。図１に示すＤＣ／ＡＣインバータ３０は、ＤＣ／ＡＣインバータであり、三相３レベルインバータであるメインインバータ９と、メインインバータ９のそれぞれの相の出力に直列に接続された単相インバータであるサブインバータ１２を備えている。図２において、メインインバータ９を構成する半導体スイッチング素子Ｑ１～Ｑ１２は、例えばＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ－Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）にダイオードが逆並列接続された構造を有している。サブインバータ１２を構成する半導体スイッチング素子Ｑ１３～Ｑ２４も、例えばＭＯＳＦＥＴにダイオードが逆並列接続された構造を有している。 FIG. 2 is a circuit diagram showing an example of the configuration of the power conversion device 3. The DC/AC inverter 30 shown in FIG. 1 is a DC/AC inverter and includes a main inverter 9, which is a three-phase three-level inverter, and a sub-inverter 12, which is a single-phase inverter connected in series to the outputs of each phase of the main inverter 9. In FIG. 2, the semiconductor switching elements Q1 to Q12 constituting the main inverter 9 have a structure in which, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is connected to a diode in inverse parallel. The semiconductor switching elements Q13 to Q24 constituting the sub-inverter 12 also have a structure in which, for example, a MOSFET is connected to a diode in inverse parallel.
　ここで、メインインバータ９を構成する半導体スイッチング素子Ｑ１～Ｑ１２及びサブインバータ１２を構成する半導体スイッチング素子Ｑ１３～Ｑ２４は、いずれもワイドバンドギャップ半導体材料による半導体スイッチング素子が好ましい。詳細は後述するが、特にサブインバータ１２を構成する半導体スイッチング素子Ｑ１３～Ｑ２４は高速スイッチングを行うので、ワイドバンドギャップ半導体材料による半導体スイッチング素子がより好適である。 Here, it is preferable that the semiconductor switching elements Q1 to Q12 constituting the main inverter 9 and the semiconductor switching elements Q13 to Q24 constituting the sub-inverter 12 are all semiconductor switching elements made of wide band gap semiconductor materials. Details will be described later, but since the semiconductor switching elements Q13 to Q24 constituting the sub-inverter 12 perform high-speed switching, semiconductor switching elements made of wide band gap semiconductor materials are particularly preferable.
　図２のメインインバータ９及びサブインバータ１２を構成する半導体スイッチング素子Ｑ１～Ｑ２４の構造について図３を用いて説明する。図３は、メインインバータ９を構成する半導体スイッチング素子Ｑ１からＱ１２とサブインバータ１２を構成する半導体スイッチング素子Ｑ１３～Ｑ２４に適用される半導体スイッチング素子の構成を示す一例で、ドレイン端子Ｄ、ゲート端子Ｇ、ソース端子Ｓを有するＭＯＳＦＥＴ１５とこれに逆並列接続されたダイオード１６とで構成される。ＭＯＳＦＥＴ１５は、Ｓｉ－ＭＯＳＦＥＴであっても、ワイドバンドギャップ半導体材料による例えばＳｉＣ－ＭＯＳＦＥＴであってもよい。また、ダイオード１６はＳｉ－ダイオードであっても、ワイドバンドギャップ半導体材料による例えばＳｉＣ－ダイオードであってもよい。しかし、望ましくはワイドバンドギャップ半導体材料による半導体スイッチング素子がよい。例えば、それぞれの半導体スイッチング素子の温度を検知する温度センサ１０２が備えられている場合もある。 The structure of the semiconductor switching elements Q1 to Q24 constituting the main inverter 9 and the sub-inverter 12 in FIG. 2 will be described with reference to FIG. 3. FIG. 3 shows an example of the configuration of the semiconductor switching elements applied to the semiconductor switching elements Q1 to Q12 constituting the main inverter 9 and the semiconductor switching elements Q13 to Q24 constituting the sub-inverter 12, and is composed of a MOSFET 15 having a drain terminal D, a gate terminal G, and a source terminal S, and a diode 16 connected in reverse parallel to the MOSFET 15. The MOSFET 15 may be a Si-MOSFET or a wide band gap semiconductor material, such as a SiC-MOSFET. The diode 16 may be a Si-diode or a wide band gap semiconductor material, such as a SiC-diode. However, a semiconductor switching element made of a wide band gap semiconductor material is preferable. For example, a temperature sensor 102 for detecting the temperature of each semiconductor switching element may be provided.
　次に、図２を用いて、メインインバータ９の回路構成について説明する。図２において、メインインバータ９は、直流源１のプラス電位が印加されるプラス端子と直流源１のマイナス電位が印加されるマイナス端子との間に直列接続されたＰ側コンデンサ５とＮ側コンデンサ６、直列接続された半導体スイッチング素子Ｑ１～半導体スイッチング素子Ｑ４、直列接続された半導体スイッチング素子Ｑ５～半導体スイッチング素子Ｑ８、直列接続された半導体スイッチング素子Ｑ９～半導体スイッチング素子Ｑ１２がＤＣリンクコンデンサ２に並列接続されて構成されている。 Next, the circuit configuration of the main inverter 9 will be described with reference to Figure 2. In Figure 2, the main inverter 9 is configured with a P-side capacitor 5 and an N-side capacitor 6 connected in series between the positive terminal to which the positive potential of the DC source 1 is applied and the negative terminal to which the negative potential of the DC source 1 is applied, semiconductor switching elements Q1 to Q4 connected in series, semiconductor switching elements Q5 to Q8 connected in series, and semiconductor switching elements Q9 to Q12 connected in series, all connected in parallel to the DC link capacitor 2.
　Ｐ側コンデンサ５とＮ側コンデンサ６との接続点Ｅ（中性点とも称する）は、ダイオードＤ１のアノード端子とダイオードＤ２のカソード端子との接続点Ｅｕ、ダイオードＤ３のアノード端子とダイオードＤ４のカソード端子との接続点Ｅｖ、及びダイオードＤ５のアノード端子とダイオードＤ６のカソード端子との接続点Ｅｗと接続されている。 The connection point E (also called the neutral point) between the P-side capacitor 5 and the N-side capacitor 6 is connected to a connection point Eu between the anode terminal of diode D1 and the cathode terminal of diode D2, a connection point Ev between the anode terminal of diode D3 and the cathode terminal of diode D4, and a connection point Ew between the anode terminal of diode D5 and the cathode terminal of diode D6.
　ダイオードＤ１のカソード端子は半導体スイッチング素子Ｑ１と半導体スイッチング素子Ｑ２との接続点Ｋｕと接続され、ダイオードＤ３のカソード端子は半導体スイッチング素子Ｑ５と半導体スイッチング素子Ｑ６との接続点Ｋｖと接続され、ダイオードＤ５のカソード端子は半導体スイッチング素子Ｑ９と半導体スイッチング素子Ｑ１０との接続点Ｋｗと接続されている。 The cathode terminal of diode D1 is connected to the connection point Ku between semiconductor switching element Q1 and semiconductor switching element Q2, the cathode terminal of diode D3 is connected to the connection point Kv between semiconductor switching element Q5 and semiconductor switching element Q6, and the cathode terminal of diode D5 is connected to the connection point Kw between semiconductor switching element Q9 and semiconductor switching element Q10.
　ダイオードＤ２のアノード端子は半導体スイッチング素子Ｑ３と半導体スイッチング素子Ｑ４との接続点Ａｕと接続され、ダイオードＤ４のアノード端子は半導体スイッチング素子Ｑ７と半導体スイッチング素子Ｑ８との接続点Ａｖと接続され、ダイオードＤ６のアノード端子は半導体スイッチング素子Ｑ１１と半導体スイッチング素子Ｑ１２との接続点Ａｗと接続されている。 The anode terminal of diode D2 is connected to the connection point Au between semiconductor switching element Q3 and semiconductor switching element Q4, the anode terminal of diode D4 is connected to the connection point Av between semiconductor switching element Q7 and semiconductor switching element Q8, and the anode terminal of diode D6 is connected to the connection point Aw between semiconductor switching element Q11 and semiconductor switching element Q12.
　半導体スイッチング素子Ｑ２と半導体スイッチング素子Ｑ３との接続点ｕ、半導体スイッチング素子Ｑ６と半導体スイッチング素子Ｑ７との接続点ｖ、及び半導体スイッチング素子Ｑ１０と半導体スイッチング素子Ｑ１１との接続点ｗはそれぞれサブインバータ１２に接続されている。直列に接続された半導体スイッチング素子Ｑ１～半導体スイッチング素子Ｑ４はＵ相のレグを、直列に接続された半導体スイッチング素子Ｑ５～半導体スイッチング素子Ｑ８はＶ相のレグを、直列に接続された半導体スイッチング素子Ｑ９～半導体スイッチング素子Ｑ１２はＷ相のレグをそれぞれ構成する。メインインバータ９は、それぞれの相において、少なくとも直流のプラス端子の電位と、直流のマイナス端子の電位と、中性点の電位の３レベルの電位を出力可能な構成となっている。 　Connection point u between semiconductor switching element Q2 and semiconductor switching element Q3, connection point v between semiconductor switching element Q6 and semiconductor switching element Q7, and connection point w between semiconductor switching element Q10 and semiconductor switching element Q11 are each connected to the sub-inverter 12. The semiconductor switching elements Q1 to Q4 connected in series form the U-phase leg, the semiconductor switching elements Q5 to Q8 connected in series form the V-phase leg, and the semiconductor switching elements Q9 to Q12 connected in series form the W-phase leg. The main inverter 9 is configured to be able to output at least three levels of potential in each phase: the potential of the positive DC terminal, the potential of the negative DC terminal, and the potential of the neutral point.
　サブインバータ１２は、各相に対応した、それぞれ４つの半導体スイッチング素子のブリッジ回路で構成された、Ｕ相インバータ、Ｖ相インバータ、およびＷ相インバータを備えている。Ｕ相インバータは、直列に接続された半導体スイッチング素子Ｑ１３と半導体スイッチング素子Ｑ１４、直列に接続された半導体スイッチング素子Ｑ１５と半導体スイッチング素子Ｑ１６、及び中間コンデンサ１０ｕが並列に接続された構成である。Ｖ相インバータは、直列に接続された半導体スイッチング素子Ｑ１７と半導体スイッチング素子Ｑ１８、直列に接続された半導体スイッチング素子Ｑ１９と半導体スイッチング素子Ｑ２０、及び中間コンデンサ１０ｖが並列に接続された構成である。Ｗ相インバータは、直列に接続された半導体スイッチング素子Ｑ２１と半導体スイッチング素子Ｑ２２、直列に接続された半導体スイッチング素子Ｑ２３と半導体スイッチング素子Ｑ２４、及び中間コンデンサ１０ｗが並列に接続された構成である。 The sub-inverter 12 includes a U-phase inverter, a V-phase inverter, and a W-phase inverter, each of which is composed of a bridge circuit of four semiconductor switching elements corresponding to each phase. The U-phase inverter is configured with semiconductor switching elements Q13 and Q14 connected in series, semiconductor switching elements Q15 and Q16 connected in series, and intermediate capacitor 10u connected in parallel. The V-phase inverter is configured with semiconductor switching elements Q17 and Q18 connected in series, semiconductor switching elements Q19 and Q20 connected in series, and intermediate capacitor 10v connected in parallel. The W-phase inverter is configured with semiconductor switching elements Q21 and Q22 connected in series, semiconductor switching elements Q23 and Q24 connected in series, and intermediate capacitor 10w connected in parallel.
　半導体スイッチング素子Ｑ１３と半導体スイッチング素子Ｑ１４との接続点Ｕはメインインバータ９の接続点ｕと接続され、半導体スイッチング素子Ｑ１７と半導体スイッチング素子Ｑ１８との接続点Ｖはメインインバータ９の接続点ｖと接続され、半導体スイッチング素子Ｑ２１と半導体スイッチング素子Ｑ２２との接続点Ｗはメインインバータ９の接続点ｗとそれぞれ接続されている。 The connection point U between semiconductor switching element Q13 and semiconductor switching element Q14 is connected to connection point u of the main inverter 9, the connection point V between semiconductor switching element Q17 and semiconductor switching element Q18 is connected to connection point v of the main inverter 9, and the connection point W between semiconductor switching element Q21 and semiconductor switching element Q22 is connected to connection point w of the main inverter 9.
　半導体スイッチング素子Ｑ１５と半導体スイッチング素子Ｑ１６との接続点Ｕｏ、半導体スイッチング素子Ｑ１９と半導体スイッチング素子Ｑ２０との接続点Ｖｏ、半導体スイッチング素子Ｑ２３と半導体スイッチング素子Ｑ２４との接続点Ｗｏは、それぞれ負荷４に接続される。 The connection point Uo between semiconductor switching element Q15 and semiconductor switching element Q16, the connection point Vo between semiconductor switching element Q19 and semiconductor switching element Q20, and the connection point Wo between semiconductor switching element Q23 and semiconductor switching element Q24 are each connected to load 4.
　制御部１９は、メインインバータ９及びサブインバータ１２に設けられた電流センサ１０１、電圧センサ（図示せず）、あるいは温度センサ１０２などのセンサから、センサ信号を受信するとともに、メインインバータ９及びサブインバータ１２が具備する半導体スイッチング素子Ｑ１～Ｑ２４にゲート駆動信号を出力し、所定の電力に変換するように制御を行う。 The control unit 19 receives sensor signals from sensors such as a current sensor 101, a voltage sensor (not shown), or a temperature sensor 102 provided in the main inverter 9 and the sub-inverter 12, and outputs gate drive signals to the semiconductor switching elements Q1 to Q24 provided in the main inverter 9 and the sub-inverter 12, controlling them to convert to a specified power.
　次に、実施の形態１に係る電力変換装置３の動作について説明する。以降、動作の説明はＵ相を例に説明する。Ｖ相およびＷ相も動作は同様である。図４Ａ～図４Ｃは、メインインバータ９およびサブインバータ１２の、Ｕ相の交流出力１周期における出力電圧指令値を説明するための図である。図４Ａは、インバータ３からの目標とする出力電圧指令値を示す図である。目標の出力波形は図のように正弦波である。図４Ｂはメインインバータ９の出力電圧指令値を示す図で、交流出力１周期において、出力波形は正負それぞれ１パルスの方形波である。図４Ｃは、サブインバータ１２の出力電圧指令値の波形を示しており、図４Ａの出力電圧指令値と図４Ｂのメインインバータ９の出力電圧指令値の差分の波形となる。 Next, the operation of the power conversion device 3 according to the first embodiment will be described. Hereinafter, the operation will be described using the U phase as an example. The operation is similar for the V phase and the W phase. Figures 4A to 4C are diagrams for explaining the output voltage command values of the main inverter 9 and the sub-inverter 12 in one cycle of the U phase AC output. Figure 4A is a diagram showing the target output voltage command value from the inverter 3. The target output waveform is a sine wave as shown in the figure. Figure 4B is a diagram showing the output voltage command value of the main inverter 9, and in one cycle of the AC output, the output waveform is a square wave with one positive and one negative pulse. Figure 4C shows the waveform of the output voltage command value of the sub-inverter 12, which is the waveform of the difference between the output voltage command value of Figure 4A and the output voltage command value of the main inverter 9 in Figure 4B.
　インバータ３０の出力は、メインインバータ９の出力に、サブインバータ１２の中間コンデンサの電圧をプラス、またはマイナス、すなわち加減することにより生成される。メインインバータ９及びサブインバータ１２は、制御部１９からのゲート駆動信号により、それぞれの所定の波形の出力電圧指令値により電圧を出力する。メインインバータ９は、低周波のスイッチング動作により、正負ワンパルスの波形を生成し、サブインバータ１２は、出力電圧指令値の電圧を出力するよう、ＰＷＭ（Ｐｕｌｓｅ Ｗｉｄｔｈ Ｍｏｄｕｌａｔｉｏｎ：パルス幅変調）制御により、多数のパルス状の電圧波形を生成する。図４Ｂに示すように、メインインバータ９の波形の波高値を１とすると、サブインバータ１２の出力電圧指令値の最高値は１よりも小さい、例えば０．５となる。サブインバータ１２の出力電圧は、中間コンデンサ１０ｕの電圧となる。このため、サブインバータ１２の各中間コンデンサの電圧が、メインインバータ９の入力コンデンサであるＰ側コンデンサ５及びＮ側コンデンサ６の電圧より小さくなるように設定する。図４Ｃに示す例のように、例えば、１／２（直流源１の電圧の１／４）に設定すれば、サブインバータ１２のＰＷＭ動作において高調波成分の少ない安定した波形を出力することができる。 The output of the inverter 30 is generated by adding or subtracting the voltage of the intermediate capacitor of the sub-inverter 12 to or from the output of the main inverter 9. The main inverter 9 and the sub-inverter 12 output voltages according to the output voltage command values of their respective predetermined waveforms in response to gate drive signals from the control unit 19. The main inverter 9 generates a positive and negative single-pulse waveform by low-frequency switching operation, and the sub-inverter 12 generates multiple pulse-shaped voltage waveforms by PWM (Pulse Width Modulation) control so as to output a voltage of the output voltage command value. As shown in FIG. 4B, if the crest value of the waveform of the main inverter 9 is 1, the maximum value of the output voltage command value of the sub-inverter 12 is smaller than 1, for example, 0.5. The output voltage of the sub-inverter 12 is the voltage of the intermediate capacitor 10u. For this reason, the voltage of each intermediate capacitor of the sub-inverter 12 is set to be smaller than the voltage of the P-side capacitor 5 and the N-side capacitor 6, which are the input capacitors of the main inverter 9. As shown in the example in FIG. 4C, for example, if it is set to 1/2 (1/4 of the voltage of DC source 1), a stable waveform with fewer harmonic components can be output in the PWM operation of sub-inverter 12.
　制御部１９は、コンデンサの電圧比の関係を保つように、メインインバータ９及びサブインバータ１２に設けられた電流センサあるいは電圧センサからのセンサ信号を用いてゲート駆動信号を演算し、各半導体スイッチング素子Ｑ１～Ｑ２４に出力する。その結果、メインインバータ９は、高い直流電圧で低周波のスイッチング動作によりワンパルスの波形を生成し、サブインバータ１２は低い直流電圧で高速スイッチング動作を行うことになる。 The control unit 19 calculates gate drive signals using sensor signals from current or voltage sensors provided in the main inverter 9 and sub-inverter 12 so as to maintain the relationship of the capacitor voltage ratios, and outputs the signals to each of the semiconductor switching elements Q1 to Q24. As a result, the main inverter 9 generates a one-pulse waveform by low-frequency switching operation at a high DC voltage, and the sub-inverter 12 performs high-speed switching operation at a low DC voltage.
　図５は、メインインバータ９のＵ相の出力電圧指令値に対応する電圧波形を出力するために、各半導体スイッチング素子に出力される理想的なゲート駆動信号を示す図である。図５において、上から順に、メインインバータ９の出力電圧指令値、メインインバータ９のＵ相のレグを構成する半導体スイッチング素子Ｑ１～半導体スイッチング素子Ｑ４を駆動するためのゲート駆動信号の波形である。半導体スイッチング素子Ｑ１～半導体スイッチング素子Ｑ４は交流出力１周期当たりオン及びオフ１回ずつスイッチングする。このとき半導体スイッチング素子のドレイン―ソース間の印加電圧はゲート駆動信号がオフ（すなわち０）の期間に入力コンデンサであるＰ側コンデンサ５またはＮ側コンデンサ６の電圧値となり、ゲート駆動信号がオン（すなわち１）の期間の電圧値は０となる（実際には内部による電圧降下分印加される）。 Figure 5 shows ideal gate drive signals that are output to each semiconductor switching element to output a voltage waveform corresponding to the output voltage command value of the U-phase of the main inverter 9. In Figure 5, from the top, the output voltage command value of the main inverter 9 and the waveforms of the gate drive signals for driving the semiconductor switching elements Q1 to Q4 that make up the U-phase leg of the main inverter 9 are shown. The semiconductor switching elements Q1 to Q4 are switched on and off once per AC output period. At this time, the voltage applied between the drain and source of the semiconductor switching element becomes the voltage value of the input capacitor P-side capacitor 5 or N-side capacitor 6 while the gate drive signal is off (i.e. 0), and the voltage value becomes 0 while the gate drive signal is on (i.e. 1) (actually, the voltage drop due to internal factors is applied).
　次に、サブインバータ１２の動作を説明する。図６Ａは、比較例として特許文献１に記載されているＰＷＭ制御方式による、Ｕ相のサブインバータ１２の出力電圧指令値に対応する電圧波形を出力するための半導体スイッチング素子に出力されるゲート駆動信号を示す図である。図において、上から順に、サブインバータ１２の出力電圧指令値及びキャリア波、サブインバータ１２のＵ相のインバータを構成する半導体スイッチング素子Ｑ１３～半導体スイッチング素子Ｑ１６を駆動するための各ゲート駆動信号の波形である。本比較例では、キャリア波Ａとキャリア波Ｂの２つのキャリア波について、レベルシフト変調方式でＰＷＭ制御を行っている。レベルシフト変調方式は、（レベル数－１）個のキャリア波にキャリア波の最大振幅に対して均等に直流オフセットを加え、出力電圧指令値とそれぞれのキャリア波とを比較する方式である。レベル数とは、出力できる電圧値のレベル数を意味する。サブインバータのレベル数は３である。 Next, the operation of the sub-inverter 12 will be described. FIG. 6A is a diagram showing gate drive signals output to semiconductor switching elements for outputting a voltage waveform corresponding to the output voltage command value of the U-phase sub-inverter 12 according to the PWM control method described in Patent Document 1 as a comparative example. In the figure, from the top, the output voltage command value and carrier wave of the sub-inverter 12, and the waveforms of each gate drive signal for driving the semiconductor switching elements Q13 to Q16 constituting the U-phase inverter of the sub-inverter 12 are shown. In this comparative example, PWM control is performed using a level shift modulation method for two carrier waves, carrier wave A and carrier wave B. The level shift modulation method is a method in which a DC offset is evenly added to the maximum amplitude of the carrier wave to (the number of levels - 1) carrier waves, and the output voltage command value and each carrier wave are compared. The number of levels means the number of levels of voltage values that can be output. The number of levels of the sub-inverter is 3.
　半導体スイッチング素子Ｑ１３（第一半導体スイッチング素子Ｑ１３とも称する）、半導体スイッチング素子Ｑ１４（第二半導体スイッチング素子Ｑ１４とも称する）、半導体スイッチング素子Ｑ１５（第三半導体スイッチング素子Ｑ１５とも称する）、および半導体スイッチング素子Ｑ１６（第四半導体スイッチング素子Ｑ１６とも称する）は交流出力１周期当たり複数回ずつオン及びオフスイッチングする。ＰＷＭ動作するサブインバータ１２を構成する半導体スイッチング素子はスイッチング回数が多いので、スイッチング損失の小さいＳｉＣ－ＭＯＳＦＥＴ等の高周波駆動に適した半導体スイッチング素子を使用すればよい。このとき半導体スイッチング素子のドレイン―ソース間の印加電圧はゲート駆動信号がオフ（すなわち０）の期間に中間コンデンサ１０ｕの電圧値となり、ゲート駆動信号がオン（すなわち１）の期間の電圧値は０となる（実際には内部による電圧降下分印加される）。図６Ａに示すように、半導体スイッチング素子Ｑ１３～半導体スイッチング素子Ｑ１６は、それぞれスイッチングの導通時間が異なるため、サブインバータを構成するそれぞれの半導体スイッチング素子に異なる損失が発生するため局所的に発熱する恐れがあり、装置の寿命低下あるいは放熱器の強化による重量増が見込まれるので好ましくない。 Semiconductor switching element Q13 (also referred to as first semiconductor switching element Q13), semiconductor switching element Q14 (also referred to as second semiconductor switching element Q14), semiconductor switching element Q15 (also referred to as third semiconductor switching element Q15), and semiconductor switching element Q16 (also referred to as fourth semiconductor switching element Q16) are switched on and off multiple times per AC output cycle. Since the semiconductor switching elements that make up the PWM-operated sub-inverter 12 switch many times, it is sufficient to use semiconductor switching elements that are suitable for high frequency driving such as SiC-MOSFETs with small switching losses. In this case, the voltage applied between the drain and source of the semiconductor switching elements becomes the voltage value of intermediate capacitor 10u during the period when the gate drive signal is off (i.e. 0), and the voltage value becomes 0 during the period when the gate drive signal is on (i.e. 1) (in reality, the voltage drop due to internal factors is applied). As shown in FIG. 6A, semiconductor switching elements Q13 to Q16 each have a different switching conduction time, which means that different losses occur in each of the semiconductor switching elements that make up the sub-inverter, which can lead to localized heat generation. This is undesirable as it can reduce the lifespan of the device or increase the weight due to the strengthening of the heat sink.
　図６Ｂは、実施の形態１による電力変換装置の、サブインバータのＵ相における動作を説明する図である。実施の形態１によるサブインバータでは、サブインバータを構成する半導体スイッチング素子に発生する損失（スイッチング損失および導通損失）が、それぞれの半導体スイッチング素子に分散される制御を行う。図６Ｂにおいて、上から順に、サブインバータ１２の出力電圧指令値及びキャリア波、サブインバータ１２のＵ相のインバータを構成する半導体スイッチング素子Ｑ１３～半導体スイッチング素子Ｑ１６を駆動するための各ゲート駆動信号の波形である。図６Ｂに示すように、本実施の形態１では、位相シフト変調方式でＰＷＭ制御を行う。位相シフト変調は、（レベル数－１）個のキャリア波の位相を均等にシフトさせ、電圧指令値とキャリア波を比較する方式である。 FIG. 6B is a diagram explaining the operation of the sub-inverter in the U-phase of the power conversion device according to the first embodiment. In the sub-inverter according to the first embodiment, the losses (switching loss and conduction loss) occurring in the semiconductor switching elements constituting the sub-inverter are distributed to each semiconductor switching element. In FIG. 6B, from the top, the output voltage command value and carrier wave of the sub-inverter 12, and the waveforms of each gate drive signal for driving the semiconductor switching elements Q13 to Q16 constituting the inverter of the U-phase of the sub-inverter 12 are shown. As shown in FIG. 6B, in the first embodiment, PWM control is performed using a phase shift modulation method. Phase shift modulation is a method in which the phases of (number of levels - 1) carrier waves are shifted evenly and the voltage command value and the carrier wave are compared.
　半導体スイッチング素子Ｑ１３～半導体スイッチング素子Ｑ１６は交流出力１周期当たり複数回ずつオン及びオフスイッチングする。ＰＷＭ動作するサブインバータ１２を構成するスイッチング素子はスイッチング回数が多いので、スイッチング損失の小さいＳｉＣ－ＭＯＳＦＥＴ等の高周波駆動に適した半導体スイッチング素子を使用すればよい。このとき半導体スイッチング素子のドレイン―ソース間の印加電圧はゲート駆動信号がオフ（すなわち０）の期間に中間コンデンサ１０ｕの電圧値となり、ゲート駆動信号がオン（すなわち１）の期間の電圧値は０となる（実際には内部による電圧降下分印加される）。 Semiconductor switching elements Q13 to Q16 are switched on and off multiple times per AC output cycle. The switching elements that make up the PWM-operated sub-inverter 12 switch many times, so semiconductor switching elements suitable for high-frequency driving, such as SiC-MOSFETs with small switching losses, can be used. In this case, the voltage applied between the drain and source of the semiconductor switching elements becomes the voltage value of the intermediate capacitor 10u while the gate drive signal is off (i.e., 0), and the voltage value becomes 0 while the gate drive signal is on (i.e., 1) (in reality, the voltage drop due to internal factors is applied).
　サブインバータ１２の各中間コンデンサの電圧を、メインインバータ９の入力コンデンサであるＰ側コンデンサ５及びＮ側コンデンサ６の電圧より小さくなるように、例えば、１／２に設定した場合、サブインバータ１２を構成する半導体スイッチング素子に印加される電圧は、メインインバータ９を構成する半導体スイッチング素子に印加される電圧の１／２となる。これらは３相の電力変換装置でなくても適用可能である。 If the voltage of each intermediate capacitor of the sub-inverter 12 is set to be smaller than the voltage of the P-side capacitor 5 and N-side capacitor 6, which are the input capacitors of the main inverter 9, for example to 1/2, the voltage applied to the semiconductor switching elements that make up the sub-inverter 12 will be 1/2 of the voltage applied to the semiconductor switching elements that make up the main inverter 9. These can be applied to other power conversion devices as well as three-phase power conversion devices.
　図６Ｂに示すように、実施の形態１による電力変換装置のサブインバータ１２の動作によれば、半導体スイッチング素子Ｑ１３～半導体スイッチング素子Ｑ１６は、それぞれスイッチングの導通時間がほぼ同じであり、サブインバータを構成するそれぞれの半導体スイッチング素子に発生する損失はほぼ同じとなる。したがって、比較例に比べて、局所的に発熱する恐れがなく、冷却ファンまたはヒートシンクの軽量化および故障のリスクを低減できる。 As shown in FIG. 6B, according to the operation of the sub-inverter 12 of the power conversion device of the first embodiment, the semiconductor switching elements Q13 to Q16 each have approximately the same switching conduction time, and the losses generated in each of the semiconductor switching elements constituting the sub-inverter are approximately the same. Therefore, compared to the comparative example, there is no risk of localized heat generation, and the cooling fan or heat sink can be made lighter and the risk of failure can be reduced.
　図７Ａおよび図７Ｂは、図５および比較例による図６Ａのゲート駆動信号を図２の半導体スイッチング素子Ｑ１～半導体スイッチング素子Ｑ４および半導体スイッチング素子Ｑ１３～半導体スイッチング素子Ｑ１６に適用したときの出力波形の一例を示す線図である。すなわち比較例の動作を示す線図である。図７Ａにおいて、上から順に、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１３およびＱ１４のドレイン電流、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１３のドレインソース電圧、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１４のドレインソース電圧、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１５およびＱ１６のドレイン電流、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１５のドレインソース電圧、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１６のドレインソース電圧、
の波形である。 7A and 7B are diagrams showing an example of output waveforms when the gate drive signals of FIG. 5 and FIG. 6A according to a comparative example are applied to the semiconductor switching elements Q1 to Q4 and the semiconductor switching elements Q13 to Q16 of FIG. 2. That is, the diagrams show the operation of the comparative example. In FIG. 7A, from the top,
The drain currents of the semiconductor switching elements Q13 and Q14 constituting the sub-inverter 12,
The drain-source voltage of the semiconductor switching element Q13 constituting the sub-inverter 12,
The drain-source voltage of the semiconductor switching element Q14 constituting the sub-inverter 12,
The drain currents of the semiconductor switching elements Q15 and Q16 constituting the sub-inverter 12,
The drain-source voltage of the semiconductor switching element Q15 constituting the sub-inverter 12,
The drain-source voltage of the semiconductor switching element Q16 constituting the sub-inverter 12,
This is the waveform.
　また、図７Ｂにおいて、上から順に
インバータ３０（メインインバータ９＋サブインバータ１２）が出力する各相電流、
インバータ３０が出力する各線間電圧、
インバータ３０が出力する各相電圧
の波形である In addition, in FIG. 7B, the phase currents output by the inverter 30 (main inverter 9+sub-inverter 12) are shown in order from the top.
Each line voltage output by the inverter 30,
1 is a waveform of each phase voltage output by the inverter 30.
　各半導体スイッチング素子のドレイン電流波形より、Ｑ１４およびＱ１６の導通時間がＱ１３およびＱ１５に対して長くなる。これにより、導通時間の割合に応じた導通損失が発生するためＱ１４およびＱ１６の素子はＱ１３およびＱ１５に比べて、発熱量が多くなり、素子の寿命低下につながる。各半導体スイッチング素子のドレインソース電圧波形より、０Ｖから５００Ｖに変化するタイミングをターンオフ、５００Ｖから０Ｖに変化するタイミングをターンオンといい、ターンオフおよびターンオン時にスイッチング損失が発生する。Ｑ１３～Ｑ１６のターンオンおよびターンオフの回数はほぼ等しいためスイッチング損失の偏りはほとんど生じていない。半導体スイッチング素子で発生する損失は主にスイッチング損失と導通損失の総量であるため（厳密にはボディーダイオードのリカバリー損失も含む）、Ｑ１３およびＱ１５で発生する損失はＱ１４およびＱ１６に比べて大きくなるので好ましくない。 The drain current waveform of each semiconductor switching element shows that the conduction time of Q14 and Q16 is longer than that of Q13 and Q15. This causes conduction loss according to the proportion of the conduction time, so the elements Q14 and Q16 generate more heat than Q13 and Q15, leading to a shorter lifespan of the elements. From the drain-source voltage waveform of each semiconductor switching element, the timing when it changes from 0V to 500V is called turn-off, and the timing when it changes from 500V to 0V is called turn-on, and switching loss occurs at turn-off and turn-on. The number of turn-ons and turn-offs of Q13 to Q16 is almost equal, so there is almost no bias in switching loss. Since the loss generated by semiconductor switching elements is mainly the sum of switching loss and conduction loss (strictly speaking, it also includes recovery loss of the body diode), the loss generated by Q13 and Q15 is larger than that of Q14 and Q16, which is not desirable.
　図８Ａおよび図８Ｂは、図５および実施の形態１による図６Ｂのゲート駆動信号を図２の半導体スイッチング素子Ｑ１～半導体スイッチング素子Ｑ４および半導体スイッチング素子Ｑ１３～半導体スイッチング素子Ｑ１６に適用したときの出力波形の一例を示す。すなわち実施の形態１による電力変換装置の動作を示す線図である。図８Ａにおいて、上から順に、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１３およびＱ１４のドレイン電流、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１３のドレインソース電圧、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１４のドレインソース電圧、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１５およびＱ１６のドレイン電流、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１５のドレインソース電圧、
サブインバータ１２を構成する半導体スイッチング素子Ｑ１６のドレインソース電圧、 8A and 8B show examples of output waveforms when the gate drive signals of FIG. 5 and FIG. 6B according to the first embodiment are applied to the semiconductor switching elements Q1 to Q4 and the semiconductor switching elements Q13 to Q16 of FIG. 2. That is, it is a diagram showing the operation of the power conversion device according to the first embodiment. In FIG. 8A, from the top,
The drain currents of the semiconductor switching elements Q13 and Q14 constituting the sub-inverter 12,
The drain-source voltage of the semiconductor switching element Q13 constituting the sub-inverter 12,
The drain-source voltage of the semiconductor switching element Q14 constituting the sub-inverter 12,
The drain currents of the semiconductor switching elements Q15 and Q16 constituting the sub-inverter 12,
The drain-source voltage of the semiconductor switching element Q15 constituting the sub-inverter 12,
The drain-source voltage of the semiconductor switching element Q16 constituting the sub-inverter 12,
　また、図８Ｂにおいて、上から順に
インバータ３０が出力する各相電流、
インバータ３０が出力する各線間電圧、
インバータ３０が出力する各相電圧
の波形である。 In addition, in FIG. 8B, the phase currents output by the inverter 30 are shown in order from the top.
Each line voltage output by the inverter 30,
4 shows the waveforms of the phase voltages output by the inverter 30.
　各半導体スイッチング素子のドレイン電流波形より、Ｑ１３～Ｑ１６の導通時間がほぼ等しいため導通損失の偏りはほとんど生じていない。各半導体スイッチング素子のドレインソース電圧波形より、０Vから５００Vに変化するタイミングをターンオフ、５００Vから０Vに変化するタイミングをターンオンといい、ターンオフおよびターンオン時にスイッチング損失が発生する。Ｑ１３～Ｑ１６のターンオンおよびターンオフの回数はほぼ等しいためスイッチング損失の偏りはほとんど生じていない。すなわち半導体スイッチング素子Ｑ１３～Ｑ１６で発生する損失はほぼ等しく分散できる。 The drain current waveforms of each semiconductor switching element show that the conduction times of Q13 to Q16 are almost equal, so there is almost no bias in conduction loss. The drain-source voltage waveforms of each semiconductor switching element show that the timing when the voltage changes from 0V to 500V is called turn-off, and the timing when the voltage changes from 500V to 0V is called turn-on, and switching losses occur at the time of turn-off and turn-on. The number of times Q13 to Q16 are turned on and off is almost equal, so there is almost no bias in switching losses. In other words, the losses generated by semiconductor switching elements Q13 to Q16 can be distributed almost equally.
　また、図７Ｂと図８Ｂとの比較からわかるように、比較例と実施の形態１において、各相電流、各線間電圧、各相電圧は、大きく異ならない。すなわち、相電流、線間電圧、相電圧を維持しながら、半導体スイッチング素子Ｑ１３～Ｑ１６における損失の偏りを抑制することができる。 Furthermore, as can be seen from a comparison between FIG. 7B and FIG. 8B, the phase currents, line voltages, and phase voltages in the comparative example and embodiment 1 do not differ significantly. In other words, it is possible to suppress the bias in losses in the semiconductor switching elements Q13 to Q16 while maintaining the phase currents, line voltages, and phase voltages.
　以上のように、本実施の形態１によれば、サブインバータを構成する各半導体スイッチング素子の損失を分散するように制御するので、局所的な損失の偏りを減少し、冷却ファンまたはヒートシンクの軽量化および故障のリスクを低減する。すなわち、重量を増加させることなく、信頼性が向上した電力変換装置を提供することができる。 As described above, according to the first embodiment, the loss of each semiconductor switching element constituting the sub-inverter is controlled so as to be distributed, thereby reducing localized loss bias, and reducing the weight of the cooling fan or heat sink and the risk of failure. In other words, it is possible to provide a power conversion device with improved reliability without increasing weight.
　負荷変動による電圧変調率が変化した場合に半導体スイッチング素子が発生する損失の分散する割合が変化する。以下、本実施の形態１の電力変換装置によれば、負荷変動時においても高い損失分散効果が維持できることを説明する。 When the voltage modulation rate changes due to load fluctuation, the distribution ratio of the loss generated by the semiconductor switching element changes. Below, it will be explained that the power conversion device of this embodiment 1 can maintain a high loss distribution effect even during load fluctuation.
　図９Ａは、比較例である図６Ａと同様の変調方式を用いて負荷モータの回転数を10000rpmに制御した時の出力電圧波形とＱ１３～Ｑ１６のゲート駆動信号波形を示している。図９Ａのゲート駆動信号波形の各図において、縦軸の１が、各半導体スイッチング素子がオン、すなわち導通している状態を示している。各半導体スイッチング素子のゲート駆動信号波形より、Ｑ１３およびＱ１５が１周期に対して導通時間の割合（導通割合）が１８％、Ｑ１４およびＱ１６の導通割合が８２％と偏りが生じる。これにより、導通時間の割合に応じた導通損失が発生するためＱ１４およびＱ１６の素子はＱ１３およびＱ１５に比べて、発熱量が多くなり、素子の寿命低下につながる。 FIG. 9A shows the output voltage waveform and gate drive signal waveforms for Q13 to Q16 when the rotation speed of the load motor is controlled to 10,000 rpm using the same modulation method as in FIG. 6A, which is a comparative example. In each diagram of the gate drive signal waveforms in FIG. 9A, 1 on the vertical axis indicates that each semiconductor switching element is on, i.e., conducting. The gate drive signal waveforms of each semiconductor switching element show that Q13 and Q15 have a conduction time ratio (conduction ratio) of 18% per cycle, while Q14 and Q16 have a conduction ratio of 82%, resulting in a bias. This causes conduction loss according to the ratio of conduction time, and so the elements Q14 and Q16 generate more heat than Q13 and Q15, leading to a shortened lifespan of the elements.
　図９Ｂは、比較例である図６Ａと同様の変調方式を用いて負荷モータの回転数を8000rpmに制御した時の出力電圧波形とＱ１３～Ｑ１６のゲート駆動信号波形を示している。各半導体スイッチング素子のゲート駆動信号波形より、Ｑ１３の導通割合が２６％、Ｑ１４の導通割合は７４％、Ｑ１５の導通割合は２１％、Ｑ１６の導通割合は７９％と偏りが生じる。10000rpmから8000rpmに減速した場合、Ｑ１４およびＱ１６とＱ１３およびＱ１５の導通時間の割合は、緩和される方向になったが、Ｑ１４およびＱ１６の素子はＱ１３およびＱ１５に比べて、約３倍発熱量が多くなり、素子の寿命低下につながる。 Figure 9B shows the output voltage waveform and gate drive signal waveforms for Q13 to Q16 when the load motor speed is controlled to 8000 rpm using the same modulation method as Figure 6A (comparison example). The gate drive signal waveforms for each semiconductor switching element show a bias in the conduction rate of Q13, 26%, Q14, 74%, Q15, 21%, and Q16, 79%. When decelerating from 10,000 rpm to 8,000 rpm, the proportion of conduction time for Q14 and Q16 and Q13 and Q15 tends to be mitigated, but the elements Q14 and Q16 generate about three times as much heat as Q13 and Q15, leading to a shortened lifespan of the elements.
　図１０Ａは、図６Ｂと同様の変調方式すなわち実施の形態１の変調方式を用いて負荷モータの回転数を10000rpmに制御した時の出力波形とＱ１３～Ｑ１６のゲート駆動信号波形を示している。各半導体スイッチング素子のゲート駆動信号波形より、Ｑ１３～Ｑ１６のいずれの半導体スイッチング素子も、導通割合が５０％と損失分散していることがわかる。 Fig. 10A shows the output waveform and the gate drive signal waveforms of Q13 to Q16 when the load motor speed is controlled to 10,000 rpm using the same modulation method as Fig. 6B, i.e., the modulation method of embodiment 1. From the gate drive signal waveforms of each semiconductor switching element, it can be seen that the conduction rate of each of the semiconductor switching elements Q13 to Q16 is 50%, and the losses are distributed.
　図１０Ｂは、図６Ｂと同様の変調方式すなわち実施の形態１の変調方式を用いて負荷モータの回転数を8000rpmに制御した時の出力波形とＱ１３～Ｑ１６のゲート駆動信号波形を示している。各半導体スイッチング素子のゲート駆動信号波形より、Ｑ１３の導通割合が５１％、Ｑ１４の導通割合は４９％、Ｑ１５の導通割合は５０％、Ｑ１６の導通割合は５０％となっている。10000rpmから8000rpmに減速した場合、若干であるがＱ１３とＱ１４の導通割合が変わり、半導体スイッチング素子Ｑ１３の発熱量が若干多くなるが、図９Ｂで示した比較例に対して、大幅に損失分散されていることが分かる。 FIG. 10B shows the output waveform and the gate drive signal waveforms of Q13 to Q16 when the rotation speed of the load motor is controlled to 8000 rpm using the same modulation method as in FIG. 6B, i.e., the modulation method of embodiment 1. The gate drive signal waveforms of each semiconductor switching element show that the conduction rate of Q13 is 51%, the conduction rate of Q14 is 49%, the conduction rate of Q15 is 50%, and the conduction rate of Q16 is 50%. When decelerating from 10,000 rpm to 8,000 rpm, the conduction rates of Q13 and Q14 change slightly, and the amount of heat generated by semiconductor switching element Q13 increases slightly, but it can be seen that the loss is distributed significantly compared to the comparative example shown in FIG. 9B.
　以上説明したように、実施の形態１による電力変換装置によれば、ＰＷＭ制御により制御される複数の半導体スイッチング素子を有するサブインバータ１２の各半導体スイッチング素子の損失が均等となるよう制御するようにしたので、半導体スイッチング素子の発熱の偏りが低減でき、冷却ファンまたはヒートシンクの軽量化および故障のリスクを低減できる電力変換装置が得られる。 As described above, the power conversion device according to embodiment 1 controls the losses of the semiconductor switching elements of the sub-inverter 12, which has multiple semiconductor switching elements controlled by PWM control, to be equal. This reduces uneven heat generation among the semiconductor switching elements, and provides a power conversion device that can reduce the weight of the cooling fan or heat sink and the risk of failure.
実施の形態２．
　実施の形態２では、サブインバータ１２において同じ電圧を出力する、それぞれで各半導体スイッチング素子の導通損失が異なるスイッチングパターンが複数あり、スイッチングパターンを選択することで、半導体スイッチング素子の損失の均等化を図ることができる技術を説明する。 Embodiment 2.
In embodiment 2, a technology is described in which there are multiple switching patterns in which the sub-inverter 12 outputs the same voltage, each of which has a different conduction loss in each semiconductor switching element, and by selecting a switching pattern, it is possible to equalize the losses in the semiconductor switching elements.
　図１１は、サブインバータ１２のスイッチングパターンを示す。記号symbolは、「＋」「ゼロＵＰ」「ゼロＤＯＷＮ」「－」とする。「＋」はサブインバータ１２の出力電圧がプラスとなる状態、「ゼロＵＰ」は電流が半導体スイッチング素子Ｑ１３とＱ１５を通過してサブインバータ１２の出力電圧が０となる状態、「ゼロＤＯＷＮ」は電流が半導体スイッチング素子Ｑ１４とＱ１６を通過してサブインバータ１２の出力電圧が０となる状態、「－」はサブインバータ１２の出力電圧がマイナスとなる状態、を意味する。また、Vsubはサブインバータが出力する電圧を意味する。Vcapは中間コンデンサの電圧であり、サブインバータ１２は、半導体スイッチング素子のオン・オフの切替により、＋Vcapまたは－Vcapの電圧を出力（発生）する。図１１に示す「＋」から「ゼロＵＰ」に切り替える、電流Ｉ＞０（負荷に流れる方向を正とする）時の各半導体スイッチング素子Ｑ１３～Ｑ１６のオン・オフ状態の遷移であるスイッチングパターンを図１２に、回路図上の電流経路の遷移を図１３に示す。また、電流Ｉ＞０時の「＋」から「ゼロＤＯＷＮ」に切り替えるようにサブインバータを制御した場合のスイッチングパターンを図１４に、電流経路の遷移を図１５に示す。なお、図１２および図１４において、「ＯＦＦ（Ｄ導通）」は、ゲート駆動信号はオフであり、半導体スイッチング素子のダイオードを電流が流れる状態を示している。以降、同様である。 Figure 11 shows the switching pattern of the sub-inverter 12. The symbols are "+", "zero up", "zero down", and "-". "+" means that the output voltage of the sub-inverter 12 is positive, "zero up" means that the current passes through the semiconductor switching elements Q13 and Q15 and the output voltage of the sub-inverter 12 is zero, "zero down" means that the current passes through the semiconductor switching elements Q14 and Q16 and the output voltage of the sub-inverter 12 is zero, and "-" means that the output voltage of the sub-inverter 12 is negative. Additionally, Vsub means the voltage output by the sub-inverter. Vcap is the voltage of the intermediate capacitor, and the sub-inverter 12 outputs (generates) a voltage of +Vcap or -Vcap by switching the semiconductor switching elements on and off. FIG. 12 shows a switching pattern, which is the transition of the on/off state of each semiconductor switching element Q13 to Q16 when current I>0 (the direction flowing to the load is positive) switching from "+" shown in FIG. 11 to "zero up," and FIG. 13 shows the transition of the current path on the circuit diagram. FIG. 14 shows the switching pattern when the sub-inverter is controlled to switch from "+" to "zero down" when current I>0, and FIG. 15 shows the transition of the current path. Note that in FIG. 12 and FIG. 14, "OFF (D conduction)" indicates that the gate drive signal is off and current flows through the diode of the semiconductor switching element. This is the same below.
　切り替え時にはデッドタイムを設けている。デットタイムとは、上下アームの短絡を防止するために、オン・オフの切り替えタイミングにおいて、上下のスイッチが同時にオンならないように同時オフの状態にする期間のことである。電力変換装置を実機で動作させる場合デッドタイムを適用することは公知であるため詳しくは説明しない。 A dead time is provided during switching. Dead time is a period during which the upper and lower switches are not turned on at the same time when switching on and off, in order to prevent a short circuit between the upper and lower arms. It is well known that dead time is used when operating a power conversion device in real equipment, so it will not be explained in detail.
　図１２のスイッチングパターンでは、Ｑ１３およびＱ１５を導通させ、ゼロ電圧を生成する。このとき、Ｑ１３およびＱ１５は導通損失が発生する。図１４のスイッチングパターンでは、Ｑ１４およびＱ１６を導通させ、ゼロ電圧を生成する。このとき、Ｑ１４およびＱ１６は導通損失が発生する。 In the switching pattern of FIG. 12, Q13 and Q15 are made conductive, generating zero voltage. At this time, conduction loss occurs in Q13 and Q15. In the switching pattern of FIG. 14, Q14 and Q16 are made conductive, generating zero voltage. At this time, conduction loss occurs in Q14 and Q16.
　図１２のスイッチングパターンと図１４のスイッチングパターンとでは、図１３と図１５を参照すれば、どちらも出力する電圧は同じであることがわかる。すなわち、導通する半導体スイッチング素子の組み合わせ、すなわちスイッチングパターンを選択することができ、導通損失の分散が可能になる。例えば、半導体スイッチング素子のＱ１３～Ｑ１６のうちＱ１３の損失が高い場合に、Ｑ１３を導通させない図１４のスイッチングパターンを選択することでＱ１３の損失を抑えることができる。半導体スイッチング素子の損失は、図３に示すように素子直下に温度センサ１０２を配置し、温度から判断することができる。具体的には、温度により、各半導体スイッチング素子の損失を把握し、温度にばらつきがある場合、サブインバータ１２の出力電圧がゼロとなるときの半導体スイッチング素子の電流経路を変更して、温度が高い半導体スイッチング素子のオン時間を短くし、損失の偏りを減らす方向に制御する。温度を同等にすることは、損失の偏りがないということになる。なお、図３では、半導体スイッチング素子１個を１個のモジュールとした例を示したが、たとえば、Ｑ１３とＱ１４を１個のモジュール、Ｑ１５とＱ１６を１個のモジュールとし、それぞれのモジュールの各半導体スイッチング素子の直下に温度センサが配置される構造もとりえる。 With reference to Figs. 13 and 15, it can be seen that the switching pattern in Fig. 12 and the switching pattern in Fig. 14 both output the same voltage. In other words, the combination of semiconductor switching elements that are conductive, i.e., the switching pattern, can be selected, making it possible to distribute the conduction loss. For example, if the loss of Q13 is high among the semiconductor switching elements Q13 to Q16, the loss of Q13 can be suppressed by selecting the switching pattern in Fig. 14, which does not make Q13 conductive. The loss of the semiconductor switching element can be determined from the temperature by placing a temperature sensor 102 directly under the element as shown in Fig. 3. Specifically, the loss of each semiconductor switching element is grasped depending on the temperature, and if there is a variation in temperature, the current path of the semiconductor switching element when the output voltage of the sub-inverter 12 becomes zero is changed, the on time of the semiconductor switching element with a high temperature is shortened, and control is performed in a direction to reduce the bias in loss. Making the temperature equal means that there is no bias in loss. In addition, while Figure 3 shows an example in which one semiconductor switching element is one module, it is also possible to use a structure in which, for example, Q13 and Q14 are one module, and Q15 and Q16 are one module, with a temperature sensor located directly under each semiconductor switching element of each module.
　次に図１１に示す「－」から「ゼロＤＯＷＮ」に切り替える、電流Ｉ＞０（負荷に流れる方向を正とする）時のスイッチングパターンを図１６に、電流経路の遷移を図１７に示す。また、電流Ｉ＞０（負荷に流れる方向を正とする）時の「－」から「ゼロＵＰ」に切り替える場合のスイッチングパターンを図１８に、電流経路の遷移を図１９に示す。図１６のスイッチングパターンでは、Ｑ１４およびＱ１６を導通させ、ゼロ電圧を生成する。このとき、Ｑ１４およびＱ１６は導通損失が発生する。図１８のスイッチングパターンでは、Ｑ１３およびＱ１５を導通させ、ゼロ電圧を生成する。このとき、Ｑ１３およびＱ１５は導通損失が発生する。図１６と図１８のスイッチングパターンでは、図１７と図１９を参照すれば、どちらも出力する電圧は同じであることがわかる。 Next, the switching pattern when switching from "-" shown in FIG. 11 to "zero DOWN" when current I>0 (the direction flowing through the load is positive) is shown in FIG. 16, and the transition of the current path is shown in FIG. 17. Also, the switching pattern when switching from "-" to "zero UP" when current I>0 (the direction flowing through the load is positive) is shown in FIG. 18, and the transition of the current path is shown in FIG. 19. In the switching pattern of FIG. 16, Q14 and Q16 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q14 and Q16. In the switching pattern of FIG. 18, Q13 and Q15 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q13 and Q15. In the switching patterns of FIG. 16 and FIG. 18, referring to FIG. 17 and FIG. 19, it can be seen that the voltage output is the same in both cases.
　次に図１１に示す「＋」から「ゼロＵＰ」に切り替える、電流Ｉ＜０（負荷に流れる方向を正とする）時のスイッチングパターンを図２０に、電流経路の遷移を図２１に示す。また、電流Ｉ＜０（負荷に流れる方向を正とする）時の「＋」から「ゼロＤＯＷＮ」に切り替える場合のスイッチングパターンを図２２に、電流経路の遷移を図２３に示す。図２０のスイッチングパターンでは、Ｑ１３およびＱ１５を導通させ、ゼロ電圧を生成する。このとき、Ｑ１３およびＱ１５は導通損失が発生する。図２２のスイッチングパターンでは、Ｑ１４およびＱ１６を導通させ、ゼロ電圧を生成する。このとき、Ｑ１４およびＱ１６は導通損失が発生する。図２０と図２２のスイッチングパターンでは、図２１と図２３を参照すれば、どちらも出力する電圧は同じであることがわかる。 Next, FIG. 20 shows the switching pattern when switching from "+" shown in FIG. 11 to "zero UP" when current I<0 (the direction flowing through the load is positive), and FIG. 21 shows the transition of the current path. Also, FIG. 22 shows the switching pattern when switching from "+" to "zero DOWN" when current I<0 (the direction flowing through the load is positive), and FIG. 23 shows the transition of the current path. In the switching pattern of FIG. 20, Q13 and Q15 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q13 and Q15. In the switching pattern of FIG. 22, Q14 and Q16 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q14 and Q16. In the switching patterns of FIG. 20 and FIG. 22, referring to FIG. 21 and FIG. 23, it can be seen that the voltage output is the same in both cases.
　次に図１１に示す「－」から「ゼロＵＰ」に切り替える、電流Ｉ＜０（負荷に流れる方向を正とする）時のスイッチングパターンを図２４に、電流経路の遷移を図２５に示す。また、電流Ｉ＜０（負荷に流れる方向を正とする）時の「－」から「ゼロＤＯＷＮ」に切り替える場合のスイッチングパターンを図２６に、電流経路の遷移を図２７に示す。図２４のスイッチングパターンでは、Ｑ１３およびＱ１５を導通させ、ゼロ電圧を生成する。このとき、Ｑ１３およびＱ１５は導通損失が発生する。図２６のスイッチングパターンでは、Ｑ１４およびＱ１６を導通させ、ゼロ電圧を生成する。このとき、Ｑ１４およびＱ１６は導通損失が発生する。図２４と図２６のスイッチングパターンでは、図２５と図２７を参照すれば、どちらも出力する電圧は同じであることがわかる。 Next, the switching pattern when switching from "-" shown in FIG. 11 to "zero UP" when current I<0 (the direction flowing through the load is positive) is shown in FIG. 24, and the transition of the current path is shown in FIG. 25. Also, the switching pattern when switching from "-" to "zero DOWN" when current I<0 (the direction flowing through the load is positive) is shown in FIG. 26, and the transition of the current path is shown in FIG. 27. In the switching pattern of FIG. 24, Q13 and Q15 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q13 and Q15. In the switching pattern of FIG. 26, Q14 and Q16 are made conductive to generate zero voltage. At this time, conduction loss occurs in Q14 and Q16. In the switching patterns of FIG. 24 and FIG. 26, by referring to FIG. 25 and FIG. 27, it can be seen that the voltage output is the same in both cases.
　上記のように、サブインバータ１２においてゼロ電圧を発生させるときの半導体スイッチング素子のスイッチングパターンを選択することができ、Ｑ１３およびＱ１５、Ｑ１４およびＱ１６で導通時間を制御できる。 As described above, the switching pattern of the semiconductor switching elements when generating zero voltage in sub-inverter 12 can be selected, and the conduction time can be controlled by Q13 and Q15, and Q14 and Q16.
　図２８は、サブインバータ１２が、プラス電圧およびマイナス電圧を発生させる場合の、Ｑ１３およびＱ１６、Ｑ１４およびＱ１５の導通時間を制御するためのサブインバータのスイッチングパターンを示す。記号symbolの、「＋」はサブインバータ１２がプラス電圧を発生する場合、「－」はマイナス電圧を発生する場合とする。図２８に示す、「＋」、すなわちプラス電圧を発生させる場合のサブインバータ１２における電流経路を図２９Ａ、図２９Ｂに、電流Ｉ＜０（負荷に流れる方向を正とする）時にプラス電圧を発生させる場合の電流経路を図２９Ｃに示す。プラス電圧を生成するときは、Ｑ１４およびＱ１５を導通する。あるいは、電流Ｉ＜０時にＱ１３～１６の全てをオフすることでもプラス電圧を生成することができる。したがって、Ｑ１４およびＱ１５を導通してプラス電圧を発生しているときに、Ｑ１４およびＱ１５をオフしてプラス電圧を発生し続けることができるため、Ｑ１４およびＱ１５の導通時間を制御できる。あるいは、プラス電圧を発生するときの、スイッチングパターン、すなわち電流経路を選択することにより、平均的な導通時間を制御することができる。 FIG. 28 shows the switching pattern of the sub-inverter for controlling the conduction time of Q13 and Q16, Q14 and Q15 when the sub-inverter 12 generates a positive voltage and a negative voltage. The symbol "+" indicates that the sub-inverter 12 generates a positive voltage, and "-" indicates that the sub-inverter generates a negative voltage. The current path in the sub-inverter 12 when "+" shown in FIG. 28, i.e., when generating a positive voltage, is shown in FIG. 29A and FIG. 29B, and the current path when generating a positive voltage when current I<0 (the direction flowing to the load is positive) is shown in FIG. 29C. When generating a positive voltage, Q14 and Q15 are made conductive. Alternatively, a positive voltage can also be generated by turning off all of Q13 to Q16 when current I<0. Therefore, when Q14 and Q15 are made conductive to generate a positive voltage, Q14 and Q15 can be turned off to continue generating a positive voltage, so that the conduction time of Q14 and Q15 can be controlled. Alternatively, the average conduction time can be controlled by selecting the switching pattern, i.e., the current path, when generating a positive voltage.
　図２８より、「－」、すなわちマイナス電圧を発生する場合の電流経路を図３０Ａ、図３０Ｂ、電流Ｉ＞０（負荷に流れる方向を正とする）時にマイナス電圧を発生させる電流経路を図３０Ｃに示す。マイナス電圧を生成するときは、Ｑ１３およびＱ１６を導通する。あるいは、電流Ｉ＞０時にＱ１３～１６の全てをオフすることでもマイナス電圧を生成することができる。したがって、Ｑ１３およびＱ１６を導通してマイナス電圧を発生しているときに、Ｑ１３およびＱ１６をオフしてマイナス電圧を発生し続けることができるため、Ｑ１３およびＱ１６の導通時間を制御できる。あるいは、マイナス電圧を発生するときの、スイッチングパターン、すなわち電流経路を選択することにより、平均的な導通時間を制御することができる。 From Figure 28, the current paths for generating "-", i.e., a negative voltage, are shown in Figures 30A and 30B, while Figure 30C shows the current path for generating a negative voltage when current I>0 (the direction flowing through the load is positive). When generating a negative voltage, Q13 and Q16 are made conductive. Alternatively, a negative voltage can also be generated by turning off all of Q13 to 16 when current I>0. Therefore, when Q13 and Q16 are made conductive to generate a negative voltage, Q13 and Q16 can be turned off to continue generating a negative voltage, so the conductive time of Q13 and Q16 can be controlled. Alternatively, the average conductive time can be controlled by selecting the switching pattern, i.e., the current path, when generating a negative voltage.
　上記のように、Ｑ１３およびＱ１６、Ｑ１４およびＱ１５で導通時間を制御できる。これを利用して、各半導体スイッチング素子の温度にばらつきが検出された場合、ばらつきを検出するまでの出力電圧の発生パターンと同一の発生パターンにおいて、各半導体スイッチング素子の電流経路を変更して、温度が高い半導体スイッチング素子の導通時間を短くするよう制御することで、損失を分散することができる。 As described above, the conduction time can be controlled by Q13 and Q16, and Q14 and Q15. By using this, when a variation in temperature of each semiconductor switching element is detected, the current path of each semiconductor switching element can be changed in the same generation pattern of the output voltage as that before the variation was detected, and the conduction time of the semiconductor switching element with a higher temperature can be controlled to be shorter, thereby dispersing losses.
　以上のように、本実施の形態２によれば、本願に開示される電力変換装置において、サブインバータを構成する各半導体スイッチング素子の温度にばらつきがある場合、半導体損失を分散するように制御でき、局所的な損失の偏りを減少し、冷却ファンまたはヒートシンクの軽量化および故障のリスクを低減する。すなわち、重量を増加さえることなく、信頼性を向上させる電力変換装置を提供することができる。 As described above, according to the second embodiment, in the power conversion device disclosed in the present application, when there is variation in temperature among the semiconductor switching elements constituting the sub-inverter, the semiconductor loss can be controlled to be distributed, reducing the bias in localized loss and reducing the weight of the cooling fan or heat sink and the risk of failure. In other words, it is possible to provide a power conversion device that improves reliability without increasing weight.
実施の形態３．
　本実施の形態は、実施の形態１あるいは実施の形態２による電力変換装置を備えた飛行物体の実施の形態である。本実施の形態の飛行物体は、例えば航空機、ヘリコプター、ドローン、空飛ぶ自動車等である。 Embodiment 3.
This embodiment is an embodiment of a flying object including the power conversion device according to embodiment 1 or embodiment 2. The flying object of this embodiment is, for example, an airplane, a helicopter, a drone, a flying car, or the like.
　図３１は、実施の形態３による飛行物体１００の概略ブロック図である。飛行物体１００は、実施の形態１あるいは実施の形態２で説明した電力変換装置を備える。飛行物体１００は、その推進系電力システム６０として、電力源６３、電力源６３に接続された電源（ＤＣ電源）１、電源１に接続され所定の電圧に変換する降圧チョッパ回路を備えたＤＣ／ＤＣコンバータ５０、ＤＣ／ＤＣコンバータ５０で降圧された直流電力を交流電力に変換するインバータ３０、インバータ３０から電力が供給される負荷６１、及びＤＣ／ＤＣコンバータ５０、インバータ３０を制御する制御部６２を備える。ここで負荷６１は推進力を得るための推進系負荷であり、例えば電動モータである。 FIG. 31 is a schematic block diagram of a flying object 100 according to embodiment 3. The flying object 100 is equipped with the power conversion device described in embodiment 1 or embodiment 2. The flying object 100 is equipped with a propulsion power system 60 including a power source 63, a power source (DC power source) 1 connected to the power source 63, a DC/DC converter 50 connected to the power source 1 and equipped with a step-down chopper circuit for converting to a predetermined voltage, an inverter 30 that converts the DC power stepped down by the DC/DC converter 50 into AC power, a load 61 to which power is supplied from the inverter 30, and a control unit 62 that controls the DC/DC converter 50 and the inverter 30. Here, the load 61 is a propulsion load for obtaining propulsive force, such as an electric motor.
　実施の形態１あるいは実施の形態２による電力変換装置のインバータは、飛行物体１００に搭載されるインバータ３０として用いられる。航空機に代表される飛行物体のように上空を飛行するものに搭載する装置は、軽量化および信頼性が求められる。このため、実施の形態１あるいは実施の形態２で説明したサブインバータの損失が分散されたインバータ３０を備えた電力変換装置を推進系電力システム６０に搭載する。これにより、冷却ファンあるいは冷却ヒートシンクを軽量化し、重量及びコストの増加を抑制することができ、また、局所的に発熱することを抑制できて信頼性を向上できる。 The inverter of the power conversion device according to embodiment 1 or embodiment 2 is used as the inverter 30 mounted on the flying object 100. Devices mounted on flying objects such as aircraft that fly in the sky are required to be lightweight and reliable. For this reason, a power conversion device equipped with an inverter 30 in which the losses of the sub-inverters described in embodiment 1 or embodiment 2 are distributed is mounted on the propulsion power system 60. This makes it possible to reduce the weight of the cooling fan or cooling heat sink, suppressing increases in weight and cost, and also suppressing localized heat generation, improving reliability.
実施の形態４．
　本実施の形態は、実施の形態１あるいは実施の形態２による電力変換装置を備えた飛行物体の実施の形態である。本実施の形態の飛行物体は、例えば航空機、ヘリコプター、ドローン、空飛ぶ自動車等である。 Embodiment 4.
This embodiment is an embodiment of a flying object including the power conversion device according to embodiment 1 or embodiment 2. The flying object of this embodiment is, for example, an airplane, a helicopter, a drone, a flying car, or the like.
　図３２は、実施の形態４による飛行物体１００の概略ブロック図である。飛行物体１００は、実施の形態１あるいは実施の形態２で説明した電力変換装置を備える。飛行物体１００は、その装備品系電力システム７０として、電力源７４、電力源７４に接続され交流電力を直流電力に変換するＡＣ／ＤＣコンバータ７２、ＡＣ／ＤＣコンバータ７２に接続された直流源１、直流源１に接続され所定の電圧に変換する降圧チョッパ回路を備えたＤＣ／ＤＣコンバータ５０、ＤＣ／ＤＣコンバータ５０で降圧された直流電力を交流電力に変換するインバータ３０、インバータ３０から電力が供給される負荷７１、及びＤＣ／ＤＣコンバータ５０、インバータ３０、ＡＣ／ＤＣコンバータ７２を制御する制御部７３を備える。ここで負荷７１は装備品系負荷であり、例えば空調、エンジンスタータ、及び補助電力装置の駆動に用いる電動モータ等を指す。 FIG. 32 is a schematic block diagram of a flying object 100 according to embodiment 4. The flying object 100 is equipped with the power conversion device described in embodiment 1 or embodiment 2. The flying object 100 is equipped with, as its equipment power system 70, a power source 74, an AC/DC converter 72 connected to the power source 74 and converting AC power to DC power, a DC source 1 connected to the AC/DC converter 72, a DC/DC converter 50 connected to the DC source 1 and equipped with a step-down chopper circuit for converting to a predetermined voltage, an inverter 30 that converts the DC power stepped down by the DC/DC converter 50 into AC power, a load 71 to which power is supplied from the inverter 30, and a control unit 73 that controls the DC/DC converter 50, the inverter 30, and the AC/DC converter 72. Here, the load 71 is an equipment load, and refers to, for example, an electric motor used to drive an air conditioner, an engine starter, and an auxiliary power device.
　実施の形態３と同様に、実施の形態１あるいは実施の形態２による電力変換装置のインバータは、飛行物体１００に搭載される装備品系電力システム７０のインバータ３０として用いられる。航空機に代表される飛行物体のように上空を飛行するものに搭載する装置は、軽量化および信頼性が求められる。実施の形態１あるいは実施の形態２で説明した電力変換装置を、装備品系電力システム７０に搭載することで、実施の形態３と同様の効果を奏する。 As in embodiment 3, the inverter of the power conversion device according to embodiment 1 or embodiment 2 is used as inverter 30 of equipment power system 70 mounted on flying object 100. Lightweight and reliable devices are required for mounting on flying objects that fly in the sky, such as flying objects represented by aircraft. By mounting the power conversion device described in embodiment 1 or embodiment 2 on equipment power system 70, the same effects as embodiment 3 can be achieved.
　なお、図２に示した制御部１９は、具体的には、図３３に示すように、ＣＰＵ（Central Processing Unit）等の演算処理装置１９１、演算処理装置１９１とデータをやり取りする記憶装置１９２、演算処理装置１９１と外部の間で信号を入出力する入出力インターフェース１９３などを備えている。演算処理装置１９１としてＡＳＩＣ（Application Specific Integrated Circuit）、ＩＣ（Integrated Circuit）、ＤＳＰ（Digital Signal Processor）、ＦＰＧＡ（Field Programmable Gate Array）、および各種の信号処理回路等が備えられても良い。また、演算処理装置１９１として、同じ種類のもの、または異なる種類のものが複数備えられ、各処理が分担して実行されてもよい。記憶装置１９２として、演算処理装置１９１からデータを読み出しおよび書き込みが可能に構成されたＲＡＭ（Random Access Memory）、演算処理装置１９１からデータを読み出し可能に構成されたＲＯＭ（Read Only Memory）等が備えられている。入出力インターフェース１９３は、例えば、メインインバータ９およびサブインバータ１２に備えられた各電圧検知手段、電流センサ１０１、温度センサ１０２などから出力されるセンサ信号を演算処理装置１９１に入力するＡ／Ｄ変換器、各半導体スイッチング素子に駆動信号を出力するための駆動回路などから構成される。 The control unit 19 shown in FIG. 2 specifically includes, as shown in FIG. 33, an arithmetic processing device 191 such as a CPU (Central Processing Unit), a storage device 192 for exchanging data with the arithmetic processing device 191, and an input/output interface 193 for inputting and outputting signals between the arithmetic processing device 191 and the outside. The arithmetic processing device 191 may include an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and various signal processing circuits. In addition, multiple arithmetic processing devices 191 of the same type or different types may be provided, and each process may be shared and executed. The storage device 192 includes a RAM (Random Access Memory) configured to be able to read and write data from the arithmetic processing device 191, a ROM (Read Only Memory) configured to be able to read data from the arithmetic processing device 191, and the like. The input/output interface 193 is composed of, for example, each voltage detection means provided in the main inverter 9 and the sub-inverter 12, an A/D converter that inputs sensor signals output from the current sensor 101, the temperature sensor 102, etc., to the arithmetic processing device 191, a drive circuit for outputting drive signals to each semiconductor switching element, etc.
　本願には、様々な例示的な実施の形態及び実施例が記載されているが、１つ、または複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるのではなく、単独で、または様々な組み合わせで実施の形態に適用可能である。従って、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。例えば、少なくとも１つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも１つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。 Although various exemplary embodiments and examples are described in this application, the various features, aspects, and functions described in one or more of the embodiments are not limited to application in a particular embodiment, but may be applied to the embodiments alone or in various combinations. Thus, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases in which at least one component is modified, added, or omitted, and even cases in which at least one component is extracted and combined with components of other embodiments.
　１　直流源、４、６１、７１　負荷、９　メインインバータ、１０ｕ、１０ｖ、１０ｗ　中間コンデンサ、１２　サブインバータ、１９　制御部、１００　飛行物体、Ｑ１３　第一半導体スイッチング素子、Ｑ１４　第二半導体スイッチング素子、Ｑ１５　第三半導体スイッチング素子、Ｑ１６　第四半導体スイッチング素子 1 DC source, 4, 61, 71 Load, 9 Main inverter, 10u, 10v, 10w Intermediate capacitor, 12 Sub-inverter, 19 Control unit, 100 Flying object, Q13 First semiconductor switching element, Q14 Second semiconductor switching element, Q15 Third semiconductor switching element, Q16 Fourth semiconductor switching element

Claims (9)

  1. 　直流のプラス電位が印加されるプラス端子と、直流のマイナス電位が印加されるマイナス端子との間に中性点を有するコンデンサを備え、少なくとも、前記プラス端子の電位と前記マイナス端子の電位と、前記中性点の電位とを出力可能なメインインバータと、
    前記メインインバータの出力に接続され、複数の半導体スイッチング素子と中間コンデンサとを有し、前記中間コンデンサの電圧を前記メインインバータの出力電圧に加減するサブインバータと、
    　前記メインインバータおよび前記サブインバータを制御する制御部と、を備え、
    前記制御部は、前記サブインバータをＰＷＭ制御により制御し、前記サブインバータが出力する電圧を制御する電力変換装置において、
    前記制御部は、前記サブインバータの前記複数の半導体スイッチング素子の各半導体スイッチング素子の損失が均等になるよう制御する電力変換装置。     a main inverter including a capacitor having a neutral point between a positive terminal to which a DC positive potential is applied and a negative terminal to which a DC negative potential is applied, and capable of outputting at least a potential of the positive terminal, a potential of the negative terminal, and a potential of the neutral point;
    a sub-inverter connected to an output of the main inverter, the sub-inverter having a plurality of semiconductor switching elements and an intermediate capacitor, and adjusting a voltage of the intermediate capacitor to an output voltage of the main inverter;
    A control unit that controls the main inverter and the sub-inverter,
    In a power conversion device, the control unit controls the sub-inverter by PWM control to control a voltage output by the sub-inverter,
    The control unit is a power conversion device that controls the plurality of semiconductor switching elements of the sub-inverter so that losses in the respective semiconductor switching elements are equalized.
  2. 　前記サブインバータは、直列に接続された第一半導体スイッチング素子と第二半導体スイッチング素子と、直列に接続された第三半導体スイッチング素子と第四半導体スイッチング素子と、前記中間コンデンサとが並列に接続され、前記第一半導体スイッチング素子と前記第二半導体スイッチング素子の接続点が、前記メインインバータの出力点に接続され、前記第三半導体スイッチング素子と前記第四半導体スイッチング素子の接続点を出力とする請求項１に記載の電力変換装置。 The power conversion device according to claim 1, wherein the sub-inverter is configured such that a first semiconductor switching element and a second semiconductor switching element are connected in series, a third semiconductor switching element and a fourth semiconductor switching element are connected in series, and the intermediate capacitor is connected in parallel, the connection point between the first semiconductor switching element and the second semiconductor switching element is connected to the output point of the main inverter, and the connection point between the third semiconductor switching element and the fourth semiconductor switching element is used as an output.
  3. 　前記制御部は、前記ＰＷＭ制御において、前記サブインバータの前記複数の半導体スイッチング素子の各半導体スイッチング素子の導通時間が均等になるよう、前記複数の半導体スイッチング素子を制御する請求項１または２に記載の電力変換装置。 The power conversion device according to claim 1 or 2, wherein the control unit controls the plurality of semiconductor switching elements of the sub-inverter in the PWM control so that the conduction times of each of the plurality of semiconductor switching elements are uniform.
  4. 　前記ＰＷＭ制御は、位相シフトされた複数のキャリア波を用いたＰＷＭ制御である請求項１から３のいずれか１項に記載の電力変換装置。 The power conversion device according to any one of claims 1 to 3, wherein the PWM control is PWM control using multiple phase-shifted carrier waves.
  5. 　前記制御部は、前記ＰＷＭ制御において、前記サブインバータの前記複数の半導体スイッチング素子の温度が均等になるよう前記複数の半導体スイッチング素子を制御する請求項１に記載の電力変換装置。 The power conversion device according to claim 1, wherein the control unit controls the plurality of semiconductor switching elements of the sub-inverter in the PWM control so that the temperatures of the plurality of semiconductor switching elements are uniform.
  6. 　前記サブインバータは、前記複数の半導体スイッチング素子として、直列に接続された第一半導体スイッチング素子と第二半導体スイッチング素子と、直列に接続された第三半導体スイッチング素子と第四半導体スイッチング素子とを備え、直列に接続された前記第一半導体スイッチング素子と前記第二半導体スイッチング素子と、直列に接続された前記第三半導体スイッチング素子と前記第四半導体スイッチング素子と、前記中間コンデンサとが並列に接続され、前記第一半導体スイッチング素子と前記第二半導体スイッチング素子の接続点が、前記メインインバータの出力点に接続され、前記第三半導体スイッチング素子と前記第四半導体スイッチング素子の接続点を出力とする請求項５に記載の電力変換装置。 The sub-inverter includes, as the plurality of semiconductor switching elements, a first semiconductor switching element and a second semiconductor switching element connected in series, and a third semiconductor switching element and a fourth semiconductor switching element connected in series, the first semiconductor switching element and the second semiconductor switching element connected in series, the third semiconductor switching element and the fourth semiconductor switching element connected in series, and the intermediate capacitor are connected in parallel, the connection point between the first semiconductor switching element and the second semiconductor switching element is connected to the output point of the main inverter, and the connection point between the third semiconductor switching element and the fourth semiconductor switching element is the output. The power conversion device according to claim 5.
  7. 　前記制御部は、前記サブインバータの前記複数の半導体スイッチング素子の各半導体スイッチング素子について、温度にばらつきが検出された場合、前記ＰＷＭ制御において、温度のばらつきを検出するまでの前記サブインバータの出力電圧の発生パターンと同一の発生パターンにおいて、前記各半導体スイッチング素子の電流経路を変更する請求項５または６に記載の電力変換装置。 The power conversion device according to claim 5 or 6, wherein when a temperature variation is detected for each of the semiconductor switching elements of the plurality of semiconductor switching elements of the sub-inverter, the control unit changes the current path of each of the semiconductor switching elements in the PWM control in the same generation pattern as the generation pattern of the output voltage of the sub-inverter until the temperature variation is detected.
  8. 　前記制御部は、前記サブインバータの前記複数の半導体スイッチング素子の各半導体スイッチング素子について、温度にばらつきが検出された場合、前記ＰＷＭ制御において、前記サブインバータの出力電圧がゼロとなるときの前記各半導体スイッチング素子の電流経路を変更する請求項５または６に記載の電力変換装置。 The power conversion device according to claim 5 or 6, wherein when a temperature variation is detected for each of the semiconductor switching elements of the plurality of semiconductor switching elements of the sub-inverter, the control unit changes the current path of each of the semiconductor switching elements when the output voltage of the sub-inverter becomes zero in the PWM control.
  9. 　直流源と、この直流源の電力を用いる負荷と、前記直流源の電力を変換して前記負荷に電力を供給する電力変換装置である、請求項１から８のいずれか１項に記載の電力変換装置とを備えた飛行物体。 A flying object comprising a DC source, a load that uses the power of the DC source, and a power conversion device according to any one of claims 1 to 8 that converts the power of the DC source and supplies the power to the load.
PCT/JP2022/042815 2022-11-18 2022-11-18 Power conversion device and flying object WO2024105872A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010146637A1 (en) * 2009-06-19 2010-12-23 三菱電機株式会社 Power conversion equipment
JP2012147559A (en) * 2011-01-12 2012-08-02 Toshiba Corp Semiconductor power converter
WO2022054155A1 (en) * 2020-09-09 2022-03-17 三菱電機株式会社 Power converter and aircraft equipped with power converter
WO2022180709A1 (en) * 2021-02-25 2022-09-01 三菱電機株式会社 Power conversion device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010146637A1 (en) * 2009-06-19 2010-12-23 三菱電機株式会社 Power conversion equipment
JP2012147559A (en) * 2011-01-12 2012-08-02 Toshiba Corp Semiconductor power converter
WO2022054155A1 (en) * 2020-09-09 2022-03-17 三菱電機株式会社 Power converter and aircraft equipped with power converter
WO2022180709A1 (en) * 2021-02-25 2022-09-01 三菱電機株式会社 Power conversion device

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