WO2024103542A1

WO2024103542A1 - Display panel

Info

Publication number: WO2024103542A1
Application number: PCT/CN2023/075403
Authority: WO
Inventors: 刘大超; 曾勉; 孙亮
Original assignee: 武汉华星光电半导体显示技术有限公司
Priority date: 2022-11-15
Filing date: 2023-02-10
Publication date: 2024-05-23
Also published as: CN115734676A

Abstract

Provided in the present application is a display panel. A subpixel comprises a connection transistor, which is electrically connected to a gate of a driving transistor and has a first electrical connection portion; two adjacent subpixels which are located in the same row are arranged in a mirrored manner; first electrical connection portions of a plurality of adjacent subpixels which are located in the same row are alternately arranged at a first distance and a second distance; two adjacent overlapping portions of each variable signal line are spaced apart by two subpixels; and each overlapping portion at least partially overlaps first electrical connection portions of two subpixels that are arranged at the first distance.

Description

显示面板Display Panel

技术领域Technical Field

本申请涉及显示技术领域，特别涉及一种显示面板。The present application relates to the field of display technology, and in particular to a display panel.

背景技术Background technique

将低温多晶硅晶体管技术及氧化物晶体管技术结合制得的LTPO（Low Temperature Polycrystalline Oxide，低温多晶氧化物）背板，虽然可用于改善显示面板的低频闪烁问题，但LTPO背板的结构和制备工艺较复杂，制备成本也较高。The LTPO (Low Temperature Polycrystalline Oxide) backplane, which is made by combining low-temperature polysilicon transistor technology and oxide transistor technology, can be used to improve the low-frequency flicker problem of display panels. However, the structure and preparation process of the LTPO backplane are relatively complex, and the preparation cost is also relatively high.

技术问题technical problem

本申请实施例提供一种显示面板，可以实现改善显示面板低频闪烁问题的方案。The embodiment of the present application provides a display panel, which can realize a solution to improve the low-frequency flicker problem of the display panel.

技术解决方案Technical Solutions

本申请实施例提供一种显示面板，包括多个子像素以及多条可变信号线。每一子像素包括发光器件及像素驱动电路，像素驱动电路包括驱动晶体管及连接晶体管，驱动晶体管与发光器件串联于第一电源线和第二电源线之间，连接晶体管电性连接于驱动晶体管的栅极。多条可变信号线被配置为传输可变信号，每一可变信号线包括多个重叠部。其中，连接晶体管包括第一有源层。第一有源层包括第一沟道部、第二沟道部及连接于第一沟道部和第二沟道部之间的第一电连接部。位于同行且相邻的两子像素镜像设置，位于同行且相邻的多个子像素的第一电连接部交替以第一间距和第二间距排布，第一间距小于第二间距；每一可变信号线的相邻的两重叠部之间间隔两子像素，且每一重叠部与两子像素的以第一间距排布的第一电连接部至少部分重叠形成两电容。The embodiment of the present application provides a display panel, including a plurality of sub-pixels and a plurality of variable signal lines. Each sub-pixel includes a light-emitting device and a pixel driving circuit, the pixel driving circuit includes a driving transistor and a connecting transistor, the driving transistor and the light-emitting device are connected in series between a first power line and a second power line, and the connecting transistor is electrically connected to the gate of the driving transistor. The plurality of variable signal lines are configured to transmit variable signals, and each variable signal line includes a plurality of overlapping portions. Among them, the connecting transistor includes a first active layer. The first active layer includes a first channel portion, a second channel portion, and a first electrical connection portion connected between the first channel portion and the second channel portion. Two sub-pixels located in the same row and adjacent to each other are mirror-set, and the first electrical connection portions of the plurality of sub-pixels located in the same row and adjacent to each other are alternately arranged at a first spacing and a second spacing, and the first spacing is smaller than the second spacing; two adjacent overlapping portions of each variable signal line are spaced by two sub-pixels, and each overlapping portion at least partially overlaps with the first electrical connection portions of the two sub-pixels arranged at the first spacing to form two capacitors.

有益效果Beneficial Effects

相较于现有技术，本申请提供一种显示面板，通过使子像素包括与驱动晶体管的栅极电性连接的连接晶体管，连接晶体管包括第一沟道部、第二沟道部及连接于第一沟道部和第二沟道部之间的第一电连接部；位于同行且相邻的两子像素镜像设置，位于同行且相邻的多个子像素的第一电连接部交替以第一间距和第二间距排布，每一可变信号线的相邻的两重叠部之间间隔两子像素，且每一重叠部与两子像素的以第一间距排布的第一电连接部至少部分重叠形成两电容，以在节省布局空间的同时，通过可变信号线传输的可变信号及电容实现改善低频闪烁问题的方案。Compared with the prior art, the present application provides a display panel, in which a sub-pixel includes a connecting transistor electrically connected to the gate of a driving transistor, the connecting transistor includes a first channel portion, a second channel portion and a first electrical connection portion connected between the first channel portion and the second channel portion; two sub-pixels located in the same row and adjacent to each other are mirror-arranged, the first electrical connection portions of a plurality of sub-pixels located in the same row and adjacent to each other are alternately arranged at a first pitch and a second pitch, two sub-pixels are spaced between two adjacent overlapping portions of each variable signal line, and each overlapping portion at least partially overlaps with the first electrical connection portions of the two sub-pixels arranged at the first pitch to form two capacitors, so as to save layout space while realizing a solution to improve the low-frequency flicker problem through variable signals and capacitors transmitted by variable signal lines.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

图1A~图1B是本申请实施例提供的子像素的结构示意图；
图2是本申请实施例提供的时序图；
图3是本申请实施例提供的显示亮度变化示意图；
图4A~图4B是本申请实施例提供的子像素的膜层结构示意图；
图5A~图5B是可变信号线与第一电连接部重叠的局部放大图；
图5C是沿图5A或图5B中的p-p’剖切的剖视图；
图5D是沿图5A或图5B中的z-z’剖切的剖视图；
图6A~图6B是本申请实施例提供的有源层的结构示意图；
图7A~图7B是本申请实施例提供的第一导电层的结构示意图；
图8A~图8B是本申请实施例提供的第二导电层的结构示意图；
图9A~图9B是本申请实施例提供的第三导电层的结构示意图；
图10是本申请实施例提供的第四导电层的结构示意图。 1A and 1B are schematic diagrams of the structure of sub-pixels provided in an embodiment of the present application;
FIG2 is a timing diagram provided by an embodiment of the present application;
FIG3 is a schematic diagram of display brightness change provided by an embodiment of the present application;
4A and 4B are schematic diagrams of the film layer structure of a sub-pixel provided in an embodiment of the present application;
5A and 5B are partial enlarged views of the variable signal line overlapping the first electrical connection portion;
FIG5C is a cross-sectional view taken along the line p-p' in FIG5A or FIG5B;
FIG5D is a cross-sectional view taken along line z-z' in FIG5A or FIG5B;
6A-6B are schematic diagrams of the structure of an active layer provided in an embodiment of the present application;
7A-7B are schematic structural diagrams of a first conductive layer provided in an embodiment of the present application;
8A-8B are schematic diagrams of the structure of the second conductive layer provided in an embodiment of the present application;
9A-9B are schematic diagrams of the structure of the third conductive layer provided in an embodiment of the present application;
FIG. 10 is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present application.

本发明的实施方式Embodiments of the present invention

为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。In order to make the purpose, technical solution and effect of the present application clearer and more specific, the present application is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described here are only used to explain the present application and are not used to limit the present application.

具体地，如图1A~图1B是本申请实施例提供的子像素的结构示意图。本申请提供一种显示面板，包括多条信号线及多个子像素Px。Specifically, Fig. 1A to Fig. 1B are schematic diagrams of the structure of a sub-pixel provided in an embodiment of the present application. The present application provides a display panel, including a plurality of signal lines and a plurality of sub-pixels Px.

多条信号线包括多条扫描线，多条数据线DL、多条发光控制线EML、多条复位线和至少一条可变信号线EML1。The plurality of signal lines include a plurality of scan lines, a plurality of data lines DL, a plurality of emission control lines EML, a plurality of reset lines and at least one variable signal line EML1.

多条扫描线包括多条第一扫描线和多条第二扫描线。第一扫描线用于传输第一扫描信号S1，多条第一扫描线包括多条第一子扫描线SL11和多条第二子扫描线SL12。第一子扫描线SL11传输的第一扫描信号的有效脉冲作用时间先于第二子扫描线SL12传输的第一扫描信号的有效脉冲作用时间。第二扫描线用于传输第二扫描信号S2，多条第二扫描线SL2包括多条第三子扫描线SL21和多条第四子扫描线SL22。可选地，第一扫描信号S1的频率小于第二扫描信号S2的频率。可选地，第一扫描信号S1的有效脉冲位于一显示周期的写入帧内，第二扫描信号S2的有效脉冲位于一显示周期的写入帧和保持帧内。其中，在一显示周期包括保持帧时，即为显示面板采用了低刷新频率的驱动方式。The plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines. The first scan line is used to transmit a first scan signal S1, and the plurality of first scan lines include a plurality of first sub-scan lines SL11 and a plurality of second sub-scan lines SL12. The effective pulse action time of the first scan signal transmitted by the first sub-scan line SL11 precedes the effective pulse action time of the first scan signal transmitted by the second sub-scan line SL12. The second scan line is used to transmit a second scan signal S2, and the plurality of second scan lines SL2 include a plurality of third sub-scan lines SL21 and a plurality of fourth sub-scan lines SL22. Optionally, the frequency of the first scan signal S1 is less than the frequency of the second scan signal S2. Optionally, the effective pulse of the first scan signal S1 is located within a write frame of a display cycle, and the effective pulse of the second scan signal S2 is located within a write frame and a hold frame of a display cycle. Wherein, when a display cycle includes a hold frame, the display panel adopts a low refresh frequency driving mode.

可选地，显示面板还包括多个级联的第一选通驱动电路、多个级联的第二选通驱动电路及多个级联的第三选通驱动电路，以分别向多条第一扫描线提供多个第一扫描信号S1、多条第二扫描线提供多个第二扫描信号S2以及向多条发光控制线EML提供发光控制信号。可选地，显示面板还包括多个级联的第四选通驱动电路，以向可变信号线EML1提供可变信号。可选地，可变信号线EML1也可与驱动芯片电性连接，以通过驱动芯片提供可变信号。Optionally, the display panel further includes a plurality of cascaded first gate drive circuits, a plurality of cascaded second gate drive circuits, and a plurality of cascaded third gate drive circuits to respectively provide a plurality of first scan signals S1 to a plurality of first scan lines, a plurality of second scan signals S2 to a plurality of second scan lines, and a plurality of light-emitting control lines EML with light-emitting control signals. Optionally, the display panel further includes a plurality of cascaded fourth gate drive circuits to provide a variable signal to the variable signal line EML1. Optionally, the variable signal line EML1 may also be electrically connected to a driver chip to provide a variable signal through the driver chip.

请继续参阅图1A~图1B，每一子像素Px包括发光器件D及像素驱动电路。可选地，发光器件D包括有机发光二极管、次毫米发光二极管、微型发光二极管等。像素驱动电路包括驱动晶体管T1、连接晶体管及电容Co。1A to 1B, each sub-pixel Px includes a light emitting device D and a pixel driving circuit. Optionally, the light emitting device D includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc. The pixel driving circuit includes a driving transistor T1, a connecting transistor and a capacitor Co.

驱动晶体管T1的源极和漏极与发光器件D串联在第一电源线VDD和第二电源线VSS之间，驱动晶体管T1用于根据传输至驱动晶体管T1的栅极的数据信号，生成驱动发光器件D发光的驱动电流。其中，写入帧包括数据信号被传输至驱动晶体管T1的栅极的阶段，保持帧则不包括数据信号被传输至驱动晶体管T1的栅极的阶段。The source and drain of the driving transistor T1 are connected in series with the light emitting device D between the first power line VDD and the second power line VSS, and the driving transistor T1 is used to generate a driving current for driving the light emitting device D to emit light according to the data signal transmitted to the gate of the driving transistor T1. The writing frame includes the stage in which the data signal is transmitted to the gate of the driving transistor T1, and the holding frame does not include the stage in which the data signal is transmitted to the gate of the driving transistor T1.

连接晶体管电性连接于驱动晶体管T1的栅极。可选地，根据连接晶体管的用途的不同，连接晶体管中的源极和漏极连接的位置也会不同。如连接晶体管用于对驱动晶体管T1的栅极电位进行复位，则连接晶体管的源极和漏极电性连接于驱动晶体管T1的栅极和第一复位线VL1之间。若连接晶体管用于检测和补偿驱动晶体管T1的阈值电压，则连接晶体管的源极和漏极电性连接于驱动晶体管T1的栅极和驱动晶体管T1的源极和漏极中的一个之间。The connecting transistor is electrically connected to the gate of the driving transistor T1. Optionally, depending on the purpose of the connecting transistor, the position where the source and drain in the connecting transistor are connected will also be different. If the connecting transistor is used to reset the gate potential of the driving transistor T1, the source and drain of the connecting transistor are electrically connected between the gate of the driving transistor T1 and the first reset line VL1. If the connecting transistor is used to detect and compensate for the threshold voltage of the driving transistor T1, the source and drain of the connecting transistor are electrically connected between the gate of the driving transistor T1 and one of the source and drain of the driving transistor T1.

可选地，连接晶体管包括串联的第一子晶体管TL1和第二子晶体管TL2，第一子晶体管TL1和第二子晶体管TL2具有第一连接节点A。第一子晶体管TL1的源极和漏极中的一个与驱动晶体管T1的栅极电性连接，第一子晶体管TL1的源极和漏极中的另一个通过第一连接节点A电性连接于第二子晶体管TL2的源极和漏极中的一个，第一子晶体管TL1的栅极和第二子晶体管TL2的栅极均电性连接于第一扫描线。若连接晶体管用于对驱动晶体管T1的栅极电位进行复位，则第二子晶体管TL2的源极和漏极中的另一个与第一复位线VL1电性连接，第一子晶体管TL1的栅极和第二子晶体管TL2的栅极与第一子扫描线SL11电性连接，如图1A所示。若连接晶体管用于检测和补偿驱动晶体管T1的阈值电压，则第二子晶体管TL2的源极和漏极中的另一个与驱动晶体管T1的源极和漏极中的一个电性连接，第一子晶体管TL1的栅极和第二子晶体管TL2的栅极与第二子扫描线SL12电性连接，如图1B所示。Optionally, the connecting transistor includes a first sub-transistor TL1 and a second sub-transistor TL2 connected in series, and the first sub-transistor TL1 and the second sub-transistor TL2 have a first connection node A. One of the source and the drain of the first sub-transistor TL1 is electrically connected to the gate of the driving transistor T1, and the other of the source and the drain of the first sub-transistor TL1 is electrically connected to one of the source and the drain of the second sub-transistor TL2 through the first connection node A, and the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are both electrically connected to the first scan line. If the connecting transistor is used to reset the gate potential of the driving transistor T1, the other of the source and the drain of the second sub-transistor TL2 is electrically connected to the first reset line VL1, and the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are electrically connected to the first sub-scan line SL11, as shown in FIG1A. If the connection transistor is used to detect and compensate the threshold voltage of the driving transistor T1, the other of the source and the drain of the second sub-transistor TL2 is electrically connected to one of the source and the drain of the driving transistor T1, and the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are electrically connected to the second sub-scan line SL12, as shown in Figure 1B.

电容Co串联于可变信号线EML1和第一连接节点A之间，用于根据可变信号线EML1传输的可变信号EM1耦合连接节点A的电位，以改变连接节点A和驱动晶体管T1的栅极电位之差。The capacitor Co is connected in series between the variable signal line EML1 and the first connection node A, and is used to couple the potential of the connection node A according to the variable signal EM1 transmitted by the variable signal line EML1 to change the difference between the connection node A and the gate potential of the driving transistor T1.

请继续参阅图1A~图1B，像素驱动电路还包括数据晶体管T2、发光晶体管、初始晶体管T5及存储电容Cst。Please continue to refer to FIG. 1A to FIG. 1B , the pixel driving circuit further includes a data transistor T2 , a light emitting transistor, an initial transistor T5 and a storage capacitor Cst.

数据晶体管T2的源极和漏极电性连接于驱动晶体管T1的源极和漏极中的另一个和数据线DL之间，数据晶体管T2的栅极电性连接于第三子扫描线SL21。数据晶体管T2用于根据对应的第三子扫描线SL21传输的第二扫描信号S2而将数据线DL传输的数据信号传输至驱动晶体管T1的栅极，以使驱动晶体管T1的栅极具有第一电位。The source and drain of the data transistor T2 are electrically connected between the other of the source and drain of the driving transistor T1 and the data line DL, and the gate of the data transistor T2 is electrically connected to the third sub-scan line SL21. The data transistor T2 is used to transmit the data signal transmitted by the data line DL to the gate of the driving transistor T1 according to the second scan signal S2 transmitted by the corresponding third sub-scan line SL21, so that the gate of the driving transistor T1 has a first potential.

在驱动晶体管T1驱动发光器件D发光的发光阶段内，可变信号EM1至少具有一次由第二电位V2至第三电位V3的跳变。其中，第一电位介于第二电位V2和第三电位V3之间。In the light emitting phase when the driving transistor T1 drives the light emitting device D to emit light, the variable signal EM1 has at least one jump from the second potential V2 to the third potential V3, wherein the first potential is between the second potential V2 and the third potential V3.

发光晶体管与驱动晶体管T1及发光器件D串联于第一电源线VDD和第二电源线VSS之间。可选地，发光晶体管包括第一开关晶体管T3和第二开关晶体管T4。第一开关晶体管T3的源极和漏极电性连接于驱动晶体管T1的源极和漏极中的另一个和第一电源线VDD之间，第二开关晶体管T4的源极和漏极电性连接于驱动晶体管T1的源极和漏极中的一个和第二连接节点B之间，第一开关晶体管T3的栅极和第二开关晶体管T4的栅极均电性连接于发光控制线EML。发光晶体管用于根据发光控制线EML传输的发光控制信号EM使驱动晶体管T1驱动发光器件D发光。可选地，位于同行的多个子像素的发光晶体管的栅极与同一发光控制线EML电性连接。The light emitting transistor is connected in series with the driving transistor T1 and the light emitting device D between the first power line VDD and the second power line VSS. Optionally, the light emitting transistor includes a first switch transistor T3 and a second switch transistor T4. The source and drain of the first switch transistor T3 are electrically connected between the other of the source and drain of the driving transistor T1 and the first power line VDD, the source and drain of the second switch transistor T4 are electrically connected between one of the source and drain of the driving transistor T1 and the second connection node B, and the gate of the first switch transistor T3 and the gate of the second switch transistor T4 are both electrically connected to the light emitting control line EML. The light emitting transistor is used to make the driving transistor T1 drive the light emitting device D to emit light according to the light emitting control signal EM transmitted by the light emitting control line EML. Optionally, the gates of the light emitting transistors of multiple sub-pixels in the same row are electrically connected to the same light emitting control line EML.

初始晶体管T5的源极和漏极电性连接于第二复位线VL2和第二连接节点B之间，初始晶体管T5的栅极电性连接于第四子扫描线SL22。初始晶体管T5用于根据第二复位线VL2传输的第二复位信号对第二连接节点B处的电位进行复位。其中，发光器件D串联于第二连接节点B和第二电源线VSS之间。The source and drain of the initial transistor T5 are electrically connected between the second reset line VL2 and the second connection node B, and the gate of the initial transistor T5 is electrically connected to the fourth sub-scan line SL22. The initial transistor T5 is used to reset the potential at the second connection node B according to the second reset signal transmitted by the second reset line VL2. The light emitting device D is connected in series between the second connection node B and the second power line VSS.

存储电容Cst串联于第一电源线VDD和驱动晶体管T1的栅极之间，用于维持驱动晶体管T1的栅极电位。The storage capacitor Cst is connected in series between the first power line VDD and the gate of the driving transistor T1 to maintain the gate potential of the driving transistor T1.

请继续参阅图1A，像素驱动电路还包括补偿晶体管，补偿晶体管的源极和漏极电性连接驱动晶体管T1的栅极和驱动晶体管T1的源极和漏极中的一个之间，补偿晶体管的栅极电性连接于第二子扫描线SL12，补偿晶体管用于根据第二子扫描线SL12传输的第一扫描信号检测和补偿驱动晶体管T1的阈值电压。可选地，补偿晶体管可包括串联的第一子补偿晶体管Tc1和第二子补偿晶体管Tc2。可选地，补偿晶体管可包括硅半导体材料或氧化物半导体。Please continue to refer to FIG. 1A , the pixel driving circuit further includes a compensation transistor, the source and drain of the compensation transistor are electrically connected between the gate of the driving transistor T1 and one of the source and drain of the driving transistor T1, the gate of the compensation transistor is electrically connected to the second sub-scan line SL12, and the compensation transistor is used to detect and compensate the threshold voltage of the driving transistor T1 according to the first scan signal transmitted by the second sub-scan line SL12. Optionally, the compensation transistor may include a first sub-compensation transistor Tc1 and a second sub-compensation transistor Tc2 connected in series. Optionally, the compensation transistor may include a silicon semiconductor material or an oxide semiconductor.

请继续参阅图1B，像素驱动电路还包括复位晶体管，复位晶体管的源极和漏极电性连接驱动晶体管T1的栅极和第一复位线VL1之间，复位晶体管的栅极电性连接于第一子扫描线SL11，复位晶体管用于根据第一子扫描线SL11传输的第一扫描信号对驱动晶体管T1的栅极电位进行复位。可选地，复位晶体管可包括串联的第一子复位晶体管Ti1和第二子复位晶体管Ti2。可选地，复位晶体管可包括硅半导体材料或氧化物半导体。Please continue to refer to FIG. 1B , the pixel driving circuit further includes a reset transistor, the source and drain of the reset transistor are electrically connected between the gate of the driving transistor T1 and the first reset line VL1, the gate of the reset transistor is electrically connected to the first sub-scan line SL11, and the reset transistor is used to reset the gate potential of the driving transistor T1 according to the first scan signal transmitted by the first sub-scan line SL11. Optionally, the reset transistor may include a first sub-reset transistor Ti1 and a second sub-reset transistor Ti2 connected in series. Optionally, the reset transistor may include a silicon semiconductor material or an oxide semiconductor.

可选地，各晶体管包括硅半导体或氧化物半导体。其中，硅半导体材料包括多晶硅、单晶硅等；氧化物半导体材料包括铟镓锌氧化物、铟镓锡氧化物或者铟镓锌锡氧化物等。Optionally, each transistor includes a silicon semiconductor or an oxide semiconductor, wherein the silicon semiconductor material includes polycrystalline silicon, single crystal silicon, etc., and the oxide semiconductor material includes indium gallium zinc oxide, indium gallium tin oxide, or indium gallium zinc tin oxide, etc.

如图2是本申请实施例提供的时序图，以子像素包括的各晶体管为P型晶体管，像素驱动电路驱动第n行的发光器件D发光为例，对如图1A所示的子像素的工作原理进行说明。其中，n大于或等于1；驱动第n行的发光器件D时，第一子晶体管TL1的栅极和第二子晶体管TL2的栅极电性连接的第一子扫描线SL11传输第n-1级的第一扫描信号S1(n-1)；第一子补偿晶体管Tc1的栅极和第二子补偿晶体管Tc2的栅极电性连接的第二子扫描线SL12传输第n级的第一扫描信号S1(n)；数据晶体管T2的栅极电性连接的第三子扫描线SL21传输第n级的第二扫描信号S2(n)，第一开关晶体管T3的栅极和第二开关晶体管T4的栅极电性连接的发光控制线EML传输第n级的发光控制信号EM(n)；初始晶体管T5的栅极电性连接的第四子扫描线SL22传输第n+1级的第二扫描信号S2(n+1)。As shown in FIG2 , a timing diagram provided by an embodiment of the present application, the working principle of the sub-pixel shown in FIG1A is described by taking the case that each transistor included in the sub-pixel is a P-type transistor and the pixel driving circuit drives the light-emitting device D of the nth row to emit light as an example. Where n is greater than or equal to 1; when driving the light-emitting device D of the nth row, the first sub-scanning line SL11 to which the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are electrically connected transmits the first scanning signal S1(n-1) of the n-1th level; the second sub-scanning line SL12 to which the gate of the first sub-compensation transistor Tc1 and the gate of the second sub-compensation transistor Tc2 are electrically connected transmits the first scanning signal S1(n) of the nth level; the third sub-scanning line SL21 to which the gate of the data transistor T2 is electrically connected transmits the second scanning signal S2(n) of the nth level, the light-emitting control line EML to which the gate of the first switch transistor T3 and the gate of the second switch transistor T4 are electrically connected transmits the light-emitting control signal EM(n) of the nth level; the fourth sub-scanning line SL22 to which the gate of the initial transistor T5 is electrically connected transmits the second scanning signal S2(n+1) of the n+1th level.

在栅极复位阶段t1，第一子扫描线SL11传输的第一扫描信号S1(n-1)有效，第一子晶体管TL1、第二子晶体管TL2导通，第一复位线VL1传输的第一复位信号经第二子晶体管TL2和第一子晶体管TL1传输至驱动晶体管T1的栅极，以对驱动晶体管T1的栅极电位进行复位。In the gate reset stage t1, the first scan signal S1(n-1) transmitted by the first sub-scan line SL11 is valid, the first sub-transistor TL1 and the second sub-transistor TL2 are turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the gate of the driving transistor T1 through the second sub-transistor TL2 and the first sub-transistor TL1 to reset the gate potential of the driving transistor T1.

在数据写入阶段t2，第二子扫描线SL12传输的第一扫描信号S1(n)及第三子扫描线SL21传输的第二扫描信号S2(n)有效，第一子补偿晶体管Tc1、第二子补偿晶体管Tc2及数据晶体管T2导通，数据线DL传输的数据信号经数据晶体管T2、第二子补偿晶体管Tc2及第一子补偿晶体管Tc1传输至驱动晶体管T1的栅极，以使驱动晶体管T1的栅极具有第一电位。In the data writing stage t2, the first scanning signal S1(n) transmitted by the second sub-scanning line SL12 and the second scanning signal S2(n) transmitted by the third sub-scanning line SL21 are valid, the first sub-compensation transistor Tc1, the second sub-compensation transistor Tc2 and the data transistor T2 are turned on, and the data signal transmitted by the data line DL is transmitted to the gate of the driving transistor T1 through the data transistor T2, the second sub-compensation transistor Tc2 and the first sub-compensation transistor Tc1, so that the gate of the driving transistor T1 has a first potential.

在阳极复位阶段t3，第四子扫描线SL22传输的第二扫描信号S2(n+1)有效，初始晶体管T5导通，第二复位线VL2传输的第二复位信号经初始晶体管T5传输至第二连接节点B，以对发光器件D的阳极电位进行复位。In the anode reset stage t3, the second scan signal S2(n+1) transmitted by the fourth sub-scan line SL22 is valid, the initial transistor T5 is turned on, and the second reset signal transmitted by the second reset line VL2 is transmitted to the second connection node B through the initial transistor T5 to reset the anode potential of the light-emitting device D.

在发光阶段t4，发光控制线EML传输的发光控制信号EM(n)有效，第一开关晶体管T3和第二开关晶体管T4响应发光控制信号EM(n)导通，驱动晶体管T1生成驱动发光器件D发光的驱动电流。In the light emitting stage t4, the light emitting control signal EM(n) transmitted by the light emitting control line EML is valid, the first switch transistor T3 and the second switch transistor T4 are turned on in response to the light emitting control signal EM(n), and the driving transistor T1 generates a driving current to drive the light emitting device D to emit light.

可选地，发光控制信号EM(n)的频率大于第一扫描信号S1(n)的频率，以通过发光器件D不断的亮暗状态改善低频闪烁问题。Optionally, the frequency of the light emitting control signal EM(n) is greater than the frequency of the first scanning signal S1(n) so as to improve the low-frequency flicker problem by changing the light emitting device D to a constant bright or dark state.

图1B所示的子像素中，第一子复位晶体管Ti1的栅极和第二子复位晶体管Ti2的栅极电性连接的第一子扫描线SL11传输第n-1级的第一扫描信号S1(n-1)，第一子晶体管TL1的栅极和第二子晶体管TL2的栅极电性连接的第二子扫描线SL12传输第n级的第一扫描信号S1(n)；图1B所示的子像素的工作原理与图1A所示的子像素的工作原理相似，在此不再进行赘述。In the sub-pixel shown in Figure 1B, the first sub-scan line SL11 electrically connected to the gate of the first sub-reset transistor Ti1 and the gate of the second sub-reset transistor Ti2 transmits the first scan signal S1(n-1) of the n-1th level, and the second sub-scan line SL12 electrically connected to the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 transmits the first scan signal S1(n) of the nth level; the working principle of the sub-pixel shown in Figure 1B is similar to the working principle of the sub-pixel shown in Figure 1A, and will not be repeated here.

在采用低频进行驱动显示时，一显示周期至少包括一保持帧HF。因此，发光阶段t4可自写入帧WF延续至保持帧HF；第二扫描信号S2在保持帧HF内具有有效脉冲，可对驱动晶体管T1的栅极电位及发光器件D的阳极电位进行修正，补偿发光器件D的亮度变化。When low frequency is used for driving display, a display cycle includes at least one holding frame HF. Therefore, the light-emitting stage t4 can be extended from the writing frame WF to the holding frame HF; the second scanning signal S2 has a valid pulse in the holding frame HF, which can correct the gate potential of the driving transistor T1 and the anode potential of the light-emitting device D, and compensate for the brightness change of the light-emitting device D.

可选地，可变信号EM1(n)的跳变时刻位于数据信号被传输至驱动晶体管T1的栅极之后。为避免可变信号EM1(n)的跳变导致发光器件D的亮度变化被人眼所察觉，可变信号EM1(n)的跳变时刻位于发光控制信号EM(n)的无效脉冲作用时间内，或可变信号EM1(n)的跳变时刻与发光控制信号EM(n)的跳变时刻相同。可选地，第一电位大于第三电位V3，且小于第二电位V2。Optionally, the change time of the variable signal EM1(n) is after the data signal is transmitted to the gate of the driving transistor T1. To prevent the change of the brightness of the light-emitting device D caused by the change of the variable signal EM1(n) from being perceived by the human eye, the change time of the variable signal EM1(n) is within the invalid pulse action time of the light-emitting control signal EM(n), or the change time of the variable signal EM1(n) is the same as the change time of the light-emitting control signal EM(n). Optionally, the first potential is greater than the third potential V3 and less than the second potential V2.

可变信号EM1(n)保持第二电位V2的时长为第一时间段t11，可变信号EM1(n)保持第三电位V3的时长为第二时间段t12。在写入帧WF的第一时间段t11内，驱动晶体管T1的栅极主要受第一复位信号和数据信号的影响，可变信号EM1(n)为第三电位V3或第二电位V2并不影响驱动晶体管T1的栅极电位。在可变信号EM1(n)在发光阶段t4内具有跳变后，第一连接节点A的电位受耦合作用而相应变化，从而使驱动晶体管T1的栅极电位也相应变化。如以子像素的各晶体管仍为P型晶体管为例进行说明，可变信号EM1(n)由第三电位V3跳变至第二电位V2，则第一连接节点A的电位经电容Co作用被耦合升高至大于驱动晶体管T1的栅极电位，第一连接节点A向驱动晶体管T1的栅极漏电，使得驱动晶体管T1的栅极电位相应变高，从而使驱动电流降低，引起发光器件D的发光亮度降低。可变信号EM1(n)由第二电位V2跳变至第三电位V3时，第一连接节点A的电位经电容Co作用被耦合降低至小于驱动晶体管T1的栅极电位，驱动晶体管T1的栅极向第一连接节点A漏电，使得驱动晶体管T1的栅极电位相应降低，从而使驱动电流升高，引起发光器件D的发光亮度升高。因此，可变信号EM1(n)的跳变可引起发光器件D的亮度变化，通过不断的使可变信号EM1(n)在第二电位V2和第三电位V3之间进行跳变，可以使驱动晶体管T1的栅极电位的均值基本稳定在第一电位。The variable signal EM1(n) maintains the second potential V2 for a first time period t11, and the variable signal EM1(n) maintains the third potential V3 for a second time period t12. In the first time period t11 of the writing frame WF, the gate of the driving transistor T1 is mainly affected by the first reset signal and the data signal, and the variable signal EM1(n) is the third potential V3 or the second potential V2 and does not affect the gate potential of the driving transistor T1. After the variable signal EM1(n) has a jump in the light-emitting stage t4, the potential of the first connection node A changes accordingly due to the coupling effect, so that the gate potential of the driving transistor T1 also changes accordingly. For example, the variable signal EM1(n) jumps from the third potential V3 to the second potential V2, and the potential of the first connection node A is coupled to be higher than the gate potential of the driving transistor T1 through the capacitor Co. The first connection node A leaks electricity to the gate of the driving transistor T1, so that the gate potential of the driving transistor T1 becomes higher accordingly, thereby reducing the driving current, causing the light-emitting brightness of the light-emitting device D to decrease. When the variable signal EM1(n) jumps from the second potential V2 to the third potential V3, the potential of the first connection node A is coupled and reduced to a level lower than the gate potential of the driving transistor T1 through the capacitor Co, and the gate of the driving transistor T1 leaks electricity to the first connection node A, so that the gate potential of the driving transistor T1 decreases accordingly, thereby increasing the driving current and causing the light emitting brightness of the light emitting device D to increase. Therefore, the jump of the variable signal EM1(n) can cause the brightness of the light emitting device D to change, and by continuously jumping the variable signal EM1(n) between the second potential V2 and the third potential V3, the average value of the gate potential of the driving transistor T1 can be basically stabilized at the first potential.

可选地，第一时间段t11的时长可与第二时间段t12的时长相等，也可不相等，可变信号EM1(n)每次维持第二电位V2的时长可均相等或均不相等，可变信号EM1(n)每次维持第三电位V3的时长也可均相等或均不相等。Optionally, the duration of the first time period t11 may be equal to or unequal to the duration of the second time period t12, the duration of the variable signal EM1(n) maintaining the second potential V2 may be equal or unequal each time, and the duration of the variable signal EM1(n) maintaining the third potential V3 may be equal or unequal each time.

本申请利用低频驱动时必然存在的较长时间段的发光阶段t4，使第一连接节点A的电位经电容Co作用在发光阶段t4内实现可变，以综合第二电位V2和第三电位V3对驱动晶体管T1的栅极电位的影响，使驱动晶体管T1的栅极电位的均值基本稳定在第一电位，从而使发光器件D的发光亮度基本维持在最初发光亮度，可以改善低频驱动存在的闪烁问题，从而改善显示品质。The present application utilizes the light-emitting stage t4, which is inevitably a long period of time during low-frequency driving, so that the potential of the first connection node A can be changed during the light-emitting stage t4 through the action of the capacitor Co, so as to combine the influence of the second potential V2 and the third potential V3 on the gate potential of the driving transistor T1, so that the average value of the gate potential of the driving transistor T1 is basically stabilized at the first potential, so that the light-emitting brightness of the light-emitting device D is basically maintained at the initial light-emitting brightness, which can improve the flicker problem existing in low-frequency driving, thereby improving the display quality.

如图3是本申请实施例提供的显示亮度变化示意图；其中，L1表示利用本申请的子像素（图1A及图1B所示的子像素）得到的随驱动晶体管T1的栅极电位变化的显示亮度变化曲线，L2表示利用现有技术中的子像素（现有技术中的子像素无电容Co）得到的随驱动晶体管的栅极电位变化的显示亮度变化曲线。经对比可知，在一显示周期(1 Display)的时长内，采用本申请的子像素的发光器件D的发光亮度会变化多次，但发光器件D的发光亮度的变化幅度明显小于现有技术中的子像素的发光器件的亮度变化幅度。FIG3 is a schematic diagram of display brightness change provided by an embodiment of the present application; wherein L1 represents the display brightness change curve obtained by using the sub-pixel of the present application (the sub-pixel shown in FIG1A and FIG1B) with the gate potential of the driving transistor T1, and L2 represents the display brightness change curve obtained by using the sub-pixel in the prior art (the sub-pixel in the prior art has no capacitor Co) with the gate potential of the driving transistor. By comparison, it can be seen that within the duration of a display cycle (1 Display), the luminous brightness of the light-emitting device D using the sub-pixel of the present application will change multiple times, but the change amplitude of the luminous brightness of the light-emitting device D is significantly smaller than the brightness change amplitude of the light-emitting device of the sub-pixel in the prior art.

此外，即使第二电位V2大于驱动晶体管T1的栅极电位的次数，与第三电位V3小于驱动晶体管T1的栅极电位的次数不相等，也仅表现为L1中亮度变化切换次数的差异，从一显示周期(1 Display)的时长内来看，亮度变化切换次数的差异对整体的亮度变化影响不大。In addition, even if the number of times the second potential V2 is greater than the gate potential of the driving transistor T1 is not equal to the number of times the third potential V3 is less than the gate potential of the driving transistor T1, it only manifests as a difference in the number of brightness change switches in L1. From the perspective of the duration of a display cycle (1 Display), the difference in the number of brightness change switches has little effect on the overall brightness change.

图4A是与图1A所示的像素驱动电路对应的膜层结构示意图；图4B是与图1B示的像素驱动电路对应的膜层结构示意图；图5A是图4A所示的膜层结构图中的可变信号线与第一电连接部重叠的局部放大图；图5B是图4B所示的膜层结构图中的可变信号线与第一电连接部重叠的局部放大图；图6A是对应图4A所示的膜层结构图中的有源层的结构示意图；图6B是对应图4B所示的膜层结构图中的有源层的结构示意图。Figure 4A is a schematic diagram of the film layer structure corresponding to the pixel driving circuit shown in Figure 1A; Figure 4B is a schematic diagram of the film layer structure corresponding to the pixel driving circuit shown in Figure 1B; Figure 5A is a local enlarged view of the overlap between the variable signal line and the first electrical connection part in the film layer structure diagram shown in Figure 4A; Figure 5B is a local enlarged view of the overlap between the variable signal line and the first electrical connection part in the film layer structure diagram shown in Figure 4B; Figure 6A is a structural schematic diagram of the active layer in the film layer structure diagram corresponding to Figure 4A; Figure 6B is a structural schematic diagram of the active layer in the film layer structure diagram corresponding to Figure 4B.

连接晶体管包括第一有源层pc，第一有源层pc包括第一沟道部Ch1、第二沟道部Ch2及连接于第一沟道部Ch1和第二沟道部Ch2之间的第一电连接部ec。位于同行且相邻的两子像素Px镜像设置，位于同行且相邻的多个子像素Px的第一电连接部ec交替以第一间距P1和第二间距P2排布，第一间距P1小于第二间距P2。The connection transistor includes a first active layer pc, and the first active layer pc includes a first channel portion Ch1, a second channel portion Ch2, and a first electrical connection portion ec connected between the first channel portion Ch1 and the second channel portion Ch2. Two sub-pixels Px located in the same row and adjacent to each other are mirror-set, and the first electrical connection portions ec of a plurality of sub-pixels Px located in the same row and adjacent to each other are alternately arranged at a first pitch P1 and a second pitch P2, and the first pitch P1 is smaller than the second pitch P2.

可选地，第一有源层pc包括第一子有源部和第二子有源部，第一子晶体管TL1包括第一子有源部，第一子有源部包括第一沟道部Ch1；第二子晶体管TL2包括第二子有源部，第二子有源部包括第二沟道部Ch2，第一电连接部ec用作第一连接节点A。STL2、DTL2分别表示第二子有源部的第一端和第二端。Optionally, the first active layer pc includes a first sub-active portion and a second sub-active portion, the first sub-transistor TL1 includes a first sub-active portion, the first sub-active portion includes a first channel portion Ch1; the second sub-transistor TL2 includes a second sub-active portion, the second sub-active portion includes a second channel portion Ch2, and the first electrical connection portion ec is used as a first connection node A. STL2 and DTL2 represent a first end and a second end of the second sub-active portion, respectively.

可选地，驱动晶体管T1包括第二有源层，数据晶体管T2包括第三有源层，第一开关晶体管T3包括第四有源层，第二开关晶体管T4包括第五有源层，初始晶体管T5包括第六有源层。第二有源层的第一端ST1与第三有源层的第二端DT2、第四有源层的第二端DT3相接，第二有源层的第二端DT1与第五有源层的第一端ST4相接，第五有源层的第二端DT4与第六有源层的第一端ST5相接。Optionally, the driving transistor T1 includes a second active layer, the data transistor T2 includes a third active layer, the first switch transistor T3 includes a fourth active layer, the second switch transistor T4 includes a fifth active layer, and the initial transistor T5 includes a sixth active layer. The first end ST1 of the second active layer is connected to the second end DT2 of the third active layer and the second end DT3 of the fourth active layer, the second end DT1 of the second active layer is connected to the first end ST4 of the fifth active layer, and the second end DT4 of the fifth active layer is connected to the first end ST5 of the sixth active layer.

如图6A，第一子补偿晶体管Tc1包括第七有源层，第二子补偿晶体管Tc2包括第八有源层，第七有源层的第一端STc1与第八有源层的第二端DTc2相接，第八有源层的第一端STc2与第二有源层的第二端DT1相接。6A , the first sub-compensation transistor Tc1 includes a seventh active layer, the second sub-compensation transistor Tc2 includes an eighth active layer, the first end STc1 of the seventh active layer is connected to the second end DTc2 of the eighth active layer, and the first end STc2 of the eighth active layer is connected to the second end DT1 of the second active layer.

如图6B，第一子复位晶体管Ti1包括第九有源层，第二子复位晶体管Ti2包括第十有源层，第九有源层的第二端DTi1与第十有源层的第一端STi2相接。DTi2表示第十有源层的第二端。6B , the first sub-reset transistor Ti1 includes a ninth active layer, the second sub-reset transistor Ti2 includes a tenth active layer, and the second end DTi1 of the ninth active layer is connected to the first end STi2 of the tenth active layer. DTi2 represents the second end of the tenth active layer.

可选地，第一有源层pc与各有源层同层，以用现有制备工艺制备显示面板。可选地，第一有源层pc包括硅半导体材料或氧化物半导体材料。硅半导体材料包括单晶硅、多晶硅等；氧化物半导体材料可以包括铟镓锌氧化物、铟镓锡氧化物或铟镓锌锡氧化物等。可选地，第一有源层pc采用低温多晶硅工艺制得。Optionally, the first active layer pc is in the same layer as each active layer, so as to prepare the display panel using an existing preparation process. Optionally, the first active layer pc includes a silicon semiconductor material or an oxide semiconductor material. Silicon semiconductor materials include single crystal silicon, polycrystalline silicon, etc.; oxide semiconductor materials may include indium gallium zinc oxide, indium gallium tin oxide, or indium gallium zinc tin oxide, etc. Optionally, the first active layer pc is prepared using a low temperature polysilicon process.

可选地，如图5C~图5D，第一有源层pc位于衬底100上。可选地，衬底100包括刚性衬底和柔性衬底。如衬底100包括玻璃、聚酰亚胺、石英等。可选地，衬底100上还设有缓冲层100a。Optionally, as shown in FIG. 5C to FIG. 5D , the first active layer pc is located on the substrate 100. Optionally, the substrate 100 includes a rigid substrate and a flexible substrate. For example, the substrate 100 includes glass, polyimide, quartz, etc. Optionally, a buffer layer 100a is further provided on the substrate 100.

请继续参阅图4A~图4B及图5A~图5B，每一可变信号线EML1包括多个重叠部EML11，每一可变信号线EML1的相邻的两重叠部EML11之间间隔两子像素Px，且每一重叠部EML11与两子像素Px的以第一间距P1排布的第一电连接部ec至少部分重叠形成两电容Co，以在节省布局空间的同时，有利于实现改善低频闪烁问题的方案。Please continue to refer to Figures 4A to 4B and Figures 5A to 5B. Each variable signal line EML1 includes a plurality of overlapping portions EML11. Two adjacent overlapping portions EML11 of each variable signal line EML1 are spaced apart by two sub-pixels Px, and each overlapping portion EML11 at least partially overlaps with the first electrical connection portions ec of the two sub-pixels Px arranged at a first pitch P1 to form two capacitors Co, so as to save layout space while facilitating the implementation of a solution to improve the low-frequency flicker problem.

可选地，为降低可变信号线EML1与扫描线、发光控制线及复位线之间的相互干涉，每一可变信号线EML1还包括走线部EML13和多个连接部EML12。走线部EML13沿行方向x延伸，每一连接部EML12沿与列方向y延伸，每一连接部EML12电性连接于一重叠部EML11和走线部EML13之间，以使多个重叠部EML11通过多个连接部EML12与走线部EML13电性连接。Optionally, in order to reduce the mutual interference between the variable signal line EML1 and the scan line, the light-emitting control line and the reset line, each variable signal line EML1 further includes a routing portion EML13 and a plurality of connecting portions EML12. The routing portion EML13 extends along the row direction x, each connecting portion EML12 extends along the column direction y, and each connecting portion EML12 is electrically connected between an overlapping portion EML11 and the routing portion EML13, so that the plurality of overlapping portions EML11 are electrically connected to the routing portion EML13 through the plurality of connecting portions EML12.

每一可变信号线EML1的相邻的两连接部EML12之间间隔两子像素Px，且每一连接部EML12位于两子像素Px的以第一间距P1排布的第一电连接部ec之间，从而降低连接部EML12的绕线距离，以在实现走线部EML13和重叠部EML11电性连接的同时，降低连接部EML12与其他信号走线的重叠几率。Two adjacent connection portions EML12 of each variable signal line EML1 are spaced apart by two sub-pixels Px, and each connection portion EML12 is located between the first electrical connection portions ec of the two sub-pixels Px arranged at a first pitch P1, thereby reducing the winding distance of the connection portion EML12, so as to reduce the probability of overlap between the connection portion EML12 and other signal routings while achieving electrical connection between the routing portion EML13 and the overlapping portion EML11.

可选地，连接部EML12与重叠部EML11异层，以避免连接部EML12与其他信号走线之间出现交叉，继而引起短路或生成寄生电容，影响像素驱动电路的正常工作。可选地，走线部EML13和重叠部EML11同层。Optionally, the connection portion EML12 and the overlapping portion EML11 are in different layers to avoid crossing between the connection portion EML12 and other signal lines, thereby causing short circuits or generating parasitic capacitance, affecting the normal operation of the pixel driving circuit. Optionally, the wiring portion EML13 and the overlapping portion EML11 are in the same layer.

可选地，如图5C~图5D，显示面板包括位于第一有源层pc上的第二导电层102，第二导电层102包括走线部EML13及重叠部EML11。可选地，显示面板包括位于第二导电层102上的第三导电层103，第三导电层103包括连接部EML12。可选地，显示面板还包括位于第一有源层pc和第二导电层之间的第一导电层，第一导电层包括驱动晶体管T1的栅极。可选地，第一绝缘层1001位于第一有源层pc和第一导电层之间，第二绝缘层1002位于第一导电层和第二导电层102之间，层间介电层1003位于第二导电层102和第三导电层103之间。Optionally, as shown in FIGS. 5C to 5D , the display panel includes a second conductive layer 102 located on the first active layer pc, and the second conductive layer 102 includes a routing portion EML13 and an overlapping portion EML11. Optionally, the display panel includes a third conductive layer 103 located on the second conductive layer 102, and the third conductive layer 103 includes a connecting portion EML12. Optionally, the display panel also includes a first conductive layer located between the first active layer pc and the second conductive layer, and the first conductive layer includes a gate of the driving transistor T1. Optionally, the first insulating layer 1001 is located between the first active layer pc and the first conductive layer, the second insulating layer 1002 is located between the first conductive layer and the second conductive layer 102, and the interlayer dielectric layer 1003 is located between the second conductive layer 102 and the third conductive layer 103.

可选地，第一导电层、第二导电层102及第三导电层103包括钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)、钨(W)、铜(Cu)等中的至少一种。可选地，第一导电层、第二导电层102或第三导电层103可为单层膜层结构，也可为Ti/Al/Ti、Mo/Al/Mo、Mo/AlGe/Mo、Cu/Mo、Cu/Ti、Cu/MoTi或Cu/MoNb等叠层结构。可选地，第一绝缘层1001、第二绝缘层1002包括硅氧化物、硅氮化物、硅氮氧化物、铝氧化物、钽氧化物、铪氧化物、锆氧化物、钛氧化物等。Optionally, the first conductive layer, the second conductive layer 102 and the third conductive layer 103 include at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), etc. Optionally, the first conductive layer, the second conductive layer 102 or the third conductive layer 103 may be a single-layer film structure, or a stacked-layer structure such as Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Cu/Mo, Cu/Ti, Cu/MoTi or Cu/MoNb. Optionally, the first insulating layer 1001 and the second insulating layer 1002 include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

请继续参阅图4A~图4B及图5A~图5B，位于同行的多个子像素px的连接晶体管的栅极与对应的第一扫描线电性连接；与位于同行的多个子像素px的连接晶体管的栅极电性连接的第一扫描线包括多个第一栅部，每一第一栅部包括相对设置的第一子栅部SL11b1和第二子栅部SL11b2，以及连接于第一子栅部SL11b1和第二子栅部SL11b2之间的第三子栅部SL11b3。Please continue to refer to Figures 4A to 4B and Figures 5A to 5B. The gates of the connecting transistors of the multiple sub-pixels px located in the same row are electrically connected to the corresponding first scanning line; the first scanning line electrically connected to the gates of the connecting transistors of the multiple sub-pixels px located in the same row includes a plurality of first gate portions, each of which includes a first sub-gate portion SL11b1 and a second sub-gate portion SL11b2 arranged opposite to each other, and a third sub-gate portion SL11b3 connected between the first sub-gate portion SL11b1 and the second sub-gate portion SL11b2.

其中，第一子栅部SL11b1和第二子栅部SL11b2均沿列方向y延伸，SL11b3沿行方向x延伸；第一子栅部SL11b1和第二子栅部SL11b2分别与子像素Px的以第一间距P1相邻的第一电连接部ec电性连接的两第一沟道部Ch1重叠，第三子栅部SL11b3与两子像素Px的以第一间距P1相邻的第一电连接部ec电性连接的两第二沟道部Ch2重叠；每一重叠部EML11位于对应的第一栅部的第一子栅部SL11b1和第二子栅部SL11b2之间。Among them, the first sub-gate portion SL11b1 and the second sub-gate portion SL11b2 both extend along the column direction y, and SL11b3 extends along the row direction x; the first sub-gate portion SL11b1 and the second sub-gate portion SL11b2 respectively overlap with the two first channel portions Ch1 electrically connected to the first electrical connection portions ec of the sub-pixels Px adjacent to each other at the first pitch P1, and the third sub-gate portion SL11b3 overlaps with the two second channel portions Ch2 electrically connected to the first electrical connection portions ec of the two sub-pixels Px adjacent to each other at the first pitch P1; each overlapping portion EML11 is located between the first sub-gate portion SL11b1 and the second sub-gate portion SL11b2 of the corresponding first gate portion.

根据第一有源层pc位置的不同，与位于同行的多个子像素px的连接晶体管的栅极电性连接的第一扫描线也会不同，可变信号线EML1的布局也不同。According to the different positions of the first active layer pc, the first scanning lines electrically connected to the gates of the connection transistors of the plurality of sub-pixels px in the same row will be different, and the layout of the variable signal line EML1 will also be different.

具体地，如图7A~图7B是本申请实施例提供的第一导电层的结构示意图，图8A~图8B是本申请实施例提供的第二导电层的结构示意图，图9A~图9B是本申请实施例提供的第三导电层的结构示意图。Specifically, Figures 7A and 7B are schematic diagrams of the structure of the first conductive layer provided in an embodiment of the present application, Figures 8A and 8B are schematic diagrams of the structure of the second conductive layer provided in an embodiment of the present application, and Figures 9A and 9B are schematic diagrams of the structure of the third conductive layer provided in an embodiment of the present application.

请继续参阅图4A、图5A、图6A、图7A、图8A及图9A，第一子扫描线SL11与位于同行的多个子像素Px的连接晶体管的栅极电性连接，每一第一子扫描线SL11包括第一栅部及多个第一子走线部SL11a。每一第一子走线部SL11a沿行方向x延伸，每一第一子走线部SL11a的两端分别与第一子栅部SL11b1和第三子栅部SL11b3的相接处、第二子栅部SL11b2和第三子栅部SL11b3的相接处电性连接。Please continue to refer to FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A and FIG. 9A. The first sub-scanning line SL11 is electrically connected to the gates of the connection transistors of the plurality of sub-pixels Px in the same row. Each first sub-scanning line SL11 includes a first gate portion and a plurality of first sub-routing portions SL11a. Each first sub-routing portion SL11a extends along the row direction x. Both ends of each first sub-routing portion SL11a are electrically connected to the junction of the first sub-gate portion SL11b1 and the third sub-gate portion SL11b3, and the junction of the second sub-gate portion SL11b2 and the third sub-gate portion SL11b3.

每一连接部EML12均与对应的第一栅部的第三子栅部SL11b3至少部分重叠，通过连接部EML12电性连接的走线部EML13和重叠部EML11分别位于第三子栅部SL11b3的相对两侧，以降低走线部EML13和复位线、扫描线之间的相互干涉程度，并降低设计复杂度。Each connecting portion EML12 at least partially overlaps with the corresponding third sub-gate portion SL11b3 of the first gate portion. The routing portion EML13 and the overlapping portion EML11 electrically connected through the connecting portion EML12 are respectively located on opposite sides of the third sub-gate portion SL11b3, so as to reduce the mutual interference between the routing portion EML13 and the reset line and the scan line, and reduce the design complexity.

为降低连接部EML12与第一栅部生成的寄生电容对子像素的影响，在显示面板的厚度方向上，每一连接部EML12距对应的第三子栅部SL11b3的距离大于每一连接部EML12距对应的重叠部EML11的距离，以使连接部EML12与第三子栅部SL11b3形成的寄生电容的电容量明显小于电容Co的电容量。In order to reduce the influence of the parasitic capacitance generated by the connecting portion EML12 and the first gate portion on the sub-pixel, in the thickness direction of the display panel, the distance between each connecting portion EML12 and the corresponding third sub-gate portion SL11b3 is greater than the distance between each connecting portion EML12 and the corresponding overlapping portion EML11, so that the capacitance of the parasitic capacitance formed by the connecting portion EML12 and the third sub-gate portion SL11b3 is significantly smaller than the capacitance of the capacitor Co.

可选地，每一第二子扫描线SL12包括至少一第二子走线部SL12a和多个第二栅部。第二子走线部SL12a沿行方向x延伸，第二子走线部SL12a和多个第二栅部电性连接。可选地，第二栅部包括第四子栅部SL12b1、第五子栅部SL12b2及第六子栅部SL12b3。第四子栅部SL12b1沿列方向y延伸，第五子栅部SL12b2和第四子栅部SL12b1平行且间隔设置，第六子栅部SL12b3沿行方向x延伸，第六子栅部SL12b3的两端分别连接于第四子栅部SL12b1和第五子栅部SL12b2。第四子栅部SL12b1和第五子栅部SL12b2分别与相邻两像素驱动电路对应的第八有源层重叠，第四子栅部SL12b1和第五子栅部SL12b2分别用作相邻两像素驱动电路中的第二子补偿晶体管Tc2的栅极。第六子栅部SL12b3与相邻两像素驱动电路对应的第七有源层重叠，以用作相邻两像素驱动电路中的第一子补偿晶体管Tc1的栅极。Optionally, each second sub-scan line SL12 includes at least one second sub-routing portion SL12a and a plurality of second gate portions. The second sub-routing portion SL12a extends along the row direction x, and the second sub-routing portion SL12a is electrically connected to the plurality of second gate portions. Optionally, the second gate portion includes a fourth sub-gate portion SL12b1, a fifth sub-gate portion SL12b2, and a sixth sub-gate portion SL12b3. The fourth sub-gate portion SL12b1 extends along the column direction y, the fifth sub-gate portion SL12b2 is parallel to and spaced from the fourth sub-gate portion SL12b1, the sixth sub-gate portion SL12b3 extends along the row direction x, and the two ends of the sixth sub-gate portion SL12b3 are respectively connected to the fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2. The fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2 overlap with the eighth active layer corresponding to the two adjacent pixel driving circuits, respectively, and the fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2 are respectively used as the gate of the second sub-compensation transistor Tc2 in the two adjacent pixel driving circuits. The sixth sub-gate portion SL12b3 overlaps with the seventh active layer corresponding to the two adjacent pixel driving circuits to be used as the gate of the first sub-compensation transistor Tc1 in the two adjacent pixel driving circuits.

可选地，每一第二子扫描线SL12还包括多个栅连接部，每一栅连接部包括第一子栅连接部SL12c1和第二子栅连接部SL12c2，同一栅连接部的第一子栅连接部SL12c1的第一端和第二子栅连接部SL12c2的第一端相接且电性连接于第二子走线部SL12a，同一栅连接部的第一子栅连接部SL12c1的第二端和第二子栅连接部SL12c2的第二端分别与同一第二栅部电性连接。可选地，第一子栅连接部SL12c1的第二端与第四子栅部SL12b1和第六子栅部SL12b3的相接处电性连接，第二子栅连接部SL12c2的第二端与第五子栅部SL12b2和第六子栅部SL12b3的相接处电性连接。Optionally, each second sub-scan line SL12 further includes a plurality of gate connection portions, each gate connection portion includes a first sub-gate connection portion SL12c1 and a second sub-gate connection portion SL12c2, a first end of the first sub-gate connection portion SL12c1 and a first end of the second sub-gate connection portion SL12c2 of the same gate connection portion are connected and electrically connected to the second sub-routing portion SL12a, and a second end of the first sub-gate connection portion SL12c1 and a second end of the second sub-gate connection portion SL12c2 of the same gate connection portion are electrically connected to the same second gate portion, respectively. Optionally, a second end of the first sub-gate connection portion SL12c1 is electrically connected to a junction of the fourth sub-gate portion SL12b1 and the sixth sub-gate portion SL12b3, and a second end of the second sub-gate connection portion SL12c2 is electrically connected to a junction of the fifth sub-gate portion SL12b2 and the sixth sub-gate portion SL12b3.

可选地，第一子栅连接部SL12c1和第二子栅连接部SL12c2关于连接部EML12对称，以使经第一子栅连接部SL12c1和第二子栅连接部SL12c2传输至两像素驱动电路中的第一扫描信号具有相近的损耗量。Optionally, the first sub-gate connection portion SL12c1 and the second sub-gate connection portion SL12c2 are symmetrical about the connection portion EML12, so that the first scan signal transmitted to the two pixel driving circuits through the first sub-gate connection portion SL12c1 and the second sub-gate connection portion SL12c2 has a similar loss.

请继续参阅图4B、图5B、图6B、图7B、图8B及图9B，第二子扫描线SL12与位于同行的多个子像素Px的连接晶体管的栅极电性连接，每一第二子扫描线SL11包括第一栅部、第二子走线部SL12a及多个栅连接部。Please continue to refer to Figures 4B, 5B, 6B, 7B, 8B and 9B. The second sub-scan line SL12 is electrically connected to the gates of the connecting transistors of multiple sub-pixels Px in the same row. Each second sub-scan line SL11 includes a first gate portion, a second sub-wiring portion SL12a and multiple gate connecting portions.

第二子走线部SL12a沿行方向x延伸，每一栅连接部电性连接于对应的第一栅部和第二子走线部SL12a之间，每一栅连接部包括关于连接部EML12对称的第一子栅连接部SL12c1和第二子栅连接部SL12c2。其中，每一栅连接部的第一子栅连接部SL12c1的第一端和第二子栅连接部SL12c2的第一端相接且电性连接于第二子走线部SL12a，每一栅连接部的第一子栅连接部SL12c1的第二端与对应的第一栅部的第一子栅部SL11b1和第三子栅部SL11b3的相接处电性连接，每一栅连接部的第二子栅连接部SL12c2的第二端与对应的第一栅部的第二子栅部SL11b2和第三子栅部SL11b3的相接处电性连接。The second sub-routing portion SL12a extends along the row direction x, each gate connection portion is electrically connected between the corresponding first gate portion and the second sub-routing portion SL12a, and each gate connection portion includes a first sub-gate connection portion SL12c1 and a second sub-gate connection portion SL12c2 that are symmetrical about the connection portion EML12. Among them, the first end of the first sub-gate connection portion SL12c1 of each gate connection portion and the first end of the second sub-gate connection portion SL12c2 are connected and electrically connected to the second sub-routing portion SL12a, the second end of the first sub-gate connection portion SL12c1 of each gate connection portion is electrically connected to the connection between the first sub-gate portion SL11b1 and the third sub-gate portion SL11b3 of the corresponding first gate portion, and the second end of the second sub-gate connection portion SL12c2 of each gate connection portion is electrically connected to the connection between the second sub-gate portion SL11b2 and the third sub-gate portion SL11b3 of the corresponding first gate portion.

每一连接部EML12位于对应的重叠部EML11远离第三子栅部SL11b3的一侧，每一走线部EML13位于对应的连接部EML12远离重叠部EML11的一侧，以降低可变信号线EML1和复位线、扫描线的相互干涉。Each connection portion EML12 is located on a side of the corresponding overlapping portion EML11 away from the third sub-gate portion SL11b3, and each routing portion EML13 is located on a side of the corresponding connection portion EML12 away from the overlapping portion EML11 to reduce mutual interference between the variable signal line EML1 and the reset line and the scan line.

可选地，每一发光控制线EML沿行方向x延伸，每一发光控制线EML与一可变信号线EML1的多个连接部EML12均至少部分重叠。为避免发光控制线EML与可变信号线EML1的连接部EML12之间出现短路，发光控制线EML与可变信号线EML1的连接部EML12异层。Optionally, each light emitting control line EML extends along the row direction x, and each light emitting control line EML at least partially overlaps with a plurality of connection portions EML12 of a variable signal line EML1. To avoid a short circuit between the light emitting control line EML and the connection portion EML12 of the variable signal line EML1, the light emitting control line EML and the connection portion EML12 of the variable signal line EML1 are in different layers.

可选地，为降低发光控制线EML与连接部EML12之间的寄生电容，在显示面板的厚度方向上，每一连接部EML12距对应的发光控制线EML的距离，大于每一连接部EML12距对应的重叠部EML11的距离。Optionally, to reduce parasitic capacitance between the light emitting control line EML and the connection portion EML12, in the thickness direction of the display panel, the distance between each connection portion EML12 and the corresponding light emitting control line EML is greater than the distance between each connection portion EML12 and the corresponding overlapping portion EML11.

可选地，每一第一子扫描线SL11包括多个第一子走线部SL11a和多个第二栅部。第二栅部包括沿列方向y延伸的第四子栅部SL12b1和第五子栅部SL12b2以及沿行方向x延伸并连接于第四子栅部SL12b1和第五子栅部SL12b2之间的第六子栅部SL12b3。第四子栅部SL12b1和第五子栅部SL12b2分别与相邻两像素驱动电路对应的第九有源层重叠，以分别用作相邻两像素驱动电路中的第一子复位晶体管Ti1的栅极。第六子栅部SL12b3与相邻两像素驱动电路对应的第十有源层重叠，以用作相邻两像素驱动电路中的第二子复位晶体管Ti2的栅极。每一第一子走线部SL11a沿行方向x延伸，每一第一子走线部SL11a的两端分别与第四子栅部SL12b1和第六子栅部SL12b3的相接处、第五子栅部SL12b2和第六子栅部SL12b3的相接处电性连接。Optionally, each first sub-scan line SL11 includes a plurality of first sub-routing portions SL11a and a plurality of second gate portions. The second gate portion includes a fourth sub-gate portion SL12b1 and a fifth sub-gate portion SL12b2 extending along the column direction y, and a sixth sub-gate portion SL12b3 extending along the row direction x and connected between the fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2. The fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2 overlap with the ninth active layer corresponding to the two adjacent pixel driving circuits, respectively, so as to be used as the gate of the first sub-reset transistor Ti1 in the two adjacent pixel driving circuits. The sixth sub-gate portion SL12b3 overlaps with the tenth active layer corresponding to the two adjacent pixel driving circuits, so as to be used as the gate of the second sub-reset transistor Ti2 in the two adjacent pixel driving circuits. Each first sub-routing portion SL11a extends along the row direction x, and two ends of each first sub-routing portion SL11a are electrically connected to the junction of the fourth sub-gate portion SL12b1 and the sixth sub-gate portion SL12b3 and the junction of the fifth sub-gate portion SL12b2 and the sixth sub-gate portion SL12b3 respectively.

可选地，第一栅部和第一子走线部SL11a异层，第二栅部和第二子走线部SL12a异层。可选地，第一子走线部SL11a、第二子走线部SL12a和走线部EML13、重叠部EML11同层。可选地，栅连接部和连接部EML12同层。Optionally, the first gate portion and the first sub-routing portion SL11a are in different layers, and the second gate portion and the second sub-routing portion SL12a are in different layers. Optionally, the first sub-routing portion SL11a, the second sub-routing portion SL12a, the routing portion EML13, and the overlapping portion EML11 are in the same layer. Optionally, the gate connection portion and the connection portion EML12 are in the same layer.

可选地，连接部EML12沿列方向y的中心线和第一栅部沿列方向y的中心线、第二栅部沿列方向y的中心线重合，以使经第一栅部和第二栅部传输至两像素驱动电路内的第一扫描信号具有相近的损耗量。Optionally, the center line of the connecting portion EML12 along the column direction y coincides with the center line of the first gate portion along the column direction y and the center line of the second gate portion along the column direction y, so that the first scanning signal transmitted to the two pixel driving circuits through the first gate portion and the second gate portion has a similar loss.

请继续参阅图7A~图7B，第一导电层还包括第一电极部E1，第一电极部E1与第二有源层重叠，第一电极部E1用作驱动晶体管T1的栅极。可选地，第一导电层还包括第三子扫描线SL21、第四子扫描线SL22及发光控制线EML。第三子扫描线SL21沿行方向x延伸且与第三有源层重叠，以用作数据晶体管T2的栅极。第四子扫描线SL22沿行方向x延伸且位于发光控制线EML远离第二有源层的一侧，第四子扫描线SL22与第六有源层重叠，以用作初始晶体管T5的栅极。发光控制线EML和第三子扫描线SL21分别位于第二有源层的相对两侧，发光控制线EML沿行方向x延伸且与第四有源层和第五有源层重叠，以分别用作第一开关晶体管T3的栅极和第二开关晶体管T4的栅极。Please continue to refer to FIG. 7A to FIG. 7B. The first conductive layer further includes a first electrode portion E1, which overlaps with the second active layer, and the first electrode portion E1 is used as the gate of the driving transistor T1. Optionally, the first conductive layer further includes a third sub-scan line SL21, a fourth sub-scan line SL22, and a light-emitting control line EML. The third sub-scan line SL21 extends along the row direction x and overlaps with the third active layer to serve as the gate of the data transistor T2. The fourth sub-scan line SL22 extends along the row direction x and is located on the side of the light-emitting control line EML away from the second active layer. The fourth sub-scan line SL22 overlaps with the sixth active layer to serve as the gate of the initial transistor T5. The light-emitting control line EML and the third sub-scan line SL21 are respectively located on opposite sides of the second active layer. The light-emitting control line EML extends along the row direction x and overlaps with the fourth active layer and the fifth active layer to serve as the gate of the first switching transistor T3 and the gate of the second switching transistor T4, respectively.

如图8A~图8B，第二导电层102包括多个第二电极部E2，每一第二电极部E2与位于两子像素Px的以第二间距P2排布的第一电连接部ec之间的两第一电极部E1至少部分重叠，以使两子像素的存储电容共用一电极，从而节省制程工序及布局空间。As shown in Figures 8A to 8B, the second conductive layer 102 includes a plurality of second electrode portions E2, each of which at least partially overlaps with two first electrode portions E1 located between first electrical connection portions ec of two sub-pixels Px arranged at a second pitch P2, so that the storage capacitors of the two sub-pixels share one electrode, thereby saving process steps and layout space.

请继续参阅图4A~图4B、图6A~图6B、图8A~图8B及图9A~图9B，可选地，复位线包括至少一第一复位走线部VLa、多个第二复位走线部VLb及多个第三复位走线部VLc。第一复位走线部VLa沿行方向x延伸，第一复位走线部VLa与第一有源连接部cn1重叠且电性连接，以实现每一像素驱动电路中对应晶体管与复位线的电性连接。每一第二复位走线部VLb沿行方向x延伸，每一第二复位走线部VLb的两端分别与相邻两像素驱动电路对应的第六有源层的第二端DT5电性连接，以实现每一像素驱动电路中初始晶体管T5与复位线的电性连接。每一第三复位走线部VLc沿列方向y延伸，每一第三复位走线部VLc连接于第一复位走线部VLa和一第二复位走线部VLb之间，以实现第一复位走线部VLa和第二复位走线部VLb的电性连接。Please continue to refer to Figures 4A to 4B, Figures 6A to 6B, Figures 8A to 8B and Figures 9A to 9B. Optionally, the reset line includes at least one first reset wiring portion VLa, multiple second reset wiring portions VLb and multiple third reset wiring portions VLc. The first reset wiring portion VLa extends along the row direction x, and the first reset wiring portion VLa overlaps and is electrically connected to the first active connection portion cn1 to achieve electrical connection between the corresponding transistor in each pixel driving circuit and the reset line. Each second reset wiring portion VLb extends along the row direction x, and the two ends of each second reset wiring portion VLb are respectively electrically connected to the second end DT5 of the sixth active layer corresponding to the two adjacent pixel driving circuits to achieve electrical connection between the initial transistor T5 in each pixel driving circuit and the reset line. Each third reset wiring portion VLc extends along the column direction y, and each third reset wiring portion VLc is connected between the first reset wiring portion VLa and a second reset wiring portion VLb to achieve electrical connection between the first reset wiring portion VLa and the second reset wiring portion VLb.

可选地，第一复位走线部VLa可与走线部EML13、重叠部EML11同层，第二复位走线部VLb、第三复位走线部VLc与连接部EML12同层。Optionally, the first reset routing portion VLa may be on the same layer as the routing portion EML13 and the overlapping portion EML11 , and the second reset routing portion VLb and the third reset routing portion VLc may be on the same layer as the connecting portion EML12 .

可选地，第三导电层103包括第一复位走线部VLa、第二复位走线部VLb和第三复位走线部VLc。Optionally, the third conductive layer 103 includes a first reset wiring portion VLa, a second reset wiring portion VLb and a third reset wiring portion VLc.

其中，需要说明的是，每一复位线与沿列方向y相邻的两像素驱动电路电性连接。如在图4A中，第二复位线VL2与像素驱动电路中的初始晶体管T5电性连接，同时也和沿列方向y与像素驱动电路相邻的下一像素驱动电路中的第二子晶体管TL2电性连接。因此，第一复位线VL1和第二复位线VL2均包括第一复位走线部VLa、第二复位走线部VLb和第三复位走线部VLc。It should be noted that each reset line is electrically connected to two pixel driving circuits adjacent to each other along the column direction y. As shown in FIG. 4A , the second reset line VL2 is electrically connected to the initial transistor T5 in the pixel driving circuit, and is also electrically connected to the second sub-transistor TL2 in the next pixel driving circuit adjacent to the pixel driving circuit along the column direction y. Therefore, the first reset line VL1 and the second reset line VL2 both include a first reset wiring portion VLa, a second reset wiring portion VLb, and a third reset wiring portion VLc.

可选地，第一有源连接部cn1位于可变信号线EML1远离第一子扫描线SL11的一侧，从而使第一复位走线部VLa和第一有源连接部cn1的电性连接处与连接部EML12和走线部EML13的电性连接处间隔设置，以降低复位线与可变信号线EML1之间的相互干涉程度。Optionally, the first active connection portion cn1 is located on a side of the variable signal line EML1 away from the first sub-scan line SL11, so that the electrical connection between the first reset wiring portion VLa and the first active connection portion cn1 is spaced apart from the electrical connection between the connection portion EML12 and the wiring portion EML13 to reduce the degree of mutual interference between the reset line and the variable signal line EML1.

请继续参阅9A~图9B，第三导电层103还包括第一导电部F1、第二导电部F2、第三导电部F3、第四导电部F4、第五导电部F5及第六导电部F6。Please continue to refer to FIG. 9A to FIG. 9B , the third conductive layer 103 further includes a first conductive portion F1 , a second conductive portion F2 , a third conductive portion F3 , a fourth conductive portion F4 , a fifth conductive portion F5 and a sixth conductive portion F6 .

如图9A，第一导电部F1电性连接于第一电极部E1和第七有源层的第二端DTc1、第一子有源部的第一端STL1之间，以实现驱动晶体管T1的栅极和第一子晶体管TL1、第一子补偿晶体管Tc1的电性连接。具体的，第二电极部E2包括暴露出第一电极部E1的第一开孔，第一导电部F1通过第一开孔及贯穿层间介电层1003和第二绝缘层1002的过孔与第一电极部E1电性连接(如图9A中的J1处)，通过贯穿层间介电层1003、第二绝缘层1002和第一绝缘层1001的两过孔分别与第七有源层的第二端DTc1、第一子有源部的第一端STL1电性连接(如图9A中的J2和J3处)。As shown in FIG9A , the first conductive portion F1 is electrically connected between the first electrode portion E1 and the second end DTc1 of the seventh active layer and the first end STL1 of the first sub-active portion, so as to realize the electrical connection between the gate of the driving transistor T1 and the first sub-transistor TL1 and the first sub-compensation transistor Tc1. Specifically, the second electrode portion E2 includes a first opening exposing the first electrode portion E1, and the first conductive portion F1 is electrically connected to the first electrode portion E1 through the first opening and a via hole penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (such as J1 in FIG9A ), and is electrically connected to the second end DTc1 of the seventh active layer and the first end STL1 of the first sub-active portion through two via holes penetrating the interlayer dielectric layer 1003, the second insulating layer 1002 and the first insulating layer 1001 (such as J2 and J3 in FIG9A ).

如图9B，第一导电部F1电性连接于第一电极部E1和第九有源层的第一端STi1、第一子有源部的第二端DTL1之间，以实现驱动晶体管T1的栅极和第一子晶体管TL1、第一子复位晶体管Ti1的电性连接。具体的，第二电极部E2包括暴露出第一电极部E1的第一开孔，第一导电部F1通过第一开孔及贯穿层间介电层1003和第二绝缘层1002的过孔与第一电极部E1电性连接(如图9B中的H1处)，通过贯穿层间介电层1003、第二绝缘层1002和第一绝缘层1001的两过孔分别与第一子有源部的第二端DTL1、第九有源层的第一端STi1电性连接(如图9B中的H2和H3处)。As shown in FIG9B , the first conductive portion F1 is electrically connected between the first electrode portion E1 and the first end STi1 of the ninth active layer and the second end DTL1 of the first sub-active portion, so as to realize the electrical connection between the gate of the driving transistor T1 and the first sub-transistor TL1 and the first sub-reset transistor Ti1. Specifically, the second electrode portion E2 includes a first opening exposing the first electrode portion E1, and the first conductive portion F1 is electrically connected to the first electrode portion E1 through the first opening and a via hole penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (such as H1 in FIG9B ), and is electrically connected to the second end DTL1 of the first sub-active portion and the first end STi1 of the ninth active layer through two via holes penetrating the interlayer dielectric layer 1003, the second insulating layer 1002 and the first insulating layer 1001 (such as H2 and H3 in FIG9B ).

如图9A~图9B，第二导电部F2与第三有源层的第一端ST2重叠，以用作数据晶体管T2的源极。具体的，第二导电部F2通过贯穿层间介电层1003、第二绝缘层1002和第一绝缘层1001的过孔与第三有源层的第一端ST2电性连接(如图9A中的J4和如图9B中的H4处)。As shown in Figures 9A and 9B, the second conductive portion F2 overlaps with the first end ST2 of the third active layer to serve as the source of the data transistor T2. Specifically, the second conductive portion F2 is electrically connected to the first end ST2 of the third active layer through a via hole penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 (such as J4 in Figure 9A and H4 in Figure 9B).

如图9A，第三导电部F3电性连接于第一栅部和第一子走线部SL11a之间，以实现第一栅部和第一子走线部SL11a的电性连接。具体的，第三导电部F3通过贯穿层间介电层1003的过孔与第一子走线部SL11a电性连接(如图9A中的J5处)，通过贯穿层间介电层1003和第二绝缘层1002的过孔与第一栅部电性连接(如图9A中的J6处)。As shown in FIG9A , the third conductive portion F3 is electrically connected between the first gate portion and the first sub-wiring portion SL11a to achieve electrical connection between the first gate portion and the first sub-wiring portion SL11a. Specifically, the third conductive portion F3 is electrically connected to the first sub-wiring portion SL11a through a via hole penetrating the interlayer dielectric layer 1003 (such as J5 in FIG9A ), and is electrically connected to the first gate portion through a via hole penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (such as J6 in FIG9A ).

如图9B，第三导电部F3电性连接于第二栅部和第一子走线部SL11a之间，以实现第二栅部和第一子走线部SL11a的电性连接。具体的，第三导电部F3通过贯穿层间介电层1003的过孔与第一子走线部SL11a电性连接(如图9B中的H5处)，通过贯穿层间介电层1003和第二绝缘层1002的过孔与第二栅部电性连接(如图9B中的H6处)。As shown in FIG9B , the third conductive portion F3 is electrically connected between the second gate portion and the first sub-wiring portion SL11a to achieve electrical connection between the second gate portion and the first sub-wiring portion SL11a. Specifically, the third conductive portion F3 is electrically connected to the first sub-wiring portion SL11a through a via hole penetrating the interlayer dielectric layer 1003 (such as H5 in FIG9B ), and is electrically connected to the second gate portion through a via hole penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (such as H6 in FIG9B ).

第四导电部F4电性连接于第二电极部E2和第四有源层的第一端ST3之间，以实现第二电极部E2和第一开关晶体管的电性连接。具体的，第四导电部F4通过贯穿层间介电层1003的过孔与第二电极部E2电性连接(如图9A中的J7和如图9B中的H7处)，通过贯穿层间介电层1003、第二绝缘层1002和第一绝缘层1001的过孔与第四有源层的第一端ST3电性连接(如图9A中的J8和如图9B中的H8处)。The fourth conductive portion F4 is electrically connected between the second electrode portion E2 and the first end ST3 of the fourth active layer to achieve electrical connection between the second electrode portion E2 and the first switch transistor. Specifically, the fourth conductive portion F4 is electrically connected to the second electrode portion E2 through a via hole penetrating the interlayer dielectric layer 1003 (such as J7 in FIG. 9A and H7 in FIG. 9B ), and is electrically connected to the first end ST3 of the fourth active layer through a via hole penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 (such as J8 in FIG. 9A and H8 in FIG. 9B ).

第五导电部F5与第五有源层的第二端DT4、第六有源层的第一端ST5电性连接，以作用第二连接节点B。具体的，第五导电部F5通过贯穿层间介电层1003、第二绝缘层1002和第一绝缘层1001的过孔与第五有源层的第二端DT4、第六有源层的第一端ST5电性连接(如图9A中的J9和图9B中的H9)。The fifth conductive portion F5 is electrically connected to the second end DT4 of the fifth active layer and the first end ST5 of the sixth active layer to serve as the second connection node B. Specifically, the fifth conductive portion F5 is electrically connected to the second end DT4 of the fifth active layer and the first end ST5 of the sixth active layer through a via hole penetrating the interlayer dielectric layer 1003, the second insulating layer 1002 and the first insulating layer 1001 (such as J9 in FIG. 9A and H9 in FIG. 9B ).

第六导电部F6电性连接于第一有源连接图案cn1和第一复位走线部VLa之间，以实现第一有源连接图案cn1和复位线的电性连接。具体的，第六导电部F6通过贯穿层间介电层1003、第二绝缘层1002和第一绝缘层1001的过孔与第一有源连接图案cn1电性连接(如图9A中的J10和图9B中的H10处)。The sixth conductive portion F6 is electrically connected between the first active connection pattern cn1 and the first reset wiring portion VLa to achieve electrical connection between the first active connection pattern cn1 and the reset line. Specifically, the sixth conductive portion F6 is electrically connected to the first active connection pattern cn1 through a via hole penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 (such as J10 in FIG. 9A and H10 in FIG. 9B).

在第三导电层103包括连接部EML12、栅连接部及第二复位走线部VLb时，连接部EML12分别通过贯穿层间介电层1003的两过孔与重叠部EML11、走线部EML13电性连接(如图9A~图9B中的HE1和HE2处)。栅连接部通过贯穿层间介电层1003与第二子走线部SL12a电性连接(如图9A~图9B中的HG1处)。通过贯穿层间介电层1003和第二绝缘层1002的两过孔与第四子栅部SL12b1和第六子栅部SL12b3的相接处以及第五子栅部SL12b2和第六子栅部SL12b3的相接处电性连接(如图9A中的HG2和HG3处)。通过贯穿层间介电层1003和第二绝缘层1002的两过孔与第一子栅部SL11b1和第三子栅部SL11b3的相接处以及第二子栅部SL11b2和第三子栅部SL11b3的相接处电性连接(如图9B中的HG2和HG3处)。第二复位走线部VLb通过贯穿层间介电层1003、第二绝缘层1002和第一绝缘层1001的过孔与第六有源层的第二端DT5电性连接(如图9A中的J11和图9B中的H11处)。When the third conductive layer 103 includes a connection portion EML12, a gate connection portion, and a second reset wiring portion VLb, the connection portion EML12 is electrically connected to the overlapping portion EML11 and the wiring portion EML13 through two vias penetrating the interlayer dielectric layer 1003 (such as HE1 and HE2 in Figures 9A to 9B). The gate connection portion is electrically connected to the second sub-wiring portion SL12a by penetrating the interlayer dielectric layer 1003 (such as HG1 in Figures 9A to 9B). The gate connection portion is electrically connected to the junction of the fourth sub-gate portion SL12b1 and the sixth sub-gate portion SL12b3 and the junction of the fifth sub-gate portion SL12b2 and the sixth sub-gate portion SL12b3 through two vias penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (such as HG2 and HG3 in Figure 9A). The second reset wiring portion VLb is electrically connected to the junction of the first sub-gate portion SL11b1 and the third sub-gate portion SL11b3 and the junction of the second sub-gate portion SL11b2 and the third sub-gate portion SL11b3 (such as HG2 and HG3 in FIG. 9B ) through two via holes penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002. The second reset wiring portion VLb is electrically connected to the second end DT5 of the sixth active layer (such as J11 in FIG. 9A and H11 in FIG. 9B ) through a via hole penetrating the interlayer dielectric layer 1003, the second insulating layer 1002 and the first insulating layer 1001.

可选地，第三导电层103还包括第三复位走线部VLc，第二导电层还包括第一复位走线部VLa，第六导电部F6通过贯穿层间介电层1003的过孔与第一复位走线部VLa电性连接(图9A中的J12)；第三复位走线部VLc通过贯穿层间介电层1003的过孔与第一复位走线部VLa电性连接(图9A中的J13处)。Optionally, the third conductive layer 103 also includes a third reset wiring portion VLc, the second conductive layer also includes a first reset wiring portion VLa, and the sixth conductive portion F6 is electrically connected to the first reset wiring portion VLa through a via penetrating the interlayer dielectric layer 1003 (J12 in Figure 9A); the third reset wiring portion VLc is electrically connected to the first reset wiring portion VLa through a via penetrating the interlayer dielectric layer 1003 (J13 in Figure 9A).

如图10是本申请实施例提供的第四导电层的结构示意图，显示面板还包括第一平坦层和第四导电层，第一平坦层位于第三导电层103上，第四导电层位于第一平坦层上。第四导电层包括多个数据线组及多个电源线组。每一数据线组和每一电源线组交替间隔设置。FIG10 is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present application. The display panel further includes a first flat layer and a fourth conductive layer. The first flat layer is located on the third conductive layer 103, and the fourth conductive layer is located on the first flat layer. The fourth conductive layer includes a plurality of data line groups and a plurality of power line groups. Each data line group and each power line group are alternately arranged.

每一数据线组包括关于第二间距的中心线对称设置的两数据线DL。每一数据线DL包括数据走线部DL1和延伸部DL2。数据走线部DL1沿列方向y延伸，延伸部DL2和数据走线部DL1相接。延伸部DL2与第二导电部F2重叠且与第二导电部F2电性连接，以实现数据晶体管T2与数据线DL的电性连接；具体地，延伸部DL2通过贯穿第一平坦层的过孔与第二导电部F2电性连接（如图10中的PLN1处）。Each data line group includes two data lines DL symmetrically arranged about the center line of the second spacing. Each data line DL includes a data routing portion DL1 and an extension portion DL2. The data routing portion DL1 extends along the column direction y, and the extension portion DL2 is connected to the data routing portion DL1. The extension portion DL2 overlaps with the second conductive portion F2 and is electrically connected to the second conductive portion F2 to achieve electrical connection between the data transistor T2 and the data line DL; specifically, the extension portion DL2 is electrically connected to the second conductive portion F2 through a via hole penetrating the first planar layer (such as PLN1 in FIG. 10).

每一电源线组包括关于第一间距的中心线对称设置的两第一电源线VDD，以及电性连接于两第一电源线VDD之间且沿行方向x延伸的的电源连接部VDDC，电源连接部VDDC位于第一栅部远离走线部EML13的一侧。每一第一电源线VDD包括第一电源部VDD1、第二电源部VDD2及连接于第一电源部VDD1和第二电源部VDD2之间的避让部VDD3。第一电源部VDD1和第二电源部VDD2均沿列方向y延伸，避让部VDD3对应延伸部DL2设置，电源连接部VDDC与避让部VDD3远离延伸部DL2的一侧相接，以避免第一电源线VDD与数据线DL之间出现短路。第二电源部VDD2的部分与第四导电部F4重叠并与第四导电部F4电性连接，以实现第一电源线VDD与第一开关晶体管、第二电极部E2的电性连接；具体地，第二电源部VDD2通过贯穿第一平坦层的过孔与第四导电部F4电性连接（如图10中的PLN2处）。Each power line group includes two first power lines VDD symmetrically arranged about the center line of the first spacing, and a power connection portion VDDC electrically connected between the two first power lines VDD and extending along the row direction x, and the power connection portion VDDC is located on the side of the first gate portion away from the routing portion EML13. Each first power line VDD includes a first power portion VDD1, a second power portion VDD2, and a avoidance portion VDD3 connected between the first power portion VDD1 and the second power portion VDD2. The first power portion VDD1 and the second power portion VDD2 both extend along the column direction y, and the avoidance portion VDD3 is arranged corresponding to the extension portion DL2, and the power connection portion VDDC is connected to a side of the avoidance portion VDD3 away from the extension portion DL2 to avoid a short circuit between the first power line VDD and the data line DL. Part of the second power supply unit VDD2 overlaps with the fourth conductive unit F4 and is electrically connected to the fourth conductive unit F4 to achieve electrical connection between the first power line VDD and the first switching transistor and the second electrode unit E2; specifically, the second power supply unit VDD2 is electrically connected to the fourth conductive unit F4 through a via that penetrates the first planar layer (such as PLN2 in Figure 10).

可选地，第四导电层还包括多个第二节点连接部B1，每一第二节点连接部B1位于第一电源线VDD远离数据线DL的一侧，每一第二节点连接部B1与第五导电部F5重叠并与第五导电部F5电性连接，第二节点连接部B1通过贯穿第一平坦层的过孔与第五导电部F5电性连接（如图10中的PLN3处）。Optionally, the fourth conductive layer also includes a plurality of second node connection portions B1, each second node connection portion B1 is located on a side of the first power line VDD away from the data line DL, each second node connection portion B1 overlaps with the fifth conductive portion F5 and is electrically connected to the fifth conductive portion F5, and the second node connection portion B1 is electrically connected to the fifth conductive portion F5 through a via that penetrates the first planar layer (such as PLN3 in Figure 10).

发光器件对应电性连接至第二连接节点处。可选地，发光器件的阳极位于第二平坦层上，第二平坦层位于第四导电层上，像素定义层位于阳极上、发光器件的发光层位于像素定义层的暴露出阳极的像素定义区内、发光器件的阴极位于发光层上。发光器件与对应的驱动晶体管的源极和漏极电性连接于第一电压端和第二电压端之间。可选地，第一电源线电性连接于第一电压端和驱动晶体管的源极和漏极中的一个之间，第二电源线电性连接于发光器件的阴极和第二电压端之间。The light-emitting device is electrically connected to the second connection node. Optionally, the anode of the light-emitting device is located on the second flat layer, the second flat layer is located on the fourth conductive layer, the pixel definition layer is located on the anode, the light-emitting layer of the light-emitting device is located in the pixel definition area of the pixel definition layer exposing the anode, and the cathode of the light-emitting device is located on the light-emitting layer. The light-emitting device and the source and drain of the corresponding driving transistor are electrically connected between the first voltage terminal and the second voltage terminal. Optionally, the first power line is electrically connected between the first voltage terminal and one of the source and drain of the driving transistor, and the second power line is electrically connected between the cathode of the light-emitting device and the second voltage terminal.

可选地，图5C中的100b为多层复合绝缘层（即包括第一平坦层、第二平坦层和像素定义层），图5D中的100c为多层复合绝缘层（即包括层间介电层、第一平坦层、第二平坦层和像素定义层）。Optionally, 100b in FIG. 5C is a multi-layer composite insulating layer (i.e., including a first planar layer, a second planar layer and a pixel definition layer), and 100c in FIG. 5D is a multi-layer composite insulating layer (i.e., including an interlayer dielectric layer, a first planar layer, a second planar layer and a pixel definition layer).

本申请还提供一种显示装置，包括显示面板。显示装置包括可移动显示装置（如笔记本电脑、手机等）、固定终端（如台式电脑、电视等）、测量装置（如运动手环、测温仪等）等。The present application also provides a display device, including a display panel. The display device includes a mobile display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.

对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。For those skilled in the art, according to the concept of this application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

一种显示面板，其中，包括：A display panel, comprising:

多个子像素，每一所述子像素包括发光器件及像素驱动电路；所述像素驱动电路包括驱动晶体管及连接晶体管，所述驱动晶体管与所述发光器件串联于第一电源线和第二电源线之间，所述连接晶体管电性连接于所述驱动晶体管的栅极；以及A plurality of sub-pixels, each of which includes a light-emitting device and a pixel driving circuit; the pixel driving circuit includes a driving transistor and a connecting transistor, the driving transistor and the light-emitting device are connected in series between a first power line and a second power line, and the connecting transistor is electrically connected to a gate of the driving transistor; and

多条可变信号线，被配置为传输可变信号，每一所述可变信号线包括多个重叠部；a plurality of variable signal lines configured to transmit variable signals, each of the variable signal lines comprising a plurality of overlapping portions;

其中，所述连接晶体管包括：Wherein, the connecting transistor comprises:

第一有源层，包括第一沟道部、第二沟道部及连接于所述第一沟道部和所述第二沟道部之间的第一电连接部；A first active layer, comprising a first channel portion, a second channel portion, and a first electrical connection portion connected between the first channel portion and the second channel portion;

位于同行且相邻的两所述子像素镜像设置，位于同行且相邻的多个所述子像素的所述第一电连接部交替以第一间距和第二间距排布，所述第一间距小于所述第二间距；每一所述可变信号线的相邻的两所述重叠部之间间隔两所述子像素，且每一所述重叠部与两所述子像素的以所述第一间距排布的所述第一电连接部至少部分重叠形成两电容。The two adjacent sub-pixels in the same row are mirror-imaged, and the first electrical connection portions of the plurality of adjacent sub-pixels in the same row are alternately arranged at a first spacing and a second spacing, and the first spacing is smaller than the second spacing; two adjacent overlapping portions of each variable signal line are spaced apart by two sub-pixels, and each overlapping portion at least partially overlaps with the first electrical connection portions of the two sub-pixels arranged at the first spacing to form two capacitors.
根据权利要求1所述的显示面板，其中，每一所述可变信号线还包括：The display panel according to claim 1, wherein each of the variable signal lines further comprises:

多个连接部，每一所述连接部沿列方向延伸，且每一所述连接部与一所述重叠部电性连接；以及A plurality of connecting portions, each of which extends along a row direction and is electrically connected to one of the overlapping portions; and

走线部，沿行方向延伸，所述走线部与多个所述重叠部通过多个所述连接部电性连接；A routing portion extending along a row direction, wherein the routing portion is electrically connected to the plurality of overlapping portions via the plurality of connecting portions;

其中，每一所述可变信号线的相邻的两所述连接部之间间隔两所述子像素，且每一所述连接部位于两所述子像素的以所述第一间距排布的所述第一电连接部之间。Wherein, two adjacent connecting portions of each of the variable signal lines are spaced apart by two sub-pixels, and each of the connecting portions is located between the first electrical connecting portions of two sub-pixels arranged at the first pitch.
根据权利要求2所述的显示面板，其中，还包括：The display panel according to claim 2, further comprising:

多条第一扫描线，位于同行的多个所述子像素的所述连接晶体管的栅极与对应的所述第一扫描线电性连接；与位于同行的多个所述子像素的所述连接晶体管的所述栅极电性连接的所述第一扫描线包括多个第一栅部，每一所述第一栅部包括相对设置的第一子栅部和第二子栅部，以及连接于所述第一子栅部和所述第二子栅部之间的第三子栅部；a plurality of first scan lines, the gates of the connection transistors of the plurality of sub-pixels in the same row being electrically connected to the corresponding first scan lines; the first scan lines electrically connected to the gates of the connection transistors of the plurality of sub-pixels in the same row comprising a plurality of first gate portions, each of the first gate portions comprising a first sub-gate portion and a second sub-gate portion arranged opposite to each other, and a third sub-gate portion connected between the first sub-gate portion and the second sub-gate portion;

其中，所述第一子栅部和所述第二子栅部均沿所述列方向延伸，所述第三子栅部沿所述行方向延伸；所述第一子栅部和所述第二子栅部分别与两所述子像素的以所述第一间距相邻的所述第一电连接部电性连接的两所述第一沟道部重叠，所述第三子栅部与两所述子像素的以所述第一间距相邻的所述第一电连接部电性连接的两所述第二沟道部重叠；每一所述重叠部位于对应的所述第一栅部的所述第一子栅部和所述第二子栅部之间。Among them, the first sub-gate portion and the second sub-gate portion both extend along the column direction, and the third sub-gate portion extends along the row direction; the first sub-gate portion and the second sub-gate portion respectively overlap with the two first channel portions electrically connected to the first electrical connection portions adjacent to the two sub-pixels at the first spacing, and the third sub-gate portion overlaps with the two second channel portions electrically connected to the first electrical connection portions adjacent to the two sub-pixels at the first spacing; each of the overlapping portions is located between the first sub-gate portion and the second sub-gate portion of the corresponding first gate portion.
根据权利要求3所述的显示面板，其中，The display panel according to claim 3, wherein:

所述连接晶体管的源极和漏极电性连接于所述驱动晶体管的栅极和第一复位线之间；The source and drain of the connecting transistor are electrically connected between the gate of the driving transistor and the first reset line;

其中，每一所述连接部均与对应的所述第一栅部的所述第三子栅部至少部分重叠，通过所述连接部电性连接的所述走线部和所述重叠部分别位于所述第三子栅部的相对两侧。Each of the connecting portions at least partially overlaps with the corresponding third sub-gate portion of the first gate portion, and the routing portion and the overlapping portion electrically connected through the connecting portion are respectively located at two opposite sides of the third sub-gate portion.
根据权利要求4所述的显示面板，其中，在所述显示面板的厚度方向上，每一所述连接部距对应的所述第三子栅部的距离，大于每一所述连接部距对应的所述重叠部的距离。The display panel according to claim 4, wherein, in the thickness direction of the display panel, a distance between each of the connecting portions and the corresponding third sub-gate portion is greater than a distance between each of the connecting portions and the corresponding overlapping portion.
根据权利要求4所述的显示面板，其中，与位于同行的多个所述子像素的所述连接晶体管的所述栅极电性连接的所述第一扫描线还包括多个第一子走线部；The display panel according to claim 4, wherein the first scan line electrically connected to the gates of the connection transistors of the plurality of sub-pixels located in the same row further comprises a plurality of first sub-routing portions;

其中，每一所述第一子走线部的两端分别与所述第一子栅部和所述第三子栅部的相接处、所述第二子栅部和所述第三子栅部的相接处电性连接。Two ends of each of the first sub-routing portions are electrically connected to a junction between the first sub-gate portion and the third sub-gate portion, and a junction between the second sub-gate portion and the third sub-gate portion, respectively.
根据权利要求3所述的显示面板，其中，The display panel according to claim 3, wherein:

所述连接晶体管的源极和漏极电性连接于所述驱动晶体管的栅极和所述驱动晶体管的源极和漏极中的一个之间；The source and drain of the connecting transistor are electrically connected between the gate of the driving transistor and one of the source and drain of the driving transistor;

其中，每一所述连接部位于对应的所述重叠部远离所述第三子栅部的一侧，每一所述走线部位于对应的所述连接部远离所述重叠部的一侧。Wherein, each of the connecting portions is located at a side of the corresponding overlapping portion away from the third sub-gate portion, and each of the routing portions is located at a side of the corresponding connecting portion away from the overlapping portion.
根据权利要求7所述的显示面板，其中，还包括：The display panel according to claim 7, further comprising:

多条发光控制线，每一所述发光控制线沿所述行方向延伸；A plurality of light-emitting control lines, each of the light-emitting control lines extending along the row direction;

其中，每一所述发光控制线与一所述可变信号线的多个所述连接部均至少部分重叠，且在所述显示面板的厚度方向上，每一所述连接部距对应的所述发光控制线的距离大于每一所述连接部距对应的所述重叠部的距离。Among them, each of the light-emitting control lines and multiple connecting parts of a variable signal line at least partially overlap, and in the thickness direction of the display panel, the distance between each connecting part and the corresponding light-emitting control line is greater than the distance between each connecting part and the corresponding overlapping part.
根据权利要求8所述的显示面板，其中，所述像素驱动电路还包括：The display panel according to claim 8, wherein the pixel driving circuit further comprises:

发光晶体管，与所述驱动晶体管和所述发光器件串联于所述第一电源线和所述第二电源线之间；a light emitting transistor, connected in series with the driving transistor and the light emitting device between the first power line and the second power line;

其中，位于同行的多个所述子像素的所述发光晶体管的栅极与同一所述发光控制线电性连接。Wherein, the gates of the light emitting transistors of the plurality of sub-pixels in the same row are electrically connected to the same light emitting control line.
根据权利要求7所述的显示面板，其中，与位于同行的多个所述子像素的所述连接晶体管的所述栅极电性连接的所述第一扫描线还包括：The display panel according to claim 7, wherein the first scan line electrically connected to the gates of the connection transistors of the plurality of sub-pixels in the same row further comprises:

第二子走线部，沿所述行方向延伸；以及A second sub-routing portion extending along the row direction; and

多个栅连接部，每一所述栅连接部电性连接于对应的所述第一栅部和所述第二子走线部之间，每一所述栅连接部包括关于所述连接部对称的第一子栅连接部和第二子栅连接部；A plurality of gate connection portions, each of the gate connection portions being electrically connected between the corresponding first gate portion and the second sub-wiring portion, and each of the gate connection portions comprising a first sub-gate connection portion and a second sub-gate connection portion that are symmetrical about the connection portion;

其中，每一所述栅连接部的所述第一子栅连接部的第一端和所述第二子栅连接部的第一端相接且电性连接于所述第二子走线部，每一所述栅连接部的所述第一子栅连接部的第二端与对应的所述第一栅部的所述第一子栅部和所述第三子栅部的相接处电性连接，每一所述栅连接部的所述第二子栅连接部的第二端与对应的所述第一栅部的所述第二子栅部和所述第三子栅部的相接处电性连接。Among them, the first end of the first sub-gate connection portion of each of the gate connection portions is connected to the first end of the second sub-gate connection portion and is electrically connected to the second sub-routing portion, the second end of the first sub-gate connection portion of each of the gate connection portions is electrically connected to the connection between the first sub-gate portion and the third sub-gate portion of the corresponding first gate portion, and the second end of the second sub-gate connection portion of each of the gate connection portions is electrically connected to the connection between the second sub-gate portion and the third sub-gate portion of the corresponding first gate portion.
根据权利要求3所述的显示面板，其中，还包括：The display panel according to claim 3, further comprising:

第一导电层，位于所述第一有源层上，包括所述第一栅部；a first conductive layer, located on the first active layer, including the first gate portion;

第二导电层，位于所述第一导电层上，包括所述走线部和所述重叠部；以及A second conductive layer, located on the first conductive layer, including the routing portion and the overlapping portion; and

第三导电层，位于所述第二导电层上，包括所述连接部。The third conductive layer is located on the second conductive layer and includes the connecting portion.
根据权利要求11所述的显示面板，其中，The display panel according to claim 11, wherein:

所述驱动晶体管包括第二有源层；The driving transistor includes a second active layer;

所述第一导电层还包括多个第一电极部，每一所述第一电极部与所述第二有源层至少部分重叠；The first conductive layer further includes a plurality of first electrode portions, each of the first electrode portions at least partially overlapping with the second active layer;

所述第二导电层还包括多个第二电极部，每一所述第二电极部与位于两所述子像素的以所述第二间距排布的所述第一电连接部之间的两所述第一电极部至少部分重叠。The second conductive layer further includes a plurality of second electrode portions, each of which at least partially overlaps with two first electrode portions located between the first electrical connection portions of two sub-pixels arranged at the second pitch.
根据权利要求11所述的显示面板，其中，还包括：The display panel according to claim 11, further comprising:

第四导电层，位于所述第三导电层上，包括所述第一电源线。The fourth conductive layer is located on the third conductive layer and includes the first power line.
根据权利要求13所述的显示面板，其中，所述第四导电层包括多个电源线组；每一所述电源线组包括关于所述连接部对称设置的两所述第一电源线及连接于两所述第一电源线之间且沿所述行方向延伸的电源连接部；The display panel according to claim 13, wherein the fourth conductive layer comprises a plurality of power line groups; each of the power line groups comprises two first power lines symmetrically arranged about the connecting portion and a power connecting portion connected between the two first power lines and extending along the row direction;

其中，所述电源连接部位于所述第一栅部远离所述走线部的一侧。Wherein, the power connection portion is located at a side of the first gate portion away from the routing portion.