WO2024100788A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2024100788A1
WO2024100788A1 PCT/JP2022/041677 JP2022041677W WO2024100788A1 WO 2024100788 A1 WO2024100788 A1 WO 2024100788A1 JP 2022041677 W JP2022041677 W JP 2022041677W WO 2024100788 A1 WO2024100788 A1 WO 2024100788A1
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layer
semiconductor layer
active element
lower semiconductor
active
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PCT/JP2022/041677
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French (fr)
Japanese (ja)
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隼人 荒井
亘 小林
学 満原
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日本電信電話株式会社
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Priority to PCT/JP2022/041677 priority Critical patent/WO2024100788A1/en
Publication of WO2024100788A1 publication Critical patent/WO2024100788A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/12—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227—Buried mesa structure ; Striped active layer

Definitions

  • the present invention relates to a semiconductor device in which multiple optically active elements are integrated.
  • EML electroabsorption-modulator integrated distributed feedback laser
  • a DFB laser that generates light as a carrier wave and an EA modulator that modulates the carrier wave are monolithically integrated on a single semiconductor substrate (Patent Document 1, Patent Document 2).
  • a conductive polarity (mainly an n-polarity InP substrate) is used for the semiconductor substrate. Therefore, the electrical polarity of the substrate in the integrated element portion is inevitably shorted due to the structure. For this reason, when the DFB laser and EA modulator are in operation, the substrate is grounded, a positive voltage is applied to the DFB laser portion, and a negative voltage is applied to the EA modulator.
  • the EA modulator is driven by applying a single-phase modulation signal. For example, one of the electrodes of the EA modulator is connected to GND for single-phase drive.
  • differential driving has the effect of improving the S/N ratio of the optical waveform by suppressing common mode noise, and halving the modulation amplitude voltage applied to each signal line (Non-Patent Document 1).
  • the substrate side is shorted, so the DFB laser is driven in a single phase and the EA modulator cannot be driven differentially.
  • the present invention was made to solve the above problems, and aims to drive two monolithically integrated optical active elements in different ways.
  • the semiconductor device comprises a substrate made of semi-insulating InP, a first optically active element formed on the substrate, a second optically active element formed on the substrate, and an optical waveguide disposed between the first optically active element and the second optically active element and functioning as an electrical separator between the first optically active element and the second optically active element, and optically connecting the first optically active element and the second optically active element;
  • the first optically active element comprises a first lower semiconductor layer made of n-type InP formed on the substrate, a first active layer formed on the first lower semiconductor layer and having a ridge-shaped waveguide structure, an upper semiconductor layer made of p-type InP formed on the first active layer, a first p electrode formed on the upper semiconductor layer, and a first n electrode formed on the first lower semiconductor layer in an area where the first active layer is not formed;
  • the second optically active element comprises a second active layer formed on the first lower semiconductor layer and having a ridge-shaped waveguide structure.
  • the optical waveguide comprises a second lower semiconductor layer made of semi-insulating or undoped InP formed in a groove formed in the first lower semiconductor layer in the optical waveguide region, a third active layer formed on the second lower semiconductor layer and having a ridge-shaped waveguide structure, and an upper semiconductor layer formed on the third active layer.
  • the first lower semiconductor layer in the region where the second active layer is not formed is formed thinner than the first lower semiconductor layer in the region where the second active layer is formed, and comprises a buried layer formed on the first lower semiconductor layer to bury the first active layer.
  • the first n electrode is formed in the location where the buried layer has been removed, and the first lower semiconductor layer in which the first n electrode is formed has a thickness of 200 to 1000 nm.
  • the region in which the first n-electrode of the first lower semiconductor layer made of n-type InP below the first active layer is formed has a thickness of 200 to 1000 nm, so that two monolithically integrated optical active elements can be driven in different ways without causing degradation of the optical output characteristics or optical modulation characteristics.
  • FIG. 1A is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1C is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1D is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1A is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1C is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1D is a cross-sectional view showing a partial configuration of a semiconductor device according to an
  • FIG. 3A is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3B is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3C is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3D is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3E is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3F is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3D is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3E is a cross-
  • FIG. 3G is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3H is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3I is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3J is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3K is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3L is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3M is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • This semiconductor device comprises a substrate 101 made of semi-insulating InP, a first optically active element 102 formed on the substrate 101, and a second optically active element 103 formed on the substrate 101. Between the first optically active element 102 and the second optically active element 103, there is provided an optical waveguide 104 which functions as an electrical separator between the first optically active element 102 and the second optically active element 103, and which optically connects the first optically active element 102 and the second optically active element 103.
  • the substrate 101 can be made of InP that has been doped with Fe to give it high resistance.
  • the substrate 101 can have the (001) plane of InP as its main surface.
  • FIG. 1A shows a cross section parallel to the guiding direction of light as a carrier wave.
  • FIGS. 11B, 1C, and 1D show cross sections perpendicular to the guiding direction.
  • the first optically active element 102 includes a first lower semiconductor layer 121 made of n-type InP (e.g., doped at 1E18 cm -3 ) formed on a substrate 101, a first active layer 122 formed on the first lower semiconductor layer 121 to have a ridge-shaped waveguide structure, and an upper semiconductor layer 105 made of p-type InP formed on the first active layer 122.
  • the first active layer 122 can be made of, for example, InGaAsP or InGaAlAs.
  • the first active layer 122 can have a thickness of about 250 nm.
  • the first optically active element 102 also includes a first p-electrode 124 formed on the upper semiconductor layer 105 and a first n-electrode 125 formed on the first lower semiconductor layer 121 in an area where the first active layer 122 is not formed.
  • the first p-electrode 124 is formed on the upper semiconductor layer 105 via a contact layer 123.
  • the contact layer 123 can be made of, for example, InGaAs doped with a high concentration of p-type impurities.
  • the first optically active element 102 is a so-called vertical current injection type semiconductor laser that injects current into the first active layer 122 in a direction perpendicular to the plane of the substrate 101.
  • the first optically active element 102 can be a distributed feedback (DFB) laser that includes a diffraction grating on the upper surface, lower surface, or side surface of the first active layer 122.
  • the length of the first optically active element 102 in the waveguiding direction is the resonator length.
  • the second optically active element 103 includes a second active layer 132 formed on the first lower semiconductor layer 121 and having a ridge-shaped waveguide structure, and an upper semiconductor layer 105 formed on the second active layer 132.
  • the second active layer 132 can be made of, for example, InGaAsP or InGaAlAs.
  • the second active layer 132 can have a thickness of about 280 nm.
  • the second optically active element 103 also includes a second p-electrode 134 formed on the upper semiconductor layer 105, and a second n-electrode 135 formed on the first lower semiconductor layer 121 in an area where the second active layer 132 is not formed.
  • the second p-electrode 134 is formed on the upper semiconductor layer 105 via the contact layer 123.
  • the second optically active element 103 is an electroabsorption type optical modulator (EA modulator).
  • the first active layer 122 and the second active layer 132 can be a multiple quantum well structure (MQW structure).
  • the first active layer 122 and the second active layer 132 represent the part including the MQW structure and the optical confinement layers (SCH) above and below it, and also function as the core of the waveguide structure.
  • the optical waveguide 104 comprises a second lower semiconductor layer 141 made of semi-insulating or undoped InP, a third active layer 142 formed on the second lower semiconductor layer 141 and having a ridge-shaped waveguide structure, and an upper semiconductor layer 105 formed on the third active layer 142.
  • the second lower semiconductor layer 141 is formed in a groove formed in the first lower semiconductor layer 121 in the region of the optical waveguide 104 between the first optical active element 102 and the second optical active element 103.
  • the upper semiconductor layer 105 is formed in common to the first optical active element 102, the second optical active element 103, and the optical waveguide 104.
  • the third active layer 142 functions as the core of the optical waveguide 104.
  • the second lower semiconductor layer 141 and the upper semiconductor layer 105 function as cladding.
  • the third active layer 142 can be composed of, for example, InGaAsP with a composition ratio of 1.1 ⁇ m band gap wavelength.
  • the device also includes an etching stop layer 106 formed over the entire surface of the substrate 101.
  • the first optically active element 102, the optical waveguide 104, and the second optically active element 103 are formed on the etching stop layer 106.
  • the etching stop layer 106 is made of a different material than the first lower semiconductor layer 121 and the second lower semiconductor layer 141.
  • the first lower semiconductor layer 121 in the region where the second active layer 132 is not formed is formed thinner than the first lower semiconductor layer 121 in the region where the second active layer 132 is formed.
  • a buried layer 107 is provided that is formed on the first lower semiconductor layer 121 and buries the first active layer 122.
  • the buried layer 107 is composed of a p-type buried layer 107a and an n-type buried layer 107b.
  • the buried layer 107 is not limited to this and can be composed of highly resistive semi-insulating InP.
  • the first n-electrode 125 is formed in the area where the buried layer 107 has been removed, and the first lower semiconductor layer 121 in which the first n-electrode 125 is formed (in the area in which the first active layer 122 is not formed) has a thickness of 200 to 1000 nm. Furthermore, the first n-electrode 125 is formed 2 to 20 ⁇ m away from the first active layer 122.
  • the resistivity ⁇ of n-type InP is 2.7E10 ⁇ 3 ( ⁇ cm) when the doping amount is 1E18 (cm ⁇ 3 ).
  • the thickness of the first lower semiconductor layer 121 in the region where the first n-electrode 125 is formed is t ( ⁇ m)
  • the length of the first optical active element 102 in the waveguiding direction is L ( ⁇ m).
  • the distance between the first n-electrode 125 and the first active layer 122 is d ( ⁇ m).
  • Figure 2 shows the calculation results of the resistance value R when the length L in the waveguide direction is 300 ⁇ m and the thickness t is 0.2, 0.5, and 0.8 ⁇ m.
  • the thickness t of the first lower semiconductor layer 121 made of n-type InP is 0.2 ⁇ m (200 nm)
  • the distance d is 20 ⁇ m or less (2 ⁇ m ⁇ d)
  • a resistance value of 10 ⁇ or less that allows the first optical active element 102 to operate normally can be achieved.
  • the first lower semiconductor layer 121 there is a limit to the thickness of the first lower semiconductor layer 121. If the first lower semiconductor layer 121 is made too thick, the following problems will occur. As is well known, in the semiconductor device according to the embodiment, when forming the buried layer 107, the first active layer 122 is patterned into a ridge shape (high mesa shape), and the buried layer 107 is grown by crystal regrowth on the first lower semiconductor layer 121 on both sides of this.
  • the thickness of the first lower semiconductor layer 121 increases, a problem of abnormal growth occurs in which the thickness of the semiconductor layer growing at the regrowth interface increases abnormally.
  • the resistance value of the first lower semiconductor layer 121 between the first n-electrode 125 and the first active layer 122 is about 1 ⁇ , according to the calculation results shown in FIG. 2.
  • This value is sufficiently smaller than the comparison of the resistance of the LD on the SI substrate and the LD on the n substrate described in Non-Patent Document 1. In this way, according to the embodiment, it can be considered that the influence on the optical output characteristics of the first optical active element 102 can be suppressed.
  • a 10 nm thick etching stop layer 106 is formed on the substrate 101 by crystal growth of undoped InGaAsP.
  • an 800 nm thick InP layer 201 is formed by crystal growth of n-type InP (doping amount 1E18).
  • an active layer 202 is formed (crystal growth) with a thickness of 250 nm from InGaAsP.
  • the crystal growth of each semiconductor layer can be performed, for example, by the well-known metalorganic vapor phase epitaxy method. The crystal growth of each semiconductor layer shown below is similar.
  • active layer 202 in the region that will become the second optically active element 103 is removed to form active layer 202a as shown in FIG. 3B, and active layer 202b of, for example, InGaAsP with a thickness of 280 nm is formed (crystal growth) in the removed area, and active layer 202a and active layer 202b are butt-jointed in the waveguiding direction (butt-joint process).
  • active layer 202a and active layer 202b may have a multiple quantum well structure (MQW structure).
  • MQW structure multiple quantum well structure
  • the thickness is set as described above, including the optical confinement layers (SCH) above and below the MQW structure.
  • predetermined regions of active layer 202a, active layer 202b, and InP layer 201 are removed by etching using a mask pattern (not shown) formed by known photolithography technology to form first lower semiconductor layer 121 and first active layer 122 of first optical active element 102, and first lower semiconductor layer 121 and second optical active element 103, as shown in FIG. 3C.
  • the region of the first optical active element 102 and the second optical active element 103 is the region where the optical waveguide 104 is formed.
  • selective wet etching using the etching stop layer 106 can be used.
  • the etching stop layer 106 made of InGaAsP is not etched, and the layer made of InP can be selectively etched away.
  • the second lower semiconductor layer 141 and the third active layer 142 of the optical waveguide 104 are formed by crystal growth.
  • the second lower semiconductor layer 141 can be formed to a thickness of about 700 nm
  • the third active layer 142 can be formed to a thickness of about 400 nm.
  • a waveguide for the first optically active element 102 is formed by etching using a mask pattern (not shown) formed by known photolithography technology.
  • the mask pattern is shaped to cover the entire area of the second optically active element 103 and the optical waveguide 104, and the area of the second optically active element 103 and the optical waveguide 104 is not patterned.
  • the first lower semiconductor layer 121 is thinned on both sides of the ridge-shaped waveguide structure of the first active layer 122.
  • the region where the first lower semiconductor layer 121 is thinned is the region where the first n-electrode 125 is formed, and as mentioned above, the thickness is thinned to a limit of 200 nm.
  • the first optical active element 102 has an optical waveguide structure with the first active layer 122 as the core.
  • a semiconductor layer doped with a high concentration of conductive impurities n-type impurities
  • the first lower semiconductor layer 121 becomes a semiconductor layer doped with a high concentration of impurities. Therefore, if only the first active layer 122 is ridge-shaped, a semiconductor layer doped with a high concentration of impurities exists not only directly below the ridge-shaped first active layer 122 but also near both side surfaces.
  • the semiconductor layer doped with a high concentration of impurities in the regions other than directly below the first active layer 122 can be separated from the first active layer 122, making it possible to suppress the waveguide loss.
  • InP is crystal-regrown on the first lower semiconductor layer 121 remaining on both sides of the ridge-shaped waveguide structure, thereby burying the ridge-shaped waveguide structure with burying layer 107.
  • a selective growth mask (not shown) made of silicon oxide or the like is first formed on the first active layer 122.
  • p-type InP is regrown to form p-type burying layer 107a.
  • n-type InP is grown to form n-type burying layer 107b, thereby forming burying layer 107 made up of p-type burying layer 107a and n-type burying layer 107b.
  • the upper semiconductor layer 105 is formed by crystal growth of p-type InP, and then the contact layer 203 is formed by crystal growth of InGaAsP or InGaAs.
  • the contact layer 203 in the region of the optical waveguide 104 is removed by etching using a mask pattern (not shown) formed by known photolithography technology, thereby forming contact layers 123 on the first optical active element 102 and on the second optical active element 103, as shown in FIG. 3I.
  • the contact layer 123 on the first optical active element 102 and the contact layer 123 on the second optical active element 103 are formed to be electrically isolated from each other in a planar direction parallel to the surface of the upper semiconductor layer 105.
  • a first p-electrode 124 is formed on the contact layer 123 above the first optically active element 102, and a second p-electrode 134 is formed on the contact layer 123 above the second optically active element 103.
  • the second optically active element 103 and the optical waveguide 104 are patterned into a high mesa structure. Note that, similar to the region of the first optically active element 102 described above, in the second optically active element 103, the first lower semiconductor layer 121 on both sides of the high mesa waveguide structure is thinned.
  • a first n-electrode 125 is formed to electrically connect to the first lower semiconductor layer 121 of the first optical active element 102, and a second n-electrode 135 is formed to electrically connect to the first lower semiconductor layer 121 of the second optical active element 103.
  • the contact layer 123, the upper semiconductor layer 105, and the buried layer 107 in the region where the first n-electrode 125 is to be formed are patterned and removed by known lithography and etching techniques to expose the upper surface of the first lower semiconductor layer 121. Thereafter, the first n-electrode 125 is formed on the exposed upper surface of the first lower semiconductor layer 121.
  • the region in which the first n-electrode of the first lower semiconductor layer made of n-type InP below the first active layer is formed has a thickness of 200 to 1000 nm, so that two monolithically integrated optical active elements can be driven in different ways without causing degradation of the optical output characteristics or optical modulation characteristics.

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Abstract

This semiconductor device comprises: a substrate (101) composed of a semi-insulating InP; a first photoactive element (102) formed on the substrate (101); and a second photoactive element (103) formed on the substrate (101). An optical waveguide (104) is provided between the first photoactive element (102) and the second photoactive element (103), the optical waveguide (104) functioning as an electrical separation part between the first photoactive element (102) and the second photoactive element (103) and also optically connecting the first photoactive element (102) and the second photoactive element (103). The thickness of a first lower semi-conducting layer (121) of the first photoactive element (102) is 200-1000 nm.

Description

半導体装置Semiconductor Device
　本発明は、複数の光能動素子が集積された半導体装置に関する。 The present invention relates to a semiconductor device in which multiple optically active elements are integrated.
　光通信では、変調機能を有する光源が用いられている。例えば、伝送距離が１００ｋｍ以下の比較的短距離の光通信では、電界吸収型の光変調器とＤＦＢレーザとが集積されたＥＭＬ（Electroabsorption-modulater Intergrated Distributed Feedback Laser）が用いられている。 In optical communications, light sources with modulation capabilities are used. For example, in relatively short-distance optical communications with transmission distances of 100 km or less, an electroabsorption-modulator integrated distributed feedback laser (EML), which integrates an electroabsorption optical modulator and a DFB laser, is used.
　従来のＥＭＬは、搬送波としての光を生成するＤＦＢレーザと、搬送波を変調するためのＥＡ変調器とが、単一の半導体基板にモノリシックに集積されている（特許文献１、特許文献２）。この構成において、半導体基板は、導電性極性（主にｎ極性ＩｎＰ基板）が用いられている。従って、集積している各素子の部分の基板の電気極性については、構造上必然的にショートしている。このため、ＤＦＢレーザおよびＥＡ変調器の動作時は、基板をＧＮＤとし、ＤＦＢレーザ部には正極性電圧を印加し、ＥＡ変調器は負極性電圧を印加している。この構成では、ＥＡ変調器には単相の変調信号を印加して駆動することになる。例えば、ＥＡ変調器の電極の片方をＧＮＤに接続して単相駆動を行う。 In conventional EML, a DFB laser that generates light as a carrier wave and an EA modulator that modulates the carrier wave are monolithically integrated on a single semiconductor substrate (Patent Document 1, Patent Document 2). In this configuration, a conductive polarity (mainly an n-polarity InP substrate) is used for the semiconductor substrate. Therefore, the electrical polarity of the substrate in the integrated element portion is inevitably shorted due to the structure. For this reason, when the DFB laser and EA modulator are in operation, the substrate is grounded, a positive voltage is applied to the DFB laser portion, and a negative voltage is applied to the EA modulator. In this configuration, the EA modulator is driven by applying a single-phase modulation signal. For example, one of the electrodes of the EA modulator is connected to GND for single-phase drive.
特許第５８２３９２０号公報Patent No. 5823920 特許第６７１７７３３号公報Patent No. 6717733
　ところで、ＥＡ変調器の特性を最大限引き出すためには、差動駆動を行うほうが望ましい。差動駆動にはコモンモードノイズの抑制による光波形のＳ／Ｎ改善、各信号線に印加する変調振幅電圧の半減という効果があるためである（非特許文献１）。しかしながら、従来の構造では、基板側がショートしているために、ＤＦＢレーザは単相駆動し、ＥＡ変調器は差動駆動することができない。このように、従来の技術では、モノリシックに集積する２つの光能動素子を各々異なる方法で駆動することができないという問題があった。 Incidentally, to maximize the characteristics of an EA modulator, it is preferable to use differential driving. This is because differential driving has the effect of improving the S/N ratio of the optical waveform by suppressing common mode noise, and halving the modulation amplitude voltage applied to each signal line (Non-Patent Document 1). However, in the conventional structure, the substrate side is shorted, so the DFB laser is driven in a single phase and the EA modulator cannot be driven differentially. Thus, with conventional technology, there was a problem in that it was not possible to drive two monolithically integrated optical active elements in different ways.
　本発明は、以上のような問題点を解消するためになされたものであり、モノリシックに集積する２つの光能動素子を各々異なる方法で駆動することを目的とする。 The present invention was made to solve the above problems, and aims to drive two monolithically integrated optical active elements in different ways.
　本発明に係る半導体装置は、半絶縁性のＩｎＰから構成された基板と、基板の上に形成された第１光能動素子と、基板の上に形成された第２光能動素子と、第１光能動素子と第２光能動素子との間に配置され、第１光能動素子と第２光能動素子との電気分離部として機能するとともに、第１光能動素子と第２光能動素子とを光学的に接続する光導波路とを備え、第１光能動素子は、基板の上に形成されたｎ型のＩｎＰからなる第１下部半導体層、第１下部半導体層の上に形成されてリッジ状の導波路構造とされた第１活性層、第１活性層の上に形成されたｐ型のＩｎＰからなる上部半導体層、上部半導体層の上に形成された第１ｐ電極、第１活性層が形成されていない領域の第１下部半導体層の上に形成された第１ｎ電極を備え、第２光能動素子は、第１下部半導体層の上に形成されリッジ状の導波路構造とされた第２活性層、第２活性層の上に形成された上部半導体層、上部半導体層の上に形成された第２ｐ電極、第２活性層が形成されていない領域の第１下部半導体層の上に形成された第２ｎ電極を備え、光導波路は、光導波路の領域における第１下部半導体層に形成された溝に形成された半絶縁性またはアンドープのＩｎＰからなる第２下部半導体層、第２下部半導体層の上に形成されリッジ状の導波路構造とされ第３活性層、第３活性層の上に形成された上部半導体層を備え、第２活性層が形成されていない領域の第１下部半導体層は、第２活性層が形成されている領域の第１下部半導体層より薄く形成され、第１下部半導体層の上に形成されて第１活性層を埋め込む埋め込み層を備え、第１ｎ電極は、埋め込み層が除去された箇所に形成され、第１ｎ電極が形成されている第１下部半導体層は、厚さが２００～１０００ｎｍとされている。 The semiconductor device according to the present invention comprises a substrate made of semi-insulating InP, a first optically active element formed on the substrate, a second optically active element formed on the substrate, and an optical waveguide disposed between the first optically active element and the second optically active element and functioning as an electrical separator between the first optically active element and the second optically active element, and optically connecting the first optically active element and the second optically active element; the first optically active element comprises a first lower semiconductor layer made of n-type InP formed on the substrate, a first active layer formed on the first lower semiconductor layer and having a ridge-shaped waveguide structure, an upper semiconductor layer made of p-type InP formed on the first active layer, a first p electrode formed on the upper semiconductor layer, and a first n electrode formed on the first lower semiconductor layer in an area where the first active layer is not formed; and the second optically active element comprises a second active layer formed on the first lower semiconductor layer and having a ridge-shaped waveguide structure. layer, an upper semiconductor layer formed on the second active layer, a second p electrode formed on the upper semiconductor layer, and a second n electrode formed on the first lower semiconductor layer in the region where the second active layer is not formed. The optical waveguide comprises a second lower semiconductor layer made of semi-insulating or undoped InP formed in a groove formed in the first lower semiconductor layer in the optical waveguide region, a third active layer formed on the second lower semiconductor layer and having a ridge-shaped waveguide structure, and an upper semiconductor layer formed on the third active layer. The first lower semiconductor layer in the region where the second active layer is not formed is formed thinner than the first lower semiconductor layer in the region where the second active layer is formed, and comprises a buried layer formed on the first lower semiconductor layer to bury the first active layer. The first n electrode is formed in the location where the buried layer has been removed, and the first lower semiconductor layer in which the first n electrode is formed has a thickness of 200 to 1000 nm.
　以上説明したように、本発明によれば、第１活性層の下層のｎ型のＩｎＰからなる第１下部半導体層の第１ｎ電極が形成されている領域は、厚さを２００～１０００ｎｍとしたので、モノリシックに集積する２つの光能動素子を、光出力特性や光変調特性の劣化を招くことなく各々異なる方法で駆動することができる。 As described above, according to the present invention, the region in which the first n-electrode of the first lower semiconductor layer made of n-type InP below the first active layer is formed has a thickness of 200 to 1000 nm, so that two monolithically integrated optical active elements can be driven in different ways without causing degradation of the optical output characteristics or optical modulation characteristics.
図１Ａは、本発明の実施の形態に係る半導体装置の構成を示す断面図である。FIG. 1A is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. 図１Ｂは、本発明の実施の形態に係る半導体装置の一部構成を示す断面図である。FIG. 1B is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention. 図１Ｃは、本発明の実施の形態に係る半導体装置の一部構成を示す断面図である。FIG. 1C is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention. 図１Ｄは、本発明の実施の形態に係る半導体装置の一部構成を示す断面図である。FIG. 1D is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention. 図２は、導波方向の長さＬを３００μｍ、厚さｔを０．２，０．５，０．８μｍとした場合の第１ｎ電極１２５と第１活性層１２２との間の第１下部半導体層１２１の抵抗値Ｒの計算結果を示す特性図である。FIG. 2 is a characteristic diagram showing the calculation results of the resistance value R of the first lower semiconductor layer 121 between the first n-electrode 125 and the first active layer 122 when the length L in the waveguide direction is 300 μm and the thickness t is 0.2, 0.5, and 0.8 μm. 図３Ａは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3A is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｂは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3B is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｃは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3C is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｄは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3D is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｅは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3E is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｆは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3F is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｇは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3G is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｈは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3H is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｉは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3I is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｊは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3J is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｋは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3K is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｌは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3L is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図３Ｍは、本発明の実施の形態に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3M is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
　以下、本発明の実施の形態に係る半導体装置について図１Ａ、図１Ｂ、図１Ｃ、図１Ｄを参照して説明する。この半導体装置は、半絶縁性のＩｎＰから構成された基板１０１と、基板１０１の上に形成された第１光能動素子１０２と、基板１０１の上に形成された第２光能動素子１０３とを備える。第１光能動素子１０２と第２光能動素子１０３との間には、第１光能動素子１０２と第２光能動素子１０３との電気分離部として機能するとともに、第１光能動素子１０２と第２光能動素子１０３とを光学的に接続する光導波路１０４を備える。 Below, a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 1A, 1B, 1C, and 1D. This semiconductor device comprises a substrate 101 made of semi-insulating InP, a first optically active element 102 formed on the substrate 101, and a second optically active element 103 formed on the substrate 101. Between the first optically active element 102 and the second optically active element 103, there is provided an optical waveguide 104 which functions as an electrical separator between the first optically active element 102 and the second optically active element 103, and which optically connects the first optically active element 102 and the second optically active element 103.
　基板１０１は、例えば、Ｆｅをドープすることで高抵抗とされたＩｎＰから構成することができる。また、基板１０１は、ＩｎＰの（００１）面を主表面とすることができる。なお、図１Ａは、搬送波としての光の導波方向に平行な断面を示している。また、図１１Ｂ、図１Ｃ、図１Ｄは、導波方向に垂直な断面を示している。 The substrate 101 can be made of InP that has been doped with Fe to give it high resistance. The substrate 101 can have the (001) plane of InP as its main surface. Note that FIG. 1A shows a cross section parallel to the guiding direction of light as a carrier wave. Also, FIGS. 11B, 1C, and 1D show cross sections perpendicular to the guiding direction.
　第１光能動素子１０２は、基板１０１の上に形成されたｎ型のＩｎＰ（例えばドープ量１Ｅ１８ｃｍ-3）からなる第１下部半導体層１２１、第１下部半導体層１２１の上に形成されてリッジ状の導波路構造とされた第１活性層１２２、第１活性層１２２の上に形成されたｐ型のＩｎＰからなる上部半導体層１０５を備える。第１活性層１２２は、例えば、ＩｎＧａＡｓＰやＩｎＧａＡｌＡｓから構成することができる。また、第１活性層１２２は、厚さ２５０ｎｍ程度とすることができる。 The first optically active element 102 includes a first lower semiconductor layer 121 made of n-type InP (e.g., doped at 1E18 cm -3 ) formed on a substrate 101, a first active layer 122 formed on the first lower semiconductor layer 121 to have a ridge-shaped waveguide structure, and an upper semiconductor layer 105 made of p-type InP formed on the first active layer 122. The first active layer 122 can be made of, for example, InGaAsP or InGaAlAs. The first active layer 122 can have a thickness of about 250 nm.
　また、第１光能動素子１０２は、上部半導体層１０５の上に形成された第１ｐ電極１２４、第１活性層１２２が形成されていない領域の第１下部半導体層１２１の上に形成された第１ｎ電極１２５を備える。この例では、上部半導体層１０５の上にコンタクト層１２３を介して第１ｐ電極１２４が形成されている。コンタクト層１２３は、例えば、ｐ型不純物が高濃度に導入されたＩｎＧａＡｓから構成することができる。第１光能動素子１０２は、第１活性層１２２に対して基板１０１の平面に垂直な方向に電流注入を行う、いわゆる縦方向電流注入型の半導体レーザである。例えば、第１光能動素子１０２は、第１活性層１２２の上面、下面、または側面に回折格子を備える分布帰還型(Distributed Feedback：ＤＦＢ)レーザとすることができる。この場合、第１光能動素子１０２の導波方向の長さが共振器長となる。 The first optically active element 102 also includes a first p-electrode 124 formed on the upper semiconductor layer 105 and a first n-electrode 125 formed on the first lower semiconductor layer 121 in an area where the first active layer 122 is not formed. In this example, the first p-electrode 124 is formed on the upper semiconductor layer 105 via a contact layer 123. The contact layer 123 can be made of, for example, InGaAs doped with a high concentration of p-type impurities. The first optically active element 102 is a so-called vertical current injection type semiconductor laser that injects current into the first active layer 122 in a direction perpendicular to the plane of the substrate 101. For example, the first optically active element 102 can be a distributed feedback (DFB) laser that includes a diffraction grating on the upper surface, lower surface, or side surface of the first active layer 122. In this case, the length of the first optically active element 102 in the waveguiding direction is the resonator length.
　第２光能動素子１０３は、第１下部半導体層１２１の上に形成されリッジ状の導波路構造とされた第２活性層１３２、第２活性層１３２の上に形成された上部半導体層１０５を備える。第２活性層１３２は、例えば、ＩｎＧａＡｓＰやＩｎＧａＡｌＡｓから構成することができる。また、第２活性層１３２は、厚さ２８０ｎｍ程度とすることができる。 The second optically active element 103 includes a second active layer 132 formed on the first lower semiconductor layer 121 and having a ridge-shaped waveguide structure, and an upper semiconductor layer 105 formed on the second active layer 132. The second active layer 132 can be made of, for example, InGaAsP or InGaAlAs. The second active layer 132 can have a thickness of about 280 nm.
　また、第２光能動素子１０３は、上部半導体層１０５の上に形成された第２ｐ電極１３４、第２活性層１３２が形成されていない領域の第１下部半導体層１２１の上に形成された第２ｎ電極１３５を備える。この例では、上部半導体層１０５の上にコンタクト層１２３を介して第２ｐ電極１３４が形成されている。第２光能動素子１０３は、電界吸収型の光変調器（ＥＡ変調器）である。 The second optically active element 103 also includes a second p-electrode 134 formed on the upper semiconductor layer 105, and a second n-electrode 135 formed on the first lower semiconductor layer 121 in an area where the second active layer 132 is not formed. In this example, the second p-electrode 134 is formed on the upper semiconductor layer 105 via the contact layer 123. The second optically active element 103 is an electroabsorption type optical modulator (EA modulator).
　また、第１活性層１２２、第２活性層１３２は、多重量子井戸構造（ＭＱＷ構造）とすることができる。第１活性層１２２、第２活性層１３２は、ＭＱＷ構造と、この上下の光閉じ込め層（ＳＣＨ）とを含めた部分を示し、導波路構造のコアとしても機能する。 The first active layer 122 and the second active layer 132 can be a multiple quantum well structure (MQW structure). The first active layer 122 and the second active layer 132 represent the part including the MQW structure and the optical confinement layers (SCH) above and below it, and also function as the core of the waveguide structure.
　光導波路１０４は、半絶縁性またはアンドープのＩｎＰからなる第２下部半導体層１４１、第２下部半導体層１４１の上に形成されリッジ状の導波路構造とされ第３活性層１４２、第３活性層１４２の上に形成された上部半導体層１０５を備える。第２下部半導体層１４１は、第１光能動素子１０２と第２光能動素子１０３との間の、光導波路１０４の領域の第１下部半導体層１２１に形成された溝に形成されている。なお、第１光能動素子１０２、第２光能動素子１０３、光導波路１０４において、上部半導体層１０５が共通に形成されている。 The optical waveguide 104 comprises a second lower semiconductor layer 141 made of semi-insulating or undoped InP, a third active layer 142 formed on the second lower semiconductor layer 141 and having a ridge-shaped waveguide structure, and an upper semiconductor layer 105 formed on the third active layer 142. The second lower semiconductor layer 141 is formed in a groove formed in the first lower semiconductor layer 121 in the region of the optical waveguide 104 between the first optical active element 102 and the second optical active element 103. The upper semiconductor layer 105 is formed in common to the first optical active element 102, the second optical active element 103, and the optical waveguide 104.
　第３活性層１４２は、光導波路１０４のコアとして機能する。光導波路１０４において、第２下部半導体層１４１および上部半導体層１０５は、クラッドとして機能する。第３活性層１４２は、例えば、バンドギャップ波長１．１μｍの組成比としたＩｎＧａＡｓＰから構成することができる。 The third active layer 142 functions as the core of the optical waveguide 104. In the optical waveguide 104, the second lower semiconductor layer 141 and the upper semiconductor layer 105 function as cladding. The third active layer 142 can be composed of, for example, InGaAsP with a composition ratio of 1.1 μm band gap wavelength.
　また、この例では、基板１０１の上の全域に形成されたエッチングストップ層１０６を備える。第１光能動素子１０２、光導波路１０４、第２光能動素子１０３は、エッチングストップ層１０６の上に形成されている。エッチングストップ層１０６は、よく知られているように、第１下部半導体層１２１、第２下部半導体層１４１とは、異なる材料から構成する。 In this example, the device also includes an etching stop layer 106 formed over the entire surface of the substrate 101. The first optically active element 102, the optical waveguide 104, and the second optically active element 103 are formed on the etching stop layer 106. As is well known, the etching stop layer 106 is made of a different material than the first lower semiconductor layer 121 and the second lower semiconductor layer 141.
　また、第２活性層１３２が形成されていない領域の第１下部半導体層１２１は、第２活性層１３２が形成されている領域の第１下部半導体層１２１より薄く形成されている。また、第１下部半導体層１２１の上に形成されて第１活性層１２２を埋め込む埋め込み層１０７を備える。この例では、埋め込み層１０７を、ｐ型埋め込み層１０７ａとｎ型埋め込み層１０７ｂとから構成している。なお、これに限らず、埋め込み層１０７は、高抵抗な半絶縁性のＩｎＰから構成することができる。 The first lower semiconductor layer 121 in the region where the second active layer 132 is not formed is formed thinner than the first lower semiconductor layer 121 in the region where the second active layer 132 is formed. Also, a buried layer 107 is provided that is formed on the first lower semiconductor layer 121 and buries the first active layer 122. In this example, the buried layer 107 is composed of a p-type buried layer 107a and an n-type buried layer 107b. However, the buried layer 107 is not limited to this and can be composed of highly resistive semi-insulating InP.
　また、第１ｎ電極１２５は、埋め込み層１０７が除去された箇所に形成され、第１ｎ電極１２５が形成されている（第１活性層１２２が形成されていない領域の）第１下部半導体層１２１は、厚さが２００～１０００ｎｍとされている。さらに、第１ｎ電極１２５は、第１活性層１２２から２～２０μｍ離れて形成されている。 The first n-electrode 125 is formed in the area where the buried layer 107 has been removed, and the first lower semiconductor layer 121 in which the first n-electrode 125 is formed (in the area in which the first active layer 122 is not formed) has a thickness of 200 to 1000 nm. Furthermore, the first n-electrode 125 is formed 2 to 20 μm away from the first active layer 122.
　次に、第１下部半導体層１２１の厚さについて説明する。ｎ型のＩｎＰの抵抗率ρは、ドープ量１Ｅ１８（ｃｍ-3）の場合、２．７Ｅ１０-3（Ωｃｍ）である。図１Ａ、図１Ｂに示すように、第１ｎ電極１２５が形成されている領域の第１下部半導体層１２１の厚さをｔ（μｍ）、第１光能動素子１０２の導波方向の長さをＬ（μｍ）とする。また、第１ｎ電極１２５と第１活性層１２２との距離をｄ（μｍ）とする。第１ｎ電極１２５と第１活性層１２２との間の第１下部半導体層１２１の抵抗値Ｒ（Ω）は、抵抗率をρ（Ωｃｍ）として、「Ｒ＝ρ×ｄ／（Ｌ×ｔ）」で表すことができる。 Next, the thickness of the first lower semiconductor layer 121 will be described. The resistivity ρ of n-type InP is 2.7E10 −3 (Ωcm) when the doping amount is 1E18 (cm −3 ). As shown in FIG. 1A and FIG. 1B, the thickness of the first lower semiconductor layer 121 in the region where the first n-electrode 125 is formed is t (μm), and the length of the first optical active element 102 in the waveguiding direction is L (μm). In addition, the distance between the first n-electrode 125 and the first active layer 122 is d (μm). The resistance value R (Ω) of the first lower semiconductor layer 121 between the first n-electrode 125 and the first active layer 122 can be expressed as "R=ρ×d/(L×t)" with the resistivity being ρ (Ωcm).
　図２に、導波方向の長さＬを３００μｍ、厚さｔを０．２，０．５，０．８μｍとした場合の抵抗値Ｒの計算結果を示す。図２に示すように、第１光能動素子１０２の導波方向の一般的な長さ３００μｍにおいても、ｎ型ＩｎＰからなる第１下部半導体層１２１の厚さｔが０．２μｍ（２００ｎｍ）においては、距離ｄが２０μｍ以下（ただし２μｍ≦ｄ）であれば、第１光能動素子１０２が正常に動作可能な抵抗値１０Ω以下を実現することができる。図２に示すように、抵抗の低減という観点からは、第１下部半導体層１２１は、厚さ２００ｎｍを超えて厚いほど抵抗の低減が可能である。 Figure 2 shows the calculation results of the resistance value R when the length L in the waveguide direction is 300 μm and the thickness t is 0.2, 0.5, and 0.8 μm. As shown in Figure 2, even with the typical length of 300 μm in the waveguide direction of the first optical active element 102, when the thickness t of the first lower semiconductor layer 121 made of n-type InP is 0.2 μm (200 nm), if the distance d is 20 μm or less (2 μm≦d), a resistance value of 10 Ω or less that allows the first optical active element 102 to operate normally can be achieved. As shown in Figure 2, from the perspective of reducing resistance, the thicker the first lower semiconductor layer 121 is, exceeding 200 nm, the more the resistance can be reduced.
　しかしながら、第１下部半導体層１２１の厚さには限界がある。第１下部半導体層１２１を厚くしすぎると、次に示すような問題が生じる。実施の形態に係る半導体装置においては、よく知られているように、埋め込み層１０７の形成においては、第１活性層１２２をパターニングしてリッジ形状（ハイメサ形状）に形成し、この両脇の第１下部半導体層１２１の上に、結晶再成長により埋め込み層１０７を成長させている。 However, there is a limit to the thickness of the first lower semiconductor layer 121. If the first lower semiconductor layer 121 is made too thick, the following problems will occur. As is well known, in the semiconductor device according to the embodiment, when forming the buried layer 107, the first active layer 122 is patterned into a ridge shape (high mesa shape), and the buried layer 107 is grown by crystal regrowth on the first lower semiconductor layer 121 on both sides of this.
　このような、結晶再成長においては、第１下部半導体層１２１の厚さが増大すると、再成長界面で成長している半導体層の厚さが異常に増加する異常成長の問題が生じる。この問題を抑制するためには、再成長する第１下部半導体層１２１の厚さを１０００ｎｍ以下に制限することが必要である。従って、第１下部半導体層１２１は、厚さが２００～１０００ｎｍとされていることが重要となる。 In this type of crystal regrowth, if the thickness of the first lower semiconductor layer 121 increases, a problem of abnormal growth occurs in which the thickness of the semiconductor layer growing at the regrowth interface increases abnormally. To suppress this problem, it is necessary to limit the thickness of the regrown first lower semiconductor layer 121 to 1000 nm or less. Therefore, it is important that the thickness of the first lower semiconductor layer 121 is set to 200 to 1000 nm.
　例えば、第１光能動素子１０２の導波方向の長さ（共振器長）を３００μｍとし、厚さｔを５００ｎｍとし、距離をｄ（μｍ）とし、第１下部半導体層１２１のドープ量が１Ｅ18（ｃｍ-3）とすると、図２に示す計算結果より、第１ｎ電極１２５と第１活性層１２２との間の第１下部半導体層１２１の抵抗値は約１Ωとなる。この値は、非特許文献１に記載のＳＩ基板上のＬＤとｎ基板上のＬＤの抵抗の比較に比べて十分小さい値である。このように、実施の形態によれば、第１光能動素子１０２の光出力特性に与える影響を抑制可能と考えることができる。 For example, if the length (resonator length) of the first optical active element 102 in the waveguiding direction is 300 μm, the thickness t is 500 nm, the distance d (μm), and the doping amount of the first lower semiconductor layer 121 is 1E 18 (cm −3 ), the resistance value of the first lower semiconductor layer 121 between the first n-electrode 125 and the first active layer 122 is about 1Ω, according to the calculation results shown in FIG. 2. This value is sufficiently smaller than the comparison of the resistance of the LD on the SI substrate and the LD on the n substrate described in Non-Patent Document 1. In this way, according to the embodiment, it can be considered that the influence on the optical output characteristics of the first optical active element 102 can be suppressed.
　次に、本発明の実施の形態に係る半導体装置の製造方法について、図３Ａ～図３Ｍを参照して説明する。 Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 3A to 3M.
　まず、図３Ａに示すように、基板１０１の上に、アンドープＩｎＧａＡｓＰを結晶成長することで、厚さ１０ｎｍのエッチングストップ層１０６を形成する。引き続き、ｎ型のＩｎＰ（ドープ量１Ｅ１８）を結晶成長して厚さ８００ｎｍのＩｎＰ層２０１を形成する。引き続き、ＩｎＧａＡｓＰによる厚さ２５０ｎｍの活性層２０２を形成（結晶成長）する。各半導体層の結晶成長は、例えば、よく知られた有機金属気相成長法により実施することができる。以下に示す各半導体層の結晶成長も同様である。 First, as shown in FIG. 3A, a 10 nm thick etching stop layer 106 is formed on the substrate 101 by crystal growth of undoped InGaAsP. Next, an 800 nm thick InP layer 201 is formed by crystal growth of n-type InP (doping amount 1E18). Next, an active layer 202 is formed (crystal growth) with a thickness of 250 nm from InGaAsP. The crystal growth of each semiconductor layer can be performed, for example, by the well-known metalorganic vapor phase epitaxy method. The crystal growth of each semiconductor layer shown below is similar.
　次に、第２光能動素子１０３とする領域の活性層２０２を除去することで、図３Ｂに示すように、活性層２０２ａとし、除去した箇所に、例えばＩｎＧａＡｓＰによる厚さ２８０ｎｍの活性層２０２ｂを形成（結晶成長）し、導波方向に、活性層２０２ａと活性層２０２ｂとをバットジョイントさせる（バットジョイントプロセス）。なお、活性層２０２ａ、活性層２０２ｂは、多重量子井戸構造（ＭＱＷ構造）とすることができる。この場合、ＭＱＷ構造の上下の光閉じ込め層（ＳＣＨ）も含めて上述した厚さとする。 Next, the active layer 202 in the region that will become the second optically active element 103 is removed to form active layer 202a as shown in FIG. 3B, and active layer 202b of, for example, InGaAsP with a thickness of 280 nm is formed (crystal growth) in the removed area, and active layer 202a and active layer 202b are butt-jointed in the waveguiding direction (butt-joint process). Note that active layer 202a and active layer 202b may have a multiple quantum well structure (MQW structure). In this case, the thickness is set as described above, including the optical confinement layers (SCH) above and below the MQW structure.
　次に、活性層２０２ａ、活性層２０２ｂ、およびＩｎＰ層２０１の所定領域を、公知のフォトリソグラフィー技術により形成したマスクパターン（不図示）を用いたエッチング処理により除去することで、図３Ｃに示すように、第１光能動素子１０２の第１下部半導体層１２１、第１活性層１２２を形成し、第２光能動素子１０３の第１下部半導体層１２１、第２光能動素子１０３を形成する。 Next, predetermined regions of active layer 202a, active layer 202b, and InP layer 201 are removed by etching using a mask pattern (not shown) formed by known photolithography technology to form first lower semiconductor layer 121 and first active layer 122 of first optical active element 102, and first lower semiconductor layer 121 and second optical active element 103, as shown in FIG. 3C.
　第１光能動素子１０２と第２光能動素子１０３との領域が、光導波路１０４を形成する領域となる。ＩｎＰ層２０１のエッチング処理では、エッチングストップ層１０６を用いた選択的なウエットエッチングを用いることができる。例えば、ＨＣｌとＨ3ＰＯ4とをエッチング液とすることで、ＩｎＧａＡｓＰからなるエッチングストップ層１０６はエッチングされず、ＩｎＰからなる層を選択的にエッチング除去できる。 The region of the first optical active element 102 and the second optical active element 103 is the region where the optical waveguide 104 is formed. In the etching process of the InP layer 201, selective wet etching using the etching stop layer 106 can be used. For example, by using HCl and H3PO4 as an etching solution, the etching stop layer 106 made of InGaAsP is not etched, and the layer made of InP can be selectively etched away.
　次に、図３Ｄに示すように、光導波路１０４の第２下部半導体層１４１と第３活性層１４２とを、結晶成長により形成する。第２下部半導体層１４１は、厚さ７００ｎｍ程度に形成し、第３活性層１４２は、厚さ４００ｎｍ程度に形成することができる。 Next, as shown in FIG. 3D, the second lower semiconductor layer 141 and the third active layer 142 of the optical waveguide 104 are formed by crystal growth. The second lower semiconductor layer 141 can be formed to a thickness of about 700 nm, and the third active layer 142 can be formed to a thickness of about 400 nm.
　次に、公知のフォトリソグラフィー技術により形成したマスクパターン（不図示）を用いたエッチング処理により、図３Ｅに示すように、第１光能動素子１０２の導波路形成を行う。上記マスクパターンは、第２光能動素子１０３、光導波路１０４の領域は全域を覆う形状とし、第２光能動素子１０３、光導波路１０４の領域はパターニングを行わない。 Next, as shown in FIG. 3E, a waveguide for the first optically active element 102 is formed by etching using a mask pattern (not shown) formed by known photolithography technology. The mask pattern is shaped to cover the entire area of the second optically active element 103 and the optical waveguide 104, and the area of the second optically active element 103 and the optical waveguide 104 is not patterned.
　なお、この第１光能動素子１０２の加工において、第１活性層１２２のリッジ状の導波路構造の両側方の第１下部半導体層１２１を薄くする。第１下部半導体層１２１を薄くする領域は、第１ｎ電極１２５が形成される領域であり、前述したように厚さ２００ｎｍを限界として薄くする。 In the processing of the first optically active element 102, the first lower semiconductor layer 121 is thinned on both sides of the ridge-shaped waveguide structure of the first active layer 122. The region where the first lower semiconductor layer 121 is thinned is the region where the first n-electrode 125 is formed, and as mentioned above, the thickness is thinned to a limit of 200 nm.
　第１光能動素子１０２は、第１活性層１２２をコアとする光導波路構造とされているが、導波方向断面において、第１活性層１２２の近くに、導電型不純物（ｎ型不純物）が高濃度にドープされた半導体層が存在すると、よく知られているように導波損失が発生する。この場合、第１下部半導体層１２１が、不純物が高濃度にドープされた半導体層となる。このため、第１活性層１２２のみをリッジ状とすると、リッジ状の第１活性層１２２の直下に加え、両側面の近傍にも、不純物が高濃度にドープされた半導体層が存在することになる。これに対し、第１活性層１２２のリッジ状の導波路構造の両側方の第１下部半導体層１２１を薄くすることで、第１活性層１２２の直下以外の領域の不純物が高濃度にドープされた半導体層を、第１活性層１２２から離すことができ、導波損失を抑制できるようになる。 The first optical active element 102 has an optical waveguide structure with the first active layer 122 as the core. However, if a semiconductor layer doped with a high concentration of conductive impurities (n-type impurities) exists near the first active layer 122 in the cross section in the waveguide direction, a waveguide loss occurs, as is well known. In this case, the first lower semiconductor layer 121 becomes a semiconductor layer doped with a high concentration of impurities. Therefore, if only the first active layer 122 is ridge-shaped, a semiconductor layer doped with a high concentration of impurities exists not only directly below the ridge-shaped first active layer 122 but also near both side surfaces. In contrast, by thinning the first lower semiconductor layer 121 on both sides of the ridge-shaped waveguide structure of the first active layer 122, the semiconductor layer doped with a high concentration of impurities in the regions other than directly below the first active layer 122 can be separated from the first active layer 122, making it possible to suppress the waveguide loss.
　次に、図３Ｆに示すように、リッジ状の導波路構造の両側方に残した第１下部半導体層１２１の上に、ＩｎＰを結晶再成長することで、リッジ状の導波路構造を埋め込み層１０７で埋め込む。例えば、まず、第１活性層１２２の上に酸化シリコンなどから構成した選択制成長マスク（不図示）を形成する。次いで、ｐ型のＩｎＰを再成長することで、ｐ型埋め込み層１０７ａを形成する。引き続き、ｎ型のＩｎＰを成長することで、ｎ型埋め込み層１０７ｂを形成し、ｐ型埋め込み層１０７ａとｎ型埋め込み層１０７ｂとから構成した埋め込み層１０７を形成する。 Next, as shown in FIG. 3F, InP is crystal-regrown on the first lower semiconductor layer 121 remaining on both sides of the ridge-shaped waveguide structure, thereby burying the ridge-shaped waveguide structure with burying layer 107. For example, a selective growth mask (not shown) made of silicon oxide or the like is first formed on the first active layer 122. Next, p-type InP is regrown to form p-type burying layer 107a. Subsequently, n-type InP is grown to form n-type burying layer 107b, thereby forming burying layer 107 made up of p-type burying layer 107a and n-type burying layer 107b.
　次に、図３Ｇ、図３Ｈに示すように、ｐ型のＩｎＰを結晶成長することで上部半導体層１０５を形成し、さらに、ＩｎＧａＡｓＰまたはＩｎＧａＡｓを結晶成長することで、コンタクト層２０３を形成する。 Next, as shown in Figures 3G and 3H, the upper semiconductor layer 105 is formed by crystal growth of p-type InP, and then the contact layer 203 is formed by crystal growth of InGaAsP or InGaAs.
　次に、光導波路１０４の領域のコンタクト層２０３を、公知のフォトリソグラフィー技術により形成したマスクパターン（不図示）を用いたエッチング処理により除去することで、図３Ｉに示すように、第１光能動素子１０２の上および第２光能動素子１０３の上の各々にコンタクト層１２３を形成する。第１光能動素子１０２の上のコンタクト層１２３と、第２光能動素子１０３の上のコンタクト層１２３とは、上部半導体層１０５の表面に平行な面方向において、互いに電気的に分離した状態に形成する。 Next, the contact layer 203 in the region of the optical waveguide 104 is removed by etching using a mask pattern (not shown) formed by known photolithography technology, thereby forming contact layers 123 on the first optical active element 102 and on the second optical active element 103, as shown in FIG. 3I. The contact layer 123 on the first optical active element 102 and the contact layer 123 on the second optical active element 103 are formed to be electrically isolated from each other in a planar direction parallel to the surface of the upper semiconductor layer 105.
　次に、図３Ｊ、図３Ｋに示すように、第１光能動素子１０２の上のコンタクト層１２３の上に第１ｐ電極１２４を形成し、第２光能動素子１０３の上のコンタクト層１２３の上に第２ｐ電極１３４を形成する。また、図３Ｌに示すように、第２光能動素子１０３と光導波路１０４を、ハイメサ構造にパターニングする。なお、前述した第１光能動素子１０２の領域と同様に、第２光能動素子１０３においては、ハイメサの導波路構造の両側方の第１下部半導体層１２１を薄くする。 Next, as shown in Figures 3J and 3K, a first p-electrode 124 is formed on the contact layer 123 above the first optically active element 102, and a second p-electrode 134 is formed on the contact layer 123 above the second optically active element 103. Also, as shown in Figure 3L, the second optically active element 103 and the optical waveguide 104 are patterned into a high mesa structure. Note that, similar to the region of the first optically active element 102 described above, in the second optically active element 103, the first lower semiconductor layer 121 on both sides of the high mesa waveguide structure is thinned.
　次に、図３Ｍに示すように、第１光能動素子１０２の第１下部半導体層１２１に電気的に接続する第１ｎ電極１２５を形成し、第２光能動素子１０３の第１下部半導体層１２１に電気的に接続する第２ｎ電極１３５を形成する。第１ｎ電極１２５の形成においては、第１ｎ電極１２５を形成する領域のコンタクト層１２３、上部半導体層１０５、埋め込み層１０７を、公知のリソグラフィー技術およびエッチング技術によりパターニングして除去し、第１下部半導体層１２１の上面を露出させる。この後、露出した第１下部半導体層１２１の上面に第１ｎ電極１２５を形成する。 Next, as shown in FIG. 3M, a first n-electrode 125 is formed to electrically connect to the first lower semiconductor layer 121 of the first optical active element 102, and a second n-electrode 135 is formed to electrically connect to the first lower semiconductor layer 121 of the second optical active element 103. In forming the first n-electrode 125, the contact layer 123, the upper semiconductor layer 105, and the buried layer 107 in the region where the first n-electrode 125 is to be formed are patterned and removed by known lithography and etching techniques to expose the upper surface of the first lower semiconductor layer 121. Thereafter, the first n-electrode 125 is formed on the exposed upper surface of the first lower semiconductor layer 121.
　以上に説明したように、本発明によれば、第１活性層の下層のｎ型のＩｎＰからなる第１下部半導体層の第１ｎ電極が形成されている領域は、厚さを２００～１０００ｎｍとしたので、モノリシックに集積する２つの光能動素子を、光出力特性や光変調特性の劣化を招くことなく各々異なる方法で駆動することができるようになる。 As described above, according to the present invention, the region in which the first n-electrode of the first lower semiconductor layer made of n-type InP below the first active layer is formed has a thickness of 200 to 1000 nm, so that two monolithically integrated optical active elements can be driven in different ways without causing degradation of the optical output characteristics or optical modulation characteristics.
　なお、本発明は以上に説明した実施の形態に限定されるものではなく、本発明の技術的思想内で、当分野において通常の知識を有する者により、多くの変形および組み合わせが実施可能であることは明白である。 The present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be implemented by those with ordinary skill in the art within the technical concept of the present invention.
　１０１…基板、１０２…第１光能動素子、１０３…第２光能動素子、１０４…光導波路、１０５…上部半導体層、１０６…エッチングストップ層、１０７…埋め込み層、１０７ａ…ｐ型埋め込み層、１０７ｂ…ｎ型埋め込み層、１２１…第１下部半導体層、１２２…第１活性層、１２３…コンタクト層、１２４…第１ｐ電極、１２５…第１ｎ電極、１３２…第２活性層、１３４…第２ｐ電極、１３５…第２ｎ電極、１４１…第２下部半導体層、１４２…第３活性層。 101...substrate, 102...first optical active element, 103...second optical active element, 104...optical waveguide, 105...upper semiconductor layer, 106...etching stop layer, 107...buried layer, 107a...p-type buried layer, 107b...n-type buried layer, 121...first lower semiconductor layer, 122...first active layer, 123...contact layer, 124...first p-electrode, 125...first n-electrode, 132...second active layer, 134...second p-electrode, 135...second n-electrode, 141...second lower semiconductor layer, 142...third active layer.

Claims (3)

  1. 　半絶縁性のＩｎＰから構成された基板と、
    　前記基板の上に形成された第１光能動素子と、前記基板の上に形成された第２光能動素子と、前記第１光能動素子と前記第２光能動素子との間に配置され、前記第１光能動素子と前記第２光能動素子との電気分離部として機能するとともに、前記第１光能動素子と前記第２光能動素子とを光学的に接続する光導波路とを備え、
    　前記第１光能動素子は、前記基板の上に形成されたｎ型のＩｎＰからなる第１下部半導体層、前記第１下部半導体層の上に形成されてリッジ状の導波路構造とされた第１活性層、前記第１活性層の上に形成されたｐ型のＩｎＰからなる上部半導体層、前記上部半導体層の上に形成された第１ｐ電極、前記第１活性層が形成されていない領域の前記第１下部半導体層の上に形成された第１ｎ電極を備え、
    　前記第２光能動素子は、前記第１下部半導体層の上に形成されリッジ状の導波路構造とされた第２活性層、前記第２活性層の上に形成された前記上部半導体層、前記上部半導体層の上に形成された第２ｐ電極、前記第２活性層が形成されていない領域の前記第１下部半導体層の上に形成された第２ｎ電極を備え、
    　前記光導波路は、前記光導波路の領域における前記第１下部半導体層に形成された溝に形成された半絶縁性またはアンドープのＩｎＰからなる第２下部半導体層、前記第２下部半導体層の上に形成されリッジ状の導波路構造とされ第３活性層、前記第３活性層の上に形成された前記上部半導体層を備え、
    　前記第２活性層が形成されていない領域の前記第１下部半導体層は、前記第２活性層が形成されている領域の前記第１下部半導体層より薄く形成され、
    　前記第１下部半導体層の上に形成されて前記第１活性層を埋め込む埋め込み層を備え、
    　前記第１ｎ電極は、前記埋め込み層が除去された箇所に形成され、
    　前記第１ｎ電極が形成されている前記第１下部半導体層は、厚さが２００～１０００ｎｍとされている
    　ことを特徴とする半導体装置。     A substrate made of semi-insulating InP;
    a first optically active element formed on the substrate; a second optically active element formed on the substrate; and an optical waveguide disposed between the first optically active element and the second optically active element, the optical waveguide functioning as an electrical separator between the first optically active element and the second optically active element and optically connecting the first optically active element and the second optically active element;
    The first optical active element includes a first lower semiconductor layer made of n-type InP formed on the substrate, a first active layer formed on the first lower semiconductor layer to have a ridge-shaped waveguide structure, an upper semiconductor layer made of p-type InP formed on the first active layer, a first p-electrode formed on the upper semiconductor layer, and a first n-electrode formed on the first lower semiconductor layer in a region where the first active layer is not formed,
    the second optically active element includes a second active layer formed on the first lower semiconductor layer and having a ridge-shaped waveguide structure, the upper semiconductor layer formed on the second active layer, a second p-electrode formed on the upper semiconductor layer, and a second n-electrode formed on the first lower semiconductor layer in an area where the second active layer is not formed;
    the optical waveguide comprises a second lower semiconductor layer made of semi-insulating or undoped InP formed in a groove formed in the first lower semiconductor layer in a region of the optical waveguide, a third active layer formed on the second lower semiconductor layer and having a ridge-shaped waveguide structure, and the upper semiconductor layer formed on the third active layer;
    the first lower semiconductor layer in a region where the second active layer is not formed is formed thinner than the first lower semiconductor layer in a region where the second active layer is formed,
    a buried layer formed on the first lower semiconductor layer to bury the first active layer;
    the first n-electrode is formed in a portion where the buried layer has been removed,
    the first lower semiconductor layer on which the first n-electrode is formed has a thickness of 200 to 1000 nm.
  2. 　請求項１記載の半導体装置において、
    　前記第１ｎ電極は、前記第１活性層から２～２０μｍ離れて形成されていることを特徴とする半導体装置。     2. The semiconductor device according to claim 1,
    The first n-electrode is formed at a distance of 2 to 20 μm from the first active layer.
  3. 　請求項１または２記載の半導体装置において、
    　前記基板の上の全域に形成されたエッチングストップ層を備え、
    　前記第１光能動素子、前記光導波路、前記第２光能動素子は、前記エッチングストップ層の上に形成されていることを特徴とする半導体装置。     3. The semiconductor device according to claim 1,
    an etch stop layer formed over the entire surface of the substrate;
    2. A semiconductor device comprising: a first optical active element, an optical waveguide, and a second optical active element, the first optical active element being formed on the etching stop layer.
PCT/JP2022/041677 2022-11-09 2022-11-09 Semiconductor device WO2024100788A1 (en)

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JP2015072980A (en) * 2013-10-02 2015-04-16 富士通株式会社 Optical semiconductor element, optical semiconductor element array, optical transmission module and optical transmission system
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