WO2024098558A1 - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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Publication number
WO2024098558A1
WO2024098558A1 PCT/CN2023/073551 CN2023073551W WO2024098558A1 WO 2024098558 A1 WO2024098558 A1 WO 2024098558A1 CN 2023073551 W CN2023073551 W CN 2023073551W WO 2024098558 A1 WO2024098558 A1 WO 2024098558A1
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WO
WIPO (PCT)
Prior art keywords
circuit
pixel circuit
display area
light
area
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Application number
PCT/CN2023/073551
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English (en)
French (fr)
Inventor
马扬昭
代好
Original Assignee
武汉天马微电子有限公司
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Publication of WO2024098558A1 publication Critical patent/WO2024098558A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • the present application relates to the field of display technology, for example, to a display panel and a display device.
  • the photosensitive element is usually built into the bottom of the screen, and by adjusting the pixel design of the photosensitive functional area, the area can be both display- and light-transmitting, thereby enabling the display device to have both full-screen display and front-facing photosensitive functions.
  • the present application provides a display panel and a display device, so as to improve the display effect of a first display area while ensuring the light transmittance of the first display area.
  • a display panel comprising a first display area and a second display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area;
  • the first display area includes a plurality of first light-emitting elements
  • the second display area includes a plurality of second light-emitting elements, and the distribution density of the first light-emitting elements and the second light-emitting elements is the same;
  • the second display area includes a plurality of first pixel circuits and a plurality of second pixel circuits; the first pixel circuits are electrically connected to the first light-emitting elements in a one-to-one correspondence; and the second pixel circuits are electrically connected to the second light-emitting elements in a one-to-one correspondence.
  • a display device comprising the display panel provided by any embodiment of the present application.
  • FIG1 is a schematic structural diagram of a display panel in the related art
  • FIG2 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • FIG3 is an enlarged structural schematic diagram of a display panel provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG12 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG13 is a schematic diagram of an enlarged structure of a display panel corresponding to the area Q4 in FIG12;
  • FIG14 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application.
  • FIG15 is a schematic diagram of an enlarged structure of another display panel corresponding to the area Q4 in FIG12;
  • FIG16 is a schematic diagram of an enlarged structure of another display panel corresponding to the area Q4 in FIG12 ;
  • FIG17 is a schematic diagram of an enlarged structure of another display panel corresponding to the area Q4 in FIG12 ;
  • FIG18 is an enlarged structural schematic diagram of another display panel corresponding to the area Q4 in FIG12 ;
  • FIG19 is a schematic diagram of an enlarged structure of another display panel corresponding to the area Q4 in FIG12;
  • FIG20 is a schematic diagram of an enlarged structure of another display panel corresponding to the area Q4 in FIG12;
  • FIG21 is an enlarged structural schematic diagram of another display panel corresponding to the area Q4 in FIG12;
  • FIG22 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG23 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application.
  • FIG. 24 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • FIG1 is a schematic diagram of the structure of a display panel in the related art.
  • the display area FA of the display panel includes a first area Q1, a second area Q2 and a third area Q3, and the second area Q2 is located between the first area Q1 and the third area Q3.
  • the first area Q1 is the above-mentioned photosensitive functional area, which has both display and photosensitive functions, and can realize photosensitive functions such as front camera or fingerprint recognition.
  • the second area Q2 and the third area Q3 are areas with only display functions.
  • the display panel realizes the display function by emitting light from sub-pixels arranged in an array.
  • the sub-pixels include light-emitting elements and pixel circuits for driving the light-emitting elements to emit light.
  • the correspondence between the light-emitting elements and the pixel circuits can be one pixel circuit corresponding to one light-emitting element, or one pixel circuit corresponding to at least two light-emitting elements.
  • the pixel circuits are usually set to correspond one to one with the light-emitting elements.
  • the pixel circuit corresponding to the light-emitting element in the first zone Q1 is set in the second zone Q2 (i.e., the above-mentioned transition zone). In this way, it is necessary to compress the size of the pixel circuit corresponding to the light-emitting element of the first zone Q1 and the light-emitting element of the second zone Q2 so that this part of the pixel circuit can be integrated in the second zone Q2. Since the area of the second zone Q2 is small, the compression space of the pixel circuit is limited.
  • An embodiment of the present application provides a display panel, including a first display area and a second display area, the transmittance of the first display area is greater than the transmittance of the second display area;
  • the first display area includes a plurality of first light-emitting elements
  • the second display area includes a plurality of second light-emitting elements, and the distribution density of the first light-emitting elements and the second light-emitting elements is the same;
  • the second display area includes a plurality of first pixel circuits and a plurality of second pixel circuits; the first pixel circuits and the first light-emitting elements are electrically connected in a one-to-one correspondence; the second pixel circuits and the second light-emitting elements are electrically connected in a one-to-one correspondence.
  • the transmittance requirement of the first display area can be guaranteed. Since the space of the second display area is more sufficient, the first pixel circuit corresponding to the first light-emitting element in the first display area and the second pixel circuit corresponding to the second light-emitting element in the second display area can be arranged in the second display area by compressing the size of at least part of the pixel circuit, and the first pixel circuit is electrically connected to the first light-emitting element in a one-to-one correspondence, and the second pixel circuit is electrically connected to the second light-emitting element in a one-to-one correspondence. Since the distribution density of the first light-emitting element and the second light-emitting element is the same, the first display area and the second display area can have the same display PPI, thereby improving the display effect of the first display area.
  • Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present application
  • Figure 3 is an enlarged structural schematic diagram of a display panel provided by an embodiment of the present application.
  • the display panel 100 provided by the embodiment of the present application includes a first display area S1 and a second display area S2, and the transmittance of the first display area S1 is greater than the transmittance of the second display area S2;
  • the first display area S1 includes a plurality of first light-emitting elements P1, and the second display area S2 includes a plurality of second light-emitting elements P2, and the distribution density of the first light-emitting elements P1 and the second light-emitting elements P2 is the same;
  • the second display area S2 includes a plurality of first pixel circuits C1 and a plurality of second pixel circuits C2;
  • the first pixel circuits C1 and the first light-emitting elements P1 are electrically connected in a one-to-one correspondence;
  • the first display area S1 is the above-mentioned photosensitive functional area, which can be used to realize photosensitive functions such as front camera and fingerprint recognition, and has display functions.
  • the second display area S2 is the display area of the total display area FA of the display panel except the first display area S1, which has display functions.
  • FIG2 only illustrates an example in which the display panel includes a first display area S1, and the first display area S1 is located inside the total display area FA of the display panel.
  • the display panel may include a greater number of first display areas S1, and any first display area S1 may be adjacent to at least one edge of the total display area FA of the display panel.
  • the embodiment of the present application does not specifically limit the number and location of the first display areas S1.
  • the first display area S1 includes a plurality of first light-emitting elements P1
  • the second display area S2 includes a plurality of second light-emitting elements P2.
  • the distribution density of the first light-emitting elements P1 and the second light-emitting elements P2 is the same. In other words, the number of the first light-emitting elements P1 and the second light-emitting elements P2 in the same space is the same.
  • the plurality of first light-emitting elements P1 may include at least two light-emitting elements with different luminous colors
  • the plurality of second light-emitting elements P2 may include at least two light-emitting elements with different luminous colors to achieve color display.
  • the first light-emitting element P1 and the second light-emitting element P2 both include a red light-emitting element R with a red luminous color, a green light-emitting element G with a green luminous color, and a blue light-emitting element B with a blue luminous color.
  • the first light-emitting element P1 and the second light-emitting element P2 have the same distribution density, which can be understood as follows: in the first display area S1 and the second display area S2, the number of red light-emitting elements R in the same space is the same, the number of green light-emitting elements G in the same space is the same, and the number of blue light-emitting elements B in the same space is the same, that is, the distribution density of light-emitting elements with the same luminous color is the same in the first display area S1 and the second display area S2.
  • the areas of the first light-emitting element P1 and the second light-emitting element P2 with the same light-emitting color in the first display area S1 and the second display area S2 may be equal or unequal.
  • the area of the first light-emitting element P1 may be set to be smaller than the area of the second light-emitting element P2 with the same light-emitting color.
  • the area of the first light-emitting element P1 may be appropriately increased so that the area of the first light-emitting element P1 is larger than the area of the second light-emitting element P2 with the same light-emitting color.
  • the area of the second light-emitting element P2 with the same light color is not limited in this embodiment of the present application.
  • the arrangement of the first light emitting element P1 and the second light emitting element P2 is only for illustration and not for limitation. Those skilled in the art can set the pixel arrangement as required, and the embodiment of the present application does not limit this, as long as the distribution density of the first light emitting element P1 and the second light emitting element P2 is the same.
  • the first light-emitting element P1 and the second light-emitting element P2 are organic light-emitting diodes (OLED).
  • OLED organic light-emitting diodes
  • the OLED includes an anode, a light-emitting layer, and a cathode that are stacked.
  • the shape of the first light-emitting element P1 or the second light-emitting element P2 shown in FIG2 can be understood as the shape of the positive projection of the anode in the light-emitting element on the plane where the display panel is located. It should be noted that in the display panel shown in FIG2, the first light-emitting element P1 and the second light-emitting element P2 with the same luminous color have the same shape, and both are polygonal, which is only for illustration and not for limitation.
  • FIG4 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • the first light-emitting element P1 includes a first anode D1
  • the shape of the orthographic projection of the first anode D1 on the plane where the display panel is located is circular.
  • Such a configuration can improve the diffraction phenomenon of the first display area S1, which is conducive to improving the imaging quality of the photosensitive element arranged below the display panel corresponding to the first display area S1.
  • the shape of the first anode of the first light-emitting element P1 can also be quasi-circular, such as an elliptical shape, which is not limited in the embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application.
  • the second display area S2 includes a first display area S21 and a second display area S22, and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first display area S21 is located in the second display area S22.
  • the first display area S21 is provided with a plurality of second light-emitting elements P2, but the second pixel circuit C2 corresponding to this part of the second light-emitting elements P2 is not provided.
  • the first display area S21 also has a certain light transmittance and can be used as a photosensitive functional area, and a photosensitive element is provided below the display panel corresponding to the first display area S21.
  • the first display area S1 corresponds to the camera area
  • the first display area portion S21 corresponds to the area where other photosensitive elements are located, for example, a photosensitive element whose requirements for incident light are lower than those of the camera for face recognition (Face ID).
  • the transmittance of the first display area portion S21 may be lower than the transmittance of the first display area S1.
  • the diffraction phenomenon of light has little effect on the face recognition result.
  • the second light-emitting element P2 in the first display area portion S21 can maintain the same area and polygonal shape as the second light-emitting element P2 in the second display area portion S22, and there is no need to adjust it to a circular or quasi-circular shape to improve diffraction.
  • the pixel circuit for driving the first light-emitting element P1 to emit light is called the first pixel circuit C1
  • the pixel circuit for driving the second light-emitting element P2 to emit light is called the second pixel circuit C2
  • the first pixel circuit C1 and the second pixel circuit C2 can be pixel circuits composed of thin film transistors and storage capacitors, such as the 7T1C (T represents a thin film transistor, and C represents a capacitor) pixel circuit commonly used in the industry, which is not limited in the embodiment of the present application.
  • the first pixel circuit C1 corresponding to the first light-emitting element P1 and the second pixel circuit C2 corresponding to the second light-emitting element P2 are both arranged in the second display area S2, so that the first light-emitting element P1 is arranged in the first display area S1 but the first pixel circuit C1 is not arranged, thereby ensuring the transmittance requirement of the first display area S1.
  • the size of at least part of the pixel circuit (the first pixel circuit C1 and/or the second pixel circuit C2) can be compressed to achieve the arrangement of the first pixel circuit C1 and the second pixel circuit C2 in the second display area S2, while ensuring that the first pixel circuit C1 and the first light-emitting element P1 are electrically connected in a one-to-one correspondence, and the second pixel circuit C2 and the second light-emitting element P2 are electrically connected in a one-to-one correspondence, so as to achieve a one-to-one driving of the pixel circuit to the light-emitting element.
  • the one-to-one driving is conducive to improving the light-emitting brightness of the first light-emitting element P1. , ensuring that the actual luminance of the first light-emitting element P1 reaches the expected brightness, thereby improving the display effect of the first display area S1; in addition, while ensuring the luminance of each light-emitting element, if a pixel circuit drives multiple light-emitting elements to emit light, it is necessary to improve the driving capability of the pixel circuit.
  • the embodiment of the present application sets the first pixel circuit C1 to be electrically connected to the first light-emitting element P1 in a one-to-one correspondence, and the second pixel circuit C2 to be electrically connected to the second light-emitting element P2 in a one-to-one correspondence, which is beneficial to reducing the requirements on the driving capability of the pixel circuit and extending the service life of the components in the pixel circuit; in addition, by setting the pixel circuit to drive the light-emitting element one-to-one, it is beneficial to more flexibly adjust the luminance of multiple light-emitting elements individually and improve the display effect.
  • the first display area S1 and the second display area S2 can have the same display PPI, effectively improving the display effect of the first display area S1.
  • the distribution density of the first light-emitting element P1 and the second light-emitting element P2 is the same, if a first pixel circuit C1 drives multiple first light-emitting elements P1 at the same time, and a second pixel circuit C2 drives one second light-emitting element P2, when the driving capabilities of the first pixel circuit C1 and the second pixel circuit C2 are the same, the luminous brightness of the multiple first light-emitting elements P1 in the first display area S1 is only equivalent to the luminous brightness of one second light-emitting element P2 in the second display area S2, resulting in the number of actual display pixels per inch in the first display area S1 being lower than the number of actual display pixels per inch in the second display area S2, resulting in poor display effect of the first display area S1.
  • the first pixel circuit C1 and the first light emitting element P1 are electrically connected in a one-to-one correspondence
  • the second pixel circuit C2 and the second light emitting element P2 are electrically connected in a one-to-one correspondence
  • the distribution density of the first light emitting element P1 and the second light emitting element P2 is set to be the same, so that the first display area
  • the display pixels per inch of S1 and the second display area S2 are consistent, so that the two have the same display PPI, which effectively improves the display effect of the first display area.
  • the size of the pixel circuit can be compressed by reducing the line width, line spacing, etc. in the pixel circuit.
  • the display panel includes a plurality of scan lines and a plurality of data lines, the extension directions of the scan lines and the data lines intersect, and the scan lines and the data lines overlap and are electrically connected to the setting area of the pixel circuit.
  • the size of the pixel circuit can be compressed by compressing the length of the pixel circuit along the extension direction of the scan lines, and/or by compressing the length of the pixel circuit along the extension direction of the data lines.
  • the length of the pixel circuit along the extension direction of the data lines can be compressed by compressing the width of the scan lines along the extension direction of the data lines, and/or by compressing the distance between two adjacent scan lines in the extension direction of the data lines.
  • the length of the pixel circuit along the extension direction of the scan lines can be compressed by compressing the width of the data lines or the power supply PVDD signal lines along the extension direction of the scan lines, and/or by compressing the distance between at least one pair of signal lines among two adjacent data lines, two adjacent PVDD signal lines, and two adjacent data lines and PVDD signal lines in the extension direction of the scan lines.
  • the first light-emitting element P1 and the first pixel circuit C1 corresponding thereto are located in different regions, and the two can be electrically connected by a connecting line 8.
  • the light-emitting element (first light-emitting element P1/second light-emitting element P2) and the pixel circuit (first pixel circuit C1/second pixel circuit C2) overlapping the two ends of a connecting line 8 represent the pixel circuit and the light-emitting element connected by the connecting line (hereinafter the same).
  • the first light-emitting element P1-1 is electrically connected to the first pixel circuit C1-1 by the connecting line 8.
  • the area of the first display area S1 is much smaller than the area of the second display area S2, it may only be necessary to adjust the area and position of part of the second pixel circuit C2 to achieve the setting of the first pixel circuit C1 in the second display area S2.
  • the relative position relationship between part of the second light-emitting element P2 and the corresponding second pixel circuit C2 has not been adjusted, and the two still overlap in the direction perpendicular to the plane where the display panel is located, so the two can be electrically connected by a via.
  • FIG3 shows that a second light-emitting element P2 overlaps with a second pixel circuit C2, and both overlap with a solid dot at the same time, indicating that the second light-emitting element P2 is electrically connected to the second pixel circuit C2 (the same below).
  • the second light-emitting element P2-1 overlaps with the second pixel circuit C2-1, and both overlap with a solid dot, indicating that the second light-emitting element P2-1 is electrically connected to the second pixel circuit C2-1.
  • first pixel circuit C1 and the second pixel circuit C2 shown in FIG3 is only for illustration and not for limitation.
  • the first pixel circuit C1 and the second pixel circuit C2 can be distributed in the second display area S2 in any manner, which is not limited in the embodiment of the present application and will be described exemplarily later.
  • a second light-emitting element P2 can also be electrically connected to at least one second pixel circuit C2 adjacent to it but not electrically connected thereto.
  • the embodiment of the present application sets a display panel including a first display area and a second display area, and sets the first display area to include a plurality of first light-emitting elements, and the second display area to include a plurality of second light-emitting elements, a plurality of first pixel circuits, and a plurality of second pixel circuits, so that the distribution density of the first light-emitting elements and the second light-emitting elements is the same, and the first pixel circuits and the first light-emitting elements are electrically connected one-to-one, and the second pixel circuits and the second light-emitting elements are electrically connected one-to-one.
  • the transmittance requirement of the first display area can be guaranteed. Since the space in the second display area is more sufficient, the size of at least part of the pixel circuits can be compressed, and the first pixel circuit corresponding to the first light-emitting element in the first display area and the second pixel circuit corresponding to the second light-emitting element in the second display area are both set in the second display area, and one first pixel circuit drives one first light-emitting element, and one second pixel circuit drives one second light-emitting element. Since the distribution density of the first light-emitting element and the second light-emitting element is the same, the first display area and the second display area can have the same display PPI, thereby improving the display effect of the first display area.
  • Figure 6 is a structural schematic diagram of another display panel provided in an embodiment of the present application.
  • the second display area S2 includes a first sub-display area 1 and a second sub-display area 2, the first sub-display area 1 is adjacent to the first display area S1, and the second sub-display area 2 is adjacent to the first sub-display area 1; a second pixel circuit C2 corresponding to at least one second light-emitting element P2 of the first sub-display area 1 (such as the second light-emitting element P2-1 and the second light-emitting element P2-2 in Figure 6) is located in the second sub-display area 2.
  • a second pixel circuit C2 corresponding to at least one second light-emitting element P2 of the first sub-display area 1 (such as the second light-emitting element P2-1 and the second light-emitting element P2-2 in Figure 6) is located in the second sub-display area 2.
  • Figure 6 takes the first light-emitting element P1 as a circle and the second light-emitting element P2 as a diamond as an example, schematically illustrates part of the first light-emitting element P1 and part of the second light-emitting element P2, and displays the electrical connection relationship between the first light-emitting element P1 and the first pixel circuit C1, the electrical connection relationship between the second light-emitting element P2 and the second pixel circuit C2, and the areas where the first pixel circuit C1 and the second pixel circuit C2 are located.
  • the arrangement of the first light-emitting element P1 and the second light-emitting element P2 and the arrangement of the first pixel circuit C1 and the second pixel circuit C2 in Figure 6 do not represent a limitation on the actual arrangement.
  • the first sub-display area 1 may be adjacent to at least part of the boundary of the first display area S1.
  • FIG6 only illustrates the case where the first sub-display area 1 is adjacent to the entire boundary of the first display area S1.
  • the first display area S1 is adjacent to only the first sub-display area 1
  • the second sub-display area 2 is adjacent to only the first sub-display area 1.
  • FIG7 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. As shown in FIG7, in other embodiments, the first sub-display area 1 may be adjacent to part of the boundary of the first display area S1. In this case, the second sub-display area 2 is also adjacent to the first display area S1.
  • the pixel circuits corresponding to the light emitting elements in the same row are misaligned in the second direction y, and are more dispersed in the display panel.
  • the scanning line Gate needs to be wound so that one scanning line is electrically connected to the pixel circuits corresponding to the light emitting elements in the same row.
  • a scan signal is sent to the pixel circuit corresponding to the light-emitting element in the same row through the scan line, so that the light-emitting elements in the same row are lit at the same time.
  • the first pixel circuit C1 is set in the first sub-display area 1 adjacent to the first display area S1 along the first direction x, the data line needs to be wound so that in the display driving process, the data signal is sent to the pixel circuit corresponding to the light-emitting element in the same column through the data line.
  • this embodiment can reduce the dispersion of the pixel circuits corresponding to the light-emitting elements in the same row or the same column in the display panel by externalizing the second pixel circuit C2 corresponding to at least one second light-emitting element P2 in the first sub-display area 1 adjacent to the first display area S1 in the second sub-display area 2, thereby reducing or avoiding the winding degree of the signal line (such as the scan line, the data line), thereby reducing the difficulty of setting the signal line.
  • the signal line such as the scan line, the data line
  • the area corresponding to the second light-emitting element P2 of the second sub-display area 2 where the second pixel circuit C2 in the first sub-display area 1 is externally placed can be reused as the above-mentioned first display area portion S21, so as to utilize this area to realize functions such as face recognition, thereby enriching the functional diversity of the display device.
  • Figure 8 is a structural schematic diagram of another display panel provided in an embodiment of the present application.
  • the first sub-display area 1 includes a first partition 11 and a second partition 12, the first partition 11 and the first display area S1 are adjacent along a first direction x, the second partition 12 and the first display area S1 are adjacent along a second direction y, and the first direction x and the second direction y intersect; the first pixel circuit C1 is located in at least one of the first partition 11 and the second partition 12.
  • the first direction x and the second direction y are orthogonal, and such a setting facilitates to simplify the difficulty of re-layout of the first pixel circuit C1 and the second pixel circuit C2.
  • FIG8 is only illustrated by taking the first direction x as the row direction and the second direction y as the column direction as an example.
  • the first direction x may be the column direction and the second direction y may be the row direction, and the embodiment of the present application is not limited to this.
  • the row direction may be consistent with the extension direction of the scan line
  • the column direction may be consistent with the extension direction of the data line. The following description will only be given by taking the first direction x as the row direction and the second direction y as the column direction as an example.
  • the first sub-display area 1 may include at least one first partition 11 and at least one second partition 12.
  • the first display area S1 is located inside the total display area FA of the display panel.
  • the first sub-display area 1 includes two first partitions 11 located on opposite sides of the first display area S1 along the first direction x, and two second partitions 12 located on opposite sides of the first display area S1 along the second direction y.
  • This setting is for illustration only and is not limiting.
  • the first sub-display area 1 may include two first partitions 11 adjacent to the first display area S1 along the first direction x and one second partition 12 adjacent to the first display area S1 along the second direction y.
  • all the first pixel circuits C1 may be arranged in the first partition 11; or all the first pixel circuits C1 may be arranged in the second partition 12; or a part of the first pixel circuits C1 may be arranged in the first partition 11, and another part of the first pixel circuits C1 may be arranged in the second partition 12, which is not limited in the embodiments of the present application.
  • FIG8 illustrates the case where all first pixel circuits C1 are located in the first partition 11.
  • FIG9 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. As shown in FIG9, in other embodiments, the first pixel circuits C1 may be located in the second partition 12. In addition, referring to FIG6, a plurality of first pixel circuits C1 may be respectively located in the first partition 11 and the second partition 12.
  • the embodiment of the present application arranges the first pixel circuit C1 in at least one of the first partition 11 and the second partition 12 adjacent to the first display area S1, thereby reducing the difficulty of connecting the first pixel circuit C1 with the first light-emitting element P1 and the difficulty of wiring in the display panel, thereby reducing the impact on the product yield.
  • the first pixel circuit C1 can be set in at least one of the first partitions 11 as needed.
  • the first pixel circuit C1 can be set in at least one of the second partitions 12 as needed.
  • the embodiment of the present application is not limited to this.
  • FIG. 8 only illustrates the example that the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first partition 11 is still located in the first partition 11, and FIG.
  • the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second partition 12 is still located in the second partition 12.
  • the second pixel circuit C2 corresponding to at least one second light-emitting element P2 in the first partition 11 and/or the second partition 12 can be set in the second sub-display area 2 with reference to FIG. 6.
  • the maximum width H4 of the first display area S1 along the first direction x is equal to the maximum width H2 of the second partition 12 along the first direction x; the maximum width H3 of the first display area S1 along the second direction y is equal to the maximum width H1 of the first partition 11 along the second direction y.
  • the first pixel circuit C1 can be arranged in at least one of the first partition 11 and the second partition 12 by translating and compressing the size of the first pixel circuit C1 and/or the second pixel circuit C2, which is conducive to reducing the layout difficulty of the pixel circuit and the wiring difficulty of the display panel, and reducing the impact on the product yield.
  • FIG6 is only for illustration of the first display area S1 being a rectangle, and is not intended to be limiting.
  • FIG10 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. As shown in FIG10 , in other embodiments, the first display area S1 may also be a circle. Of course, the first display area S1 may also be any other shape known to those skilled in the art, and the embodiment of the present application does not limit this.
  • the first sub-display area 1 can also be set to include a first partition 11 and a second partition 12, the first partition 11 and the first display area S1 are adjacent to each other along the first direction x, the second partition 12 and the first display area S1 are adjacent to each other along the second direction y, the maximum width H4 of the first display area S1 along the first direction x is equal to the maximum width H2 of the second partition 12 along the first direction x, and the maximum width H3 of the first display area S1 along the second direction y is equal to the maximum width H1 of the first partition 11 along the second direction y.
  • the difference between the embodiment shown in FIG. 10 and FIG. 6 is that, since the first display area S1 is circular, when the maximum width H4 of the first display area S1 along the first direction x is equal to the maximum width H2 of the second partition 12 along the first direction x, and the maximum width H3 of the first display area S1 along the second direction y is equal to the maximum width H1 of the first partition 11 along the second direction y, the first partition 11 and the second partition 12 have an overlapping area.
  • the second pixel circuit C2 corresponding to the second light-emitting element P2 in the overlapping area of the first partition 11 and the second partition 12 can be moved together with the first pixel circuit C1 to the first partition 11 and/or the second partition 12 outside the overlapping area.
  • FIG. 11 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application
  • FIG. 12 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application.
  • the first pixel circuit C1 is located in at least one of the first partition 11 and the second partition 12
  • the second pixel circuit C2 corresponding to at least one second light-emitting element P2 of the first sub-display area 1 is located in the second sub-display area 2
  • the first pixel circuit C1 is located in the first region 3
  • the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second region 4 is located in the second sub-display area 2
  • the first region 3 is one of the first partition 11 and the second partition 12
  • the second region 4 is the other of the first partition 11 and the second partition 12.
  • FIG. 11 takes the first region 3 as the first partition 11 and the second region 4 as the second partition 12 as an example for illustration.
  • the first pixel circuit C1 can be located in the first partition 11
  • the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second partition 12 can be located in the second sub-display area 2.
  • the first pixel circuit C1 corresponding to the first light-emitting element P1 in the first display area S1 and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second partition 12 adjacent to the first display area S1 along the second direction y can be respectively located in the first partition 11 and the second sub-display area 2 adjacent to each other along the second direction y, which is beneficial to reducing the dispersion degree of the pixel circuits corresponding to the light-emitting elements located in the same column along the second direction y in the first direction x, and can even make the pixel circuits corresponding to the light-emitting elements in the same column located in the same column, thereby reducing the winding of the data lines and reducing the wiring difficulty.
  • no pixel circuits are arranged in the first display area S1 and the second partition 12, the winding of the data lines in the border area around the first display area S1 can be avoided, thereby reducing the border width and improving the display effect.
  • FIG11 is illustrated by taking the first light-emitting element P1 as a circle and the second light-emitting element P2 as a diamond as an example, and the filled rectangle represents the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second partition 12, and the unfilled rectangle represents the original second pixel circuit C2 in the first partition 11 and the second sub-display area 2.
  • the rectangle representing the first pixel circuit C1 is also filled.
  • the second pixel circuits corresponding to the second light-emitting elements in different areas are distinguished in the same filling manner.
  • FIG12 takes the first area 3 as the second partition 12 and the second area 4 as the first partition 11 as an example for illustration.
  • the first pixel circuit C1 may be located in the second partition 12
  • the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first partition 11 may be located in the second sub-display area 2.
  • the first pixel circuit C1 corresponding to the first light-emitting element P1 in the first display area S1 and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first partition 11 adjacent to the first display area S1 along the first direction x are respectively located in the second partition 12 and the second sub-display area 2 adjacent to the first direction x, which is conducive to reducing the dispersion of the pixel circuits corresponding to the light-emitting elements in the same row along the first direction x in the second direction y, and even the pixel circuits corresponding to the light-emitting elements in the same row can be located in the same row, thereby reducing the winding of the scan line and reducing the wiring difficulty.
  • the pixel circuit since the pixel circuit is not arranged in the first display area S1 and the first partition 11, the winding of the scan line in the frame area around the first display area S1 can be avoided, thereby reducing the frame width and improving the display effect.
  • FIG12 is illustrated by taking the first light-emitting element P1 as a circle and the second light-emitting element P2 as a diamond as an example, and the filled rectangle represents the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first partition 11, and the unfilled rectangle represents the original second pixel circuit C2 in the second partition 12 and the second sub-display area 2.
  • the rectangle representing the first pixel circuit C1 is also filled.
  • the second pixel circuits corresponding to the second light-emitting elements in different areas are distinguished in the same filling manner.
  • FIG. 12 is only illustrated by taking as an example that all first pixel circuits C1 are located in the second partition 12 below the first display area S1, and all second pixel circuits C2 corresponding to the second light-emitting elements P2 in the first partition 11 are located in the second sub-display area 2 below the first partition 11, and this arrangement is not limiting.
  • part of the first pixel circuits C1 may be located in the second partition 12 above the first display area S1
  • another part of the first pixel circuits C1 may be located in the second partition 12 below the first display area S1
  • the second pixel circuits C2 corresponding to the second light-emitting elements P2 in the first partition 11 may be respectively arranged in the second sub-display area 2 above the first partition 11 and the second sub-display area 2 below the first partition 11.
  • the embodiment of the present application arranges the first pixel circuit C1 in the first area 3 (such as the first partition 11) and arranges the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second area 4 (such as the second partition 12) in the second sub-display area 2.
  • the first pixel circuit corresponding to the first light-emitting element P1 in the first display area S1 and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second area 4 can be moved along the same direction to an area other than the second area 4 in the second display area S2, which is beneficial to reduce the layout difficulty of the pixel circuit, reduce the dispersion of the pixel circuit, and thereby reduce the wiring difficulty of the display panel.
  • the layout of the first pixel circuit C1 and the second pixel circuit C2 in the second partition 12 and the second sub-display area 2 is exemplarily described.
  • Figure 13 is an enlarged structural schematic diagram of a display panel corresponding to area Q4 in Figure 12.
  • the first area 3 includes at least one first circuit group 51 and at least one second circuit group 52
  • the first circuit group 51 includes a first pixel circuit C1
  • the second circuit group 52 includes a second pixel circuit C2
  • at least one first circuit group 51 is located on a side of the second circuit group 52 close to the first display area S1
  • the second sub-display area 2 includes at least one third circuit group 53 and at least one fourth circuit group 54
  • the third circuit group 53 includes a second pixel circuit C2 corresponding to the second light-emitting element P2 of the second area 4
  • the fourth circuit group 54 includes other second pixel circuits C2 in the second sub-display area 2
  • at least one third circuit group 53 is located on a side of the fourth circuit group 54 close to the second area 4.
  • the first circuit group 51 including the first pixel circuit C1 means that one first circuit group 51 may include one first pixel circuit C1, or one first circuit group 51 may include at least two first pixel circuits C1 arranged adjacent to each other.
  • one second circuit group 52 may include one second pixel circuit C2 in the first region 3, or one second circuit group 52 may also include at least two second pixel circuits C2 arranged adjacent to each other in the first region 3; the third circuit group 53 and the fourth circuit group 54 may be understood with reference to the configuration of the first circuit group 51, and will not be described in detail here.
  • the sizes of the multiple first pixel circuits C1 in the same first circuit group 51 can be the same or different; the number and size of the first pixel circuits C1 in different first circuit groups 51 can be the same or different, and the embodiment of the present application does not limit this.
  • the sizes of the multiple second pixel circuits C2 in the same circuit group can be the same or different, and the number and size of the second pixel circuits C2 in different circuit groups (second circuit group 52/third circuit group 53/fourth circuit group 54) can be the same or different, and the embodiment of the present application does not limit this.
  • the pixel circuits (the first pixel circuit C1 and/or the second pixel circuit C2) located in the same row have equal sizes along the column direction (such as the y direction), and the pixel circuits (the first pixel circuit C1 and/or the second pixel circuit C2) located in the same column have equal sizes along the row direction (such as the x direction).
  • Such an arrangement facilitates the arrangement of signal lines such as scanning lines and data lines, reduces winding, and reduces the difficulty of designing and manufacturing the display panel.
  • FIG. 13 illustrates an example in which the first area 3 includes a plurality of first circuit groups 51 and a plurality of second circuit groups 52 , and the second sub-display area 2 includes a plurality of third circuit groups 53 and a plurality of fourth circuit groups 54 .
  • multiple adjacent first pixel circuits C1 located in the same row in the first area 3 can constitute a first circuit group 51; multiple adjacent second pixel circuits C2 located in the same row in the first area 3 can constitute a second circuit group 52 (such as 52-1); in addition, second pixel circuits C2 located in at least two adjacent rows in the first area 3 can also constitute a second circuit group 52 (such as 52-2); in the second sub-display area 2, corresponding to the second light-emitting element P2 in the second area 4 and multiple adjacent second pixel circuits C2 located in the same row can constitute a third circuit group 53; among other second pixel circuits C2 in the second sub-display area 2, multiple adjacent second pixel circuits C2 located in the same row can constitute a fourth circuit group 54 (such as 54-1), and in addition, second pixel circuits C2 located in at least two adjacent rows can also constitute a fourth circuit group 54 (such as 54-2).
  • FIG13 illustrates an example in which the first pixel circuit C1 is located in the second partition 12 and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first partition 11 is located in the second sub-display area 2, at this time, by setting the first circuit group 51 to be composed of the first pixel circuits C1 in the same row or several adjacent rows, and the second circuit group 52/the third circuit group 53/the fourth circuit group 54 to be composed of the second pixel circuits C2 in the same row or several adjacent rows in the area where they are located, the first light-emitting element P1 and/or the second light-emitting element P2 in the same row can be set corresponding to the first pixel circuit C1 and/or the second pixel circuit C2 in the same row, so that the position and size of the pixel circuit only need to be adjusted along one direction (the second direction y in FIG13), thereby reducing the difficulty of layout of the pixel circuit, reducing the difficulty of wiring the display panel, and reducing the impact on product yield.
  • Figure 14 is a schematic diagram of the local structure of a display panel provided in an embodiment of the present application.
  • the first pixel circuit C1 in the same row in the same first circuit group 51 is electrically connected to the first light-emitting element P1 in the same row
  • the second pixel circuit C2 in the same row in the same second circuit group 52 is electrically connected to the second light-emitting element P2 in the same row in the second partition 12
  • the second pixel circuit C2 in the same row in the same third circuit group 53 is electrically connected to the second light-emitting element P2 in the same row in the first partition 11
  • the second pixel circuit C2 in the same row in the same fourth circuit group 54 is electrically connected to the second light-emitting element P2 in the same row in the second sub-display area 2.
  • the pixel circuits (first pixel circuit C1 and/or second pixel circuit C2) corresponding to the light-emitting elements in the same row (first light-emitting element P1 and/or second light-emitting element P2) can be located in the same row, thereby avoiding winding the scan line Gate, reducing the difficulty of layout of the pixel circuit, reducing the difficulty of wiring the display panel, and reducing the impact on product yield.
  • FIG. 13 only illustrates the alternate arrangement of the first circuit group 51 and the second circuit group 52 in the first area 3 and the alternate arrangement of the third circuit group 53 and the fourth circuit group 54 in the second sub-display area 2 as an example, and this arrangement is not limited.
  • the enlarged structural diagram of another display panel corresponding to the domain Q4 is shown in FIG15.
  • the first region 3 (such as the second partition 12) adjacent to one side of the first display region S1 may include a first circuit group 51 and a second circuit group 52, and the first circuit group 51 is located on the side of the second circuit group 52 close to the first display region S1.
  • the second sub-display region 2 adjacent to one side of the second region 4 may include a third circuit group 53 and a fourth circuit group 54, and the third circuit group 53 is located on the side of the fourth circuit group 54 close to the second region 4.
  • the first pixel circuit C1 and the first light-emitting element P1 can be arranged close to each other, and the second pixel circuit C2 in the third circuit group 53 and the second light-emitting element P2 in the second region 4 can be arranged close to each other, so that the first pixel circuit C1 and the first light-emitting element P1 are electrically connected, and the second pixel circuit C2 in the third circuit group 53 and the second light-emitting element P2 in the second region 4 are electrically connected, thereby reducing the wiring difficulty.
  • the size of the first pixel circuit C1 is equal to the size of the second pixel circuit C2 in the third circuit group 53; the size of the first pixel circuit C1 is equal to the size of at least one second pixel circuit C2 in the second circuit group 52; the size of the second pixel circuit C2 in the third circuit group 53 is equal to the size of at least one second pixel circuit C2 in the fourth circuit group 54.
  • the size of the first pixel circuit C1 includes the first side length L1 of the area where the first pixel circuit C1 is located along the first direction x and the second side length L2 along the second direction y;
  • the size of the second pixel circuit C2 includes the third side length L3 of the area where the second pixel circuit C2 is located along the first direction x and the fourth side length L4 along the second direction y; if the first side length L1 corresponding to the first pixel circuit C1 and the third side length L3 corresponding to the second pixel circuit C2 are equal, and the second side length L2 corresponding to the first pixel circuit C1 and the fourth side length L4 corresponding to the second pixel circuit C2 are equal, then the sizes of the first pixel circuit C1 and the second pixel circuit C2 are equal, otherwise, if the first side length L1 corresponding to the first pixel circuit C1 and the third side length L3 of the second pixel circuit C2 are not equal, and/or the second side length L2 corresponding to the first pixel
  • first side length L1 and the second side length L2 of the area where the two first pixel circuits C1 are located are respectively equal, then the sizes of the two first pixel circuits C1 are equal, otherwise the sizes of the two first pixel circuits C1 are not equal; if the third side length L3 and the fourth side length L4 of the area where the two second pixel circuits C2 are located are respectively equal, then the sizes of the two second pixel circuits C2 are equal, otherwise the sizes of the two second pixel circuits C2 are not equal.
  • the size of the first pixel circuit C1 is equal to the size of the second pixel circuit C2 in the third circuit group 53, which means that the sizes of the plurality of second pixel circuits C2 in the third circuit group 53 are all equal and equal to the size of the first pixel circuit C1.
  • the positions and sizes of the first pixel circuits C1 and the second pixel circuits C2 can be adjusted in the same manner, which is conducive to reducing the difficulty of pixel circuit layout.
  • the size of the first pixel circuit C1 is equal to the size of at least one second pixel circuit C2 in the second circuit group 52, which means that for all the second pixel circuits C2 in the second circuit group 52, the size of the first pixel circuit C1 is equal to the size of at least one of the second pixel circuits C2.
  • the size of the second pixel circuit C2 in the third circuit group 53 is equal to the size of at least one of the second pixel circuits C2 in the fourth circuit group 54, which means that for all the second pixel circuits C2 in the fourth circuit group 54, the size of the second pixel circuit C2 in the third circuit group 53 is equal to the size of at least one of the second pixel circuits C2.
  • the compressible amounts of the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first area 3 and the second sub-display area 2 are different. Under the condition of meeting the line width and line spacing requirements, it may be necessary to only compress the size of part of the second pixel circuit C2 so as to set the first pixel circuit C1 corresponding to the first light-emitting element P1 in the first display area S1 in the first area 3, and set the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second area 4 in the second sub-display area 2.
  • the sizes of the multiple second pixel circuits C2 in the second circuit group 52-1 are equal and equal to the size of the first pixel circuit C1 group; the sizes of the second pixel circuits C2 in the second circuit group 52-2 are equal, but not equal to the size of the first pixel circuit C1 (the fourth side length L4 of the second pixel circuit C2 in the second circuit group 52-2 is greater than the second side length L2 of the first pixel circuit C1); the sizes of the multiple second pixel circuits C2 in the fourth circuit group 54-1 are equal and equal to the size of the second pixel circuit C2 in the third circuit group 53; the sizes of the multiple second pixel circuits C2 in the fourth circuit group 54-2 are equal, but not equal to the size of the second pixel circuit C2 in the third circuit group 53 (the fourth side length L4 of the second pixel circuit C2 in the fourth circuit group 54-2 is greater than the fourth side length L4 of the second pixel circuit C2 in the third circuit group 53).
  • the second circuit group 52 includes a first circuit group 521 and a second circuit group 522, the sizes of the second pixel circuits C2 in the first circuit group 521 and the second circuit group 522 are not equal, and the first circuit group 521 is located on the side of the second circuit group 522 close to the first circuit group 51; the size of the second pixel circuit C2 in the first circuit group 521 is equal to the size of the first pixel circuit C1; the fourth circuit group 54 includes a third circuit group 541 and a fourth circuit group 542, the sizes of the second pixel circuits C2 in the third circuit group 541 and the fourth circuit group 542 are not equal, and the third circuit group 541 is located on the side of the fourth circuit group 542 close to the third circuit group 53; the size of the second pixel circuit C2 in the third circuit group 541 is equal to the size of the second pixel circuit C2 in the third circuit group 53;
  • the second circuit group 52 is located on the side of the first circuit group 51 away from the first display area S1, and the second circuit group 52 is divided into a first circuit group 521 and a second circuit group 522, wherein the size of the plurality of second pixel circuits C2 in the first circuit group 521 is The sizes of the second pixel circuits C2 in the second circuit group 522 are all equal, the sizes of the second pixel circuits C2 in the first circuit group 521 and the second pixel circuits C2 in the second circuit group 522 are not equal (the fourth side length L4 is not equal), the first circuit group 521 is located on the side of the second circuit group 522 close to the first circuit group 51, and the size of the second pixel circuit C2 in the first circuit group 521 is equal to the size of the first pixel circuit C1.
  • the first pixel circuit C1 with the compressed size can be set in the first area 3, and such a setting can make the first circuit group 51 closer to the first display area S1, which is convenient for the first pixel circuit C1 and the corresponding first light-emitting element P1 to be electrically connected, reducing the wiring difficulty and reducing the impact on the product yield.
  • the third circuit group 53 is located on a side of the fourth circuit group 54 close to the second region 4, and the fourth circuit group 54 includes a third circuit grouping 541 and a fourth circuit grouping 542, wherein the sizes of the plurality of second pixel circuits C2 in the third circuit grouping 541 are all equal, the sizes of the plurality of second pixel circuits C2 in the fourth circuit grouping 542 are all equal, the sizes of the second pixel circuits C2 in the third circuit grouping 541 and the second pixel circuits C2 in the fourth circuit grouping 542 are not equal (the fourth side length L4 is not equal), the third circuit grouping 541 is located on a side of the fourth circuit grouping 542 close to the third circuit group 53, and the size of the second pixel circuit C2 in the third circuit grouping 541 is equal to the size of the second pixel circuit C2 in the third circuit grouping 543.
  • the sizes of all the first pixel circuits C1 and the second pixel circuits C2 can also be compressed to make the sizes of the first pixel circuits C1 and the second pixel circuits C2 equal. In this way, the first pixel circuits C1 and the second pixel circuits C2 can have the same driving capabilities, which is beneficial to display uniformity.
  • Figure 16 is an enlarged structural schematic diagram of another display panel corresponding to area Q4 in Figure 12.
  • the sizes of the first pixel circuit C1 and the second pixel circuit C2 are equal; the display panel 100 also includes a plurality of first virtual pixel circuits C01, the first virtual pixel circuit C01 is located in the first area 3 and the second sub-display area 2, and the orthographic projection of the first virtual pixel circuit C01 on the plane where the display panel is located does not overlap with the orthographic projection of the first pixel circuit C1 and the second pixel circuit C2 on the plane where the display panel is located.
  • the sizes of the first pixel circuit C1 and the second pixel circuit C2 are equal, if the sizes of the first pixel circuit C1 and the second pixel circuit C2 are compressed to a greater extent, it may happen that after accommodating the first pixel circuit C1 and the second pixel circuit C2, there is still a situation where there is free space in the first area 3 and the second sub-display area 2.
  • the metal structure in the pixel circuit will reflect ambient light.
  • the orthographic projection of the first virtual pixel circuit C01 on the plane where the display panel is located does not overlap with the orthographic projection of the first pixel circuit C1 and the second pixel circuit C2 on the plane where the display panel is located.
  • the first virtual pixel circuit C01 can be used to balance the distribution of pixel circuits in the display panel, thereby balancing the reflectivity differences between different areas of the display panel, and avoiding the split screen phenomenon caused by the local lack of pixel circuits.
  • a second virtual pixel circuit C02 is provided in the second region 4.
  • the structure of the first virtual pixel circuit C01/the second virtual pixel circuit C02 is the same as the structure of the first pixel circuit C1/the second pixel circuit C2, and the only difference is that the first virtual pixel circuit C01 and the second virtual pixel circuit C02 cannot drive any of the first light-emitting element P1 and the second light-emitting element P2 to emit light.
  • the virtual pixel circuit cannot drive the light-emitting element to emit light, such as the virtual pixel circuit is not electrically connected to the scan line, the data line, and the PVDD line, or the virtual pixel circuit is not electrically connected to the light-emitting element, or the virtual pixel circuit is electrically connected to the light-emitting element, but the light-emitting element itself cannot be driven to emit light (such as the cathode, the anode, the pixel defining layer opening, and the light-emitting layer. At least one of the light-emitting layer is missing), and the embodiment of the present application is not limited to this.
  • the size of the first virtual pixel circuit C01/the second virtual pixel circuit C02 can be the same as the size of the first pixel circuit C1/the second pixel circuit C2, or it can be different, and the embodiment of the present application is not limited to this.
  • the following is an exemplary description of the layout of the first virtual pixel circuit C01 in the first area 3 and the second sub-display area 2 .
  • the first virtual pixel circuit C01 is located on a side of the second circuit group 52 away from the first circuit group 51, and is located on a side of the fourth circuit group 54 away from the third circuit group 53.
  • This arrangement can reduce the impact on the layout of the first pixel circuit C1 and the second pixel circuit C2, and reduce the difficulty of the layout of the pixel circuit.
  • Figure 17 is an enlarged structural schematic diagram of another display panel corresponding to area Q4 in Figure 12.
  • at least one first virtual pixel circuit C01 is located between two adjacent first pixel circuits C1 and/or second pixel circuits C2.
  • the first virtual pixel circuit C01 may be inserted into the layout of the first pixel circuit C1 and the second pixel circuit C2.
  • a first virtual pixel circuit C01 may be located between two adjacent first pixel circuits C1, or between two adjacent second pixel circuits C2, or between two adjacent first pixel circuits C1 and second pixel circuits C2, which is not limited in the present embodiment of the application.
  • any two first virtual pixel circuits C01 adjacent to each other along the first direction x include m actual pixels.
  • the actual pixel circuit refers to a pixel circuit such as the first pixel circuit C1 and the second pixel circuit C2 that is electrically connected to the first light-emitting element P1 or the second light-emitting element P2.
  • the actual pixel circuit may be at least one of the first pixel circuit C1 and the second pixel circuit C2.
  • Figure 18 is an enlarged structural schematic diagram of another display panel corresponding to area Q4 in Figure 12.
  • Multiple first virtual pixel circuits C01 are arranged in the same column and interspersed between several columns of actual pixel circuits.
  • any two first virtual pixel circuits C01 adjacent along the first direction x include 3 actual pixel circuits
  • any two first virtual pixel circuits C01 adjacent along the second direction y include 2 actual pixel circuits
  • FIG20 is an enlarged structural schematic diagram of another display panel corresponding to the area Q4 in FIG12 .
  • the sizes of the first pixel circuit C1 and the second pixel circuit C2 are equal and are distributed in the area other than the second area 4 in the second display area S2.
  • the first virtual pixel circuit C01 is not provided in the first area 3 and the second sub-display area 2, so that the compression degree of the first pixel circuit C1 and the second pixel circuit C2 can be relatively small, that is, compared with the solution in which the first virtual pixel circuit C01 is provided in the first area 3 and the second sub-display area 2, the sizes of the first pixel circuit C1 and the second pixel circuit C2 can be relatively large, ensuring that the line width and line spacing have a certain design margin, thereby reducing the risk of short circuit and ensuring the product yield.
  • FIG. 20 only illustrates an example in which a first region 3 includes a first circuit group 51 and a second circuit group 52, the first circuit group 51 is located on the side of the second circuit group 52 close to the first display region S1, a second sub-display region 2 includes a third circuit group 53 and a fourth circuit group 54, the third circuit group 53 is located on the side of the fourth circuit group 54 close to the second region 4, and the sizes of the multiple first pixel circuits C1 in the first circuit group 51 and the sizes of the multiple second pixel circuits C2 in the second circuit group 52, the third circuit group 53 and the fourth circuit group 54 are equal.
  • a first region 3 may include multiple first circuit groups 51 and second circuit groups 52 arranged alternately
  • a second sub-display region 2 may include multiple third circuit groups 53 and fourth circuit groups 54 arranged alternately
  • the embodiment of the present application does not limit the arrangement of the first pixel circuit C1 and the second pixel circuit C2, as long as the sizes of the first pixel circuit C1 and the second pixel circuit C2 are equal.
  • Figures 13-20 only take the first area 3 as the second partition 12, the second area 4 as the first partition 11, and the first sub-display area 1 includes a first partition 11 and a second partition 12 as an example for illustration.
  • the layout of the first pixel circuit C1 and the second pixel circuit C2 in other second partitions 12 and the second sub-display area 2 in Figure 12 can be symmetrically arranged with reference to any of the settings in Figures 13-20, which will not be repeated here.
  • the first display area S1 is the camera area
  • the first pixel circuit C1 is located in the second partition 12
  • the second pixel circuit C2 corresponding to the second light-emitting element P2 of the first partition 11 is located in the second sub-display area 2
  • the second partition 12 can be used to set part of the first pixel circuit C1 according to actual conditions.
  • the two second sub-display areas 2 above the first partition 11 can be used to set part of the second pixel circuit C2 corresponding to the second light-emitting element P2 of the first partition 11 according to actual conditions.
  • the embodiment of the present application is not limited to this.
  • the above embodiment takes the first area 3 as the second partition 12, the second area 4 as the first partition 11, the first pixel circuit C1 is located in the second partition 12, and the second pixel circuit C2 corresponding to the second light-emitting element P2 of the first partition 11 is located in the second sub-display area 2 as an example, and the arrangement of the first pixel circuit C1 and the second pixel circuit C2 is described in detail.
  • Any of the above implementations can be used for reference in the embodiment in which the first area 3 is the first partition 11 and the second area 4 is the second partition 12.
  • the arrangement of the first pixel circuit C1 and the second pixel circuit C2 is briefly described.
  • FIG21 is an enlarged structural diagram of another display panel corresponding to the area Q4 in FIG12.
  • the first area 3 is the first partition 11
  • the second area 4 is the second partition 12
  • the first pixel circuit C1 is located in the first partition 11
  • the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second partition 12 is located in the second sub-display area 2.
  • FIG21 fills the rectangles representing the first pixel circuit C1 and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second partition 12 for distinction.
  • one of the first subareas 11 of the display panel includes a first circuit group 51 and a second circuit group 52, and the first circuit group 51 is located on the side of the second circuit group 52 close to the first display area S1, and one of the second sub-display areas 2 of the display panel includes a third circuit group 53 and a fourth circuit group 54, and the third circuit group 53 is located on the side of the fourth circuit group 54 close to the second subarea 12, and the sizes of the first pixel circuit C1 and the second pixel circuit C2 are equal, and a second virtual pixel circuit C02 is provided in the first subarea 11.
  • Other feasible configuration methods for the first pixel circuit C1 and the second pixel circuit C2 can be configured with reference to the relevant embodiments in which the first area 3 is the second subarea 12 and the second area 4 is the first subarea 11, and will not be described one by one here.
  • Figure 22 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • the first light-emitting elements P1 located in the same row are electrically connected one-to-one with the first pixel circuits C1 located in the same row
  • the second light-emitting elements P2 located in the same row are electrically connected one-to-one with the second pixel circuits C2 located in the same row.
  • the second area 4 may be one of the first partition 11 and the second partition 12. Referring to FIG6 , taking the first direction x as the row direction and the second direction y as the column direction as an example, if the second area 4 is the first partition 11, the direction from the first display area S1 to the second area 4 is the row direction, the first light emitting elements P1 in the same row are the first light emitting elements P1 in the same row, the first pixel circuits C1 in the same row are the first pixel circuits C1 in the same row, the second light emitting elements P2 in the same row are the second light emitting elements P2 in the same row, and the second pixel circuits C2 in the same row are the second pixel circuits C2 in the same row.
  • the first light-emitting elements P1 located in the same row are the first light-emitting elements P1 located in the same column
  • the first pixel circuits C1 located in the same row are the first pixel circuits C1 located in the same column
  • the second light-emitting elements P2 located in the same row are the second light-emitting elements P2 located in the same column
  • the second pixel circuits C2 located in the same row are the second pixel circuits C2 located in the same column.
  • FIG22 illustrates the second area 4 as the first partition 11 as an example.
  • the first light-emitting elements P1 located in the same row are electrically connected to the first pixel circuits C1 located in the same row in sequence
  • the second light-emitting elements P2 located in the same row are electrically connected to the second pixel circuits C2 located in the same row in sequence.
  • the second area 4 may be the second partition 12, in which case the first light-emitting elements P1 located in the same column are electrically connected to the first pixel circuits C1 located in the same column in sequence, and the second light-emitting elements P2 located in the same column are electrically connected to the second pixel circuits C2 located in the same column in sequence.
  • the embodiment of the present application arranges the first light-emitting elements P1 located in the same row to be electrically connected in sequence with the first pixel circuits C1 located in the same row, and arranges the second light-emitting elements P2 located in the same row to be electrically connected in sequence with the second pixel circuits C2 located in the same row, so that the first pixel circuits C1 and the second pixel circuits C2 corresponding to the first light-emitting elements P1 and the second light-emitting elements P2 located in the same row in the first display area S1 and the second area 4 are located in the same row, thereby reducing the dispersion of the pixel circuits, and at the same time facilitating the wiring of signal lines such as scan lines or data lines, reducing winding, and reducing the impact on product yield.
  • first pixel circuits C1 corresponding to two adjacent rows (rows/columns) of first light-emitting elements P1 can be arranged adjacent to each other or not.
  • second pixel circuits C2 corresponding to two adjacent rows of second light-emitting elements P2 can be arranged adjacent to each other or not. The embodiment of the present application does not limit this.
  • the first light-emitting element P1 and the corresponding first pixel circuit C1 are electrically connected via the first connection line 81; at least part of the second light-emitting element P2 and the corresponding second pixel circuit C2 are electrically connected via the second connection line 82; along the direction from the first area 3 to the first display area S1, the first connection line 81 corresponding to the first pixel circuit C1 closer to the first display area S1 is longer, and the second connection line 82 corresponding to the second pixel circuit C2 closer to the first display area S1 or the second area 4 is longer.
  • connection line electrically connected to the first pixel circuit C1 is the first connection line 81, and the first connection line 81 corresponding to the first pixel circuit C1 closer to the first display area S1 is longer (for example, Z1>Z2), and the connection line electrically connected to the second pixel circuit C2 is the second connection line 82, and the second connection line 82 corresponding to the second pixel circuit C2 closer to the first display area S1 or the second area 4 is longer (for example, Z4>Z5).
  • FIG. 22 only illustrates a portion of the first connection line 81 between the first light emitting element P1 and the first pixel circuit C1 , and a portion of the second connection line 82 between the second light emitting element P2 and the second pixel circuit C2 .
  • the direction in which the first area 3 points to the first display area S1 is parallel to the second direction y (the same as or opposite to the y direction in the figure), and when the first area 3 is the first partition 11, the direction in which the first area 3 points to the first display area S1 is parallel to the first direction x (the same as or opposite to the x direction in the figure).
  • the direction in which the second partition 12 below the first display area S1 points to the first display area S1 is the same as the y direction
  • the direction in which the second partition 12 above the first display area S1 points to the first display area S1 is opposite to the y direction.
  • the relative position relationship of multiple first pixel circuits C1 located in the same first region 3 and arranged along the direction from the first region 3 to the first display region S1 can be made the same as the relative position relationship of the multiple first light-emitting elements P1 corresponding thereto (the multiple first light-emitting elements P1 are also arranged along the direction from the first region 3 where the first pixel circuit C1 is located to the first display region S1), thereby facilitating the improvement of the wiring regularity of the first connection line 81, reducing wiring complexity, and reducing the impact on product yield.
  • the relative position relationship of multiple first pixel circuits C1 located in the same first region 3 and arranged along the direction from the first region 3 to the first display region S1 can be made the same as the relative position relationship of the multiple first light-emitting elements P1 corresponding thereto (the multiple first light-emitting elements P1 are also arranged along the direction from the first region 3 where the first pixel circuit C1 is located to the first display region S1).
  • the relative position relationship of the multiple second pixel circuits C2 arranged in the area 3 and along the direction from the first area 3 to the first display area S1 is the same as the relative position relationship of the multiple second light-emitting elements P2 corresponding to them.
  • the relative position relationship of the multiple second pixel circuits C2 located in the same second sub-display area 2 and arranged along the direction from the second sub-display area 2 to the second area 4 can be made the same as the relative position relationship of the multiple second light-emitting elements P2 corresponding to them, which is beneficial to improve the wiring regularity of the second connecting line 82, reduce the wiring complexity, and reduce the impact on product yield.
  • Figure 22 only illustrates an example in which a plurality of first pixel circuits C1 arranged in a direction from the first area 3 to the first display area S1 are adjacently arranged and close to the first display area S1, and a plurality of second pixel circuits C2 arranged in a direction from the second sub-display area 2 to the second area 4, and corresponding to the second light-emitting element P2 in the second area 4 are adjacently arranged and close to the second area 4.
  • a plurality of second pixel circuits C2 may be included between two adjacent first pixel circuits C1
  • a plurality of second pixel circuits C2 in the fourth circuit group 54 may be included between the second pixel circuits C2 corresponding to the second light-emitting element P2 in the second area 4 (refer to Figure 13), and the embodiment of the present application is not limited to this.
  • the display panel 100 also includes a non-display area FNA, the non-display area FNA includes a binding area S3, the first sub-display area 1 includes at least one first area 3, one of the first areas 3 is located between the first display area S1 and the binding area S3, the first pixel circuits C1 are all located in the first area 3, and the second pixel circuits C2 corresponding to the second light-emitting elements P2 in the second area 4 are all located in the second sub-display area 2 adjacent to the first area 3.
  • the non-display area FNA includes a binding area S3
  • the first sub-display area 1 includes at least one first area 3
  • one of the first areas 3 is located between the first display area S1 and the binding area S3
  • the first pixel circuits C1 are all located in the first area 3
  • the second pixel circuits C2 corresponding to the second light-emitting elements P2 in the second area 4 are all located in the second sub-display area 2 adjacent to the first area 3.
  • the first light-emitting elements P1 located in the same row are electrically connected to the first pixel circuits C1 located in the same row in sequence
  • the second light-emitting elements P2 located in the same row are electrically connected to the second pixel circuits C2 located in the same row in sequence
  • the i-th row of light-emitting devices is electrically connected to the i-th row of actual pixel circuits, and i is a positive integer; wherein a row of light-emitting devices includes at least one of the first light-emitting element P1 and the second light-emitting element P2, and a row of actual pixel circuits includes at least one of the first pixel circuit C1 and the second pixel circuit C2.
  • the binding area S3 is located at the lower border of the display panel, that is, at the bottom of the display panel along the column direction. Therefore, when the second direction y is the column direction, the first area 3 is the second partition 12, and the second area 4 is the first partition 11.
  • the number of first areas 3 is consistent with the number of second partitions 12, and the number of second areas 4 is consistent with the number of first partitions 11. For example, it can be determined according to the position of the first display area S1 with reference to the above description.
  • the first display area S1 is usually adjacent to or close to the upper boundary of the total display area.
  • Figure 22 illustrates the first display area S1 adjacent to the upper boundary of the total display area as an example.
  • the first display area S1 and the binding area S3 include a first area 3, and the area of the first area 3 is larger.
  • the first pixel circuit C1 is set in the first area 3 between the first display area S1 and the binding area S3, and the second pixel circuit C2 corresponding to the second light-emitting element P2 of the second area 4 is set in the second sub-display area 2 adjacent to the first area 3.
  • the first light-emitting elements P1 located in the same row along the direction from the first display area S1 to the second area 4 are electrically connected one-to-one with the first pixel circuit C1 located in the same row in sequence
  • the second light-emitting elements P2 located in the same row along the direction from the first display area S1 to the second area 4 are electrically connected one-to-one with the second pixel circuit C2 located in the same row in sequence
  • the i-th row of light-emitting devices is electrically connected to the i-th row of actual pixel circuits along the direction from the first display area S1 to the binding area S3, so that the length of the connecting line corresponding to the i-th row of actual pixel circuits can be made greater than the length of the connecting line corresponding to the i+1-th row of actual pixel circuits, that is, the closer the connecting line corresponding to the actual pixel circuit to the first display area S1 (the first connecting line 81 or the second connecting line 82), the longer the length.
  • the driving chip is electrically connected to the binding area S3 and transmits data signals to multiple actual pixel circuits through data lines, the farther the actual pixel circuit is from the binding area S3, the greater the data line load, that is, there is a load gradient when the data signal is transmitted to the actual pixel circuit through the data line.
  • the related technology can improve display uniformity by adopting a certain software algorithm, and the above-mentioned setting method is adopted in this embodiment to make the length of the connecting line corresponding to the actual pixel circuit farther away from the binding area S3 longer, thereby maintaining the load gradient situation, without having to break the driving software algorithm in the related technology, which is conducive to ensuring display uniformity.
  • FIG23 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application.
  • the display panel 100 includes a substrate 901, a pixel circuit layer 6, and a light-emitting element layer 7.
  • the pixel circuit layer 6 includes a plurality of first pixel circuits and a plurality of second pixel circuits.
  • FIG23 only illustrates a thin film transistor T1 in the first pixel circuit and a thin film transistor T2 in the second pixel circuit.
  • the light-emitting element layer 7 includes a plurality of first light-emitting elements P1 and a plurality of second light-emitting elements P2.
  • the first light-emitting element P1 is located in the first display area S1, and the second light-emitting element P2 is located in the second display area S2.
  • the pixel circuits in the pixel circuit layer 6 are electrically connected to the corresponding light-emitting elements. As shown in FIG23 , the first light-emitting element P1 is electrically connected to the first pixel circuit C1 through a first connecting line 81, and the second light-emitting element P2 is electrically connected to the second pixel circuit C2 through a second connecting line 82.
  • the substrate 901 to the light-emitting element layer 7 includes a buffer layer 902, an active layer 911, a gate insulating layer 903, a first metal layer 912, a first interlayer dielectric layer 904, a capacitor plate layer 913, a second interlayer dielectric layer 905, a third interlayer dielectric layer 906, a second metal layer 914, a fourth interlayer dielectric layer 907, a first planarization layer 908, a third metal layer 915, a second planarization layer 909, a conductive film layer where the first connection line 81 and the second connection line 82 are located, a third planarization layer 910 and a pixel defining layer 911 are stacked in sequence; the first light-emitting element P1
  • the first metal layer 912 is used to form at least the gate electrode of the thin film transistor
  • the capacitor plate layer 913 is used to form at least the capacitor plate of the storage capacitor
  • the second metal layer 914 is used to form at least the source and drain electrode of the thin film transistor
  • Figure 23 only illustrates the example that the first connecting line 81 and the second connecting line 82 are located in the same layer. In other embodiments, at least one first connecting line 81 and/or at least one second connecting line 82 can be located in a different film layer from other first connecting lines 81 and second connecting lines 82. The embodiments of the present application are not limited to this.
  • the first connection line 81 includes a first connection sub-portion 811 , and the first connection sub-portion 811 is located in the first display area S1 ; at least one first connection sub-portion 811 is a transparent wiring line.
  • the transmittance of the transparent wiring to light is much greater than the reflectivity of the transparent wiring to light.
  • the reflectivity of the transparent wiring to light can even be zero, for example, which can be determined according to the material of the selected transparent wiring.
  • the first connection sub-portion 811 being located in the first display area S1 can be understood as the orthographic projection of the first connection sub-portion 811 on the plane where the display panel is located being located in the first display area S1. Since the first display area S1 needs to allow the light carrying the object information to pass through the display panel and be emitted to the photosensitive element on the back side (non-display side) of the display panel to be received and recognized by the photosensitive element, the first display area S1 has a high requirement for the light transmittance. In the embodiment of the present application, by setting at least one first connection sub-portion 811 as a transparent wiring, it is helpful to reduce the influence on the light transmittance of the first display area S1.
  • first connection subsections 811 of all first connection lines 81 may be transparent wirings, or the first connection subsections 811 of a portion of the first connection lines 81 may be transparent wirings, which is not limited in the present embodiment.
  • the first connection subsection 811 of a first connection line 81 is located at the edge of the first display area S1, since the light transmittance at the edge of the first display area S1 has a relatively small effect on the imaging quality, the first connection subsection 811 may also be a metal wiring.
  • first connection line 81 can be set as a transparent line as a whole, or only the first connection section 811 located in the first display area S1 can be set as a transparent line, and the rest can be set as a metal line, which is not limited in the embodiment of the present application.
  • second connection line 82 can be a transparent line or a metal line, which is also not limited in the embodiment of the present application.
  • FIG. 24 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • the display device 200 includes a photosensitive element 210 and a display panel 100 provided in any of the above embodiments, and the photosensitive element 210 is arranged corresponding to the first display area S1. Since the display device includes the display panel provided in any of the above embodiments, it has the same beneficial effects as the above display panel. The similarities can be referred to the description of the above display panel embodiment, which will not be repeated here.
  • the display device 200 provided in the embodiment of the present application can be a mobile phone as shown in Figure 24, or it can be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present application does not make special limitations on this.

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Abstract

本申请公开了一种显示面板及显示装置，显示面板包括第一显示区和第二显示区，第一显示区的透光率大于第二显示区的透光率；第一显示区包括多个第一发光元件，第二显示区包括多个第二发光元件，第一发光元件和第二发光元件的分布密度相同；第二显示区包括多个第一像素电路和多个第二像素电路；第一像素电路和第一发光元件一一对应电连接；第二像素电路和第二发光元件一一对应电连接。

Description

一种显示面板及显示装置
本申请要求在2022年11月10日提交中国专利局、申请号为202211407066.3的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种显示面板及显示装置。
背景技术
随着显示设备的发展，全面屏技术受到了广泛的关注和研究。
为使显示设备兼具全面屏显示和前置感光功能，例如在显示区实现指纹识别、前置摄像等功能，通常将感光元件内置于屏幕下方，并通过调整感光功能区的像素设计，使得该区域既能显示又能透光，从而使显示设备兼具全面屏显示和前置感光功能。
相关技术通常采取减小感光功能区的像素密度或者将其中的像素电路外置于感光功能区周边的过渡区等方式，满足感光功能区对透光率的需求，但是，上述方式大多存在感光功能区的显示效果不佳等问题。
发明内容
本申请提供了一种显示面板及显示装置，以在保证第一显示区的透光率的同时，改善第一显示区的显示效果。
根据本申请的一方面，提供了一种显示面板，包括第一显示区和第二显示区，第一显示区的透光率大于第二显示区的透光率；
第一显示区包括多个第一发光元件，第二显示区包括多个第二发光元件，第一发光元件和第二发光元件的分布密度相同；
第二显示区包括多个第一像素电路和多个第二像素电路；第一像素电路和第一发光元件一一对应电连接；第二像素电路和第二发光元件一一对应电连接。
根据本申请的另一方面，提供了一种显示装置，包括本申请任一实施例提供的显示面板。
附图说明
图1是相关技术中的一种显示面板的结构示意图；
图2是本申请实施例提供的一种显示面板的结构示意图；
图3是本申请实施例提供的一种显示面板的放大结构示意图；
图4是本申请实施例提供的另一种显示面板的结构示意图；
图5是本申请实施例提供的另一种显示面板的结构示意图；
图6是本申请实施例提供的另一种显示面板的结构示意图；
图7是本申请实施例提供的另一种显示面板的结构示意图；
图8是本申请实施例提供的另一种显示面板的结构示意图；
图9是本申请实施例提供的另一种显示面板的结构示意图；
图10是本申请实施例提供的另一种显示面板的结构示意图；
图11是本申请实施例提供的另一种显示面板的结构示意图；
图12是本申请实施例提供的另一种显示面板的结构示意图；
图13是与图12中区域Q4对应的一种显示面板的放大结构示意图；
图14是本申请实施例提供的一种显示面板的局部结构示意图；
图15是与图12中区域Q4对应的另一种显示面板的放大结构示意图；
图16是与图12中区域Q4对应的另一种显示面板的放大结构示意图；
图17是与图12中区域Q4对应的另一种显示面板的放大结构示意图；
图18是与图12中区域Q4对应的另一种显示面板的放大结构示意图；
图19是与图12中区域Q4对应的另一种显示面板的放大结构示意图；
图20是与图12中区域Q4对应的另一种显示面板的放大结构示意图；
图21是与图12中区域Q4对应的另一种显示面板的放大结构示意图；
图22是本申请实施例提供的另一种显示面板的结构示意图；
图23是本申请实施例提供的一种显示面板的剖面结构示意图；
图24是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
图1是相关技术中的一种显示面板的结构示意图，如图1所示，显示面板的显示区FA包括第一区Q1、第二区Q2和第三区Q3，第二区Q2位于第一区Q1和第三区Q3之间。其中，第一区Q1即上述感光功能区，该区域兼具显示和感光的功能，可以实现诸如前置摄像或指纹识别等感光功能。第二区Q2和第三区Q3则是仅具有显示功能的区域。显示面板由阵列排布的子像素发光实现显示功能，子像素包括发光元件和用于驱动发光元件发光的像素电路，发光元件与像素电路之间的对应关系可以是一个像素电路对应一个发光元件，也可以是一个像素电路对应至少两个发光元件。为保证显示效果，通常设置像素电路与发光元件一一对应。
相关技术中，为满足第一区Q1对透光率的需求，将与第一区Q1内的发光元件相对应的像素电路设置于第二区Q2(即上述过渡区)内。如此，需要通过压缩与第一区Q1的发光元件和第二区Q2的发光元件相对应的像素电路的尺寸，以使这部分像素电路可以集成于第二区Q2内。由于第二区Q2的面积较小，像素电路的压缩空间受限，在第一区Q1的发光元件的解析度较高的情况下，难以实现像素电路与发光元件一一对应的设计，而是通常会采取一个像素电路同时驱动多个发光元件的方案，导致第一区Q1的实际显示PPI(Pixels Per Inch，每英寸像素数目)低于第三区Q3，导致第一区Q1的显示效果较差。
本申请实施例提供了一种显示面板，包括第一显示区和第二显示区，第一显示区的透光率大于第二显示区的透光率；第一显示区包括多个第一发光元件，第二显示区包括多个第二发光元件，第一发光元件和第二发光元件的分布密度相同；第二显示区包括多个第一像素电路和多个第二像素电路；第一像素电路和第一发光元件一一对应电连接；第二像素电路和第二发光元件一一对应电连接。
采取以上方案，由于第一显示区内设置有第一发光元件而未设置与其对应的像素电路，从而可以保证第一显示区对透光率的要求，由于第二显示区的空间更为充足，可以通过压缩至少部分像素电路的尺寸，将与第一显示区的第一发光元件相对应的第一像素电路以及与第二显示区的第二发光元件相对应的第二像素电路均设置于第二显示区内，并且实现第一像素电路与第一发光元件一一对应电连接，第二像素电路与第二发光元件一一对应电连接，又由于第一发光元件和第二发光元件的分布密度相同，从而可使第一显示区和第二显示区具有相同的显示PPI，改善第一显示区的显示效果。
图2是本申请实施例提供的一种显示面板的结构示意图，图3是本申请实施例提供的一种显示面板的放大结构示意图，结合图2和图3所示，本申请实施例提供的显示面板100包括第一显示区S1和第二显示区S2，第一显示区S1的透光率大于第二显示区S2的透光率；第一显示区S1包括多个第一发光元件P1，第二显示区S2包括多个第二发光元件P2，第一发光元件P1和第二发光元件P2的分布密度相同；第二显示区S2包括多个第一像素电路C1和多个第二像素电路C2；第一像素电路C1和第一发光元件P1一一对应电连接；第二像素电路C2和第二发光元件P2一一对应电连接。
其中，第一显示区S1即上述感光功能区，该区域既可以用于实现诸如前置摄像和指纹识别等感光功能，又具备显示功能。第二显示区S2即显示面板的总显示区FA中除第一显示区S1以外的显示区域，具备显示功能。
需要说明的是，图2仅以显示面板包括一个第一显示区S1，第一显示区S1位于显示面板的总显示区FA的内部为例进行示意。在其他实施例中，显示面板可以包括更多数量的第一显示区S1，任一第一显示区S1可以与显示面板的总显示区FA的至少一个边缘毗邻，本申请实施例对第一显示区S1的数量和设置位置不作特殊限定。
如图2所示，第一显示区S1包括多个第一发光元件P1，第二显示区S2包括多个第二发光元件P2，第一发光元件P1和第二发光元件P2的分布密度相同，换而言之，相同空间内第一发光元件P1的数量与第二发光元件P2的数量相同。
示例性的，多个第一发光元件P1可以包括至少两种发光颜色不同的发光元件，多个第二发光元件P2可以包括至少两种发光颜色不同的发光元件，以实现彩色显示。示例性的，参见图2，第一发光元件P1和第二发光元件P2均包括发光颜色为红色的红色发光元件R、发光颜色为绿色的绿色发光元件G以及发光颜色为蓝色的蓝色发光元件B。示例性的，第一发光元件P1和第二发光元件P2的分布密度相同，可以理解为，在第一显示区S1和第二显示区S2内，相同空间的红色发光元件R的数量相同，相同空间的绿色发光元件G的数量相同，相同空间的蓝色发光元件B的数量相同，即相同发光颜色的发光元件在第一显示区S1和第二显示区S2的分布密度相同。
需要说明的是，第一显示区S1和第二显示区S2内发光颜色相同的第一发光元件P1和第二发光元件P2的面积可以相等，也可以不相等。示例性的，为提高第一显示区S1的透光率，可设置第一发光元件P1的面积小于与之发光颜色相同的第二发光元件P2的面积。或者，由于本申请实施例中第一显示区S1内未设置与第一发光元件P1对应电连接的第一像素电路C1，因此，在其他实施例中，在保证第一显示区S1的透光率需求的情况下，也可以适当增大第一发光元件P1的面积，使第一发光元件P1的面积大于与之发 光颜色相同的第二发光元件P2的面积，本申请实施例对此不作限定。
还需要说明的是，图2所示显示面板中，第一发光元件P1和第二发光元件P2的排布方式仅为示意，并非限定。本领域技术人员可以根据需求设置像素排布方式，本申请实施例对此不作限定，只要保证第一发光元件P1和第二发光元件P2的分布密度相同即可。
示例性的，第一发光元件P1和第二发光元件P2为有机发光二极管(Organic Light-Emitting Diode，OLED)。OLED包括层叠设置的阳极、发光层和阴极，图2所示第一发光元件P1或第二发光元件P2的形状可以理解为该发光元件中的阳极在显示面板所在平面的正投影的形状。需要说明的是，图2所示显示面板中，发光颜色相同的第一发光元件P1和第二发光元件P2的形状相同，且均为多边形仅为示意，并非限定。
图4是本申请实施例提供的另一种显示面板的结构示意图，如图4所示，在其他实施例中，第一发光元件P1包括第一阳极D1，第一阳极D1在显示面板所在平面的正投影的形状为圆形。如此设置，可以改善第一显示区S1的衍射现象，有利于提高显示面板下方对应第一显示区S1设置的感光元件的成像质量。需要说明的是，在其他实施例中，第一发光元件P1的第一阳极的形状也可以为类圆形，例如椭圆形，本申请实施例对此不作限定。
此外，图5是本申请实施例提供的另一种显示面板的结构示意图，如图5所示，示例性的，第二显示区S2包括第一显示区分部S21和第二显示区分部S22，与第一显示区分部S21中的第二发光元件P2相对应的第二像素电路C2位于第二显示区分部S22内。示例性的，第一显示区分部S21设置有多个第二发光元件P2，却未设置与这部分第二发光元件P2相对应的第二像素电路C2。如此，第一显示区分部S21也具有一定的透光率，可作为感光功能区，在显示面板下方对应第一显示区分部S21设置感光元件。在一实施例中，第一显示区S1对应摄像头区，第一显示区分部S21对应其他感光元件所在区域，例如，人脸识别(Face ID)等对入射光线的要求低于摄像头对入射光线的要求的感光元件，如此，第一显示区分部S21的透光率可低于第一显示区S1的透光率，此外，光出现衍射现象对人脸识别结果的影响较小，因此，第一显示区分部S21内的第二发光元件P2可以与第二显示区分部S22内的第二发光元件P2保持相同的面积和多边形形状，无需为改善衍射而将其调整为圆形或类圆形。
示例性的，本实施例中，用于驱动第一发光元件P1发光的像素电路称之为第一像素电路C1，用于驱动第二发光元件P2发光的像素电路称之为第二像素电路C2，以示区分。示例性的，第一像素电路C1和第二像素电路C2可以是由薄膜晶体管和存储电容构成的像素电路，例如业内常用的7T1C(T表示薄膜晶体管，C表示电容)像素电路，本申请实施例对此不作限定。
本申请实施例通过将与第一发光元件P1相对应的第一像素电路C1以及与第二发光元件P2相对应的第二像素电路C2均设置于第二显示区S2内，使得第一显示区S1内设置有第一发光元件P1而未设置第一像素电路C1，从而可以保证第一显示区S1对透光率的需求。
此外，由于第二显示区S2的空间充足，可以通过压缩至少部分像素电路(第一像素电路C1和/或第二像素电路C2)的尺寸，实现将第一像素电路C1和第二像素电路C2均设置于第二显示区S2内，同时保证第一像素电路C1和第一发光元件P1一一对应电连接，第二像素电路C2和第二发光元件P2一一对应电连接，实现像素电路对发光元件的一对一驱动，如此，在第一像素电路C1和第二像素电路C2具有相同驱动能力的情况下，相比于一个第一像素电路C1驱动多个第一发光元件P1发光而言，一对一驱动有利于提高第一发光元件P1的发光亮度，保证第一发光元件P1的实际发光亮度达到预期亮度，改善第一显示区S1的显示效果；此外，在保证每个发光元件的发光亮度的情况下，若一个像素电路驱动多个发光元件发光，则需要提高像素电路的驱动能力，相比之下，本申请实施例设置第一像素电路C1与第一发光元件P1一一对应电连接，第二像素电路C2与第二发光元件P2一一对应电连接，有利于降低对像素电路的驱动能力的要求，延长像素电路中的元器件的使用寿命；另外，通过设置像素电路对发光元件进行一对一驱动，有利于更加灵活地单独调整多个发光元件的发光亮度，改善显示效果。
本实施例中，由于第一像素电路C1和第一发光元件P1一一对应电连接，第二像素电路C2和第二发光元件P2一一对应电连接，且第一发光元件P1和第二发光元件P2的分布密度相同，从而可使第一显示区S1和第二显示区S2具有相同的显示PPI，有效改善第一显示区S1的显示效果。示例性的，当第一发光元件P1和第二发光元件P2的分布密度相同时，若一个第一像素电路C1同时驱动多个第一发光元件P1，而一个第二像素电路C2驱动一个第二发光元件P2，在第一像素电路C1和第二像素电路C2的驱动能力相同的情况下，使得第一显示区S1内的多个第一发光元件P1的发光亮度仅相当于第二显示区S2内的一个第二发光元件P2的发光亮度，导致第一显示区S1内每英寸所拥有的实际显示像素的数量低于第二显示区S2内每英寸所拥有的实际显示像素的数量，导致第一显示区S1的显示效果不佳。相比之下，本申请实施例通过设置第一像素电路C1和第一发光元件P1一一对应电连接，第二像素电路C2和第二发光元件P2一一对应电连接，并且设置第一发光元件P1和第二发光元件P2的分布密度相同，从而可使第一显示区 S1和第二显示区S2的每英寸所拥有的显示像素一致，使二者具有相同的显示PPI，有效改善第一显示区的显示效果。
示例性的，可以通过减小像素电路中的线宽、线距等方式压缩像素电路的尺寸。示例性的，显示面板包括多条扫描线和多条数据线，扫描线和数据线的延伸方向相交，且扫描线和数据线均与像素电路的设置区域存在交叠和电连接关系，可以通过压缩像素电路沿扫描线延伸方向的长度，和/或，通过压缩像素电路沿数据线延伸方向的长度，压缩像素电路的尺寸。例如，可以通过压缩扫描线沿数据线延伸方向的宽度，和/或，压缩相邻两条扫描线在数据线延伸方向上的距离，来压缩像素电路沿数据线延伸方向的长度。又如，可以通过压缩数据线或功率电源PVDD信号线沿扫描线延伸方向的宽度，和/或，压缩相邻两条数据线、相邻两条PVDD信号线和相邻两条数据线和PVDD信号线中的至少一对信号线在扫描线延伸方向上的距离，来压缩像素电路沿扫描线延伸方向的长度。
如图3所示，第一发光元件P1与其对应的第一像素电路C1位于不同的区域，可以通过连接线8将二者电连接，示例性的，与一条连接线8的两端交叠的发光元件(第一发光元件P1/第二发光元件P2)和像素电路(第一像素电路C1/第二像素电路C2)，表示该连接线所连接的像素电路和发光元件(下同)。例如，图3中，第一发光元件P1-1通过连接线8与第一像素电路C1-1电连接。此外，由于第一显示区S1的面积远小于第二显示区S2的面积，因此，可能只需要调整部分第二像素电路C2的面积和位置，即可实现将第一像素电路C1设置于第二显示区S2内，此时，部分第二发光元件P2和与之对应的第二像素电路C2的相对位置关系未做调整，二者仍在垂直于显示面板所在平面的方向上存在交叠，因而可以通过过孔将二者电连接。对此，图3以一个第二发光元件P2和一个第二像素电路C2交叠，且二者同时与一个实心圆点交叠，表示该第二发光元件P2与该第二像素电路C2电连接(下同)。例如，图3中，第二发光元件P2-1与第二像素电路C2-1交叠，且二者均与一实心圆点交叠，表示第二发光元件P2-1与第二像素电路C2-1电连接。
需要说明的是，图3所示第一像素电路C1和第二像素电路C2的分布方式仅为示意，并非限定，第一像素电路C1和第二像素电路C2可以以任意方式分布于第二显示区S2内，本申请实施例对此不做限定，后续做示例性说明。并且，一个第二发光元件P2还可以与其相邻但并未电连接的至少一个第二像素电路C2电连接。
综上，本申请实施例通过设置显示面板包括第一显示区和第二显示区，并设置第一显示区包括多个第一发光元件，第二显示区包括多个第二发光元件、多个第一像素电路和多个第二像素电路，使第一发光元件和第二发光元件的分布密度相同，且第一像素电路和第一发光元件一一对应电连接，第二像素电路与第二发光元件一一对应电连接，如此，由于第一显示区内仅设置有第一发光元件，从而可以保证第一显示区对透光率的要求，由于第二显示区的空间更为充足，可以通过压缩至少部分像素电路的尺寸，将与第一显示区的第一发光元件相对应的第一像素电路以及与第二显示区的第二发光元件相对应的第二像素电路均设置于第二显示区内，并且实现一个第一像素电路驱动一个第一发光元件，一个第二像素电路驱动一个第二发光元件，又由于第一发光元件和第二发光元件的分布密度相同，从而可使第一显示区和第二显示区具有相同的显示PPI，改善第一显示区的显示效果。
在上述实施例的基础上，图6是本申请实施例提供的另一种显示面板的结构示意图，如图6所示，示例性的，第二显示区S2包括第一子显示区1和第二子显示区2，第一子显示区1与第一显示区S1毗邻，第二子显示区2与第一子显示区1毗邻；与第一子显示区1的至少一个第二发光元件P2(如图6中第二发光元件P2-1和第二发光元件P2-2)相对应的第二像素电路C2位于第二子显示区2内。
需要说明的是，图6以第一发光元件P1为圆形，第二发光元件P2为菱形为例，示意出部分第一发光元件P1和部分第二发光元件P2，并对第一发光元件P1和第一像素电路C1的电连接关系，第二发光元件P2与第二像素电路C2的电连接关系，以及第一像素电路C1和第二像素电路C2所处的区域进行展示，图6中第一发光元件P1和第二发光元件P2的排布方式以及第一像素电路C1和第二像素电路C2的排布方式并不表示对实际排布方式的限定。
示例性的，第一子显示区1可以和第一显示区S1的至少部分边界毗邻。图6仅以第一子显示区1与第一显示区S1的全部边界毗邻为例进行示意，此时，第一显示区S1仅与第一子显示区1毗邻，第二子显示区2仅与第一子显示区1毗邻。图7是本申请实施例提供的另一种显示面板的结构示意图，如图7所示，在其他实施例中，第一子显示区1可以与第一显示区S1的部分边界毗邻，此时，第二子显示区2也与第一显示区S1毗邻。
参照图3，若只将第一像素电路C1设置于第二显示区S2，例如将第一像素电路C1设置于第一显示区S1下方与之毗邻的第一子显示区1内，使得位于同一行发光元件(同一行的第一发光元件P1和第二发光元件P2，或者同一行的第二发光元件P2)所对应的像素电路在第二方向y上出现错位，在显示面板中的分布较为分散，此时需要对扫描线Gate进行绕线，使一条扫描线与同一行发光元件对应的像素电路电连接， 以在显示驱动过程中，通过扫描线向同一行发光元件对应的像素电路发送扫描信号，实现同一行发光元件的同时点亮。同理，可以理解的，若将第一像素电路C1设置于沿第一方向x与第一显示区S1毗邻的第一子显示区1内，则需要对数据线进行绕线，以在显示驱动过程中，通过数据线向同一列发光元件对应的像素电路发送数据信号。相比于只将第一像素电路C1设置于第二显示区S2而言，本实施例通过将与第一显示区S1毗邻的第一子显示区1内的至少一个第二发光元件P2所对应的第二像素电路C2外置于第二子显示区2内，可以降低同一行或同一列发光元件所对应的像素电路在显示面板中的分散程度，减轻或避免信号线(如扫描线、数据线)的绕线程度，进而降低信号线的设置难度。此外，在一实施例中，通过将第一子显示区1的至少一个第二发光元件P2所对应的第二像素电路C2设置于第二子显示区2内，从而可以将第一子显示区1内第二像素电路C2被外置于第二子显示区2的第二发光元件P2所对应的区域复用为上述第一显示区分部S21，以利用该区域实现诸如人脸识别等功能，丰富显示装置的功能多样性。
图8是本申请实施例提供的另一种显示面板的结构示意图，如图8所示，示例性的，第一子显示区1包括第一分区11和第二分区12，第一分区11和第一显示区S1沿第一方向x毗邻，第二分区12和第一显示区S1沿第二方向y毗邻，第一方向x和第二方向y相交；第一像素电路C1位于第一分区11和第二分区12中的至少一者内。
示例性的，第一方向x和第二方向y正交，如此设置便于简化第一像素电路C1和第二像素电路C2的重新布局的难度。需要说明的是，图8仅以第一方向x为行方向，第二方向y为列方向为例进行示意，在其他实施例中，也可以是第一方向x为列方向，第二方向y为行方向，本申请实施例对此不作限定。示例性的，行方向可以与扫描线的延伸方向一致，相应的，列方向可以与数据线的延伸方向一致。后续仅以第一方向x为行方向，第二方向y为列方向为例进行说明。
示例性的，根据第一显示区S1在显示面板的总显示区FA的位置，第一子显示区1可以包括至少一个第一分区11和至少一个第二分区12。示例性的，图8中，第一显示区S1位于显示面板的总显示区FA的内部，此时，第一子显示区1包括沿第一方向x位于第一显示区S1相对两侧的两个第一分区11，以及沿第二方向y位于第一显示区S1相对两侧的两个第二分区12。此设置方式仅为示意，并非限定。示例性的，在其他实施例中，第一子显示区1可以包括为沿第一方向x与第一显示区S1毗邻的两个第一分区11以及沿第二方向y与第一显示区S1毗邻的一个第二分区12。
示例性的，可以将全部第一像素电路C1设置于第一分区11内；也可以将全部第一像素电路C1设置于第二分区12内；还可以将一部分第一像素电路C1设置于第一分区11内，并将另一部分第一像素电路C1设置于第二分区12内，本申请实施例对此不作限定。
示例性的，图8以第一像素电路C1均位于第一分区11内为例进行示意。此外，图9是本申请实施例提供的另一种显示面板的结构示意图，如图9所示，在其他实施例中，可以设置第一像素电路C1均位于第二分区12内。此外，还可参照图6，设置多个第一像素电路C1分别位于第一分区11和第二分区12内。本申请实施例通过将第一像素电路C1设置于与第一显示区S1毗邻的第一分区11和第二分区12的至少一者内，便于降低第一像素电路C1与第一发光元件P1的连接难度，以及显示面板内的布线难度，降低对产品良率的影响。
需要说明的是，当第一分区11的数量为两个时，可以根据需求将第一像素电路C1设置于其中至少一个第一分区11内，同理，当第二分区12的数量为两个时，可以根据需求将第一像素电路C1设置于其中至少一个第二分区12内，本申请实施例对此不作限定。
还需要说明的是，当第一像素电路C1位于第一分区11和第二分区12中的至少一者内时，针对与第一分区11和/或第二分区12(即第一子显示区1)内的至少一个第二发光元件P2相对应的第二像素电路C2，可以根据实际需求选择是否将其设置于第二子显示区2内，本申请实施例对此不作限定。图8仅以第一分区11内的第二发光元件P2所对应的第二像素电路C2仍然位于第一分区11内为例进行示意，图9仅以第二分区12内的第二发光元件P2所对应的第二像素电路C2仍然位于第二分区12内为例进行示意，在其他实施例中，可以参照图6，将第一分区11和/或第二分区12内的至少一个第二发光元件P2所对应的第二像素电路C2设置于第二子显示区2内。
继续参见图6，示例性的，第一显示区S1沿第一方向x的最大宽度H4等于第二分区12沿第一方向x的最大宽度H2；第一显示区S1沿第二方向y的最大宽度H3等于第一分区11沿第二方向y的最大宽度H1。如此设置，可以通过平移并压缩第一像素电路C1和/或第二像素电路C2的尺寸的方式，将第一像素电路C1设置于第一分区11和第二分区12的至少一者内，有利于降低像素电路的布局难度和显示面板的布线难度，降低对产品良率的影响。
需要说明的是，图6仅以第一显示区S1为矩形为例进行示意，并非限定。图10是本申请实施例提供的另一种显示面板的结构示意图，如图10所示，在其他实施例中，第一显示区S1也可以是圆形。当然，第一显示区S1还可以是本领域技术人员任意可知的其他形状，本申请实施例对此不作限定。
如图10所示，当第一显示区S1为圆形时，同样可以设置第一子显示区1包括第一分区11和第二分区12，第一分区11和第一显示区S1沿第一方向x毗邻，第二分区12和第一显示区S1沿第二方向y毗邻，第一显示区S1沿第一方向x的最大宽度H4等于第二分区12沿第一方向x的最大宽度H2，第一显示区S1沿第二方向y的最大宽度H3等于第一分区11沿第二方向y的最大宽度H1。
需要说明的是，图10所示实施方式与图6的区别在于，由于第一显示区S1为圆形，当第一显示区S1沿第一方向x的最大宽度H4等于第二分区12沿第一方向x的最大宽度H2，第一显示区S1沿第二方向y的最大宽度H3等于第一分区11沿第二方向y的最大宽度H1时，使得第一分区11和第二分区12具有交叠区域。例如，图10中虚线b、虚线c以及第一显示区S1的外边界d围城的类似三角形的区域，为第一显示区S1右侧的第一分区11和第一显示区S1下方的第二分区12之间的交叠区域。为降低像素电路的布局难度，当第一显示区S1为圆形时，可以将第一分区11和第二分区12的交叠区域内的第二发光元件P2所对应的第二像素电路C2，随第一像素电路C1一起，移动至交叠区域之外的第一分区11和/或第二分区12内。
图11是本申请实施例提供的另一种显示面板的结构示意图，图12是本申请实施例提供的另一种显示面板的结构示意图，如图11和图12所示，当第一子显示区1包括第一分区11和第二分区12，第一像素电路C1位于第一分区11和第二分区12中的至少一者内，并且，与第一子显示区1的至少一个第二发光元件P2相对应的第二像素电路C2位于第二子显示区2内时，示例性的，第一像素电路C1位于第一区域3内；与第二区域4内的第二发光元件P2相对应的第二像素电路C2位于第二子显示区2内；其中，第一区域3为第一分区11和第二分区12中的一者，第二区域4为第一分区11和第二分区12中的另一者。示例性的，图11以第一区域3为第一分区11，第二区域4为第二分区12为例进行示意。如图11所示，在一实施例中，第一像素电路C1可以位于第一分区11内，与第二分区12内的第二发光元件P2相对应的第二像素电路C2可以位于第二子显示区2内。如此设置，可使第一显示区S1内的第一发光元件P1所对应的第一像素电路C1，以及沿第二方向y与第一显示区S1毗邻的第二分区12内的第二发光元件P2所对应的第二像素电路C2，分别位于沿第二方向y毗邻的第一分区11和第二子显示区2内，有利于减小沿第二方向y位于同一列的发光元件所对应的像素电路在第一方向x上的分散程度，甚至可使同一列发光元件所对应的像素电路位于同一列，从而可以减少数据线的绕线，降低布线难度，而且，由于第一显示区S1和第二分区12内未设置像素电路，从而可以避免在第一显示区S1周围的边框区进行数据线的绕线，进而可以减小边框宽度，改善显示效果。
需要说明的是，图11以第一发光元件P1为圆形，第二发光元件P2为菱形为例进行示意，以具有填充的矩形表示与第二分区12内的第二发光元件P2相对应的第二像素电路C2，以未填充的矩形表示第一分区11和第二子显示区2内原有的第二像素电路C2。此外，为便于示意第一像素电路C1的位置移动，对表示第一像素电路C1的矩形同样进行了填充。后续以相同的填充方式对不同区域的第二发光元件所对应的第二像素电路进行区分。
示例性的，图12以第一区域3为第二分区12，第二区域4为第一分区11为例进行示意。如图12所示，在另一实施例中，第一像素电路C1可以位于第二分区12内，与第一分区11内的第二发光元件P2相对应的第二像素电路C2可以位于第二子显示区2内。如此设置，可使第一显示区S1内的第一发光元件P1所对应的第一像素电路C1，以及沿第一方向x与第一显示区S1毗邻的第一分区11内的第二发光元件P2所对应的第二像素电路C2，分别位于沿第一方向x毗邻的第二分区12和第二子显示区2内，有利于减小沿第一方向x位于同一行的发光元件所对应的像素电路在第二方向y上的分散程度，甚至可使同一行发光元件所对应的像素电路位于同一行，从而可以减少扫描线的绕线，降低布线难度，而且，由于第一显示区S1和第一分区11内未设置像素电路，从而可以避免在第一显示区S1周围的边框区进行扫描线的绕线，进而可以减小边框宽度，改善显示效果。
需要说明的是，图12以第一发光元件P1为圆形，第二发光元件P2为菱形为例进行示意，以具有填充的矩形表示与第一分区11内的第二发光元件P2相对应的第二像素电路C2，以未填充的矩形表示第二分区12和第二子显示区2内原有的第二像素电路C2。此外，为便于示意第一像素电路C1的位置移动，对表示第一像素电路C1的矩形同样进行了填充。后续以相同的填充方式对不同区域的第二发光元件所对应的第二像素电路进行区分。
还需要说明的是，图12仅以所有第一像素电路C1位于第一显示区S1下方的第二分区12内，与第一分区11内的第二发光元件P2相对应的所有第二像素电路C2位于第一分区11下方的第二子显示区2内为例进行示意，此设置方式并非限定。示例性的，在其他实施例中，可以设置部分第一像素电路C1位于第一显示区S1上方的第二分区12内，另一部分第一像素电路C1位于第一显示区S1下方的第二分区12内，与第一分区11内的第二发光元件P2相对应的第二像素电路C2，可以分别设置于第一分区11上方的第二子显示区2以及第一分区11下方的第二子显示区2内。
由于第一分区11和第二分区12分别沿第一方向x和第二方向y与第一显示区S1毗邻，本申请实施例通过将第一像素电路C1设置于第一区域3(如第一分区11)内，将与第二区域4(如第二分区12)内的第二发光元件P2相对应的第二像素电路C2设置于第二子显示区2内，可使第一显示区S1内的第一发光元件P1所对应的第一像素电路以及第二区域4内的第二发光元件P2所对应的第二像素电路C2沿同一方向移动至第二显示区S2中除第二区域4以外的区域内，有利于降低像素电路的布局难度，降低像素电路的分散程度，进而降低显示面板的布线难度。
下面，以第一区域3为第二分区12，第二区域4为第一分区11为例，对第一像素电路C1和第二像素电路C2在第二分区12和第二子显示区2内的布局做示例性说明。
图13是与图12中区域Q4对应的一种显示面板的放大结构示意图，如图13所示，示例性的，第一区域3包括至少一个第一电路组51和至少一个第二电路组52，第一电路组51包括第一像素电路C1，第二电路组52包括第二像素电路C2，至少一个第一电路组51位于一第二电路组52靠近第一显示区S1的一侧；第二子显示区2包括至少一个第三电路组53和至少一个第四电路组54，第三电路组53包括与第二区域4的第二发光元件P2相对应的第二像素电路C2，第四电路组54包括第二子显示区2内的其他第二像素电路C2，至少一个第三电路组53位于一第四电路组54靠近第二区域4的一侧。
其中，第一电路组51包括第一像素电路C1是指，一个第一电路组51可以包括一个第一像素电路C1，或者，一个第一电路组51可以包括相邻设置的至少两个第一像素电路C1。同理，一个第二电路组52可以包括第一区域3内的一个第二像素电路C2，或者一个第二电路组52也可以包括第一区域3内相邻设置的至少两个第二像素电路C2；第三电路组53和第四电路组54可以参照第一电路组51的构成方式进行理解，在此不再赘述。
需要说明的是，同一第一电路组51中的多个第一像素电路C1的尺寸可以相同，也可以不同；不同第一电路组51中的第一像素电路C1的数量和尺寸可以相同，也可以不同，本申请实施例对此不作限定。同理，对于第二电路组52、第三电路组53和第四电路组54，同一电路组(第二电路组52/第三电路组53/第四电路组54)中的多个第二像素电路C2的尺寸可以相同，也可以不同，不同电路组(第二电路组52/第三电路组53/第四电路组54)中的第二像素电路C2的数量和尺寸可以相同，也可以不同，本申请实施例对此亦不作限定。
示例性的，位于同一行的像素电路(第一像素电路C1和/或第二像素电路C2)沿列方向(如y方向)的尺寸相等，位于同一列的像素电路(第一像素电路C1和/或第二像素电路C2)沿行方向(如x方向)的尺寸相等，如此设置，便于扫描线、数据线等信号线的设置，减少绕线，降低显示面板的设计和制造难度。
示例性的，图13以第一区域3包括多个第一电路组51和多个第二电路组52，第二子显示区2包括多个第三电路组53和多个第四电路组54为例进行示意。示例性的，参照图13，第一区域3内位于同一行的多个相邻的第一像素电路C1可构成一个第一电路组51；第一区域3内位于同一行的多个相邻的第二像素电路C2可构成一个第二电路组52(如52-1)；此外，第一区域3内位于相邻的至少两行的第二像素电路C2也可构成一个第二电路组52(如52-2)；第二子显示区2内，与第二区域4内的第二发光元件P2对应，且位于同一行的多个相邻的第二像素电路C2可构成一个第三电路组53；第二子显示区2内的其他第二像素电路C2中，位于同一行的多个相邻的第二像素电路C2可构成一个第四电路组54(如54-1)，此外，位于相邻的至少两行的第二像素电路C2也可构成一个第四电路组54(如54-2)。由于图13以第一像素电路C1位于第二分区12内，与第一分区11内的第二发光元件P2相对应的第二像素电路C2位于第二子显示区2内为例进行示意，此时，通过设置第一电路组51由同一行或相邻若干行的第一像素电路C1构成，第二电路组52/第三电路组53/第四电路组54由其所在区域的同一行或相邻若干行的第二像素电路C2构成，可使同一行第一发光元件P1和/或第二发光元件P2与同一行的第一像素电路C1和/或第二像素电路C2对应设置，从而只需要沿一个方向(图13中为第二方向y)调整像素电路的位置和尺寸，降低像素电路的布局难度，降低显示面板的布线难度，降低对产品良率的影响。
示例性的，图14是本申请实施例提供的一种显示面板的局部结构示意图，如图14所示，同一第一电路组51中的同一行第一像素电路C1与同一行第一发光元件P1对应电连接，同一第二电路组52中的同一行第二像素电路C2与第二分区12内位于同一行的第二发光元件P2对应电连接，同一第三电路组53中的同一行第二像素电路C2与第一分区11内位于同一行的第二发光元件P2对应电连接，同一第四电路组54中的同一行第二像素电路C2与第二子显示区2内的同一行的第二发光元件P2对应电连接，如此设置，可以实现同一行发光元件(第一发光元件P1和/或第二发光元件P2)所对应的像素电路(第一像素电路C1和/或第二像素电路C2)位于同一行，从而可以避免对扫描线Gate进行绕线，降低像素电路的布局难度，降低显示面板的布线难度，降低对产品良率的影响。
需要说明的是，图13仅以第一区域3内的第一电路组51和第二电路组52交替排列，第二子显示区2内的第三电路组53和第四电路组54交替排列为例进行示意，此设置方式并非限定。图15是与图12中区 域Q4对应的另一种显示面板的放大结构示意图，如图15所示，在其他实施例中，与第一显示区S1的一侧毗邻的第一区域3(如第二分区12)内，可以包括一个第一电路组51和一个第二电路组52，第一电路组51位于第二电路组52靠近第一显示区S1的一侧，同理，与第二区域4(如第一分区11)的一侧毗邻的第二子显示区2内，可以包括一个第三电路组53和一个第四电路组54，第三电路组53位于第四电路组54靠近第二区域4的一侧。如此设置，可使第一像素电路C1与第一发光元件P1靠近设置，第三电路组53中的第二像素电路C2与第二区域4内的第二发光元件P2靠近设置，便于将第一像素电路C1与第一发光元件P1电连接，将第三电路组53中的第二像素电路C2与第二区域4内的第二发光元件P2电连接，降低布线难度。
参照图13，示例性的，第一像素电路C1的尺寸等于第三电路组53中的第二像素电路C2的尺寸；第一像素电路C1的尺寸等于第二电路组52中的至少一个第二像素电路C2的尺寸；第三电路组53中的第二像素电路C2的尺寸等于第四电路组54中的至少一个第二像素电路C2的尺寸。
其中，第一像素电路C1的尺寸包括第一像素电路C1所在区域沿第一方向x的第一边长L1和沿第二方向y的第二边长L2；第二像素电路C2的尺寸包括第二像素电路C2所在区域沿第一方向x的第三边长L3和沿第二方向y的第四边长L4；若第一像素电路C1对应的第一边长L1和第二像素电路C2对应的第三边长L3相等，且第一像素电路C1对应的第二边长L2和第二像素电路C2对应的第四边长L4相等，则第一像素电路C1和第二像素电路C2的尺寸相等，否则，若第一像素电路C1对应的第一边长L1和第二像素电路C2的第三边长L3不等，和/或，第一像素电路C1对应的第二边长L2和第二像素电路C2对应的第四边长L4不等，则第一像素电路C1和第二像素电路C2的尺寸不等。同理，若两个第一像素电路C1所在区域的第一边长L1和第二边长L2分别对应相等，则这两个第一像素电路C1的尺寸相等，否则这两个第一像素电路C1的尺寸不等；若两个第二像素电路C2所在区域的第三边长L3和第四边长L4分别对应相等，则这两个第二像素电路C2的尺寸相等，否则这两个第二像素电路C2的尺寸不等。
示例性的，第一像素电路C1的尺寸等于第三电路组53中第二像素电路C2的尺寸是指，第三电路组53中的多个第二像素电路C2的尺寸均相等，且等于第一像素电路C1的尺寸。如此设置，由于第一像素电路C1和第三电路组53中的第二像素电路C2均与其对应的第一发光元件P1或第二发光元件P2位于不同的区域内，通过设置第一像素电路C1的尺寸等于第三电路组53中第二像素电路C2的尺寸，可以采用相同的方式对这部分第一像素电路C1和第二像素电路C2的位置和尺寸进行调整，有利于降低像素电路的布局难度。
示例性的，第一像素电路C1的尺寸等于第二电路组52中的至少一个第二像素电路C2的尺寸是指，对于所有的第二电路组52中的第二像素电路C2，第一像素电路C1的尺寸与其中至少一个第二像素电路C2的尺寸相等。同理，第三电路组53中的第二像素电路C2的尺寸等于第四电路组54中的至少一个第二像素电路C2的尺寸是指，对于所有的第四电路组54中的第二像素电路C2，第三电路组53中的第二像素电路C2的尺寸等于其中至少一个第二像素电路C2的尺寸。
对于不同的显示面板而言，其第一区域3和第二子显示区2内的第二发光元件P2所对应的第二像素电路C2的可压缩量不同，在满足线宽、线距要求的情况下，可能只需要压缩部分第二像素电路C2的尺寸即可实现将第一显示区S1内的第一发光元件P1所对应的第一像素电路C1设置于第一区域3内，将第二区域4内的第二发光元件P2所对应的第二像素电路C2设置于第二子显示区2内。
示例性的，图13中，第二电路组52-1中的多个第二像素电路C2的尺寸相等，且均等于第一像素电路C1组的尺寸；第二电路组52-2中的的个第二像素电路C2的尺寸相等，但不等于第一像素电路C1的尺寸(第二电路组52-2中的第二像素电路C2的第四边长L4大于第一像素电路C1的第二边长L2)；第四电路组54-1中的多个第二像素电路C2的尺寸相等，且均等于第三电路组53中的第二像素电路C2的尺寸；第四电路组54-2中的多个第二像素电路C2的尺寸相等，但不等于第三电路组53中的第二像素电路C2的尺寸(第四电路组54-2中的第二像素电路C2的第四边长L4大于第三电路组53中的第二像素电路C2的第四边长L4)。
当然，图13所示实施方式仅为其中一种可行的实施方式。在其他实施例中，参见图15，示例性的，第二电路组52包括第一电路分组521和第二电路分组522，第一电路分组521和第二电路分组522中的第二像素电路C2的尺寸不等，且第一电路分组521位于第二电路分组522靠近第一电路组51的一侧；第一电路分组521中的第二像素电路C2的尺寸等于第一像素电路C1的尺寸；第四电路组54包括第三电路分组541和第四电路分组542，第三电路分组541和第四电路分组542中的第二像素电路C2的尺寸不等，且第三电路分组541位于第四电路分组542靠近第三电路组53的一侧；第三电路分组541中的第二像素电路C2的尺寸等于第三电路组53中的第二像素电路C2的尺寸。
示例性的，本实施例中，第二电路组52位于第一电路组51远离第一显示区S1的一侧，第二电路组52分为第一电路分组521和第二电路分组522，其中，第一电路分组521中的多个第二像素电路C2的尺 寸均相等，第二电路分组522中的多个第二像素电路C2的尺寸均相等，第一电路分组521中的第二像素电路C2和第二电路分组522中的第二像素电路C2尺寸不等(第四边长L4不相等)，第一电路分组521位于第二电路分组522靠近第一电路组51的一侧，且第一电路分组521中的第二像素电路C2的尺寸等于第一像素电路C1的尺寸。此时，只需要压缩第一区域3内原有的部分第二像素电路C2的尺寸形成第一电路分组521，便可将尺寸压缩后的第一像素电路C1设置于第一区域3内，并且，如此设置可使第一电路组51更加靠近第一显示区S1，便于第一像素电路C1和对应的第一发光元件P1电连接，降低布线难度，降低对产品良率的影响。
此外，本实施例中，第三电路组53位于第四电路组54靠近第二区域4的一侧，第四电路组54包括第三电路分组541和第四电路分组542，其中，第三电路分组541中的多个第二像素电路C2的尺寸均相等，第四电路分组542中的多个第二像素电路C2的尺寸均相等，第三电路分组541中的第二像素电路C2和第四电路分组542中的第二像素电路C2尺寸不等(第四边长L4不相等)，第三电路分组541位于第四电路分组542靠近第三电路组53的一侧，且第三电路分组541中的第二像素电路C2的尺寸等于第三电路组53中的第二像素电路C2的尺寸。此时，只需要压缩第二子显示区2内原有的部分第二像素电路C2的尺寸形成第三电路分组541，便可将第二区域4的第二发光元件P2所对应的第二像素电路C2压缩尺寸后设置于第二子显示区2内，并且，如此设置可使第三电路组53更加靠近第二区域4，便于第三电路组53中的第二像素电路C2与第二区域4内对应的第二发光元件P2电连接，降低布线难度，降低对产品良率的影响。
在其他实施例中，在满足线宽、线距要求的前提下，也可以压缩所有第一像素电路C1和第二像素电路C2的尺寸，使第一像素电路C1和第二像素电路C2的尺寸均相等。如此，可使第一像素电路C1和第二像素电路C2具有相同的驱动能力，有利于显示均一性。
图16是与图12中区域Q4对应的另一种显示面板的放大结构示意图，如图16所示，示例性的，第一像素电路C1与第二像素电路C2的尺寸均相等；显示面板100还包括多个第一虚拟像素电路C01，第一虚拟像素电路C01位于第一区域3和第二子显示区2内，且第一虚拟像素电路C01在显示面板所在平面的正投影与第一像素电路C1和第二像素电路C2在显示面板所在平面的正投影均不交叠。
示例性的，当第一像素电路C1与第二像素电路C2的尺寸均相等时，若第一像素电路C1和第二像素电路C2的尺寸压缩程度较大，则可能出现第一区域3和第二子显示区2在容纳第一像素电路C1和第二像素电路C2之后，仍有空余空间的情况。像素电路中的金属结构会反射环境光，本申请实施例通过在第一区域3和第二子显示区2内设置第一虚拟像素电路C01，使第一虚拟像素电路C01在显示面板所在平面的正投影与第一像素电路C1和第二像素电路C2在显示面板所在平面的正投影均不交叠，可以利用第一虚拟像素电路C01均衡像素电路在显示面板中的分布，从而可以平衡显示面板不同区域间的反射率差异，避免局部未设置像素电路而使人眼视觉上出现分屏现象。
同理，参见图15或图16，示例性的，第二区域4内设置有第二虚拟像素电路C02。需要说明的是，第一虚拟像素电路C01/第二虚拟像素电路C02的结构与第一像素电路C1/第二像素电路C2的结构相同，区别仅在于第一虚拟像素电路C01和第二虚拟像素电路C02均无法驱动第一发光元件P1和第二发光元件P2中的任一者发光。本领域技术人员可以采取任意方式达到虚拟像素电路无法驱动发光元件发光的目的，如虚拟像素电路未与扫描线、数据线、PVDD线电连接，或者虚拟像素电路未与发光元件电连接，或者虚拟像素电路虽与发光元件电连接，但发光元件本身无法实现被驱动发光(如阴极、阳极、像素限定层开口、发光层中的至少一者缺失)，本申请实施例对此不作限定。此外，第一虚拟像素电路C01/第二虚拟像素电路C02的尺寸可以与第一像素电路C1/第二像素电路C2的尺寸相同，也可以不相同，本申请实施例对此不作限定。
下面，针对第一虚拟像素电路C01在第一区域3和第二子显示区2内的布局做示例性说明。
参见图16，示例性的，第一虚拟像素电路C01位于第二电路组52远离第一电路组51的一侧，且位于第四电路组54远离第三电路组53的一侧。如此设置，可以降低对第一像素电路C1和第二像素电路C2的布局的影响，降低像素电路的布局难度。
当然，图16所示第一虚拟像素电路C01的设置方式仅为其中一种可行的实施方式，在其他实施例中，如图17所示，图17是与图12中区域Q4对应的另一种显示面板的放大结构示意图，示例性的，至少一个第一虚拟像素电路C01位于相邻两个第一像素电路C1和/或第二像素电路C2之间。
示例性的，第一虚拟像素电路C01可以穿插至第一像素电路C1和第二像素电路C2的布局之中。示例性的，一个第一虚拟像素电路C01可以位于相邻两个第一像素电路C1之间，也可以位于相邻两个第二像素电路C2之间，还可以位于相邻两个第一像素电路C1和第二像素电路C2之间，本申请实施例对此不做限定。
参照图17，示例性的，任意两个沿第一方向x相邻的第一虚拟像素电路C01之间包括m个实际像素 电路；其中，m为自然数；m＞0时，m个实际像素电路包括第一像素电路C1和第二像素电路C2中的至少一者；任意两个沿第二方向y相邻的第一虚拟像素电路C01之间包括n个实际像素电路；其中，n为自然数；n＞0时，n个实际像素电路包括第一像素电路C1和第二像素电路C2中的至少一者；m和n不同时为0。
其中，实际像素电路是指第一像素电路C1和第二像素电路C2等与第一发光元件P1或第二发光元件P2存在电连接关系的像素电路。沿第一方向x或第二方向y，当相邻两个第一虚拟像素电路C01之间存在实际像素电路时，该实际像素电路可以是第一像素电路C1和第二像素电路C2中的至少一者。
示例性的，图17以m＝0，n＝3为例进行示意，此时，任意两个沿第一方向x相邻的第一虚拟像素电路C01之间不存在实际像素电路，任意两个沿第二方向y相邻的第一虚拟像素电路C01之间包括3个实际像素电路，多个第一像虚拟像素电路同行设置，且穿插于若干行的实际像素电路之间。
图18是与图12中区域Q4对应的另一种显示面板的放大结构示意图，如图18所示，在其他实施例中，可设置m≠0(图18以m＝3为例进行示意)，n＝0，此时，任意两个沿第一方向x相邻的第一虚拟像素电路C01之间包括3实际像素电路，任意两个沿第二方向y相邻的第一虚拟像素电路C01之间不存在实际像素电路，多个第一虚拟像素电路C01同列设置，且穿插于若干列的实际像素电路之间。
当然，在其他实施例中，m和n可均不等于0。示例性的，图19是与图12中区域Q4对应的另一种显示面板的放大结构示意图，图19以m＝3，n＝2为例进行示意，此时，任意两个沿第一方向x相邻的第一虚拟像素电路C01之间包括3实际像素电路，任意两个沿第二方向y相邻的第一虚拟像素电路C01之间包括2个实际像素电路，多个第一像虚拟像素电路独立穿插于相邻两个实际像素电路之间。可以理解的，当m＝n时，第一虚拟像素电路C01均匀地穿插于相邻两个实际像素电路之间。
图20是与图12中区域Q4对应的另一种显示面板的放大结构示意图，如图20所示，示例性的，第一像素电路C1和第二像素电路C2的尺寸均相等，且分布于第二显示区S2中除第二区域4以外的区域。示例性的，本实施例中，第一区域3和第二子显示区2内未设置第一虚拟像素电路C01，如此，可使第一像素电路C1和第二像素电路C2的压缩程度相对较小，即相比于第一区域3和第二子显示区2内设置有第一虚拟像素电路C01的方案而言，可使第一像素电路C1和第二像素电路C2的尺寸相对较大，保证线宽、线距具有一定的设计余量，进而降低短路风险，保证产品良率。
需要说明的是，图20仅以一个第一区域3包括一个第一电路组51和一个第二电路组52，第一电路组51位于第二电路组52靠近第一显示区S1的一侧，一个第二子显示区2包括一个第三电路组53和一个第四电路组54，第三电路组53位于第四电路组54靠近第二区域4的一侧，且第一电路组51中的多个第一像素电路C1的尺寸以及第二电路组52、第三电路组53和第四电路组54中的多个第二像素电路C2的尺寸均相等为例进行示意。此设置方式并非限定，在其他实施例中，一个第一区域3可以包括多个交替设置的第一电路组51和第二电路组52，一个第二子显示区2可以包括多个交替设置的第三电路组53和第四电路组54，本申请实施例对第一像素电路C1和第二像素电路C2的排布方式不作限定，只要保证第一像素电路C1和第二像素电路C2的尺寸均相等即可。
还需要说明的是，为便于展示，图13-图20仅以第一区域3为第二分区12，第二区域4为第一分区11，且第一子显示区1包括一个第一分区11和一个第二分区12为例进行示意，图12中其他第二分区12和第二子显示区2内的第一像素电路C1和第二像素电路C2的布局可以参照图13-图20中的任意一种设置方式进行对称式布局，在此不再赘述。
参照图12，还需要说明的是，当第一显示区S1为摄像头区，第一像素电路C1位于第二分区12，与第一分区11的第二发光元件P2对应的第二像素电路C2位于第二子显示区2时，由于图12中第一显示区S1上方的第二分区12，以及第一分区11上方的两个第二子显示区2的面积通常较小，因此，该第二分区12可以根据实际情况选择是否用于设置部分第一像素电路C1，同理，第一分区11上方的两个第二子显示区2可以实际情况选择是否用于设置第一分区11的第二发光元件P2所对应的部分第二像素电路C2，本申请实施例对此不作限定。
综上，上述实施例以第一区域3为第二分区12，第二区域4为第一分区11，第一像素电路C1位于第二分区12，与第一分区11的第二发光元件P2相对应的第二像素电路C2位于第二子显示区2内为例，对第一像素电路C1和第二像素电路C2的设置方式做了详细说明。上述任一实施方式均可借鉴应用于第一区域3为第一分区11，第二区域4为第二分区12的实施例之中。下面，以第一区域3为第一分区11，第二区域4为第二分区12为例，对第一像素电路C1和第二像素电路C2的设置方式做简要举例说明。
示例性的，图21是与图12中区域Q4对应的另一种显示面板的放大结构示意图，如图21所示，第一区域3为第一分区11，第二区域4为第二分区12，第一像素电路C1位于第一分区11内，与第二分区12内的第二发光元件P2相对应的第二像素电路C2位于第二子显示区2内。图21对表示第一像素电路C1以及与第二分区12内的第二发光元件P2相对应的第二像素电路C2所在区域的矩形进行填充，以便区分。 图21所示实施方式中，显示面板的其中一个第一分区11内包括一个第一电路组51和一个第二电路组52，第一电路组51位于第二电路组52靠近第一显示区S1的一侧，显示面板的其中一个第二子显示区2内包括一个第三电路组53和一个第四电路组54，第三电路组53位于第四电路组54靠近第二分区12的一侧，第一像素电路C1和第二像素电路C2的尺寸均相等，且第一分区11内设置有第二虚拟像素电路C02。其他关于第一像素电路C1和第二像素电路C2的可行的设置方式可参照第一区域3为第二分区12，第二区域4为第一分区11的相关实施例进行设置，在此不再一一赘述。
在上述实施例的基础上，图22是本申请实施例提供的另一种显示面板的结构示意图，如图22所示，示例性的，沿第一显示区S1指向第二区域4的方向，位于同一排的第一发光元件P1依次与位于同一排的第一像素电路C1一一对应电连接，位于同一排的第二发光元件P2依次与位于同一排的第二像素电路C2一一对应电连接。
如上所述，第二区域4可以为第一分区11和第二分区12中的其中一者。参照图6，以第一方向x为行方向，第二方向y为列方向为例，若第二区域4为第一分区11，则沿第一显示区S1指向第二区域4的方向即行方向，位于同一排的第一发光元件P1即位于同一行的第一发光元件P1，位于同一排的第一像素电路C1即位于同一行的第一像素电路C1，位于同一排的第二发光元件P2即位于同一行的第二发光元件P2，位于同一排的第二像素电路C2即位于同一行的第二像素电路C2。
同理，继续参照图6，若第二区域4为第二分区12，则沿第一显示区S1指向第二区域4的方向即列方向，位于同一排的第一发光元件P1即位于同一列的第一发光元件P1，位于同一排的第一像素电路C1即位于同一列的第一像素电路C1，位于同一排的第二发光元件P2即位于同一列的第二发光元件P2，位于同一排的第二像素电路C2即位于同一列的第二像素电路C2。
示例性的，图22以第二区域4为第一分区11为例进行示意。如图22所示，位于同一行的第一发光元件P1依次与位于同一行的第一像素电路C1一一对应电连接，位于同一行的第二发光元件P2依次与位于同一行的第二像素电路C2一一对应电连接。在其他实施例中，第二区域4可以为第二分区12，此时，位于同一列的第一发光元件P1依次与位于同一列的第一像素电路C1一一对应电连接，位于同一列的第二发光元件P2依次与位于同一列的第二像素电路C2一一对应电连接。
沿第一显示区S1指向第二区域4的方向，本申请实施例通过设置位于同一排的第一发光元件P1依次与位于同一排的第一像素电路C1一一对应电连接，并设置位于同一排的第二发光元件P2依次与位于同一排的第二像素电路C2一一对应电连接，可使第一显示区S1和第二区域4内位于同一排的第一发光元件P1和第二发光元件P2所对应的第一像素电路C1和第二像素电路C2位于同一排，从而可以降低像素电路的分散程度，同时有利于扫描线或数据线等信号线的布线，减少绕线，降低对产品良率的影响。
需要说明的是，相邻两排(行/列)第一发光元件P1所对应的两排第一像素电路C1可以相邻设置，也可以不相邻设置，同理，相邻两排第二发光元件P2所对应的两排第二像素电路C2可以相邻设置，也可以不相邻设置，本申请实施例对此不作限定。
继续参见图22，示例性的，第一发光元件P1和对应的第一像素电路C1通过第一连接线81电连接；至少部分第二发光元件P2和对应的第二像素电路C2通过第二连接线82电连接；沿第一区域3指向第一显示区S1的方向，越靠近第一显示区S1的第一像素电路C1所对应的第一连接线81的长度越长，越靠近第一显示区S1或第二区域4的第二像素电路C2所对应的第二连接线82的长度越长。如图22所示，与第一像素电路C1电连接的连接线为第一连接线81，越靠近第一显示区S1的第一像素电路C1所对应的第一连接线81的长度越长(例如Z1＞Z2)，与第二像素电路C2电连接的连接线为第二连接线82，越靠近第一显示区S1或第二区域4的第二像素电路C2所对应的第二连接线82的长度越长(例如Z4＞Z5)。为便于观察，图22仅示意出一部分第一发光元件P1与第一像素电路C1之间的第一连接线81，以及一部分第二发光元件P2与第二像素电路C2之间的第二连接线82。
示例性的，当第一区域3为第二分区12时，第一区域3指向第一显示区S1的方向平行于第二方向y(与图示y方向相同或相反)，当第一区域3为第一分区11时，第一区域3指向第一显示区S1的方向平行于第一方向x(与图示x方向相同或相反)。示例性的，参照图12，以第一区域3为第二分区12为例，第一显示区S1下方的第二分区12指向第一显示区S1的方向与y方向相同，第一显示区S1上方的第二分区12指向第一显示区S1的方向与y方向相反。
无论第一像素电路C1位于哪个第一区域3，通过设置越靠近第一显示区S1的第一像素电路C1所对应的第一连接线81越长，可使位于同一第一区域3内，且沿该第一区域3指向第一显示区S1的方向排列的多个第一像素电路C1的相对位置关系，与其对应的多个第一发光元件P1的相对位置关系相同(该多个第一发光元件P1同样沿其第一像素电路C1所在的第一区域3指向第一显示区S1的方向排列)，从而有利于提高第一连接线81的布线规律性，降低布线复杂度，降低对产品良率的影响。同理，通过设置越靠近第一显示区S1或第二区域4的第二像素电路C2所对应的第二连接线82的长度越长，可使位于同一第一 区域3内，且沿该第一区域3指向第一显示区S1的方向排列的多个第二像素电路C2的相对位置关系，与其对应的多个第二发光元件P2的相对位置关系相同，此外，可使位于同一第二子显示区2，且沿该第二子显示区2指向第二区域4的方向排列的多个第二像素电路C2的相对位置关系，与其对应的多个第二发光元件P2的相对位置关系相同，从而有利于提高第二连接线82的布线规律性，降低布线复杂度，降低对产品良率的影响。
需要说明的是，图22仅以沿第一区域3指向第一显示区S1的方向排列的多个第一像素电路C1相邻设置且靠近第一显示区S1，沿第二子显示区2指向第二区域4的方向排列，且与第二区域4内的第二发光元件P2相对应的多个第二像素电路C2相邻设置且靠近第二区域4为例进行示意，在其他实施例中，沿第一区域3指向第一显示区S1的方向排列的多个第一像素电路C1中，相邻两个第一像素电路C1之间可以包括若干第二像素电路C2，与第二区域4内的第二发光元件P2相对应的第二像素电路C2之间可以包括第四电路组54中的若干第二像素电路C2(参照图13)，本申请实施例对此不作限定。
如图22所示，在一实施例中，显示面板100还包括非显示区FNA，非显示区FNA包括绑定区S3，第一子显示区1包括至少一个第一区域3，其中一个第一区域3位于第一显示区S1与绑定区S3之间，第一像素电路C1均位于该第一区域3内，与第二区域4内的第二发光元件P2相对应的第二像素电路C2均位于与该第一区域3毗邻的第二子显示区2内，沿第一显示区S1指向第二区域4的方向，位于同一排的第一发光元件P1依次与位于同一排的第一像素电路C1一一对应电连接，位于同一排的第二发光元件P2依次与位于同一排的第二像素电路C2一一对应电连接，并且，沿第一显示区S1指向绑定区S3的方向，第i排发光器件与第i排实际像素电路对应电连接，i为正整数；其中，一排发光器件包括第一发光元件P1和第二发光元件P2中的至少一者，一排实际像素电路包括第一像素电路C1和第二像素电路C2中的至少一者。
通常，绑定区S3位于显示面板的下边框，即沿列方向位于显示面板的底端，因此，当第二方向y为列方向时，第一区域3为第二分区12，第二区域4则为第一分区11，第一区域3的数量与第二分区12的数量一致，第二区域4的数量与第一分区11的数量一致，例如可以参照上文描述根据第一显示区S1所处的位置确定。
以第一显示区S1为摄像头区为例，第一显示区S1通常与总显示区的上边界毗邻或靠近总显示区的上边界，图22以第一显示区S1与总显示区的上边界毗邻为例进行示意，第一显示区S1与绑定区S3之间包括一个第一区域3，该第一区域3的面积较大。从图22可以看出，本实施例通过将第一像素电路C1设置于第一显示区S1与绑定区S3之间的第一区域3内，将与第二区域4的第二发光元件P2相对应的第二像素电路C2设置于与该第一区域3毗邻的第二子显示区2内，将沿第一显示区S1指向第二区域4的方向位于同一行的第一发光元件P1依次与位于同一行的第一像素电路C1一一对应电连接，将沿第一显示区S1指向第二区域4的方向位于同一行的第二发光元件P2依次与位于同一行的第二像素电路C2一一对应电连接，并且，沿第一显示区S1指向绑定区S3的方向，设置第i排发光器件与第i排实际像素电路对应电连接，从而可使第i排实际像素电路对应的连接线的长度大于第i+1排实际像素电路对应的连接线的长度，即，越靠近第一显示区S1的实际像素电路对应的连接线(第一连接线81或第二连接线82)的长度越长。如图22所示，图示第二列前三个绿色发光元件G对应的连接线长度的长度依次为Z1、Z2、Z3，采用上述设置方式可使Z1＞Z2＞Z3。
如此，由于驱动芯片与绑定区S3电连接，并通过数据线向多个实际像素电路传输数据信号，实际像素电路距离绑定区S3越远，数据线负载越大，即通过数据线向实际像素电路传输数据信号时本身便存在负载渐变的情况，相关技术可通过采用一定的软件算法改善显示均一性，而本实施例采用上述设置方式可使越远离绑定区S3的实际像素电路对应的连接线的长度越长，从而可以保持该负载渐变的情况，不必打破相关技术中的驱动软件算法，有利于保证显示均一性。
图23是本申请实施例提供的一种显示面板的剖面结构示意图，如图23所示，显示面板100包括衬底901、像素电路层6以及发光元件层7。其中，像素电路层6包括多个第一像素电路和多个第二像素电路，图23仅示意出第一像素电路中的一个薄膜晶体管T1，以及第二像素电路中的一个薄膜晶体管T2。发光元件层7包括多个第一发光元件P1和多个第二发光元件P2，第一发光元件P1位于第一显示区S1，第二发光元件P2位于第二显示区S2，像素电路层6中的像素电路与对应的发光元件电连接。如图23所示，第一发光元件P1与第一像素电路C1通过第一连接线81电连接，第二发光元件P2与第二像素电路C2通过第二连接线82电连接。
继续参见图23，衬底901至发光元件层7之间包括依次层叠设置的缓冲层902、有源层911、栅绝缘层903、第一金属层912、第一层间介质层904、电容极板层913、第二层间介质层905、第三层间介质层906、第二金属层914、第四层间介质层907、图23第一平坦化层908、第三金属层915、第二平坦化层909、第一连接线81和第二连接线82所在导电膜层、第三平坦化层910和像素限定层911；第一发光元件P1 和第二发光元件P2均包括阳极916、发光层917和阴极918。其中，第一金属层912至少用于形成薄膜晶体管的栅极，电容极板层913至少用于形成存储电容的电容极板，第二金属层914至少用于形成薄膜晶体管的源极和漏极，第三金属层915用于形成连接薄膜晶体管的源极(漏极)与连接线(第一连接线81或第二连接线82)的金属结构，像素限定层911具有像素开口，该像素开口露出发光元件的阳极916，且发光层917的材料沉积于像素开口内。示例性的，第一连接线81和第二连接线82位于第二平坦化层909和第三平坦化层910之间。
需要说明的是，图23仅以第一连接线81和第二连接线82位于同一层为例进行示意，在其他实施例中，至少一条第一连接线81和/或至少一条第二连接线82可以与其他第一连接线81和第二连接线82位于不同的膜层，本申请实施例对此不作限定。
参照图23，示例性的，第一连接线81包括第一连接分部811，第一连接分部811位于第一显示区S1；至少一条第一连接分部811为透明走线。
其中，透明走线对光线的透过率远大于透明走线对光线的反射率，透明走线对光线的反射率甚至可以为零，例如可以根据选用的透明走线的材质决定。
其中，第一连接分部811位于第一显示区S1可以理解为，第一连接分部811在显示面板所在平面的正投影位于第一显示区S1。由于第一显示区S1需要使携带物体信息的光线穿过显示面板射向显示面板背面(非显示侧)的感光元件，被感光元件接收和识别，因此，第一显示区S1对透光率的要求较高，本申请实施例通过设置至少一条第一连接分部811为透明走线，有利于降低对第一显示区S1的透光率的影响。
需要说明的是，可以设置所有第一连接线81的第一连接分部811均为透明走线，也可以设置一部分第一连接线81的第一连接分部811为透明走线，本申请实施例对此不作限定。示例性的，若一条第一连接线81的第一连接分部811位于第一显示区S1的边缘，由于第一显示区S1的边缘的透光量对成像质量的影响相对较小，因此，该第一连接分部811也可以采用金属走线。
还需要说明的是，第一连接线81可以整体设置为透明走线，也可以仅将位于第一显示区S1的第一连接分部811设置为透明走线，其余部分设置为金属走线，本申请实施例对此不作限定。此外，第二连接线82可以为透明走线，也可以为金属走线，本申请实施例对此亦不做限定。
基于同一构思，本申请实施例还提供了一种显示装置。图24是本申请实施例提供的一种显示装置的结构示意图，如图24所示，该显示装置200包括感光元件210和上述任一实施例提供的显示面板100，感光元件210与第一显示区S1对应设置。由于该显示装置包括上述任一实施例提供的显示面板，因而具备与上述显示面板相同的有益效果，相同之处可参照上述显示面板实施例的描述，在此不再赘述。本申请实施例提供的显示装置200可以为图24所示的手机，也可以为任何具有显示功能的电子产品，包括但不限于以下类别：电视机、笔记本电脑、桌上型显示器、平板电脑、数码相机、智能手环、智能眼镜、车载显示器、医疗设备、工控设备、触摸交互终端等，本申请实施例对此不作特殊限定。

Claims (19)

  1. 一种显示面板，包括第一显示区和第二显示区，所述第一显示区的透光率大于所述第二显示区的透光率；
    所述第一显示区包括多个第一发光元件，所述第二显示区包括多个第二发光元件，所述第一发光元件和所述第二发光元件的分布密度相同；
    所述第二显示区包括多个第一像素电路和多个第二像素电路；所述第一像素电路和所述第一发光元件一一对应电连接；所述第二像素电路和所述第二发光元件一一对应电连接。
  2. 根据权利要求1所述的显示面板，其中，所述第二显示区包括第一子显示区和第二子显示区，所述第一子显示区与所述第一显示区毗邻，所述第二子显示区与所述第一子显示区毗邻；
    与所述第一子显示区的至少一个所述第二发光元件相对应的所述第二像素电路位于所述第二子显示区内。
  3. 根据权利要求2所述的显示面板，其中，所述第一子显示区包括第一分区和第二分区，所述第一分区和所述第一显示区沿第一方向毗邻，所述第二分区和所述第一显示区沿第二方向毗邻，所述第一方向和所述第二方向相交；
    所述第一像素电路位于所述第一分区和所述第二分区中的至少一者内。
  4. 根据权利要求3所述的显示面板，其中，所述第一显示区沿所述第一方向的最大宽度等于所述第二分区沿所述第一方向的最大宽度；
    所述第一显示区沿所述第二方向的最大宽度等于所述第一分区沿所述第二方向的最大宽度。
  5. 根据权利要求3所述的显示面板，其中，所述第一像素电路位于第一区域内；
    与第二区域内的所述第二发光元件相对应的所述第二像素电路位于所述第二子显示区内；
    其中，所述第一区域为所述第一分区，所述第二区域为所述第二分区；或者所述第一区域为所述第二分区，所述第二区域为所述第一分区。
  6. 根据权利要求5所述的显示面板，其中，所述第一区域包括至少一个第一电路组和至少一个第二电路组，所述第一电路组包括所述第一像素电路，所述第二电路组包括所述第二像素电路，至少一个所述第一电路组位于一所述第二电路组靠近所述第一显示区的一侧；
    所述第二子显示区包括至少一个第三电路组和至少一个第四电路组，所述第三电路组包括与所述第二区域的所述第二发光元件相对应的所述第二像素电路，所述第四电路组包括所述第二子显示区内除所述第三电路组中的所述第二像素电路之外的所述第二像素电路，至少一个所述第三电路组位于一所述第四电路组靠近所述第二区域的一侧。
  7. 根据权利要求6所述的显示面板，其中，所述第一像素电路的尺寸等于所述第三电路组中的所述第二像素电路的尺寸；
    所述第一像素电路的尺寸等于所述第二电路组中的至少一个所述第二像素电路的尺寸；
    所述第三电路组中的所述第二像素电路的尺寸等于所述第四电路组中的至少一个所述第二像素电路的尺寸；
    其中，所述第一像素电路的尺寸包括所述第一像素电路所在区域沿所述第一方向的第一边长和沿所述第二方向的第二边长；所述第二像素电路的尺寸包括所述第二像素电路所在区域沿所述第一方向的第三边长和沿所述第二方向的第四边长；响应于确定所述第一像素电路对应的所述第一边长和所述第二像素电路对应的所述第三边长相等，且所述第一像素电路对应的所述第二边长和所述第二像素电路对应的所述第四边长相等，确定所述第一像素电路和所述第二像素电路的尺寸相等。
  8. 根据权利要求7所述的显示面板，其中，所述第二电路组包括第一电路分组和第二电路分组，所述第一电路分组和所述第二电路分组中的所述第二像素电路的尺寸不等，且所述第一电路分组位于所述第二电路分组靠近所述第一电路组的一侧；所述第一电路分组中的所述第二像素电路的尺寸等于所述第一像素电路的尺寸；
    所述第四电路组包括第三电路分组和第四电路分组，所述第三电路分组和所述第四电路分组中的所述第二像素电路的尺寸不等，且所述第三电路分组位于所述第四电路分组靠近所述第三电路组的一侧；所述第三电路分组中的所述第二像素电路的尺寸等于所述第三电路组中的所述第二像素电路的尺寸。
  9. 根据权利要求7所述的显示面板，其中，所述第一像素电路与所述第二像素电路的尺寸相等；
    所述显示面板还包括多个第一虚拟像素电路，所述第一虚拟像素电路位于所述第一区域和所述第二子显示区内，且所述第一虚拟像素电路在所述显示面板所在平面的正投影与所述第一像素电路和所述第二像素电路在所述显示面板所在平面的正投影分别不交叠。
  10. 根据权利要求9所述的显示面板，其中，所述第一虚拟像素电路位于所述第二电路组远离所述第一电路组的一侧，且位于所述第四电路组远离所述第三电路组的一侧。
  11. 根据权利要求9所述的显示面板，其中，至少一个所述第一虚拟像素电路位于以下至少之一的位 置：相邻两个所述第一像素电路之间，相邻两个所述第二像素电路之间。
  12. 根据权利要求11所述的显示面板，其中，任意两个沿所述第一方向相邻的所述第一虚拟像素电路之间包括m个实际像素电路；其中，m为自然数；m＞0时，m个所述实际像素电路包括所述第一像素电路和所述第二像素电路中的至少一者；
    任意两个沿所述第二方向相邻的所述第一虚拟像素电路之间包括n个所述实际像素电路；其中，n为自然数；n＞0时，n个所述实际像素电路包括所述第一像素电路和所述第二像素电路中的至少一者；
    m和n不同时为0。
  13. 根据权利要求7所述的显示面板，其中，所述第一像素电路和所述第二像素电路的尺寸相等，且分布于所述第二显示区中除所述第二区域以外的区域。
  14. 根据权利要求5所述的显示面板，其中，所述第二区域内设置有第二虚拟像素电路。
  15. 根据权利要求5所述的显示面板，其中，沿所述第一显示区指向所述第二区域的方向，位于同一排的所述第一发光元件依次与位于同一排的所述第一像素电路一一对应电连接，位于同一排的所述第二发光元件依次与位于同一排的所述第二像素电路一一对应电连接。
  16. 根据权利要求15所述的显示面板，其中，所述第一发光元件和对应的所述第一像素电路通过第一连接线电连接；至少部分所述第二发光元件和对应的所述第二像素电路通过第二连接线电连接；
    沿所述第一区域指向所述第一显示区的方向，越靠近所述第一显示区的所述第一像素电路所对应的所述第一连接线的长度越长，越靠近所述第一显示区或所述第二区域的所述第二像素电路所对应的所述第二连接线的长度越长。
  17. 根据权利要求16所述的显示面板，其中，所述第一连接线包括第一连接分部，所述第一连接分部位于所述第一显示区；
    至少一条所述第一连接分部为透明走线。
  18. 根据权利要求1所述的显示面板，其中，所述第一发光元件包括第一阳极，所述第一阳极在所述显示面板所在平面的正投影的形状为圆形。
  19. 一种显示装置，包括感光元件和权利要求1-18任一项所述的显示面板，所述感光元件与所述第一显示区对应设置。
PCT/CN2023/073551 2022-11-10 2023-01-28 一种显示面板及显示装置 WO2024098558A1 (zh)

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Citations (4)

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US20180293936A1 (en) * 2017-04-06 2018-10-11 Japan Display Inc. Display device
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CN114242759A (zh) * 2021-12-13 2022-03-25 昆山国显光电有限公司 显示面板及显示装置
CN114784073A (zh) * 2022-04-18 2022-07-22 京东方科技集团股份有限公司 显示面板和显示装置

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Publication number Priority date Publication date Assignee Title
US20180293936A1 (en) * 2017-04-06 2018-10-11 Japan Display Inc. Display device
CN110265455A (zh) * 2019-06-25 2019-09-20 武汉华星光电半导体显示技术有限公司 一种显示面板及显示装置
CN114242759A (zh) * 2021-12-13 2022-03-25 昆山国显光电有限公司 显示面板及显示装置
CN114784073A (zh) * 2022-04-18 2022-07-22 京东方科技集团股份有限公司 显示面板和显示装置

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