WO2024095727A1 - Simulation method, information processing device, and information processing program - Google Patents

Simulation method, information processing device, and information processing program Download PDF

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Publication number
WO2024095727A1
WO2024095727A1 PCT/JP2023/036944 JP2023036944W WO2024095727A1 WO 2024095727 A1 WO2024095727 A1 WO 2024095727A1 JP 2023036944 W JP2023036944 W JP 2023036944W WO 2024095727 A1 WO2024095727 A1 WO 2024095727A1
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simulation
chip
chips
active element
stress
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PCT/JP2023/036944
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French (fr)
Japanese (ja)
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保博 落合
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ソニーセミコンダクタソリューションズ株式会社
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/08—Thermal analysis or thermal optimisation

Definitions

  • This disclosure relates to a simulation method, an information processing device, and an information processing program.
  • Patent Document 1 discloses a technique for adjusting MOSFET parameters in a circuit simulation based on the size of the MOSFET within the chip and the stress generated due to the surrounding structure.
  • Patent Document 1 does not consider the effects of such stress.
  • One aspect of the present disclosure makes it possible to reflect the effects of stress caused by heat generation due to chip operation in a circuit simulation.
  • a simulation method includes simulating the heat distribution within each of the multiple chips, taking into account the power consumption during operation of multiple chips that include active elements and are arranged in a concentrated manner, simulating the stress distribution within each of the multiple chips based on the results of the simulation of the heat distribution, and reflecting the results of the simulation of the stress distribution in the circuit simulation of each of the multiple chips.
  • An information processing device includes a processing unit that simulates the heat distribution within each of the multiple chips while taking into account the power consumption during operation of the multiple chips arranged in a concentrated manner, simulates the stress distribution within each of the multiple chips based on the results of the heat distribution simulation, and reflects the results of the stress distribution simulation in the circuit simulation of each of the multiple chips.
  • An information processing program causes a computer to execute a process that takes into account the power consumption during operation of multiple chips arranged in a concentrated manner, simulates the heat distribution within each of the multiple chips, simulates the stress distribution within each of the multiple chips based on the results of the heat distribution simulation, and reflects the results of the stress distribution simulation in the circuit simulation of each of the multiple chips.
  • FIG. 1 is a diagram illustrating an example of a model.
  • FIG. 11 is a diagram showing an example of a thermal distribution simulation result.
  • FIG. 1 is a diagram showing an example of a chip structure.
  • FIG. 13 is a diagram showing an example of a stress distribution simulation result.
  • FIG. 13 is a diagram illustrating an example of correspondence of stress distributions.
  • FIG. 13 is a diagram illustrating an example of correspondence of stress distributions.
  • FIG. 13 is a diagram illustrating an example of association of heat distributions.
  • FIG. 13 is a diagram illustrating an example of association of heat distributions.
  • FIG. 1 is a diagram showing an example of characteristic fluctuation of a MOSFET;
  • FIG. 1 is a diagram showing an example of characteristic fluctuation of a MOSFET;
  • FIG. 1 is a diagram showing an example of characteristic fluctuation of a MOSFET;
  • FIG. 13 is a diagram showing an example of characteristic fluctuation of a MOSFET;
  • FIG. 1 is a diagram showing an example of characteristic fluctuation of a MOSFET;
  • 1A to 1C are diagrams showing examples of the size and peripheral structure of an active element.
  • FIG. 13 is a diagram illustrating an example of fitting parameters.
  • FIG. 13 is a diagram showing an example of reflection of a simulation result of temperature distribution in a circuit simulation.
  • FIG. 13 is a diagram showing an example of reflection of a simulation result of temperature distribution in a circuit simulation.
  • FIG. 13 is a diagram showing an example of reflection of a simulation result of stress distribution in a circuit simulation.
  • FIG. 13 is a diagram showing an example of reflection of a simulation result of stress distribution in a circuit simulation.
  • FIG. 1 is a flowchart showing an example of the flow of a simulation method.
  • FIG. 1 is a diagram showing an example of a chip arrangement.
  • FIG. 1 is a diagram showing an example of a chip arrangement.
  • FIG. 1 is a diagram showing an example of a chip arrangement.
  • FIG. 1 is a diagram illustrating an example of an active element.
  • FIG. 1 is a diagram illustrating an example of a schematic configuration of an information processing device.
  • FIG. 2 is a diagram illustrating an example of a hardware configuration of an information processing device.
  • multiple chips may be mounted on a substrate or package for device integration.
  • There are various methods for mounting multiple chips on a substrate such as stacking another chip on a substrate, arranging multiple chips in parallel on a substrate or package (on a flat surface), and combining stacking and parallel arrangement.
  • the thermal expansion coefficients also called linear expansion coefficients
  • stress is generated due to heat generated by chip operation, resulting in shape changes (distortion, etc.).
  • shape changes disortion, etc.
  • the characteristics of the active elements in the chip fluctuate, and the chip performance also changes.
  • the threshold voltage Vth, carrier mobility ⁇ , etc. may fluctuate.
  • the threshold voltage Vth and carrier mobility ⁇ are important parameters that determine the saturation current of a MOSFET, and these fluctuations have a significant impact on chip performance. Reflecting the effects of stress generated due to heat generated by chip operation in a circuit simulation is useful for improving the accuracy of the simulation, etc.
  • FIG. 1 is a diagram showing an example of a model.
  • Model 1 includes a support 2 and multiple chips 3.
  • An example of the support 2 is a single substrate or a single package.
  • Chip 3 is a semiconductor chip including an active element.
  • An example of an active element is a field effect transistor (FET), more specifically a MOS (Metal-Oxide-Semiconductor) FET, and hereinafter, unless otherwise specified, the active element is assumed to be a MOSFET.
  • FET field effect transistor
  • MOS Metal-Oxide-Semiconductor
  • the multiple chips 3 are arranged in a concentrated manner. Four chips 3 are illustrated in FIG. 1. To distinguish between the chips 3, they are illustrated as chip 3-A, chip 3-B, chip 3-C, and chip 3-D.
  • At least some of the chips 3 among the multiple chips 3 may be stacked on one another. At least some of the chips 3 among the multiple chips 3 may be provided on the support 2 directly or via other chips 3.
  • chip 3-A and chip 3-B are stacked on one another.
  • Chip 3-A and chip 3-C are also stacked on one another.
  • Chip 3-A and chip 3-D are also stacked on one another.
  • Chip 3-A is provided directly on the support 2.
  • Chip 3-B, chip 3-C, and chip 3-D are provided on chip 3-A.
  • FIG. 1 An XYZ coordinate system is also shown in FIG. 1.
  • the X-axis direction and Y-axis direction correspond to the surface directions of the support 2 and chip 3.
  • the Z-axis direction corresponds to the thickness direction of the support 2 and chip 3, and also corresponds to the stacking direction of the chip 3.
  • the support 2 and chip 3 are provided in this order in the positive direction of the Z axis.
  • ⁇ Heat distribution simulation> the power consumption during operation of the multiple chips 3 is taken into consideration, and the heat distribution within each of the multiple chips 3 is simulated. Specifically, the power consumption of the operating chip 3 is given, and thermal analysis is performed to obtain the heat distribution. Various known thermal analysis techniques, including a commercially available thermal distribution simulator, may be used.
  • the power consumption of the chip 3 may be given so as to accurately reflect this distribution. However, the average power may be given uniformly for the size of the chip.
  • the power consumption may be the power consumption distribution obtained by operating the chip, or may be the power distribution converted from the heat distribution within the chip surface obtained from actual measurements (thermography or thermocouples), etc.
  • Thermal analysis is performed including the materials that join the support 2 and each of the multiple chips 3 (including between the chips 3).
  • the physical properties in the thermal analysis are set so that the physical properties of each material are appropriately reflected. Examples of physical properties are thermal conductivity and thermal emissivity.
  • an appropriate heat transfer coefficient that takes into account the surrounding conditions may also be used. For example, if the chip 3 is exposed to air, the corresponding heat transfer coefficient between the chip 3 and the air is used.
  • Thermal analysis may be either a steady-state analysis or a non-steady-state analysis.
  • the thermal distribution simulation can be said to include a simulation of the change in thermal distribution over time. Even in complex cases where the operation timing of multiple chips 3 is different, the thermal distribution can be accurately grasped.
  • Figure 2 is a diagram showing an example of the results of a heat distribution simulation.
  • the heat distribution within chip 3 is shown in grayscale.
  • this type of heat distribution can be obtained by a heat distribution simulation based on model 1.
  • ⁇ Stress distribution simulation> Based on the results of the heat distribution simulation, the stress distribution within each of the multiple chips 3 is simulated. That is, the stress generated within each chip 3 due to heat generated by the operation of the multiple chips 3 is analyzed.
  • the stress may be the stress on the silicon surface of the active layer portion in which the MOSFET is configured.
  • FIG. 3 is a diagram showing an example of a chip structure.
  • chip 3 within chip 3 there are materials such as an insulating film (in this example, an interlayer insulating film), metal 31 (in this example, wiring metal 31a and metal for contact with wiring 31b), metal silicide 32, and silicon (in this example, a silicon wafer) forming a MOSFET.
  • an insulating film in this example, an interlayer insulating film
  • metal 31 in this example, wiring metal 31a and metal for contact with wiring 31b
  • metal silicide 32 in this example, a silicon wafer
  • silicon in this example, a silicon wafer
  • the stress distribution is determined in the surface direction (XY plane direction) and height direction (Z-axis direction) of chip 3.
  • Various known stress analysis techniques may be used, including commercially available stress distribution simulators.
  • the stress analysis is performed including the materials that join the support 2 and each of the multiple chips 3.
  • the physical properties in the stress analysis are set so that the physical properties of each material are appropriately reflected. Examples of physical properties are the thermal expansion coefficient, Young's modulus, Poisson's ratio, elasticity modulus, etc.
  • Various forces such as tensile force, compressive force, shear force, bending force, and torsional force may be taken into account for the stress.
  • Plastic deformation and elastic deformation may also be taken into account.
  • the fatigue life (number of repetitions) and repetitive stress required for plastic deformation may also be taken into account.
  • Figure 4 shows an example of the stress distribution simulation results.
  • the stress distribution in chip 3 is shown in grayscale.
  • such a stress distribution can be obtained by a stress distribution simulation based on model 1.
  • the stress analysis may also be a steady-state analysis. If the previous thermal analysis was a non-steady-state analysis, the stress analysis may also be a non-steady-state analysis.
  • the stress distribution simulation in the case of a non-steady-state analysis can also be said to include a simulation of the change in stress distribution over time.
  • the insulating film, metal 31, metal silicide 32, silicon, and other materials forming the MOSFET in the chip 3 as described above with reference to FIG. 3 are manufactured by combining materials with different thermal expansion coefficients as described above through high-temperature heat treatment in the semiconductor manufacturing process. Therefore, when the chip 3 is manufactured, residual stress exists in each material even when the chip 3 is not in operation.
  • the stress distribution within the chip may be simulated based on the residual stress of each material when the chip 3 is manufactured. That is, starting from a state in which the residual stress of each material is taken into account, the stress distribution within each of the multiple chips 3 may be simulated based on the results of the heat distribution simulation as described above. For example, the stress on the silicon surface due to heat generation can be obtained from a state in which residual stresses of various materials exist. A stress distribution simulation that also takes into account the residual stress of each material becomes possible.
  • FIGS. 5 and 6 are diagrams showing examples of stress distribution correspondence.
  • the stress value of each segment in one chip 3 is obtained from the results of the stress distribution simulation.
  • the stress value is also referred to as stress value ⁇ .
  • a segment may correspond to a portion in chip 3 where a MOSFET is present.
  • FIG. 5 shows an example of 25 segments in chip 3 in the surface direction (XY plane) of chip 3.
  • the stress value ⁇ of each segment is shown as stress value ⁇ _1 to stress value ⁇ _25.
  • the stress value ⁇ in the chip plane is associated with the chip in-plane coordinates.
  • the chip in-plane coordinates are referred to as in-plane coordinates (X, Y).
  • the in-plane coordinates (X, Y) corresponding to the 25 segments in the above-mentioned chip 3 are referred to as in-plane coordinates (X_1, Y_1) to in-plane coordinates (X_25, Y_25) and are illustrated.
  • the stress value ⁇ _1 is associated with the in-plane coordinates (X_1, Y_1) and indicates the stress value of the segment at the in-plane coordinates (X_1, Y_1).
  • the stress value ⁇ _25 is associated with the in-plane coordinates (X_25, Y_25) and indicates the stress value of the segment at the in-plane coordinates (X_25, Y_25).
  • the in-plane coordinates (X, Y) may be set to an arbitrary point on the support 2 as the origin, or an arbitrary point (e.g., the center point) on each chip 3 as the origin. In the latter case, information on which chip 3 among the multiple chips 3 the in-plane coordinates (X, Y) belong to may also be given.
  • the distance to the adjacent segment for example the difference ( ⁇ X) between X_1 and X_2, the difference ( ⁇ Y) between Y_1 and Y_2, etc., may be set arbitrarily by the user.
  • the stress value ⁇ is also associated with a MOSFET instance i in chip 3.
  • MOSFET instance i corresponds to the instance name of the MOSFET in the circuit simulation described below.
  • MOSFET instances i corresponding to in-plane coordinates (X_1, Y_1) to in-plane coordinates (X_25, Y_25) are referred to as MOSFET instance i_1 to MOSFET instance i_25 and are illustrated.
  • the stress value ⁇ _1 corresponding to the in-plane coordinates (X_1, Y_1) is associated with MOSFET instance i_1 and indicates the value of stress applied to MOSFET instance i_1.
  • the stress value ⁇ _25 corresponding to the in-plane coordinates (X_25, Y_25) is associated with MOSFET instance i_25 and indicates the value of stress applied to MOSFET instance i_25.
  • MOSFET instance i includes a Pch (P-channel type) MOSFET instance Pch_i and an Nch (N-channel type) MOSFET instance Nch_i.
  • FIG. 6 illustrates an example in which each MOSFET instance i includes one PchMOSFET instance Pch_i and one NchMOSFET instance Nch_i, but each MOSFET instance i may include a greater number of PchMOSFET instances Pch_i and NchMOSFET instances Nch_i.
  • Data such as a netlist and a Graphic Date System (GDS) may be used to associate the stress value ⁇ , the chip in-plane coordinates (X, Y), and the MOSFET instance i as shown in FIG. 6.
  • GDS Graphic Date System
  • the chip in-plane ⁇ is associated with the chip in-plane coordinates (X, Y).
  • the chip in-plane coordinates (X, Y) are associated with the MOSFET instance i, and thus the stress value ⁇ is associated with the MOSFET instance i.
  • FIGS. 7 and 8 are diagrams showing examples of stress distribution correspondence. As shown in FIG. 7, the temperature of each segment in one chip 3 is obtained from the results of the above heat distribution simulation. The temperature is also referred to as temperature Tj. The temperatures Tj of each segment are illustrated and referred to as temperature Tj_1 to temperature Tj_25.
  • the temperature Tj within the chip plane is associated with the in-plane coordinates (X, Y) of the chip 3.
  • temperature Tj_1 is associated with the in-plane coordinates (X_1, Y_1) and indicates the temperature of the segment at the in-plane coordinates (X_1, Y_1).
  • Temperature Tj_25 is associated with the in-plane coordinates (X_25, Y_25) and indicates the temperature of the segment at the in-plane coordinates (X_25, Y_25).
  • the temperature Tj is also associated with a MOSFET instance i in the chip 3.
  • the temperature Tj_1 corresponding to the in-plane coordinates (X_1, Y_1) is associated with the MOSFET instance i_1 and indicates the temperature of the MOSFET instance i_1.
  • the temperature Tj_25 corresponding to the in-plane coordinates (X_25, Y_25) is associated with the MOSFET instance i_25 and indicates the temperature of the MOSFET instance i_25.
  • Data such as a netlist and a GDS (Graphic Date System) may also be used to associate the temperature Tj, the chip in-plane coordinates (X, Y), and the MOSFET instance i as shown in FIG. 8.
  • GDS Graphic Date System
  • the characteristic variations of the MOSFETs in the chip 3 are calculated. Since the stress value ⁇ and the temperature Tj are associated with the chip in-plane coordinates (X, Y) and the MOSFET instance i as described above, the characteristic variations of the MOSFETs located at the same coordinates (within the same segment) are calculated based on the stress value ⁇ and the temperature Tj at each coordinate in the chip 3. Some examples of the characteristic variations will be described with reference to FIGS. 9 to 12.
  • FIGS. 9 to 12 are diagrams showing examples of characteristic fluctuations in a MOSFET. Ids-Vds drain characteristics are shown in FIGS. 9 and 10. The characteristics before the fluctuation are shown in FIG. 9. The characteristics after the fluctuation are shown in FIG. 10. Ids-Vgs subthreshold characteristics are shown in FIGS. 11 and 12. The characteristics before the fluctuation are shown in FIG. 11. The characteristics after the fluctuation are shown in FIG. 12.
  • Fluctuations in characteristics such as the Ids-Vds drain characteristic and the Ids-Vgs subthreshold characteristic may correspond to fluctuations in parameters related to the electrical characteristics of a MOSFET. Examples of such parameters include the threshold voltage Vth and the carrier mobility ⁇ .
  • the threshold voltage Vth and the carrier mobility ⁇ are important parameters that determine the current value of a MOSFET.
  • Ids ⁇ (Vgs - Vth) 2 ⁇ ⁇ (1/2) ⁇ Cox ⁇ ⁇ ⁇ (W/L)
  • W the active layer width of the MOSFET
  • L the gate length of the MOSFET
  • Cox the gate capacitance (oxide film capacitance) of the MOSFET.
  • the relationship between stress values and temperature may be understood in advance so that the characteristic fluctuations of the MOSFET can be calculated from these values.
  • the amount of characteristic fluctuation of the MOSFET due to changes in stress values and temperature may be confirmed in advance by calculation or the like. Actual measurement data may be used, or various known device simulations may be used.
  • a MOSFET gate, drain, source, and substrate terminals are prepared in advance, and external stress, temperature, etc. are intentionally applied, and a voltage is applied between the terminals for each stress value and temperature, and the characteristic fluctuations of the MOSFET are measured.
  • force and temperature are applied from the outside, if it is estimated in advance using a simulator or calculations, etc., how much stress value or temperature will be generated in which segment in the chip 3, it is possible to obtain accurate stress values and temperatures generated in the MOSFET in the actual chip 3, and perform efficient measurements.
  • a 3D device simulator can be used that can estimate the electric field distribution fluctuations at points related to electrical characteristics that are affected by stress or heat generated inside a MOSFET.
  • TCAD Technicalnology Computer-Aided Design
  • the tool may be a general-purpose tool such as a spreadsheet software.
  • the size and peripheral structure of a MOSFET may affect the characteristic variation of the MOSFET due to stress.
  • the calculation of the characteristic variation of a MOSFET may also be based on the size and peripheral structure of the MOSFET in the chip 3 that includes the MOSFET. This will be described with reference to FIGS. 13 and 14.
  • FIG. 13 is a diagram showing an example of the size and peripheral structure of an active element, and shows a schematic planar layout of MOSFETs in a chip 3.
  • the arrows in the diagram indicate the following: W: active layer width of MOSFET L: gate length of MOSFET LDD: active layer length of MOSFET SA: length from gate end of MOSFET to element isolation insulator PDX: active layer distance of MOSFET in X-axis direction PDY: active layer distance of MOSFET in Y-axis direction
  • the characteristics after the variation in FIG. 10 and FIG. 12 described above may be used as the basic characteristics, and the characteristic variation of the MOSFET may be further calculated (adjusted) according to the size of the MOSFET and the peripheral structure as shown in FIG. 13 above.
  • the influence of the size and peripheral structure of the MOSFET can also be reflected in the characteristic variation of the MOSFET.
  • fitting parameters may be used to incorporate the variables into the basic characteristics. The description will also refer to FIG. 14.
  • FIG. 14 is a diagram showing an example of fitting parameters.
  • the value of the saturation current Ids for the stress value ⁇ is changed by PDX, with PDX being a variable.
  • the diagram shows Ids for three different PDX values, PDX1 to PDX3.
  • the fitting parameters A to D may be calculated based on the characteristic fluctuations grasped by actually varying PDX in FIG. 10 and FIG. 12 described above. The same applies to W, L, LDD, SA, and PDY.
  • This method makes it possible to properly calculate the characteristic variations of a MOSFET even when there are various variations in the size and surrounding structure of the MOSFET.
  • the characteristic variations of a MOSFET calculated taking into account the size and surrounding structure of the MOSFET are also referred to as stress variation MOSFET characteristic values.
  • ⁇ Reflection in circuit simulation> The results of the simulation of the heat distribution and the simulation of the stress distribution are reflected in the circuit simulation of each of the chips 3. The reflection is performed, for example, by adjusting parameters in the circuit simulation.
  • An example of the circuit simulation is Spice simulation, and the following description will be given assuming that it is Spice simulation.
  • FIGS. 15 and 16 are diagrams showing an example of reflecting the results of a temperature distribution simulation in a circuit simulation.
  • the temperature Tj of MOSFET instance i at each coordinate (within each segment) on the chip surface of chip 3 is already known.
  • the numerical values of temperatures Tj_1 to Tj_25 in the diagram are examples. Based on this temperature information, the parameters in the Spice netlist are adjusted (the temperature information is fed back to the parameters).
  • temp is a parameter that indicates the temperature of the entire chip 3.
  • dtemp is a parameter used to correct the temperature of each MOSFET instance i in the chip 3.
  • the parameter temp which corresponds to the temperature of the entire chip, is set to 40.
  • the difference ⁇ Tx between this temp value of 40 and the temperature Tj ( Figure 15) of each MOSFET instance i is set as dtemp for each MOSFET instance i in the Spice netlist. This causes the temperature distribution to be reflected in the MOSFET instance i in Spice.
  • Figures 17 and 18 show an example of reflecting the results of a simulation of stress distribution in a circuit simulation. More specifically, the characteristic variation of a MOSFET calculated based on the results of a simulation of stress distribution is reflected in a circuit simulation of a chip 3 including that MOSFET. As explained above, the stress value ⁇ of a MOSFET instance i at each coordinate on the chip surface of chip 3 is already known, and the characteristic variation of the MOSFET at each coordinate based on this has also been calculated. Based on this characteristic variation information, the parameters in the Spice netlist are adjusted (the characteristic variation is fed back to the parameters).
  • parameters describing the characteristics of the MOSFET are adjusted (set, corrected, etc.). More specifically, parameters describing the threshold voltage Vth of the MOSFET, parameters describing the carrier mobility ⁇ of the MOSFET, etc. are adjusted. Examples of such parameters are DELVT0 and MULU0, etc.
  • DELVT0 is a parameter used to correct the threshold voltage Vth of the MOSFET.
  • MULU0 is a parameter used to correct the carrier mobility ⁇ of the MOSFET.
  • the difference between the threshold voltage Vth when there is no stress due to heat generation caused by chip operation and the threshold voltage Vth when there is stress due to heat generation caused by chip operation is set to ⁇ Vth.
  • the difference in carrier mobility ⁇ is set to ⁇ .
  • a value for correcting the threshold voltage Vth by ⁇ Vth is set in DELVT0 in the Spice netlist.
  • a value for correcting the carrier mobility ⁇ by ⁇ is set in MULU0 in the Spice netlist. Note that parameters corresponding to both PchMOSFETs and NchMOSFETs may be used. Also, the values of DELVT0 and MULU0 set here may be determined using the stress variation MOSFET characteristic values described above.
  • DELVT0 is set for each MOSFET instance i. All DELVT0 values are shown diagrammatically as "xxx”, but each value may be different. Also, as shown in FIG. 18, MULU0 is set for each MOSFET instance i. All MULU0 values are shown diagrammatically as "xxx”, but each value may be different.
  • the above-mentioned parameters such as temp, dtemp, DELVT0, and MULU0 may be input automatically or manually by the user.
  • manual input may be effective when varying the characteristics of a MOSFET in a limited, localized area.
  • Figure 19 is a flowchart showing an overview of the simulation method. The specific content of each process has been explained so far, so explanations will be omitted as appropriate.
  • step S1 chip data and a model are prepared.
  • the chip data may include netlist data for each of the multiple chips 3, GDS data, etc.
  • the model is, for example, model 1 including multiple chips 3 arranged in a concentrated manner and a support 2, as described above with reference to FIG. 1.
  • step S2 the heat distribution within each of the multiple chips 3 arranged in a concentrated manner during operation is simulated.
  • step S3 the stress distribution within each of the multiple chips 3 is simulated based on the results of the thermal distribution simulation.
  • step S4 the thermal distribution and stress distribution are associated with coordinates within chip 3 and MOSFET instance i.
  • step S5 the characteristic variations of the MOSFETs located at each coordinate (within each segment) are calculated.
  • step S6 the results are reflected in the circuit simulation for each of the multiple chips 3.
  • the results here include the simulation results of heat distribution, the simulation results of stress distribution, and the calculation results of MOSFET characteristic fluctuations. The results are reflected by adjusting parameters in the circuit simulation, etc.
  • the arrangement of the multiple chips 3 is not limited to the example shown in FIG. 1. The following description will be given with reference to FIGS. 20 to 22.
  • FIGS. 20 to 22 are diagrams showing examples of chip arrangements.
  • the diagrams show exploded perspective views of the support 2 and multiple chips 3 disassembled in the Z-axis direction.
  • chips 3-B, 3-C, and 3-C are mounted on the support 2 (first layer), and chip 3-A is stacked on top of them (second layer).
  • chip 3-A is mounted on the support 2.
  • chips 3-B, 3-C, and 3-D are stacked on top of that.
  • the shapes and orientations of each chip 3 can also vary.
  • the active element included in chip 3 is a MOSFET.
  • the active element is not limited to a MOSFET. The following description will be given with reference to FIG. 23.
  • FIG. 23 is a diagram showing an example of an active element.
  • An example of an active element is a current control element made of a semiconductor. Examples of such current control elements include a field effect transistor, a bipolar transistor, a PN junction diode, and a thyristor.
  • the MOSFET described so far is an example of a field effect transistor.
  • FIG. 24 is a diagram showing an example of the schematic configuration of an information processing device.
  • the information processing device 4 includes a user interface unit 5, a processing unit 6, and a storage unit 7.
  • the user interface unit 5 accepts user operations and presents information to the user.
  • the processing unit 6 executes various types of processing.
  • Examples of information stored in the memory unit 7 include a heat distribution simulation program 71, a stress distribution simulation program 72, a circuit simulation program 73, and an information processing program 74.
  • the heat distribution simulation program 71, the stress distribution simulation program 72, and the circuit simulation program 73 are used to perform the heat distribution simulation, the stress distribution simulation, and the circuit simulation described above.
  • the information processing program 74 is a program (software, application) for causing the computer to function as the information processing device 4 (for example, as the user interface unit 5, the processing unit 6, etc.).
  • the processing unit 6 executes various processes in response to user operations via the user interface unit 5, thereby proceeding with the procedure of the simulation method according to the embodiment described above.
  • the model 1 as described above with reference to FIG. 1 and the chip data of each chip 3 contained therein are prepared.
  • a heat distribution simulation program 71 is executed to obtain a simulation result of the heat distribution.
  • a stress distribution simulation program 72 is executed to obtain a simulation result of the stress distribution.
  • the characteristic fluctuation of the MOSFET in the chip 3 is calculated. As described above, this calculation may be performed using a separately prepared device simulator, any tool, etc.
  • the simulation results and calculation results are reflected in the circuit simulation, and a circuit simulation program 73 is executed.
  • some of the functions of the information processing device 4 may be provided in an external server device configured to be able to communicate with the information processing device 4.
  • Examples of functions that may be provided in the external server device include some of the functions of the processing unit 6, some or all of the heat distribution simulation program 71, some or all of the stress distribution simulation program 72, some or all of the circuit simulation program 73, etc.
  • FIG. 25 is a diagram showing an example of the hardware configuration of an information processing device.
  • the information processing device 4 can be realized by a computer 1000 as shown in the figure.
  • the computer 1000 has a CPU 1100, a RAM 1200, a ROM (Read Only Memory) 1300, a HDD (Hard Disk Drive) 1400, a communication interface 1500, and an input/output interface 1600.
  • Each part of the computer 1000 is connected by a bus 1050.
  • the CPU 1100 operates based on the programs stored in the ROM 1300 or the HDD 1400, and controls each part. For example, the CPU 1100 loads the programs stored in the ROM 1300 or the HDD 1400 into the RAM 1200, and executes processing corresponding to the various programs.
  • the programs include the heat distribution simulation program 71, the stress distribution simulation program 72, the circuit simulation program 73, and the information processing program 74, which are mentioned above.
  • the ROM 1300 stores boot programs such as the Basic Input Output System (BIOS) that is executed by the CPU 1100 when the computer 1000 starts up, as well as programs that depend on the hardware of the computer 1000.
  • BIOS Basic Input Output System
  • HDD 1400 is a computer-readable recording medium that non-temporarily records programs executed by CPU 1100 and data used by such programs.
  • HDD 1400 is a recording medium that records information processing program 74, which is an example of program data 1450.
  • the communication interface 1500 is an interface for connecting the computer 1000 to an external network 1550 (e.g., the Internet).
  • the CPU 1100 receives data from other devices and transmits data generated by the CPU 1100 to other devices via the communication interface 1500.
  • the input/output interface 1600 is an interface for connecting the input/output device 1650 and the computer 1000.
  • the CPU 1100 receives data from an input device such as a keyboard or a mouse via the input/output interface 1600.
  • the CPU 1100 also transmits data to an output device such as a display, a speaker or a printer via the input/output interface 1600.
  • the input/output interface 1600 may also function as a media interface that reads programs and the like recorded on a specific recording medium.
  • Examples of media include optical recording media such as DVDs (Digital Versatile Discs) and PDs (Phase change rewritable Disks), magneto-optical recording media such as MOs (Magneto-Optical Disks), tape media, magnetic recording media, and semiconductor memories.
  • optical recording media such as DVDs (Digital Versatile Discs) and PDs (Phase change rewritable Disks)
  • magneto-optical recording media such as MOs (Magneto-Optical Disks)
  • tape media magnetic recording media
  • magnetic recording media and semiconductor memories.
  • the CPU 1100 of the computer 1000 executes the information processing program 74 loaded onto the RAM 1200 to realize the functions of the information processing device 4.
  • the CPU 1100 reads and executes the program data 1450 from the HDD 1400, but as another example, the CPU 1100 may obtain these programs from other devices via the external network 1550.
  • the simulation method includes simulating the heat distribution in each of the multiple chips 3 by taking into account the power consumption during operation of multiple chips 3 including active elements (for example, current control elements composed of semiconductors such as field effect transistors (including MOSFETs), bipolar transistors, PN junction diodes, and thyristors) arranged in a concentrated manner (step S2), simulating the stress distribution in each of the multiple chips 3 based on the simulation result of the heat distribution (step S3), and reflecting the simulation result of the stress distribution in the circuit simulation of each of the multiple chips 3 (step S6).
  • active elements for example, current control elements composed of semiconductors such as field effect transistors (including MOSFETs), bipolar transistors, PN junction diodes, and thyristors
  • step S3 simulating the stress distribution in each of the multiple chips 3 based on the simulation result of the heat distribution
  • step S6 reflecting the simulation result of the stress distribution in the circuit simulation of each of the multiple chips 3
  • the simulation method includes calculating the characteristic variation of the active element based on the simulation results of the stress distribution (step S5), and reflecting the result in the circuit simulation (step S6) may include reflecting the calculation results of the characteristic variation of the active element in the circuit simulation of the chip 3 including the active element. This allows the characteristic variation of the active element caused by stress to be reflected in the circuit simulation.
  • the simulation method includes associating the stress distribution with coordinates within the chip 3 including the active element (step S4), and calculating the characteristic variation of the active element (step S5) may include calculating the characteristic variation of the active element located at the same coordinates based on the stress value ⁇ at each coordinate within the chip 3. For example, in this manner, the characteristic variation of the active element at each position within the chip 3 can be calculated.
  • calculating the characteristic variation of the active element may include calculating the variation characteristic of the active element based on the size and peripheral structure of the active element in the chip 3 that includes the active element. This makes it possible to appropriately calculate the characteristic variation of the active element even when there are various variations in the size and peripheral structure of the active element.
  • the chip 3 is a chip manufactured by combining multiple materials with different thermal expansion coefficients, and simulating the stress distribution (step S3) may include simulating the stress distribution within the chip based on the residual stresses of the multiple materials when the chip 3 was manufactured. This makes it possible to perform a stress distribution simulation that also takes into account the residual stresses of each material in the chip 3.
  • calculating the characteristic variations of the active elements may include calculating the characteristic variations of the active elements in the chip 3 based on the results of the heat distribution simulation. This allows the characteristic variations of the active elements caused by heat generation due to the operation of the chip 3 to be reflected in the circuit simulation.
  • reflecting in the circuit simulation may include adjusting parameters describing the characteristics of the active element in the circuit simulation.
  • the active element may include a field effect transistor, and the parameters may include at least one of a parameter describing the carrier mobility ⁇ and a parameter describing the threshold voltage Vth.
  • the circuit simulation may include a Spice simulation, and the parameters describing the carrier mobility ⁇ may include MULU0, and the parameters describing the threshold voltage Vth may include DELVT0. For example, by adjusting the parameters in this way, the characteristic fluctuations of the active element can be reflected in the circuit simulation.
  • the simulation method may include adjusting parameters describing temperature in the circuit simulation based on the simulation results of the heat distribution.
  • the circuit simulation may include a Spice simulation
  • the parameters describing temperature may include dtemp. This allows the temperature distribution to be reflected in the circuit simulation.
  • At least some of the chips 3 among the multiple chips 3 may be stacked on top of each other. Also, at least some of the chips 3 among the multiple chips 3 may be provided directly on a single substrate or package (support 2). For example, for multiple chips 3 arranged in a concentrated manner in this manner, the effect of stress caused by heat generation due to chip operation can be reflected in the circuit simulation.
  • simulating the heat distribution may include simulating the change in heat distribution over time
  • simulating the stress distribution may include simulating the change in stress distribution over time. This makes it possible to reflect the effects of stress caused by heat generation due to chip operation in the circuit simulation, even in complex cases where the operation timing of multiple chips 3 is different.
  • the information processing device 4 and the information processing program 74 described with reference to Figures 1 to 19, 24, and 25 are also examples of the disclosed technology.
  • the information processing device 4 includes a processing unit 6 that takes into account the power consumption during operation of the multiple chips 3 arranged in a concentrated manner, simulates the heat distribution within each of the multiple chips 3, simulates the stress distribution within each of the multiple chips 3 based on the simulation result of the heat distribution, and reflects the simulation result of the stress distribution in the circuit simulation of each of the multiple chips 3.
  • the information processing program 74 causes the computer 1000 to execute a process that takes into account the power consumption during operation of the multiple chips 3 arranged in a concentrated manner, simulates the heat distribution within each of the multiple chips 3, simulates the stress distribution within each of the multiple chips 3 based on the simulation result of the heat distribution, and reflects the simulation result of the stress distribution in the circuit simulation of each of the multiple chips 3.
  • the influence of stress generated due to heat generation caused by chip operation can also be reflected in the circuit simulation, as described above.
  • the present technology can also be configured as follows. (1) Taking into account the power consumption during operation of a plurality of chips including active elements arranged in a concentrated manner, a simulation is performed of a heat distribution within each of the plurality of chips; simulating a stress distribution within each of the plurality of chips based on a result of the simulation of the heat distribution; and reflecting a result of the simulation of the stress distribution in a circuit simulation of each of the plurality of chips; including, Simulation method. (2) calculating a characteristic variation of the active element based on a simulation result of the stress distribution; Reflecting the calculation result of the characteristic variation of the active element in the circuit simulation includes reflecting the calculation result of the characteristic variation of the active element in the circuit simulation of a chip including the active element. A simulation method according to (1).
  • Calculating the characteristic variation of the active element includes calculating the characteristic variation of an active element located at the same coordinate based on the stress value at each coordinate in the chip.
  • Calculating the characteristic variation of the active element includes calculating the variation characteristic of the active element based on a size and a peripheral structure of the active element in a chip including the active element.
  • the chip is manufactured by combining a plurality of materials having different thermal expansion coefficients, simulating the stress distribution includes simulating a stress distribution in the chip based on residual stresses of the materials when the chip is manufactured.
  • Calculating the characteristic variation of the active element includes calculating the characteristic variation of the active element in the chip based on the simulation result of the heat distribution.
  • Reflecting the result in the circuit simulation includes adjusting a parameter describing a characteristic of the active element in the circuit simulation.
  • the active element includes a field effect transistor;
  • the parameters include at least one of a parameter describing a threshold voltage and a parameter describing carrier mobility.
  • the circuit simulation includes a Spice simulation,
  • the parameters describing the carrier mobility include MULU0;
  • the parameters describing the threshold voltage include DELVT0;
  • a simulation method according to any one of (1) to (9).
  • the circuit simulation includes a Spice simulation, The parameters describing the temperature include dtemp;
  • (12) At least some of the chips among the plurality of chips are stacked on one another.
  • a simulation method according to any one of (1) to (11).
  • (13) At least some of the chips among the plurality of chips are provided directly on one substrate or package.
  • a simulation method according to any one of (1) to (12).
  • the active element includes a current control element made of a semiconductor;
  • the current control element is Field effect transistors, Bipolar transistors, PN junction diode, and a thyristor;
  • the active element includes a MOSFET.
  • simulating the heat distribution includes simulating a change in the heat distribution over time;
  • the simulating of the stress distribution includes simulating a change in the stress distribution over time.
  • a simulation is performed for a heat distribution within each of the plurality of chips; simulating a stress distribution within each of the plurality of chips based on a result of the simulation of the heat distribution; reflecting a result of the simulation of the stress distribution in a circuit simulation of each of the plurality of chips;
  • a processing unit is provided. Information processing device.

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Abstract

This simulation method comprises: taking into consideration the power consumption during operation of a plurality of chips that include active elements and are in an aggregated arrangement to simulate the in-chip heat distribution of each of the plurality of chips; simulating the in-chip stress distribution of each of the plurality of chips on the basis of heat distribution simulation results; and reflecting the stress distribution simulation results in a circuit simulation for each of the plurality of chips.

Description

シミュレーション方法、情報処理装置及び情報処理プログラムSimulation method, information processing device, and information processing program
　本開示は、シミュレーション方法、情報処理装置及び情報処理プログラムに関する。 This disclosure relates to a simulation method, an information processing device, and an information processing program.
　半導体チップ等のチップの回路シミュレーションに関して、例えば特許文献１は、チップ内のＭＯＳＦＥＴのサイズ及び周辺構造に起因して発生する応力に基づいて、回路シミュレーションにおけるＭＯＳＦＥＴのパラメータを調整する技術を開示する。 Regarding circuit simulation of chips such as semiconductor chips, for example, Patent Document 1 discloses a technique for adjusting MOSFET parameters in a circuit simulation based on the size of the MOSFET within the chip and the stress generated due to the surrounding structure.
特開２０１１－１５０６０７号公報JP 2011-150607 A
　デバイス集積化のために、基板又はパッケージ上に複数のチップを集約配置することがある。チップ動作による発熱に起因して、応力が発生する。このような応力の影響について、特許文献１は検討していない。 In order to integrate devices, multiple chips may be arranged in a concentrated manner on a substrate or package. Heat generated by chip operation generates stress. Patent Document 1 does not consider the effects of such stress.
　本開示の一側面は、チップ動作による発熱に起因して発生する応力の影響を回路シミュレーションに反映させることを可能にする。 One aspect of the present disclosure makes it possible to reflect the effects of stress caused by heat generation due to chip operation in a circuit simulation.
　本開示の一側面に係るシミュレーション方法は、能動素子を含み集約配置された複数のチップの動作時における消費電力を加味し、複数のチップそれぞれのチップ内熱分布をシミュレーションすることと、熱分布のシミュレーション結果に基づいて、複数のチップそれぞれのチップ内応力分布をシミュレーションすることと、応力分布のシミュレーション結果を、複数のチップそれぞれの回路シミュレーションに反映させることと、を含む。 A simulation method according to one aspect of the present disclosure includes simulating the heat distribution within each of the multiple chips, taking into account the power consumption during operation of multiple chips that include active elements and are arranged in a concentrated manner, simulating the stress distribution within each of the multiple chips based on the results of the simulation of the heat distribution, and reflecting the results of the simulation of the stress distribution in the circuit simulation of each of the multiple chips.
　本開示の一側面に係る情報処理装置は、集約配置された複数のチップの動作時における消費電力を加味し、複数のチップそれぞれのチップ内熱分布をシミュレーションし、熱分布のシミュレーション結果に基づいて、複数のチップそれぞれのチップ内応力分布をシミュレーションし、応力分布のシミュレーション結果を、複数のチップそれぞれの回路シミュレーションに反映させる、処理部を備える。 An information processing device according to one aspect of the present disclosure includes a processing unit that simulates the heat distribution within each of the multiple chips while taking into account the power consumption during operation of the multiple chips arranged in a concentrated manner, simulates the stress distribution within each of the multiple chips based on the results of the heat distribution simulation, and reflects the results of the stress distribution simulation in the circuit simulation of each of the multiple chips.
　本開示の一側面に係る情報処理プログラムは、コンピュータに、集約配置された複数のチップの動作時における消費電力を加味し、複数のチップそれぞれのチップ内熱分布をシミュレーションし、熱分布のシミュレーション結果に基づいて、複数のチップそれぞれのチップ内応力分布をシミュレーションし、応力分布のシミュレーション結果を、複数のチップそれぞれの回路シミュレーションに反映させる、処理を実行させる。 An information processing program according to one aspect of the present disclosure causes a computer to execute a process that takes into account the power consumption during operation of multiple chips arranged in a concentrated manner, simulates the heat distribution within each of the multiple chips, simulates the stress distribution within each of the multiple chips based on the results of the heat distribution simulation, and reflects the results of the stress distribution simulation in the circuit simulation of each of the multiple chips.
モデルの例を示す図である。FIG. 1 is a diagram illustrating an example of a model. 熱分布シミュレーション結果の例を示す図である。FIG. 11 is a diagram showing an example of a thermal distribution simulation result. チップ構造の例を示す図である。FIG. 1 is a diagram showing an example of a chip structure. 応力分布シミュレーション結果の例を示す図である。FIG. 13 is a diagram showing an example of a stress distribution simulation result. 応力分布の対応付けの例を示す図である。FIG. 13 is a diagram illustrating an example of correspondence of stress distributions. 応力分布の対応付けの例を示す図である。FIG. 13 is a diagram illustrating an example of correspondence of stress distributions. 熱分布の対応付けの例を示す図である。FIG. 13 is a diagram illustrating an example of association of heat distributions. 熱分布の対応付けの例を示す図である。FIG. 13 is a diagram illustrating an example of association of heat distributions. ＭＯＳＦＥＴの特性変動の例を示す図である。FIG. 1 is a diagram showing an example of characteristic fluctuation of a MOSFET; ＭＯＳＦＥＴの特性変動の例を示す図である。FIG. 1 is a diagram showing an example of characteristic fluctuation of a MOSFET; ＭＯＳＦＥＴの特性変動の例を示す図である。FIG. 1 is a diagram showing an example of characteristic fluctuation of a MOSFET; ＭＯＳＦＥＴの特性変動の例を示す図である。FIG. 1 is a diagram showing an example of characteristic fluctuation of a MOSFET; 能動素子のサイズ及び周辺構造の例を示す図である。1A to 1C are diagrams showing examples of the size and peripheral structure of an active element. フィッティングパラメータの例を示す図である。FIG. 13 is a diagram illustrating an example of fitting parameters. 温度分布のシミュレーション結果の、回路シミュレーションへの反映の例を示す図である。FIG. 13 is a diagram showing an example of reflection of a simulation result of temperature distribution in a circuit simulation. 温度分布のシミュレーション結果の、回路シミュレーションへの反映の例を示す図である。FIG. 13 is a diagram showing an example of reflection of a simulation result of temperature distribution in a circuit simulation. 応力分布のシミュレーション結果の、回路シミュレーションへの反映の例を示す図である。FIG. 13 is a diagram showing an example of reflection of a simulation result of stress distribution in a circuit simulation. 応力分布のシミュレーション結果の、回路シミュレーションへの反映の例を示す図である。FIG. 13 is a diagram showing an example of reflection of a simulation result of stress distribution in a circuit simulation. シミュレーション方法のフローの例を示すフローチャートである。1 is a flowchart showing an example of the flow of a simulation method. チップ配置の例を示す図である。FIG. 1 is a diagram showing an example of a chip arrangement. チップ配置の例を示す図である。FIG. 1 is a diagram showing an example of a chip arrangement. チップ配置の例を示す図である。FIG. 1 is a diagram showing an example of a chip arrangement. 能動素子の例を示す図である。FIG. 1 is a diagram illustrating an example of an active element. 情報処理装置の概略構成の例を示す図である。FIG. 1 is a diagram illustrating an example of a schematic configuration of an information processing device. 情報処理装置のハードウェア構成の例を示す図である。FIG. 2 is a diagram illustrating an example of a hardware configuration of an information processing device.
　以下に、本開示の実施形態について図面に基づいて詳細に説明する。なお、以下の各実施形態において、同一の要素には同一の符号を付することにより重複する説明を省略する。 Below, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that in each of the following embodiments, the same elements will be designated by the same reference numerals, and duplicate descriptions will be omitted.
　以下に示す項目順序に従って本開示を説明する。
　　０．序
　　１．実施形態
　　２．変形例
　　３．効果の例 The present disclosure will be described in the following order.
0. Introduction 1. Embodiments 2. Modifications 3. Examples of Effects
０．序
　例えばデバイスの集積化のために、基板又はパッケージ上に複数のチップを搭載することがある。チップ上に更に別のチップを積層させる手法、複数のチップを基板又はパッケージ上（平面上）に並列に配置する手法、それらの積層及び並列配置を組み合わせる手法等のさまざまな手法がある。 0. Introduction For example, multiple chips may be mounted on a substrate or package for device integration. There are various methods for mounting multiple chips on a substrate, such as stacking another chip on a substrate, arranging multiple chips in parallel on a substrate or package (on a flat surface), and combining stacking and parallel arrangement.
　チップ間、基板又はパッケージの界面の熱膨張係数（線膨張係数とも呼ばれる）は異なるので、チップ動作による発熱に起因して応力が発生し、形状変化（歪み等）が生じる。その結果、チップ内の能動素子の特性が変動し、チップ性能も変化する。能動素子としてＭＯＳＦＥＴを例に挙げて説明すると、閾値電圧Ｖｔｈ、キャリア移動度μ等が変動し得る。閾値電圧Ｖｔｈ及びキャリア移動度μは、ＭＯＳＦＥＴの飽和電流を決める重要なパラメータであり、これらの変動はチップ性能に大きく影響する。チップ動作による発熱に起因して発生する応力の影響を回路シミュレーションに反映させることは、シミュレーション精度向上等に役立つ。 Since the thermal expansion coefficients (also called linear expansion coefficients) between chips and at the interface of the substrate or package are different, stress is generated due to heat generated by chip operation, resulting in shape changes (distortion, etc.). As a result, the characteristics of the active elements in the chip fluctuate, and the chip performance also changes. Taking a MOSFET as an example of an active element, the threshold voltage Vth, carrier mobility μ, etc. may fluctuate. The threshold voltage Vth and carrier mobility μ are important parameters that determine the saturation current of a MOSFET, and these fluctuations have a significant impact on chip performance. Reflecting the effects of stress generated due to heat generated by chip operation in a circuit simulation is useful for improving the accuracy of the simulation, etc.
１．実施形態
＜モデル準備＞
　開示される技術の１つは、シミュレーション方法である。実施形態に係るシミュレーション方法では、まず、集約配置された複数のチップを含むモデル（シミュレーションモデル）を準備する。図１を参照して説明する。 1. Implementation Example <Model Preparation>
One of the techniques disclosed herein is a simulation method. In the simulation method according to the embodiment, first, a model (simulation model) including a plurality of chips arranged in a concentrated manner is prepared. The simulation method will be described with reference to FIG.
　図１は、モデルの例を示す図である。モデル１は、支持体２と、複数のチップ３とを含む。支持体２の例は、１つの基板又は１つのパッケージである。チップ３は、能動素子を含む半導体チップである。能動素子の一例は、電界効果トランジスタ（ＦＥＴ：Field　Effect　Transistor）、より具体的にはＭＯＳ（Metal-Oxide-Semiconductor）ＦＥＴであり、とくに説明がある場合を除き、以下では、能動素子はＭＯＳＦＥＴであるものとする。 FIG. 1 is a diagram showing an example of a model. Model 1 includes a support 2 and multiple chips 3. An example of the support 2 is a single substrate or a single package. Chip 3 is a semiconductor chip including an active element. An example of an active element is a field effect transistor (FET), more specifically a MOS (Metal-Oxide-Semiconductor) FET, and hereinafter, unless otherwise specified, the active element is assumed to be a MOSFET.
　複数のチップ３は、集約配置される。図１には、４つのチップ３が例示される。各チップ３を区別できるように、チップ３－Ａ、チップ３－Ｂ、チップ３－Ｃ及びチップ３－Ｄと称し図示する。 The multiple chips 3 are arranged in a concentrated manner. Four chips 3 are illustrated in FIG. 1. To distinguish between the chips 3, they are illustrated as chip 3-A, chip 3-B, chip 3-C, and chip 3-D.
　複数のチップ３のうちの少なくとも一部のチップ３は、互いに積層されてよい。複数のチップ３のうちの少なくとも一部のチップ３は、支持体２上に直接又は他のチップ３を介して設けられてよい。図１に示される例では、チップ３－Ａ及びチップ３－Ｂは、互いに積層される。チップ３－Ａ及びチップ３－Ｃも、互いに積層される。チップ３－Ａ及びチップ３－Ｄも、互いに積層される。チップ３－Ａは、支持体２上に直接設けられる。チップ３－Ｂ、チップ３－Ｃ及びチップ３－Ｄは、チップ３－Ａ上に設けられる。 At least some of the chips 3 among the multiple chips 3 may be stacked on one another. At least some of the chips 3 among the multiple chips 3 may be provided on the support 2 directly or via other chips 3. In the example shown in FIG. 1, chip 3-A and chip 3-B are stacked on one another. Chip 3-A and chip 3-C are also stacked on one another. Chip 3-A and chip 3-D are also stacked on one another. Chip 3-A is provided directly on the support 2. Chip 3-B, chip 3-C, and chip 3-D are provided on chip 3-A.
　なお、図１において、ＸＹＺ座標系も示される。Ｘ軸方向及びＹ軸方向（ＸＹ平面方向）は、支持体２及びチップ３の面方向に相当する。Ｚ軸方向は、支持体２及びチップ３の厚さ方向に相当し、また、チップ３の積層方向に相当する。Ｚ軸正方向に、支持体２及びチップ３がこの順に設けられる。 In addition, an XYZ coordinate system is also shown in FIG. 1. The X-axis direction and Y-axis direction (XY plane direction) correspond to the surface directions of the support 2 and chip 3. The Z-axis direction corresponds to the thickness direction of the support 2 and chip 3, and also corresponds to the stacking direction of the chip 3. The support 2 and chip 3 are provided in this order in the positive direction of the Z axis.
＜熱分布シミュレーション＞
　次に、複数のチップ３の動作時における消費電力を加味し、複数のチップ３それぞれのチップ内熱分布をシミュレーションする。具体的に、動作するチップ３の消費電力を与え、熱解析を行うことで、熱分布を得る。市販の熱分布シミュレータ等を含め種々の公知の熱解析技術が用いられてよい。 <Heat distribution simulation>
Next, the power consumption during operation of the multiple chips 3 is taken into consideration, and the heat distribution within each of the multiple chips 3 is simulated. Specifically, the power consumption of the operating chip 3 is given, and thermal analysis is performed to obtain the heat distribution. Various known thermal analysis techniques, including a commercially available thermal distribution simulator, may be used.
　消費電力は、チップ３の面内で強弱分布を有するので、この分布が正確に反映されるように、チップ３の消費電力が与えられてよい。ただし、平均電力をチップのサイズに対して均一に与えてもよい。消費電力は、チップを動作させて得られる消費電力分布を用いてもよいし、実測(サーモグラフィーや熱電対)等から得られるチップ面内の熱分布から、電力分布へ換算させたものを用いてもよい。 Since the power consumption has a distribution of strengths and weaknesses within the surface of the chip 3, the power consumption of the chip 3 may be given so as to accurately reflect this distribution. However, the average power may be given uniformly for the size of the chip. The power consumption may be the power consumption distribution obtained by operating the chip, or may be the power distribution converted from the heat distribution within the chip surface obtained from actual measurements (thermography or thermocouples), etc.
　熱解析は、支持体２及び複数のチップ３それぞれ(チップ３間も含む)を接合する材料等を含めて行われる。各材料の物性値が適切に反映されるように、熱解析における物性値が設定される。物性値の例は、熱伝導率、熱放射率等である。熱解析において、周囲状況を考慮した適切な熱伝達係数も用いられてよい。例えばチップ３が空気に晒されている場合には、それに対応するチップ３と空気の間の熱伝達係数が用いられる。 Thermal analysis is performed including the materials that join the support 2 and each of the multiple chips 3 (including between the chips 3). The physical properties in the thermal analysis are set so that the physical properties of each material are appropriately reflected. Examples of physical properties are thermal conductivity and thermal emissivity. In the thermal analysis, an appropriate heat transfer coefficient that takes into account the surrounding conditions may also be used. For example, if the chip 3 is exposed to air, the corresponding heat transfer coefficient between the chip 3 and the air is used.
　熱解析は、定常解析であってもよいし、非定常解析であってもよい。非定常解析の場合の熱分布シミュレーションは、熱分布の経時変化のシミュレーションを含むともいえる。複数のチップ３それぞれの動作タイミグが異なるような複雑な場合でも、その熱分布を的確に把握することができる。 Thermal analysis may be either a steady-state analysis or a non-steady-state analysis. In the case of a non-steady-state analysis, the thermal distribution simulation can be said to include a simulation of the change in thermal distribution over time. Even in complex cases where the operation timing of multiple chips 3 is different, the thermal distribution can be accurately grasped.
　図２は、熱分布シミュレーション結果の例を模式的に示す図である。チップ３内の熱分布がグレースケールで示される。例えばこのような熱分布が、モデル１に基づく熱分布シミュレーションによって得られる。 Figure 2 is a diagram showing an example of the results of a heat distribution simulation. The heat distribution within chip 3 is shown in grayscale. For example, this type of heat distribution can be obtained by a heat distribution simulation based on model 1.
＜応力分布シミュレーション＞
　熱分布シミュレーションの結果に基づいて、複数のチップ３それぞれのチップ内応力分布をシミュレーションする。すなわち、複数のチップ３の動作による発熱に起因して各チップ３内に発生した応力の解析が行われる。応力は、ＭＯＳＦＥＴが構成される活性層部分のシリコン表面における応力であってよい。チップ構造の一例について、図３を参照して説明する。 <Stress distribution simulation>
Based on the results of the heat distribution simulation, the stress distribution within each of the multiple chips 3 is simulated. That is, the stress generated within each chip 3 due to heat generated by the operation of the multiple chips 3 is analyzed. The stress may be the stress on the silicon surface of the active layer portion in which the MOSFET is configured. An example of the chip structure will be described with reference to FIG.
　図３は、チップ構造の例を示す図である。例えば図３に示されるように、チップ３内には、絶縁膜（この例では層間絶縁膜）、金属３１（この例では配線金属３１ａや配線とのコンタクト用金属３１ｂ）、金属シリサイド３２、ＭＯＳＦＥＴを形成するシリコン（この例ではシリコンウエハ）等の材料が存在する。これらを考慮した応力分布を、チップ３の面方向（ＸＹ平面方向）及び高さ方向（Ｚ軸方向）について求める。市販の応力分布シミュレータ等を含め種々の公知の応力析技術が用いられてよい。 FIG. 3 is a diagram showing an example of a chip structure. For example, as shown in FIG. 3, within chip 3 there are materials such as an insulating film (in this example, an interlayer insulating film), metal 31 (in this example, wiring metal 31a and metal for contact with wiring 31b), metal silicide 32, and silicon (in this example, a silicon wafer) forming a MOSFET. Taking these into consideration, the stress distribution is determined in the surface direction (XY plane direction) and height direction (Z-axis direction) of chip 3. Various known stress analysis techniques may be used, including commercially available stress distribution simulators.
　応力解析は、支持体２及び複数のチップ３それぞれを接合する材料等を含めて行われる。各材料の物性値が適切に反映されるように、応力解析における物性値が設定される。物性値の例は、熱膨張係数、ヤング率、ポアソン比、弾性率等である。応力には、引張り力、圧縮力、せん断力、曲げ力、ねじり力等の各種の力が考慮されてよい。塑性変形及び弾性変形も考慮されてよい。塑性変形に必要となる疲労寿命(繰り返し数)、繰返し応力も考慮されてよい。 The stress analysis is performed including the materials that join the support 2 and each of the multiple chips 3. The physical properties in the stress analysis are set so that the physical properties of each material are appropriately reflected. Examples of physical properties are the thermal expansion coefficient, Young's modulus, Poisson's ratio, elasticity modulus, etc. Various forces such as tensile force, compressive force, shear force, bending force, and torsional force may be taken into account for the stress. Plastic deformation and elastic deformation may also be taken into account. The fatigue life (number of repetitions) and repetitive stress required for plastic deformation may also be taken into account.
　図４は、応力分布シミュレーション結果の例を示す図である。チップ３内の応力分布がグレースケールで示される。例えばこのような応力分布が、モデル１に基づく応力分布シミュレーションによって得られる。 Figure 4 shows an example of the stress distribution simulation results. The stress distribution in chip 3 is shown in grayscale. For example, such a stress distribution can be obtained by a stress distribution simulation based on model 1.
　先の熱解析が定常解析の場合、応力解析も定常解析であてよい。先に熱解析が非定常解析の場合、応力解析も非定常解析であってよい。非定常解析の場合の応力分布シミュレーションは、応力分布の経時変化のシミュレーションを含むともいえる。 If the previous thermal analysis was a steady-state analysis, the stress analysis may also be a steady-state analysis. If the previous thermal analysis was a non-steady-state analysis, the stress analysis may also be a non-steady-state analysis. The stress distribution simulation in the case of a non-steady-state analysis can also be said to include a simulation of the change in stress distribution over time.
　例えば先に図３を参照して説明したようなチップ３内の絶縁膜、金属３１、金属シリサイド３２、ＭＯＳＦＥＴを形成するシリコン等の材料は、半導体製造プロセス上の高温熱処理等により、上述の熱膨張係数がそれぞれ異なる材料が組み合わされ製造される。故に、チップ３が製造された際、チップ３が非動作状態でも、それぞれの材料には残留応力が存在する。一実施形態において、チップ３が製造された際の各材料の残存応力にも基づいて、チップ内応力分布をシミュレーションしてよい。すなわち、各材料の残留応力が考慮された状態を起点とし、そこからさらに、上記のように熱分布のシミュレーション結果に基づいて、複数のチップ３それぞれのチップ内応力分布をシミュレーションしてよい。例えば、種々材料の残留応力が存在した状態から、発熱によるシリコン表面の応力が求められる。各材料の残存応力をも考慮した応力分布シミュレーションが可能になる。 For example, the insulating film, metal 31, metal silicide 32, silicon, and other materials forming the MOSFET in the chip 3 as described above with reference to FIG. 3 are manufactured by combining materials with different thermal expansion coefficients as described above through high-temperature heat treatment in the semiconductor manufacturing process. Therefore, when the chip 3 is manufactured, residual stress exists in each material even when the chip 3 is not in operation. In one embodiment, the stress distribution within the chip may be simulated based on the residual stress of each material when the chip 3 is manufactured. That is, starting from a state in which the residual stress of each material is taken into account, the stress distribution within each of the multiple chips 3 may be simulated based on the results of the heat distribution simulation as described above. For example, the stress on the silicon surface due to heat generation can be obtained from a state in which residual stresses of various materials exist. A stress distribution simulation that also takes into account the residual stress of each material becomes possible.
＜応力分布のチップ内座標及びインスタンスへの対応付け＞
　応力分布のシミュレーション結果に基づいて、応力分布を、チップ３内の座標、さらにはインスタンスに対応付ける（紐づける）。図５及び図６を参照して説明する。 <Association of stress distribution with chip coordinates and instances>
Based on the simulation results of the stress distribution, the stress distribution is associated (linked) with coordinates in the chip 3 and further with an instance. This will be described with reference to FIGS.
　図５及び図６は、応力分布の対応付けの例を示す図である。図５に示されるように、先の応力分布のシミュレーション結果から、１つのチップ３内の各セグメントの応力値が得られる。なお、応力値を、応力値σとも称する。セグメントは、チップ３内においてＭＯＳＦＥＴが存在する部分に対応してよい。図５には、チップ３の面方向（ＸＹ平面）におけるチップ３内の２５個のセグメントが例示される。各セグメントの応力値σを、応力値σ_１～応力値σ_２５と称し図示する。 FIGS. 5 and 6 are diagrams showing examples of stress distribution correspondence. As shown in FIG. 5, the stress value of each segment in one chip 3 is obtained from the results of the stress distribution simulation. The stress value is also referred to as stress value σ. A segment may correspond to a portion in chip 3 where a MOSFET is present. FIG. 5 shows an example of 25 segments in chip 3 in the surface direction (XY plane) of chip 3. The stress value σ of each segment is shown as stress value σ_1 to stress value σ_25.
　図６に示されるように、チップ面内の応力値σを、チップ面内座標に対応付ける。チップ面内座標を、面内座標（Ｘ，Ｙ）と称する。上述のチップ３内の２５個のセグメントに対応する面内座標（Ｘ，Ｙ）を、面内座標（Ｘ_１，Ｙ_１）～面内座標（Ｘ_２５，Ｙ_２５）と称し図示する。例えば、応力値σ_１は、面内座標（Ｘ_１，Ｙ_１）に対応付けられ、面内座標（Ｘ_１，Ｙ_１）のセグメントの応力値を示す。応力値σ_２５は、面内座標（Ｘ_２５，Ｙ_２５）に対応付けられ、面内座標（Ｘ_２５，Ｙ_２５）のセグメントの応力値を示す。 As shown in FIG. 6, the stress value σ in the chip plane is associated with the chip in-plane coordinates. The chip in-plane coordinates are referred to as in-plane coordinates (X, Y). The in-plane coordinates (X, Y) corresponding to the 25 segments in the above-mentioned chip 3 are referred to as in-plane coordinates (X_1, Y_1) to in-plane coordinates (X_25, Y_25) and are illustrated. For example, the stress value σ_1 is associated with the in-plane coordinates (X_1, Y_1) and indicates the stress value of the segment at the in-plane coordinates (X_1, Y_1). The stress value σ_25 is associated with the in-plane coordinates (X_25, Y_25) and indicates the stress value of the segment at the in-plane coordinates (X_25, Y_25).
　面内座標（Ｘ，Ｙ）は、先に説明した図１のモデル１において、支持体２の任意の点を原点として設定されてもよいし、各チップ３の任意の点（例えば中央点）を原点として設定されてもよい。後者の場合は、複数のチップ３のうちのどのチップ３の面内座標（Ｘ，Ｙ）であるのかという情報も与えられてよい。隣接セグメントまでの距離、例えばＸ_１とＸ_２との差分（ΔＸ）、Ｙ_１とＹ_２の差分（ΔＹ）等は、ユーザが任意に設定してよい。 In the model 1 of FIG. 1 described above, the in-plane coordinates (X, Y) may be set to an arbitrary point on the support 2 as the origin, or an arbitrary point (e.g., the center point) on each chip 3 as the origin. In the latter case, information on which chip 3 among the multiple chips 3 the in-plane coordinates (X, Y) belong to may also be given. The distance to the adjacent segment, for example the difference (ΔX) between X_1 and X_2, the difference (ΔY) between Y_1 and Y_2, etc., may be set arbitrarily by the user.
　また、図６にさらに示されるように、応力値σを、チップ３内のＭＯＳＦＥＴインスタンスｉにも対応付ける。ＭＯＳＦＥＴインスタンスｉは、後述の回路シミュレーションにおけるＭＯＳＦＥＴのインスタンス名に相当する。面内座標（Ｘ_１，Ｙ_１）～面内座標（Ｘ_２５，Ｙ_２５）に対応するＭＯＳＦＥＴインスタンスｉを、ＭＯＳＦＥＴインスタンスｉ_１～ＭＯＳＦＥＴインスタンスｉ_２５と称し図示する。例えば、面内座標（Ｘ_１，Ｙ_１）に対応する応力値σ_１は、ＭＯＳＦＥＴインスタンスｉ_１に対応付けられ、ＭＯＳＦＥＴインスタンスｉ_１に加わる応力の値を示す。面内座標（Ｘ_２５，Ｙ_２５）に対応する応力値σ_２５は、ＭＯＳＦＥＴインスタンスｉ_２５に対応付けられ、ＭＯＳＦＥＴインスタンスｉ_２５に加わる応力の値を示す。 As further shown in FIG. 6, the stress value σ is also associated with a MOSFET instance i in chip 3. MOSFET instance i corresponds to the instance name of the MOSFET in the circuit simulation described below. MOSFET instances i corresponding to in-plane coordinates (X_1, Y_1) to in-plane coordinates (X_25, Y_25) are referred to as MOSFET instance i_1 to MOSFET instance i_25 and are illustrated. For example, the stress value σ_1 corresponding to the in-plane coordinates (X_1, Y_1) is associated with MOSFET instance i_1 and indicates the value of stress applied to MOSFET instance i_1. The stress value σ_25 corresponding to the in-plane coordinates (X_25, Y_25) is associated with MOSFET instance i_25 and indicates the value of stress applied to MOSFET instance i_25.
　より具体的に、この例では、ＭＯＳＦＥＴインスタンスｉは、Ｐｃｈ（Ｐチャネル型）ＭＯＳＦＥＴインスタンスＰｃｈ_ｉ及びＮｃｈ（Ｎチャネル型）ＭＯＳＦＥＴインスタンスＮｃｈ_ｉを含む。図６には、各ＭＯＳＦＥＴインスタンスｉが、１つのＰｃｈＭＯＳＦＥＴインスタンスＰｃｈ_ｉ及び１つのＮｃｈＭＯＳＦＥＴインスタンスＮｃｈ_ｉを含む場合が例示されるが、それよりも多い数のＰｃｈＭＯＳＦＥＴインスタンスＰｃｈ_ｉ及びＮｃｈＭＯＳＦＥＴインスタンスＮｃｈ_ｉを含んでもよい。 More specifically, in this example, MOSFET instance i includes a Pch (P-channel type) MOSFET instance Pch_i and an Nch (N-channel type) MOSFET instance Nch_i. FIG. 6 illustrates an example in which each MOSFET instance i includes one PchMOSFET instance Pch_i and one NchMOSFET instance Nch_i, but each MOSFET instance i may include a greater number of PchMOSFET instances Pch_i and NchMOSFET instances Nch_i.
　図６のような応力値σ、チップ面内座標（Ｘ，Ｙ）及びＭＯＳＦＥＴインスタンスｉの対応付けには、ネットリスト、ＧＤＳ（Graphic　Date　System）等のデータが用いられてよい。例えば、ＧＤＳのデータに基づいて、チップ面内のσがチップ面内座標（Ｘ，Ｙ）に対応付けられる。ネットリストのデータに基づいて、チップ面内座標（Ｘ，Ｙ）がＭＯＳＦＥＴインスタンスｉに対応付けられ、ひいては応力値σがＭＯＳＦＥＴインスタンスｉに対応付けられる。 Data such as a netlist and a Graphic Date System (GDS) may be used to associate the stress value σ, the chip in-plane coordinates (X, Y), and the MOSFET instance i as shown in FIG. 6. For example, based on the GDS data, the chip in-plane σ is associated with the chip in-plane coordinates (X, Y). Based on the netlist data, the chip in-plane coordinates (X, Y) are associated with the MOSFET instance i, and thus the stress value σ is associated with the MOSFET instance i.
＜熱分布のチップ内座標及びインスタンスへの対応付け＞
　また、先の熱分布のシミュレーション結果に基づいて、熱分布を、チップ３内の座標、さらにはインスタンスに対応付ける。図７及び図８を参照して説明する。 <Association of heat distribution with chip coordinates and instances>
Based on the results of the above simulation of the heat distribution, the heat distribution is associated with coordinates in the chip 3 and further with instances. This will be described with reference to FIGS.
　図７及び図８は、応力分布の対応付けの例を示す図である。図７に示されるように、先の熱分布のシミュレーション結果から、１つのチップ３内の各セグメントの温度が得られる。なお、温度を、温度Ｔｊとも称する。各セグメントの温度Ｔｊを、温度Ｔｊ_１～温度Ｔｊ_２５と称し図示する。 FIGS. 7 and 8 are diagrams showing examples of stress distribution correspondence. As shown in FIG. 7, the temperature of each segment in one chip 3 is obtained from the results of the above heat distribution simulation. The temperature is also referred to as temperature Tj. The temperatures Tj of each segment are illustrated and referred to as temperature Tj_1 to temperature Tj_25.
　図８に示されるように、チップ面内の温度Ｔｊを、チップ３の面内座標（Ｘ，Ｙ）に対応付ける。例えば、温度Ｔｊ_１は、面内座標（Ｘ_１，Ｙ_１）に対応付けられ、面内座標（Ｘ_１，Ｙ_１）のセグメントの温度を示す。温度Ｔｊ_２５は、面内座標（Ｘ_２５，Ｙ_２５）に対応付けられ、面内座標（Ｘ_２５，Ｙ_２５）のセグメントの温度を示す。 As shown in FIG. 8, the temperature Tj within the chip plane is associated with the in-plane coordinates (X, Y) of the chip 3. For example, temperature Tj_1 is associated with the in-plane coordinates (X_1, Y_1) and indicates the temperature of the segment at the in-plane coordinates (X_1, Y_1). Temperature Tj_25 is associated with the in-plane coordinates (X_25, Y_25) and indicates the temperature of the segment at the in-plane coordinates (X_25, Y_25).
　また、図８にさらに示されるように、温度Ｔｊを、チップ３内のＭＯＳＦＥＴインスタンスｉにも対応付ける。例えば、面内座標（Ｘ_１，Ｙ_１）に対応する温度Ｔｊ_１は、ＭＯＳＦＥＴインスタンスｉ_１に対応付けられ、ＭＯＳＦＥＴインスタンスｉ_１の温度を示す。面内座標（Ｘ_２５，Ｙ_２５）に対応する温度Ｔｊ_２５は、ＭＯＳＦＥＴインスタンスｉ_２５に対応付けられ、ＭＯＳＦＥＴインスタンスｉ_２５の温度を示す。 As further shown in FIG. 8, the temperature Tj is also associated with a MOSFET instance i in the chip 3. For example, the temperature Tj_1 corresponding to the in-plane coordinates (X_1, Y_1) is associated with the MOSFET instance i_1 and indicates the temperature of the MOSFET instance i_1. The temperature Tj_25 corresponding to the in-plane coordinates (X_25, Y_25) is associated with the MOSFET instance i_25 and indicates the temperature of the MOSFET instance i_25.
　図８のような温度Ｔｊ、チップ面内座標（Ｘ，Ｙ）及びＭＯＳＦＥＴインスタンスｉの対応付けにも、ネットリスト、ＧＤＳ（Graphic　Date　System）等のデータが用いられてよい。 Data such as a netlist and a GDS (Graphic Date System) may also be used to associate the temperature Tj, the chip in-plane coordinates (X, Y), and the MOSFET instance i as shown in FIG. 8.
＜能動素子の特性変動の計算＞
　応力分布のシミュレーション結果に基づいて、また、温度分布シミュレーション結果にも基づいて、チップ３内のＭＯＳＦＥＴの特性変動を計算する。上述のように応力値σ及び温度Ｔｊのチップ面内座標（Ｘ，Ｙ）及びＭＯＳＦＥＴインスタンスｉへの対応付けが出来ているので、チップ３内の各座標での応力値σ及び温度Ｔｊに基づいて、同じ座標に位置する（同じセグメント内の）ＭＯＳＦＥＴの特性変動を計算する。特性変動のいくつかの例について、図９～図１２を参照して説明する。 <Calculation of characteristic fluctuations of active elements>
Based on the results of the stress distribution simulation and also based on the results of the temperature distribution simulation, the characteristic variations of the MOSFETs in the chip 3 are calculated. Since the stress value σ and the temperature Tj are associated with the chip in-plane coordinates (X, Y) and the MOSFET instance i as described above, the characteristic variations of the MOSFETs located at the same coordinates (within the same segment) are calculated based on the stress value σ and the temperature Tj at each coordinate in the chip 3. Some examples of the characteristic variations will be described with reference to FIGS. 9 to 12.
　図９～図１２は、ＭＯＳＦＥＴの特性変動の例を示す図である。図９及び図１０には、Ｉｄｓ－Ｖｄｓドレイン特性が例示される。図９には、変動前の特性が模式的に示される。図１０には、変動後の特性が模式的に示される。図１１及び図１２には、Ｉｄｓ－Ｖｇｓサブスレッショルド特性が例示される。図１１には、変動前の特性が模式的に示される。図１２には、変動後の特性が模式的に示される。 FIGS. 9 to 12 are diagrams showing examples of characteristic fluctuations in a MOSFET. Ids-Vds drain characteristics are shown in FIGS. 9 and 10. The characteristics before the fluctuation are shown in FIG. 9. The characteristics after the fluctuation are shown in FIG. 10. Ids-Vgs subthreshold characteristics are shown in FIGS. 11 and 12. The characteristics before the fluctuation are shown in FIG. 11. The characteristics after the fluctuation are shown in FIG. 12.
　Ｉｄｓ－Ｖｄｓドレイン特性、Ｉｄｓ－Ｖｇｓサブスレッショルド特性等の特性変動は、ＭＯＳＦＥＴの電気的特性に関するパラメータの変動に対応し得る。そのようなパラメータの例は、閾値電圧Ｖｔｈ、キャリア移動度μ等である。閾値電圧Ｖｔｈ及びキャリア移動度μは、ＭＯＳＦＥＴの電流値を決める重要なパラメータとなる。ＭＯＳＦＥＴの飽和電流Ｉｄｓが、以下のように表されるからである。
　　Ｉｄｓ＝β（Ｖｇｓ－Ｖｔｈ）２
　　　　β∝（１／２）×Ｃｏｘ×μ×（Ｗ／Ｌ）
　なお、Ｗは、ＭＯＳＦＥＴの活性層幅である。Ｌは、ＭＯＳＦＥＴのゲート長さである。Ｃｏｘは、ＭＯＳＦＥＴのゲート容量（酸化膜容量）である。 Fluctuations in characteristics such as the Ids-Vds drain characteristic and the Ids-Vgs subthreshold characteristic may correspond to fluctuations in parameters related to the electrical characteristics of a MOSFET. Examples of such parameters include the threshold voltage Vth and the carrier mobility μ. The threshold voltage Vth and the carrier mobility μ are important parameters that determine the current value of a MOSFET. This is because the saturation current Ids of a MOSFET is expressed as follows:
Ids = β (Vgs - Vth) 2
β ∝ (1/2) × Cox × μ × (W/L)
Here, W is the active layer width of the MOSFET, L is the gate length of the MOSFET, and Cox is the gate capacitance (oxide film capacitance) of the MOSFET.
　応力値及び温度からＭＯＳＦＥＴの特性変動を計算できるように、それらの関係を予め把握しておいてよい。例えば、応力値及び温度の変化によるＭＯＳＦＥＴの特性変動量を計算等によって予め確認しておいてよい。実測データを用いてもよいし、種々の公知のデバイスシミュレーション等を用いてもよい。 The relationship between stress values and temperature may be understood in advance so that the characteristic fluctuations of the MOSFET can be calculated from these values. For example, the amount of characteristic fluctuation of the MOSFET due to changes in stress values and temperature may be confirmed in advance by calculation or the like. Actual measurement data may be used, or various known device simulations may be used.
　実測では、例えば、予めＭＯＳＦＥＴのゲート、ドレイン、ソース、基板端子が用意されたものを用い、意図的に外部から応力、温度等を与え、それぞれの応力値、温度について、端子間に電圧を与え、ＭＯＳＦＥＴの特性変動を測定する。外部から力や温度を与えることになるが、事前にチップ３内のどのセグメントにどの程度の応力値、あるいは温度が発生するか、シミュレータ又は計算等で見積もっておくと、実際のチップ３内のＭＯＳＦＥＴに発生する正確な応力値や温度を得ることが出来、効率的な測定が行える。 In actual measurements, for example, a MOSFET gate, drain, source, and substrate terminals are prepared in advance, and external stress, temperature, etc. are intentionally applied, and a voltage is applied between the terminals for each stress value and temperature, and the characteristic fluctuations of the MOSFET are measured. Although force and temperature are applied from the outside, if it is estimated in advance using a simulator or calculations, etc., how much stress value or temperature will be generated in which segment in the chip 3, it is possible to obtain accurate stress values and temperatures generated in the MOSFET in the actual chip 3, and perform efficient measurements.
　デバイスシミュレーションには、例えば、ＭＯＳＦＥＴ内部に発生する応力あるいは熱が影響し、電気特性に関係する箇所の電界分布変動を見積もることが出来る３Ｄのデバイスシミュレータを用いてよい。そのようなシミュレータの一例は、ＴＣＡＤ（Technology　Computer-Aided　Design）である。 For device simulation, for example, a 3D device simulator can be used that can estimate the electric field distribution fluctuations at points related to electrical characteristics that are affected by stress or heat generated inside a MOSFET. One example of such a simulator is TCAD (Technology Computer-Aided Design).
　必要な計算が行える任意のツールを用いてもよい。ツールは、例えば表計算ソフト等のような汎用のものであってもよい。 Any tool capable of performing the necessary calculations may be used. The tool may be a general-purpose tool such as a spreadsheet software.
＜能動素子のサイズ及び周辺構造も考慮した特性変動の計算＞
　ＭＯＳＦＥＴのサイズ及び周辺構造は、応力によるＭＯＳＦＥＴの特性変動に影響し得る。一実施形態において、ＭＯＳＦＥＴの特性変動の計算は、そのＭＯＳＦＥＴを含むチップ３におけるそのＭＯＳＦＥＴのサイズ及び周辺構造にも基づいて行われてよい。図１３及び図１４を参照して説明する。 <Calculation of characteristic fluctuations taking into account the size of active elements and surrounding structures>
The size and peripheral structure of a MOSFET may affect the characteristic variation of the MOSFET due to stress. In one embodiment, the calculation of the characteristic variation of a MOSFET may also be based on the size and peripheral structure of the MOSFET in the chip 3 that includes the MOSFET. This will be described with reference to FIGS. 13 and 14.
　図１３は、能動素子のサイズ及び周辺構造の例を示す図である。チップ３中のＭＯＳＦＥＴの平面レイアウトが模式的に示される。図中の矢印は下記のとおりである。
　　　　Ｗ：ＭＯＳＦＥＴの活性層幅
　　　　Ｌ：ＭＯＳＦＥＴのゲート長さ
　　ＬＤＤ：ＭＯＳＦＥＴの活性層長さ
　　　ＳＡ：ＭＯＳＦＥＴのゲート端部から素子分離絶縁体までの長さ
　　ＰＤＸ：Ｘ軸方向におけるＭＯＳＦＥＴの活性層間距離
　　ＰＤＹ：Ｙ軸方向におけるＭＯＳＦＥＴの活性層間距離 13 is a diagram showing an example of the size and peripheral structure of an active element, and shows a schematic planar layout of MOSFETs in a chip 3. The arrows in the diagram indicate the following:
W: active layer width of MOSFET L: gate length of MOSFET LDD: active layer length of MOSFET SA: length from gate end of MOSFET to element isolation insulator PDX: active layer distance of MOSFET in X-axis direction PDY: active layer distance of MOSFET in Y-axis direction
　先に説明した図１０や図１２の変動後の特性を基礎特性としたうえで、上記の図１３のようなＭＯＳＦＥＴのサイズや周辺構造に合わせてＭＯＳＦＥＴの特性変動がさらに計算（調整）されてよい。例えば、上記のＷ、Ｌ、ＬＤＤ、ＳＡ、ＰＤＸ及びＰＤＹの少なくとも１つを変数とし、基礎特性と組み入れることで、ＭＯＳＦＥＴのサイズ及び周辺構造の影響もＭＯＳＦＥＴの特性変動に反映させることができる。変数を基礎特性に組み入れるために、例えばフィッティングパラメータが用いられてよい。図１４も参照して説明する。 The characteristics after the variation in FIG. 10 and FIG. 12 described above may be used as the basic characteristics, and the characteristic variation of the MOSFET may be further calculated (adjusted) according to the size of the MOSFET and the peripheral structure as shown in FIG. 13 above. For example, by using at least one of the above W, L, LDD, SA, PDX, and PDY as a variable and incorporating it into the basic characteristics, the influence of the size and peripheral structure of the MOSFET can also be reflected in the characteristic variation of the MOSFET. For example, fitting parameters may be used to incorporate the variables into the basic characteristics. The description will also refer to FIG. 14.
　図１４は、フィッティングパラメータの例を示す図である。この例では、ＰＤＸを変数とすることで、応力値σに対する飽和電流Ｉｄｓの値を、ＰＤＸによって変化させる。図には、ＰＤＸがＰＤＸ１～ＰＤＸ３の３通りの場合のＩｄｓが例示される。飽和電流Ｉｄｓは、例えば、フィッティングパラメータＡ～Ｄを用いて以下のように表される。
　　Ｉｄｓ＝（Ａ×σＢ）×（Ｃ×ｌｎ（ＰＤＸ）＋Ｄ） 14 is a diagram showing an example of fitting parameters. In this example, the value of the saturation current Ids for the stress value σ is changed by PDX, with PDX being a variable. The diagram shows Ids for three different PDX values, PDX1 to PDX3. The saturation current Ids is expressed, for example, as follows using fitting parameters A to D:
Ids = (A x σ B ) x (C x ln(PDX) + D)
　フィッティングパラメータＡ～Ｄは、先に説明した図１０や図１２において実際にＰＤＸを変化させることによって把握される特性変動に基づいて計算されてよい。Ｗ、Ｌ、ＬＤＤ、ＳＡ及びＰＤＹについても同様である。 The fitting parameters A to D may be calculated based on the characteristic fluctuations grasped by actually varying PDX in FIG. 10 and FIG. 12 described above. The same applies to W, L, LDD, SA, and PDY.
　このような手法によれば、ＭＯＳＦＥＴのサイズ及び周辺構造のさまざまなバリエーションが存在する場合でも、ＭＯＳＦＥＴの特性変動を適切に計算することができる。なお、ＭＯＳＦＥＴのサイズや周辺構造も考慮して計算されたＭＯＳＦＥＴの特性変動を、応力変動ＭＯＳＦＥＴ特性値とも称する。 This method makes it possible to properly calculate the characteristic variations of a MOSFET even when there are various variations in the size and surrounding structure of the MOSFET. Note that the characteristic variations of a MOSFET calculated taking into account the size and surrounding structure of the MOSFET are also referred to as stress variation MOSFET characteristic values.
　なお、フィッティングパラメータを用いない手法も可能である。例えば、ＭＯＳＦＥＴのさまざまなサイズや周辺構造に対応する多数の特性データ（ルックアップテーブル等）を準備し、そのデータを参照するようにしてもよい。 It should be noted that a method that does not use fitting parameters is also possible. For example, a large amount of characteristic data (such as a lookup table) corresponding to various sizes and peripheral structures of MOSFETs can be prepared and the data can be referenced.
＜回路シミュレーションへの反映＞
　先の熱分布のシミュレーション結果及び応力分布のシミュレーション結果を、複数のチップ３それぞれの回路シミュレーションに反映させる。反映は、例えば回路シミュレーションにおけるパラメータを調整することによって行われる。回路シミュレーションの例は、Ｓｐｉｃｅシミュレーション等であり、以下では、Ｓｐｉｃｅシミュレーションであるものとして説明する。 <Reflection in circuit simulation>
The results of the simulation of the heat distribution and the simulation of the stress distribution are reflected in the circuit simulation of each of the chips 3. The reflection is performed, for example, by adjusting parameters in the circuit simulation. An example of the circuit simulation is Spice simulation, and the following description will be given assuming that it is Spice simulation.
　図１５及び図１６は、温度分布のシミュレーション結果の回路シミュレーションへの反映の例を示す図である。図１５に示されるように、チップ３のチップ面内の各座標（各セグメント内）のＭＯＳＦＥＴインスタンスｉの温度Ｔｊはすでに分かっている。図中の温度Ｔｊ_１～温度Ｔｊ_２５の数値は例示である。この温度情報に基づいて、Ｓｐｉｃｅネットリスト内のパラメータを調整する（温度情報をパラメータにフィードバックする）。 FIGS. 15 and 16 are diagrams showing an example of reflecting the results of a temperature distribution simulation in a circuit simulation. As shown in FIG. 15, the temperature Tj of MOSFET instance i at each coordinate (within each segment) on the chip surface of chip 3 is already known. The numerical values of temperatures Tj_1 to Tj_25 in the diagram are examples. Based on this temperature information, the parameters in the Spice netlist are adjusted (the temperature information is fed back to the parameters).
　具体的に、Ｓｐｉｃｅシミュレーションにおいて温度を記述するパラメータを調整する。そのようなパラメータの例は、ｔｅｍｐ及びｄｔｅｍｐ等である。ｔｅｍｐは、チップ３全体の温度を示すパラメータである。ｄｔｅｍｐは、チップ３内のＭＯＳＦＥＴインスタンスｉごとの温度を補正するために用いられるパラメータである。 Specifically, the parameters describing the temperature in the Spice simulation are adjusted. Examples of such parameters are temp and dtemp. temp is a parameter that indicates the temperature of the entire chip 3. dtemp is a parameter used to correct the temperature of each MOSFET instance i in the chip 3.
　図１６を参照して、チップ全体の温度に相当するパラメータｔｅｍｐを４０に設定する場合を例に挙げて説明する。このｔｅｍｐの値４０と、各ＭＯＳＦＥＴインスタンスｉの温度Ｔｊ（図１５）との差分ΔＴｘを、Ｓｐｉｃｅネットリスト内のＭＯＳＦＥＴインスタンスｉごとのｄｔｅｍｐに設定する。これにより、温度分布がＳｐｉｃｅ内のＭＯＳＦＥＴインスタンスｉに反映される。 With reference to Figure 16, an example will be described in which the parameter temp, which corresponds to the temperature of the entire chip, is set to 40. The difference ΔTx between this temp value of 40 and the temperature Tj (Figure 15) of each MOSFET instance i is set as dtemp for each MOSFET instance i in the Spice netlist. This causes the temperature distribution to be reflected in the MOSFET instance i in Spice.
　図１７及び図１８は、応力分布のシミュレーション結果の回路シミュレーションへの反映の例を示す図である。より具体的には、応力分布のシミュレーション結果に基づいて計算したＭＯＳＦＥＴの特性変動を、そのＭＯＳＦＥＴを含むチップ３の回路シミュレーションに反映させる。先に説明したように、チップ３のチップ面内の各座標のＭＯＳＦＥＴインスタンスｉの応力値σはすでに分かっており、それに基づく各座標のＭＯＳＦＥＴの特性変動も計算済みである。この特性変動情報に基づいて、Ｓｐｉｃｅネットリスト内のパラメータを調整する（特性変動をパラメータにフィードバックする）。 Figures 17 and 18 show an example of reflecting the results of a simulation of stress distribution in a circuit simulation. More specifically, the characteristic variation of a MOSFET calculated based on the results of a simulation of stress distribution is reflected in a circuit simulation of a chip 3 including that MOSFET. As explained above, the stress value σ of a MOSFET instance i at each coordinate on the chip surface of chip 3 is already known, and the characteristic variation of the MOSFET at each coordinate based on this has also been calculated. Based on this characteristic variation information, the parameters in the Spice netlist are adjusted (the characteristic variation is fed back to the parameters).
　具体的に、ＳｐｉｃｅシミュレーションにおいてＭＯＳＦＥＴの特性を記述するパラメータを調整（設定、補正等）する。より具体的には、ＭＯＳＦＥＴの閾値電圧Ｖｔｈを記述するパラメータ、ＭＯＳＦＥＴのキャリア移動度μを記述するパラメータ等を調整する。そのようなパラメータの例は、ＤＥＬＶＴ０及びＭＵＬＵ０等である。ＤＥＬＶＴ０は、ＭＯＳＦＥＴの閾値電圧Ｖｔｈを補正するために用いられるパラメータである。ＭＵＬＵ０は、ＭＯＳＦＥＴのキャリア移動度μを補正するために用いられるパラメータである。 Specifically, in the Spice simulation, parameters describing the characteristics of the MOSFET are adjusted (set, corrected, etc.). More specifically, parameters describing the threshold voltage Vth of the MOSFET, parameters describing the carrier mobility μ of the MOSFET, etc. are adjusted. Examples of such parameters are DELVT0 and MULU0, etc. DELVT0 is a parameter used to correct the threshold voltage Vth of the MOSFET. MULU0 is a parameter used to correct the carrier mobility μ of the MOSFET.
　チップ動作による発熱に起因する応力が無い場合の閾値電圧Ｖｔｈと、チップ動作による発熱に起因する応力がある場合の閾値電圧Ｖｔｈとの差分を、ΔＶｔｈとする。同様に、キャリア移動度μの差分を、Δμとする。閾値電圧ＶｔｈをΔＶｔｈだけ補正するための値が、Ｓｐｉｃｅネットリスト内のＤＥＬＶＴ０に設定される。キャリア移動度μをΔμだけ補正するための値が、Ｓｐｉｃｅネットリスト内のＭＵＬＵ０に設定される。なお、ＰｃｈＭＯＳＦＥＴ及びＮｃｈＭＯＳＦＥＴの両方に対応するパラメータが使用されてよい。また、ここで設定されるＤＥＬＶＴ０及びＭＵＬＵ０の値は、先に述べた応力変動ＭＯＳＦＥＴ特性値を用いて決定されてよい。 The difference between the threshold voltage Vth when there is no stress due to heat generation caused by chip operation and the threshold voltage Vth when there is stress due to heat generation caused by chip operation is set to ΔVth. Similarly, the difference in carrier mobility μ is set to Δμ. A value for correcting the threshold voltage Vth by ΔVth is set in DELVT0 in the Spice netlist. A value for correcting the carrier mobility μ by Δμ is set in MULU0 in the Spice netlist. Note that parameters corresponding to both PchMOSFETs and NchMOSFETs may be used. Also, the values of DELVT0 and MULU0 set here may be determined using the stress variation MOSFET characteristic values described above.
　図１７に示されるように、ＭＯＳＦＥＴインスタンスｉごとにＤＥＬＶＴ０が設定される。ＤＥＬＶＴ０の値はいずれも「ｘｘｘ」として模式的に示されるが、各値は異なっていてよい。また、図１８に示されるように、ＭＯＳＦＥＴインスタンスｉごとにＭＵＬＵ０が設定される。ＭＵＬＵ０の値はいずれも「ｘｘｘ」として模式的に示されるが、各値は異なっていてよい。 As shown in FIG. 17, DELVT0 is set for each MOSFET instance i. All DELVT0 values are shown diagrammatically as "xxx", but each value may be different. Also, as shown in FIG. 18, MULU0 is set for each MOSFET instance i. All MULU0 values are shown diagrammatically as "xxx", but each value may be different.
　上述のｔｅｍｐ、ｄｔｅｍｐ、ＤＥＬＶＴ０、ＭＵＬＵ０等のパラメータ入力は、自動的に行われてもよいし、ユーザ操作によって（手動で）行われてもよい。例えば局所的な部分に限定してＭＯＳＦＥＴの特性を変動させる場合は、手動入力が有効となり得る。 The above-mentioned parameters such as temp, dtemp, DELVT0, and MULU0 may be input automatically or manually by the user. For example, manual input may be effective when varying the characteristics of a MOSFET in a limited, localized area.
　例えば上記のように回路シミュレーション内のパラメータを調整することで、チップ動作による発熱に起因して発生する応力の影響を回路シミュレーションに反映させることができる。熱、応力及び電気（回路）の連成解析が可能になる。 For example, by adjusting the parameters in the circuit simulation as described above, it is possible to reflect the effects of stress caused by heat generation due to chip operation in the circuit simulation. This makes it possible to perform coupled analysis of heat, stress, and electricity (circuit).
　図１９は、シミュレーション方法の概要を示すフローチャートである。各処理の具体的な内容はこれまで説明したとおりであるので、説明は適宜省略する。 Figure 19 is a flowchart showing an overview of the simulation method. The specific content of each process has been explained so far, so explanations will be omitted as appropriate.
　ステップＳ１において、チップデータ及びモデルを準備する。チップデータは、複数のチップ３それぞれのネットリストのデータ、ＧＤＳのデータ等を含んでよい。モデルは、例えば先に図１を参照して説明したような、集約配置された複数のチップ３及び支持体２を含むモデル１である。 In step S1, chip data and a model are prepared. The chip data may include netlist data for each of the multiple chips 3, GDS data, etc. The model is, for example, model 1 including multiple chips 3 arranged in a concentrated manner and a support 2, as described above with reference to FIG. 1.
　ステップＳ２において、集約配置された複数のチップ３の動作時におけるチップ３それぞれのチップ内熱分布をシミュレーションする。 In step S2, the heat distribution within each of the multiple chips 3 arranged in a concentrated manner during operation is simulated.
　ステップＳ３において、熱分布シミュレーション結果に基づいて、複数のチップ３それぞれのチップ内応力分布をシミュレーションする。 In step S3, the stress distribution within each of the multiple chips 3 is simulated based on the results of the thermal distribution simulation.
　ステップＳ４において、熱分布及び応力分布をチップ３内の座標及びＭＯＳＦＥＴインスタンスｉに対応付ける。 In step S4, the thermal distribution and stress distribution are associated with coordinates within chip 3 and MOSFET instance i.
　ステップＳ５において、各座標に位置する（各セグメント内の）ＭＯＳＦＥＴの特性変動を計算する。 In step S5, the characteristic variations of the MOSFETs located at each coordinate (within each segment) are calculated.
　ステップＳ６において、結果を、複数のチップ３それぞれの回路シミュレーションに反映させる。ここでの結果は、熱分布のシミュレーション結果、応力分布のシミュレーション結果、ＭＯＳＦＥＴの特性変動の計算結果等である。反映は、回路シミュレーション内のパラメータの調整等である。 In step S6, the results are reflected in the circuit simulation for each of the multiple chips 3. The results here include the simulation results of heat distribution, the simulation results of stress distribution, and the calculation results of MOSFET characteristic fluctuations. The results are reflected by adjusting parameters in the circuit simulation, etc.
２．変形例
　開示される技術は上記の実施形態に限定されない。いくつかの変形例について述べる。 2. Modifications The disclosed technology is not limited to the above-described embodiment. Some modifications will be described.
　複数のチップ３の配置は、先に説明した図１の例に限られない。図２０～図２２を参照して説明する。 The arrangement of the multiple chips 3 is not limited to the example shown in FIG. 1. The following description will be given with reference to FIGS. 20 to 22.
　図２０～図２２は、チップ配置の例を示す図である。支持体２及び複数のチップ３をＺ軸方向に分解した分解斜視図が示される。図２０に示される例では、支持体２の上に（１層目に）、チップ３－Ｂ、チップ３－Ｃ及びチップ３－Ｃが搭載され、それらの上に（２層目に）、チップ３－Ａが積層される。図２１に示される例では、支持体２の上に、チップ３－Ｂ、チップ３－Ｃ及びチップ３－Ｃだけが搭載される。図２２に示される例では、支持体２の上にチップ３－Ａが搭載され、その上に、チップ３－Ｂ、チップ３－Ｃ及びチップ３－Ｄが積層される。各チップ３の形状や向きもさまざまに異なり得る。 FIGS. 20 to 22 are diagrams showing examples of chip arrangements. The diagrams show exploded perspective views of the support 2 and multiple chips 3 disassembled in the Z-axis direction. In the example shown in FIG. 20, chips 3-B, 3-C, and 3-C are mounted on the support 2 (first layer), and chip 3-A is stacked on top of them (second layer). In the example shown in FIG. 21, only chips 3-B, 3-C, and 3-C are mounted on the support 2. In the example shown in FIG. 22, chip 3-A is mounted on the support 2, and chips 3-B, 3-C, and 3-D are stacked on top of that. The shapes and orientations of each chip 3 can also vary.
　上記実施形態では、チップ３に含まれる能動素子がＭＯＳＦＥＴである場合を例に挙げて説明した。ただし、能動素子は、ＭＯＳＦＥＴに限定されない。図２３を参照して説明する。 In the above embodiment, the active element included in chip 3 is a MOSFET. However, the active element is not limited to a MOSFET. The following description will be given with reference to FIG. 23.
　図２３は、能動素子の例を示す図である。能動素子として、半導体で構成される電流制御素子が例示される。また、このような電流制御素子として、電界効果トランジスタ、バイポーラトランジスタ、ＰＮ接合ダイオード及びサイリスタが例示される。これまで説明したＭＯＳＦＥＴは、電界効果トランジスタの一例である。 FIG. 23 is a diagram showing an example of an active element. An example of an active element is a current control element made of a semiconductor. Examples of such current control elements include a field effect transistor, a bipolar transistor, a PN junction diode, and a thyristor. The MOSFET described so far is an example of a field effect transistor.
　上記の実施形態に係るシミュレーション方法に供することのできる情報処理装置及び情報処理プログラムが提供されてもよい。図２４及び図２５を参照して説明する。 An information processing device and an information processing program that can be used for the simulation method according to the above embodiment may be provided. This will be described with reference to Figures 24 and 25.
　図２４は、情報処理装置の概略構成の例を示す図である。情報処理装置４は、ユーザインタフェース部５と、処理部６と、記憶部７とを含む。ユーザインタフェース部５は、ユーザ操作を受け付けたり、ユーザに情報を提示したりする。処理部６は、各種の処理を実行する。 FIG. 24 is a diagram showing an example of the schematic configuration of an information processing device. The information processing device 4 includes a user interface unit 5, a processing unit 6, and a storage unit 7. The user interface unit 5 accepts user operations and presents information to the user. The processing unit 6 executes various types of processing.
　記憶部７に記憶される情報として、熱分布シミュレーションプログラム７１、応力分布シミュレーションプログラム７２、回路シミュレーションプログラム７３及び情報処理プログラム７４が例示される。熱分布シミュレーションプログラム７１、応力分布シミュレーションプログラム７２及び回路シミュレーションプログラム７３は、これまで説明した熱分布シミュレーション、応力分布シミュレーション及び回路シミュレーションを行うために用いられる。情報処理プログラム７４は、コンピュータを情報処理装置４（の例えばユーザインタフェース部５、処理部６等として）機能させるためのプログラム（ソフトウェア、アプリケーション）である。 Examples of information stored in the memory unit 7 include a heat distribution simulation program 71, a stress distribution simulation program 72, a circuit simulation program 73, and an information processing program 74. The heat distribution simulation program 71, the stress distribution simulation program 72, and the circuit simulation program 73 are used to perform the heat distribution simulation, the stress distribution simulation, and the circuit simulation described above. The information processing program 74 is a program (software, application) for causing the computer to function as the information processing device 4 (for example, as the user interface unit 5, the processing unit 6, etc.).
　処理部６が、ユーザインタフェース部５を介したユーザ操作に応じて各種の処理を実行することにより、先に説明した実施形態に係るシミュレーション方法の手順がすすめられる。先に図１を参照して説明したようなモデル１、また、そこに含まれる各チップ３のチップデータが準備される。熱分布シミュレーションプログラム７１が実行され、熱分布のシミュレーション結果が得られる。熱分布のシミュレーション結果に基づいて、応力分布シミュレーションプログラム７２が実行され、応力分布のシミュレーション結果が得られる。それらのシミュレーション結果に基づいて、チップ３内のＭＯＳＦＥＴの特性変動が計算される。この計算は、先にも述べたように、別途用意されたデバイスシミュレータ、任意のツール等が用いられてよい。シミュレーション結果や計算結果が回路シミュレーションに反映されるとともに、回路シミュレーションプログラム７３が実行される。 The processing unit 6 executes various processes in response to user operations via the user interface unit 5, thereby proceeding with the procedure of the simulation method according to the embodiment described above. The model 1 as described above with reference to FIG. 1 and the chip data of each chip 3 contained therein are prepared. A heat distribution simulation program 71 is executed to obtain a simulation result of the heat distribution. Based on the simulation result of the heat distribution, a stress distribution simulation program 72 is executed to obtain a simulation result of the stress distribution. Based on these simulation results, the characteristic fluctuation of the MOSFET in the chip 3 is calculated. As described above, this calculation may be performed using a separately prepared device simulator, any tool, etc. The simulation results and calculation results are reflected in the circuit simulation, and a circuit simulation program 73 is executed.
　なお、情報処理装置４の機能の一部は、情報処理装置４と通信可能に構成された外部サーバ装置に備えられてもよい。外部サーバ装置が備え得る機能の例は、処理部６の一部の機能、熱分布シミュレーションプログラム７１の一部又は全部、応力分布シミュレーションプログラム７２の一部又は全部、回路シミュレーションプログラム７３の一部又は全部等である。 In addition, some of the functions of the information processing device 4 may be provided in an external server device configured to be able to communicate with the information processing device 4. Examples of functions that may be provided in the external server device include some of the functions of the processing unit 6, some or all of the heat distribution simulation program 71, some or all of the stress distribution simulation program 72, some or all of the circuit simulation program 73, etc.
　図２５は、情報処理装置のハードウェア構成の例を示す図である。例えば図示されるようなコンピュータ１０００によって、情報処理装置４が実現され得る。コンピュータ１０００は、ＣＰＵ１１００、ＲＡＭ１２００、ＲＯＭ（Read　Only　Memory）１３００、ＨＤＤ（Hard　Disk　Drive）１４００、通信インタフェース１５００、及び入出力インタフェース１６００を有する。コンピュータ１０００の各部は、バス１０５０によって接続される。 FIG. 25 is a diagram showing an example of the hardware configuration of an information processing device. For example, the information processing device 4 can be realized by a computer 1000 as shown in the figure. The computer 1000 has a CPU 1100, a RAM 1200, a ROM (Read Only Memory) 1300, a HDD (Hard Disk Drive) 1400, a communication interface 1500, and an input/output interface 1600. Each part of the computer 1000 is connected by a bus 1050.
　ＣＰＵ１１００は、ＲＯＭ１３００又はＨＤＤ１４００に格納されたプログラムに基づいて動作し、各部の制御を行う。例えば、ＣＰＵ１１００は、ＲＯＭ１３００又はＨＤＤ１４００に格納されたプログラムをＲＡＭ１２００に展開し、各種プログラムに対応した処理を実行する。プログラムには、先に述べた熱分布シミュレーションプログラム７１、応力分布シミュレーションプログラム７２、回路シミュレーションプログラム７３及び情報処理プログラム７４等が含まれる。 The CPU 1100 operates based on the programs stored in the ROM 1300 or the HDD 1400, and controls each part. For example, the CPU 1100 loads the programs stored in the ROM 1300 or the HDD 1400 into the RAM 1200, and executes processing corresponding to the various programs. The programs include the heat distribution simulation program 71, the stress distribution simulation program 72, the circuit simulation program 73, and the information processing program 74, which are mentioned above.
　ＲＯＭ１３００は、コンピュータ１０００の起動時にＣＰＵ１１００によって実行されるＢＩＯＳ（Basic　Input　Output　System）等のブートプログラムや、コンピュータ１０００のハードウェアに依存するプログラム等を格納する。 The ROM 1300 stores boot programs such as the Basic Input Output System (BIOS) that is executed by the CPU 1100 when the computer 1000 starts up, as well as programs that depend on the hardware of the computer 1000.
　ＨＤＤ１４００は、ＣＰＵ１１００によって実行されるプログラム、及び、かかるプログラムによって使用されるデータ等を非一時的に記録する、コンピュータが読み取り可能な記録媒体である。具体的には、ＨＤＤ１４００は、プログラムデータ１４５０の一例である情報処理プログラム７４等を記録する記録媒体である。 HDD 1400 is a computer-readable recording medium that non-temporarily records programs executed by CPU 1100 and data used by such programs. Specifically, HDD 1400 is a recording medium that records information processing program 74, which is an example of program data 1450.
　通信インタフェース１５００は、コンピュータ１０００が外部ネットワーク１５５０（例えばインターネット）と接続するためのインタフェースである。例えば、ＣＰＵ１１００は、通信インタフェース１５００を介して、他の機器からデータを受信したり、ＣＰＵ１１００が生成したデータを他の機器へ送信したりする。 The communication interface 1500 is an interface for connecting the computer 1000 to an external network 1550 (e.g., the Internet). For example, the CPU 1100 receives data from other devices and transmits data generated by the CPU 1100 to other devices via the communication interface 1500.
　入出力インタフェース１６００は、入出力デバイス１６５０とコンピュータ１０００とを接続するためのインタフェースである。例えば、ＣＰＵ１１００は、入出力インタフェース１６００を介して、キーボードやマウス等の入力デバイスからデータを受信する。また、ＣＰＵ１１００は、入出力インタフェース１６００を介して、ディスプレイやスピーカやプリンタ等の出力デバイスにデータを送信する。また、入出力インタフェース１６００は、所定の記録媒体（メディア）に記録されたプログラム等を読み取るメディアインタフェースとして機能してもよい。メディアとは、例えばＤＶＤ（Digital　Versatile　Disc）、ＰＤ（Phase　change　rewritable　Disk）等の光学記録媒体、ＭＯ（Magneto-Optical　disk）等の光磁気記録媒体、テープ媒体、磁気記録媒体、又は半導体メモリ等である。 The input/output interface 1600 is an interface for connecting the input/output device 1650 and the computer 1000. For example, the CPU 1100 receives data from an input device such as a keyboard or a mouse via the input/output interface 1600. The CPU 1100 also transmits data to an output device such as a display, a speaker or a printer via the input/output interface 1600. The input/output interface 1600 may also function as a media interface that reads programs and the like recorded on a specific recording medium. Examples of media include optical recording media such as DVDs (Digital Versatile Discs) and PDs (Phase change rewritable Disks), magneto-optical recording media such as MOs (Magneto-Optical Disks), tape media, magnetic recording media, and semiconductor memories.
　例えば、コンピュータ１０００のＣＰＵ１１００は、ＲＡＭ１２００上にロードされた情報処理プログラム７４を実行することにより、情報処理装置４の機能を実現する。なお、ＣＰＵ１１００は、プログラムデータ１４５０をＨＤＤ１４００から読み取って実行するが、他の例として、外部ネットワーク１５５０を介して、他の装置からこれらのプログラムを取得してもよい。 For example, the CPU 1100 of the computer 1000 executes the information processing program 74 loaded onto the RAM 1200 to realize the functions of the information processing device 4. The CPU 1100 reads and executes the program data 1450 from the HDD 1400, but as another example, the CPU 1100 may obtain these programs from other devices via the external network 1550.
３．効果の例
　以上で説明した技術は、例えば次のように特定される。開示される技術の１つは、シミュレーション方法である。図１～図１９等を参照して説明したように、シミュレーション方法は、能動素子（例えば、電界効果トランジスタ（ＭＯＳＦＥＴを含む）、バイポーラトランジスタ、ＰＮ接合ダイオード、サイリスタといった、半導体で構成される電流制御素子）を含み集約配置された複数のチップ３の動作時における消費電力を加味し、複数のチップ３それぞれのチップ内熱分布をシミュレーションすること（ステップＳ２）と、熱分布のシミュレーション結果に基づいて、複数のチップ３それぞれのチップ内応力分布をシミュレーションすること（ステップＳ３）と、応力分布のシミュレーション結果を、複数のチップ３それぞれの回路シミュレーションに反映させること（ステップＳ６）と、を含む。これにより、チップ動作による発熱に起因して発生する応力の影響を回路シミュレーションに反映させることができる。 3. Example of Effects The above-described technology is specified, for example, as follows. One of the disclosed technologies is a simulation method. As described with reference to FIG. 1 to FIG. 19, the simulation method includes simulating the heat distribution in each of the multiple chips 3 by taking into account the power consumption during operation of multiple chips 3 including active elements (for example, current control elements composed of semiconductors such as field effect transistors (including MOSFETs), bipolar transistors, PN junction diodes, and thyristors) arranged in a concentrated manner (step S2), simulating the stress distribution in each of the multiple chips 3 based on the simulation result of the heat distribution (step S3), and reflecting the simulation result of the stress distribution in the circuit simulation of each of the multiple chips 3 (step S6). This allows the influence of stress generated due to heat generation caused by chip operation to be reflected in the circuit simulation.
　図９～図１４及び図１９等を参照して説明したように、シミュレーション方法は、応力分布のシミュレーション結果に基づいて、能動素子の特性変動を計算すること（ステップＳ５）を含み、回路シミュレーションに反映させること（ステップＳ６）は、能動素子の特性変動の計算結果を、当該能動素子を含むチップ３の回路シミュレーションに反映させることを含んでよい。これにより、応力に起因する能動素子の特性変動を回路シミュレーションに反映させることができる。 As described with reference to Figures 9 to 14 and 19, the simulation method includes calculating the characteristic variation of the active element based on the simulation results of the stress distribution (step S5), and reflecting the result in the circuit simulation (step S6) may include reflecting the calculation results of the characteristic variation of the active element in the circuit simulation of the chip 3 including the active element. This allows the characteristic variation of the active element caused by stress to be reflected in the circuit simulation.
　図５、図６、図９～図１４及び図１９等を参照して説明したように、シミュレーション方法は、応力分布を、能動素子を含むチップ３内の座標に対応付けること（ステップＳ４）を含み、能動素子の特性変動を計算すること（ステップＳ５）は、チップ３内の各座標での応力値σに基づいて、同じ座標に位置する能動素子の特性変動を計算することを含んでよい。例えばこのようにして、チップ３内の各位置の能動素子の特性変動を計算することができる。 As described with reference to Figures 5, 6, 9 to 14, and 19, the simulation method includes associating the stress distribution with coordinates within the chip 3 including the active element (step S4), and calculating the characteristic variation of the active element (step S5) may include calculating the characteristic variation of the active element located at the same coordinates based on the stress value σ at each coordinate within the chip 3. For example, in this manner, the characteristic variation of the active element at each position within the chip 3 can be calculated.
　図１３、図１４及び図１９等を参照して説明したように、能動素子の特性変動を計算すること（ステップＳ５）は、能動素子を含むチップ３における当該能動素子のサイズ及び周辺構造に基づいて、当該能動素子の変動特性を計算することを含んでよい。これにより、能動素子のサイズ及び周辺構造のさまざまなバリエーションが存在する場合でも、能動素子の特性変動を適切に計算することができる。 As described with reference to Figures 13, 14, and 19, calculating the characteristic variation of the active element (step S5) may include calculating the variation characteristic of the active element based on the size and peripheral structure of the active element in the chip 3 that includes the active element. This makes it possible to appropriately calculate the characteristic variation of the active element even when there are various variations in the size and peripheral structure of the active element.
　図３及び図１９等を参照して説明したように、チップ３は、熱膨張係数が異なる複数の材料が組み合わせて製造されたチップであり、応力分布をシミュレーションすること（ステップＳ３）は、チップ３が製造された際の複数の材料の残存応力に基づいて、チップ内応力分布をシミュレーションすることを含んでよい。これにより、チップ３の各材料の残存応力をも考慮した応力分布シミュレーションが可能になる。 As described with reference to Figures 3 and 19, etc., the chip 3 is a chip manufactured by combining multiple materials with different thermal expansion coefficients, and simulating the stress distribution (step S3) may include simulating the stress distribution within the chip based on the residual stresses of the multiple materials when the chip 3 was manufactured. This makes it possible to perform a stress distribution simulation that also takes into account the residual stresses of each material in the chip 3.
　図９～図１２及び図１９等を参照して説明したように、能動素子の特性変動を計算すること（ステップＳ５）は、熱分布のシミュレーション結果にも基づいて、チップ３内の能動素子の特性変動を計算することを含んでよい。これにより、チップ３の動作による発熱に起因する能動素子の特性変動も回路シミュレーションに反映させることができる。 As described with reference to Figures 9 to 12 and 19, calculating the characteristic variations of the active elements (step S5) may include calculating the characteristic variations of the active elements in the chip 3 based on the results of the heat distribution simulation. This allows the characteristic variations of the active elements caused by heat generation due to the operation of the chip 3 to be reflected in the circuit simulation.
　図１、図１５～図１９及び図２３等を参照して説明したように、回路シミュレーションに反映させること（ステップＳ６）は、回路シミュレーションにおいて能動素子の特性を記述するパラメータを調整することを含んでよい。能動素子は、電界効果トランジスタを含み、パラメータは、キャリア移動度μを記述するパラメータ及び閾値電圧Ｖｔｈを記述するパラメータの少なくとも一方を含んでよい。例えば、回路シミュレーションは、Ｓｐｉｃｅシミュレーションを含み、キャリア移動度μを記述するパラメータは、ＭＵＬＵ０を含み、閾値電圧Ｖｔｈを記述するパラメータは、ＤＥＬＶＴ０を含んでよい。例えばこのようなパラメータ調整により、能動素子の特性変動を回路シミュレーションに反映させることができる。 As described with reference to Figures 1, 15 to 19, and 23, etc., reflecting in the circuit simulation (step S6) may include adjusting parameters describing the characteristics of the active element in the circuit simulation. The active element may include a field effect transistor, and the parameters may include at least one of a parameter describing the carrier mobility μ and a parameter describing the threshold voltage Vth. For example, the circuit simulation may include a Spice simulation, and the parameters describing the carrier mobility μ may include MULU0, and the parameters describing the threshold voltage Vth may include DELVT0. For example, by adjusting the parameters in this way, the characteristic fluctuations of the active element can be reflected in the circuit simulation.
　図１５、図１６及び図１９等を参照して説明したように、シミュレーション方法は、熱分布のシミュレーション結果に基づいて、回路シミュレーションにおいて温度を記述するパラメータを調整することを含んでよい。例えば、回路シミュレーションは、Ｓｐｉｃｅシミュレーションを含み、温度を記述するパラメータは、ｄｔｅｍｐを含んでよい。これにより、温度分布も回路シミュレーションに反映させることができる。 As described with reference to Figures 15, 16, and 19, the simulation method may include adjusting parameters describing temperature in the circuit simulation based on the simulation results of the heat distribution. For example, the circuit simulation may include a Spice simulation, and the parameters describing temperature may include dtemp. This allows the temperature distribution to be reflected in the circuit simulation.
　図１及び図２０～図２２等を参照して説明したように、複数のチップ３のうちの少なくとも一部のチップ３は、互いに積層されてよい。また、複数のチップ３のうちの少なくとも一部のチップ３は、１つの基板又はパッケージ（支持体２）上に直接設けられてよい。例えばこのようなさまざまな態様で集約配置された複数のチップ３について、チップ動作による発熱に起因して発生する応力の影響を回路シミュレーションに反映させることができる。 As described with reference to FIG. 1 and FIG. 20 to FIG. 22, at least some of the chips 3 among the multiple chips 3 may be stacked on top of each other. Also, at least some of the chips 3 among the multiple chips 3 may be provided directly on a single substrate or package (support 2). For example, for multiple chips 3 arranged in a concentrated manner in this manner, the effect of stress caused by heat generation due to chip operation can be reflected in the circuit simulation.
　図１～図４及び図１９等を参照して説明したように、熱分布をシミュレーションすること（ステップＳ２）は、熱分布の経時変化のシミュレーションを含み、応力分布をシミュレーションすること（ステップＳ３）は、応力分布の経時変化のシミュレーションを含んでよい。これにより、例えば複数のチップ３それぞれの動作タイミグが異なるような複雑な場合でも、チップ動作による発熱に起因して発生する応力の影響を回路シミュレーションに反映させることができる。 As described with reference to Figures 1 to 4 and 19, simulating the heat distribution (step S2) may include simulating the change in heat distribution over time, and simulating the stress distribution (step S3) may include simulating the change in stress distribution over time. This makes it possible to reflect the effects of stress caused by heat generation due to chip operation in the circuit simulation, even in complex cases where the operation timing of multiple chips 3 is different.
　図１～図１９、図２４及び図２５等を参照して説明した情報処理装置４及び情報処理プログラム７４も、開示される技術の例である。情報処理装置４は、集約配置された複数のチップ３の動作時における消費電力を加味し、複数のチップ３それぞれのチップ内熱分布をシミュレーションし、熱分布のシミュレーション結果に基づいて、複数のチップ３それぞれのチップ内応力分布をシミュレーションし、応力分布のシミュレーション結果を、複数のチップ３それぞれの回路シミュレーションに反映させる、処理部６を備える。情報処理プログラム７４は、コンピュータ１０００に、集約配置された複数のチップ３の動作時における消費電力を加味し、複数のチップ３それぞれのチップ内熱分布をシミュレーションし、熱分布のシミュレーション結果に基づいて、複数のチップ３それぞれのチップ内応力分布をシミュレーションし、応力分布のシミュレーション結果を、複数のチップ３それぞれの回路シミュレーションに反映させる、処理を実行させる。このような情報処理装置４及び情報処理プログラム７４によっても、これまで説明したように、チップ動作による発熱に起因して発生する応力の影響を回路シミュレーションに反映させることができる。 The information processing device 4 and the information processing program 74 described with reference to Figures 1 to 19, 24, and 25 are also examples of the disclosed technology. The information processing device 4 includes a processing unit 6 that takes into account the power consumption during operation of the multiple chips 3 arranged in a concentrated manner, simulates the heat distribution within each of the multiple chips 3, simulates the stress distribution within each of the multiple chips 3 based on the simulation result of the heat distribution, and reflects the simulation result of the stress distribution in the circuit simulation of each of the multiple chips 3. The information processing program 74 causes the computer 1000 to execute a process that takes into account the power consumption during operation of the multiple chips 3 arranged in a concentrated manner, simulates the heat distribution within each of the multiple chips 3, simulates the stress distribution within each of the multiple chips 3 based on the simulation result of the heat distribution, and reflects the simulation result of the stress distribution in the circuit simulation of each of the multiple chips 3. With such information processing device 4 and information processing program 74, the influence of stress generated due to heat generation caused by chip operation can also be reflected in the circuit simulation, as described above.
　なお、本開示に記載された効果は、あくまで例示であって、開示された内容に限定されない。他の効果があってもよい。 Note that the effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also exist.
　以上、本開示の実施形態について説明したが、本開示の技術的範囲は、上述の実施形態そのままに限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更が可能である。また、異なる実施形態及び変形例にわたる構成要素を適宜組み合わせてもよい。 The above describes the embodiments of the present disclosure, but the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present disclosure. In addition, components from different embodiments and modified examples may be combined as appropriate.
　なお、本技術は以下のような構成も取ることができる。
（１）
　能動素子を含み集約配置された複数のチップの動作時における消費電力を加味し、前記複数のチップそれぞれのチップ内熱分布をシミュレーションすることと、
　前記熱分布のシミュレーション結果に基づいて、前記複数のチップそれぞれのチップ内応力分布をシミュレーションすることと、
　前記応力分布のシミュレーション結果を、前記複数のチップそれぞれの回路シミュレーションに反映させることと、
　を含む、
　シミュレーション方法。
（２）
　前記応力分布のシミュレーション結果に基づいて、前記能動素子の特性変動を計算することを含み、
　前記回路シミュレーションに反映させることは、前記能動素子の特性変動の計算結果を、当該能動素子を含むチップの回路シミュレーションに反映させることを含む、
　（１）に記載のシミュレーション方法。
（３）
　前記応力分布を、前記能動素子を含むチップ内の座標に対応付けることを含み、
　前記能動素子の特性変動を計算することは、チップ内の各座標での応力値に基づいて、同じ座標に位置する能動素子の特性変動を計算することを含む、
　（２）に記載のシミュレーション方法。
（４）
　前記能動素子の特性変動を計算することは、前記能動素子を含むチップにおける当該能動素子のサイズ及び周辺構造に基づいて、当該能動素子の変動特性を計算することを含む、
　（２）又は（３）に記載のシミュレーション方法。
（５）
　前記チップは、熱膨張係数が異なる複数の材料が組み合わせて製造されたチップであり、
　前記応力分布をシミュレーションすることは、前記チップが製造された際の前記複数の材料の残存応力に基づいて、前記チップ内応力分布をシミュレーションすることを含む、
　（１）～（４）のいずれかに記載のシミュレーション方法。
（６）
　前記能動素子の特性変動を計算することは、前記熱分布のシミュレーション結果にも基づいて、前記チップ内の能動素子の特性変動を計算することを含む、
　（２）～（５）のいずれかに記載のシミュレーション方法。
（７）
　前記回路シミュレーションに反映させることは、前記回路シミュレーションにおいて前記能動素子の特性を記述するパラメータを調整することを含む、
　（１）～（６）のいずれかに記載のシミュレーション方法。
（８）
　前記能動素子は、電界効果トランジスタを含み、
　前記パラメータは、閾値電圧を記述するパラメータ及びキャリア移動度を記述するパラメータの少なくとも一方を含む、
　（７）に記載のシミュレーション方法。
（９）
　前記回路シミュレーションは、Ｓｐｉｃｅシミュレーションを含み、
　前記キャリア移動度を記述するパラメータは、ＭＵＬＵ０を含み、
　前記閾値電圧を記述するパラメータは、ＤＥＬＶＴ０を含む、
　（８）に記載のシミュレーション方法。
（１０）
　前記熱分布のシミュレーション結果に基づいて、前記回路シミュレーションにおいて温度を記述するパラメータを調整することを含む、
　（１）～（９）のいずれかに記載のシミュレーション方法。
（１１）
　前記回路シミュレーションは、Ｓｐｉｃｅシミュレーションを含み、
　前記温度を記述するパラメータは、ｄｔｅｍｐを含む、
　（１０）に記載のシミュレーション方法。
（１２）
　前記複数のチップのうちの少なくとも一部のチップは、互いに積層される、
　（１）～（１１）のいずれかに記載のシミュレーション方法。
（１３）
　前記複数のチップのうちの少なくとも一部のチップは、１つの基板又はパッケージ上に直接設けられる、
　（１）～（１２）のいずれかに記載のシミュレーション方法。
（１４）
　前記能動素子は、半導体で構成される電流制御素子を含み、
　前記電流制御素子は、
　　電界効果トランジスタ、
　　バイポーラトランジスタ、
　　ＰＮ接合ダイオード、
　及び
　　サイリスタ
　の少なくとも１つを含む、
　（１）～（１３）いずれかに記載のシミュレーション方法。
（１５）
　前記能動素子は、ＭＯＳＦＥＴを含む、
　（１）～（１４）のいずれかに記載のシミュレーション方法。
（１６）
　前記熱分布をシミュレーションすることは、熱分布の経時変化のシミュレーションを含み、
　前記応力分布をシミュレーションすることは、応力分布の経時変化のシミュレーションを含む、
　（１）～（１５）のいずれかに記載のシミュレーション方法。
（１７）
　集約配置された複数のチップの動作時における消費電力を加味し、前記複数のチップそれぞれのチップ内熱分布をシミュレーションし、
　前記熱分布のシミュレーション結果に基づいて、前記複数のチップそれぞれのチップ内応力分布をシミュレーションし、
　前記応力分布のシミュレーション結果を、前記複数のチップそれぞれの回路シミュレーションに反映させる、
　処理部を備える、
　情報処理装置。
（１８）
　コンピュータに、
　集約配置された複数のチップの動作時における消費電力を加味し、前記複数のチップそれぞれのチップ内熱分布をシミュレーションし、
　前記熱分布のシミュレーション結果に基づいて、前記複数のチップそれぞれのチップ内応力分布をシミュレーションし、
　前記応力分布のシミュレーション結果を、前記複数のチップそれぞれの回路シミュレーションに反映させる、
　処理を実行させる、
　情報処理プログラム。 The present technology can also be configured as follows.
(1)
Taking into account the power consumption during operation of a plurality of chips including active elements arranged in a concentrated manner, a simulation is performed of a heat distribution within each of the plurality of chips;
simulating a stress distribution within each of the plurality of chips based on a result of the simulation of the heat distribution; and
reflecting a result of the simulation of the stress distribution in a circuit simulation of each of the plurality of chips;
including,
Simulation method.
(2)
calculating a characteristic variation of the active element based on a simulation result of the stress distribution;
Reflecting the calculation result of the characteristic variation of the active element in the circuit simulation includes reflecting the calculation result of the characteristic variation of the active element in the circuit simulation of a chip including the active element.
A simulation method according to (1).
(3)
Correlating the stress distribution to coordinates within a chip including the active device;
Calculating the characteristic variation of the active element includes calculating the characteristic variation of an active element located at the same coordinate based on the stress value at each coordinate in the chip.
The simulation method according to (2).
(4)
Calculating the characteristic variation of the active element includes calculating the variation characteristic of the active element based on a size and a peripheral structure of the active element in a chip including the active element.
The simulation method according to (2) or (3).
(5)
The chip is manufactured by combining a plurality of materials having different thermal expansion coefficients,
simulating the stress distribution includes simulating a stress distribution in the chip based on residual stresses of the materials when the chip is manufactured.
A simulation method according to any one of (1) to (4).
(6)
Calculating the characteristic variation of the active element includes calculating the characteristic variation of the active element in the chip based on the simulation result of the heat distribution.
A simulation method according to any one of (2) to (5).
(7)
Reflecting the result in the circuit simulation includes adjusting a parameter describing a characteristic of the active element in the circuit simulation.
A simulation method according to any one of (1) to (6).
(8)
the active element includes a field effect transistor;
The parameters include at least one of a parameter describing a threshold voltage and a parameter describing carrier mobility.
(7) A simulation method according to the above item.
(9)
The circuit simulation includes a Spice simulation,
The parameters describing the carrier mobility include MULU0;
The parameters describing the threshold voltage include DELVT0;
The simulation method according to (8).
(10)
adjusting a parameter describing a temperature in the circuit simulation based on a result of the simulation of the heat distribution.
A simulation method according to any one of (1) to (9).
(11)
The circuit simulation includes a Spice simulation,
The parameters describing the temperature include dtemp;
The simulation method according to (10).
(12)
At least some of the chips among the plurality of chips are stacked on one another.
A simulation method according to any one of (1) to (11).
(13)
At least some of the chips among the plurality of chips are provided directly on one substrate or package.
A simulation method according to any one of (1) to (12).
(14)
the active element includes a current control element made of a semiconductor;
The current control element is
Field effect transistors,
Bipolar transistors,
PN junction diode,
and a thyristor;
A simulation method according to any one of (1) to (13).
(15)
The active element includes a MOSFET.
A simulation method according to any one of (1) to (14).
(16)
simulating the heat distribution includes simulating a change in the heat distribution over time;
The simulating of the stress distribution includes simulating a change in the stress distribution over time.
A simulation method according to any one of (1) to (15).
(17)
Taking into account the power consumption during operation of the plurality of chips arranged in a concentrated manner, a simulation is performed for a heat distribution within each of the plurality of chips;
simulating a stress distribution within each of the plurality of chips based on a result of the simulation of the heat distribution;
reflecting a result of the simulation of the stress distribution in a circuit simulation of each of the plurality of chips;
A processing unit is provided.
Information processing device.
(18)
On the computer,
Taking into account the power consumption during operation of the plurality of chips arranged in a concentrated manner, a simulation is performed for a heat distribution within each of the plurality of chips;
simulating a stress distribution within each of the plurality of chips based on a result of the simulation of the heat distribution;
reflecting a result of the simulation of the stress distribution in a circuit simulation of each of the plurality of chips;
Execute the process,
Information processing program.
　　１　モデル
　　２　支持体
　　３　チップ
　　４　情報処理装置
　　５　ユーザインタフェース部
　　６　処理部
　　７　記憶部
　７１　熱分布シミュレーションプログラム
　７２　応力分布シミュレーションプログラム
　７３　回路シミュレーションプログラム
　７４　情報処理プログラム REFERENCE SIGNS LIST 1 Model 2 Support 3 Chip 4 Information processing device 5 User interface unit 6 Processing unit 7 Storage unit 71 Heat distribution simulation program 72 Stress distribution simulation program 73 Circuit simulation program 74 Information processing program

Claims (18)

  1. 　能動素子を含み集約配置された複数のチップの動作時における消費電力を加味し、前記複数のチップそれぞれのチップ内熱分布をシミュレーションすることと、
    　前記熱分布のシミュレーション結果に基づいて、前記複数のチップそれぞれのチップ内応力分布をシミュレーションすることと、
    　前記応力分布のシミュレーション結果を、前記複数のチップそれぞれの回路シミュレーションに反映させることと、
    　を含む、
    　シミュレーション方法。     Taking into account the power consumption during operation of a plurality of chips including active elements arranged in a concentrated manner, a simulation is performed of a heat distribution within each of the plurality of chips;
    simulating a stress distribution within each of the plurality of chips based on a result of the simulation of the heat distribution; and
    reflecting a result of the simulation of the stress distribution in a circuit simulation of each of the plurality of chips;
    including,
    Simulation method.
  2. 　前記応力分布のシミュレーション結果に基づいて、前記能動素子の特性変動を計算することを含み、
    　前記回路シミュレーションに反映させることは、前記能動素子の特性変動の計算結果を、当該能動素子を含むチップの回路シミュレーションに反映させることを含む、
    　請求項１に記載のシミュレーション方法。     calculating a characteristic variation of the active element based on a simulation result of the stress distribution;
    Reflecting the calculation result of the characteristic variation of the active element in the circuit simulation includes reflecting the calculation result of the characteristic variation of the active element in the circuit simulation of a chip including the active element.
    The simulation method according to claim 1 .
  3. 　前記応力分布を、前記能動素子を含むチップ内の座標に対応付けることを含み、
    　前記能動素子の特性変動を計算することは、チップ内の各座標での応力値に基づいて、同じ座標に位置する能動素子の特性変動を計算することを含む、
    　請求項２に記載のシミュレーション方法。     Correlating the stress distribution to coordinates within a chip including the active device;
    Calculating the characteristic variation of the active element includes calculating the characteristic variation of an active element located at the same coordinate based on the stress value at each coordinate in the chip.
    The simulation method according to claim 2 .
  4. 　前記能動素子の特性変動を計算することは、前記能動素子を含むチップにおける当該能動素子のサイズ及び周辺構造に基づいて、当該能動素子の変動特性を計算することを含む、
    　請求項２に記載のシミュレーション方法。     Calculating the characteristic variation of the active element includes calculating the variation characteristic of the active element based on a size and a peripheral structure of the active element in a chip including the active element.
    The simulation method according to claim 2 .
  5. 　前記チップは、熱膨張係数が異なる複数の材料が組み合わせて製造されたチップであり、
    　前記応力分布をシミュレーションすることは、前記チップが製造された際の前記複数の材料の残存応力に基づいて、前記チップ内応力分布をシミュレーションすることを含む、
    　請求項１に記載のシミュレーション方法。     The chip is manufactured by combining a plurality of materials having different thermal expansion coefficients,
    simulating the stress distribution includes simulating a stress distribution in the chip based on residual stresses of the materials when the chip is manufactured.
    The simulation method according to claim 1 .
  6. 　前記能動素子の特性変動を計算することは、前記熱分布のシミュレーション結果にも基づいて、前記チップ内の能動素子の特性変動を計算することを含む、
    　請求項２に記載のシミュレーション方法。     Calculating the characteristic variation of the active element includes calculating the characteristic variation of the active element in the chip based on the simulation result of the heat distribution.
    The simulation method according to claim 2 .
  7. 　前記回路シミュレーションに反映させることは、前記回路シミュレーションにおいて前記能動素子の特性を記述するパラメータを調整することを含む、
    　請求項１に記載のシミュレーション方法。     Reflecting the result in the circuit simulation includes adjusting a parameter describing a characteristic of the active element in the circuit simulation.
    The simulation method according to claim 1 .
  8. 　前記能動素子は、電界効果トランジスタを含み、
    　前記パラメータは、閾値電圧を記述するパラメータ及びキャリア移動度を記述するパラメータの少なくとも一方を含む、
    　請求項７に記載のシミュレーション方法。     the active element includes a field effect transistor;
    The parameters include at least one of a parameter describing a threshold voltage and a parameter describing carrier mobility.
    The simulation method according to claim 7.
  9. 　前記回路シミュレーションは、Ｓｐｉｃｅシミュレーションを含み、
    　前記キャリア移動度を記述するパラメータは、ＭＵＬＵ０を含み、
    　前記閾値電圧を記述するパラメータは、ＤＥＬＶＴ０を含む、
    　請求項８に記載のシミュレーション方法。     The circuit simulation includes a Spice simulation.
    The parameters describing the carrier mobility include MULU0,
    The parameters describing the threshold voltage include DELVT0;
    The simulation method according to claim 8.
  10. 　前記熱分布のシミュレーション結果に基づいて、前記回路シミュレーションにおいて温度を記述するパラメータを調整することを含む、
    　請求項１に記載のシミュレーション方法。     adjusting a parameter describing a temperature in the circuit simulation based on a result of the simulation of the heat distribution.
    The simulation method according to claim 1 .
  11. 　前記回路シミュレーションは、Ｓｐｉｃｅシミュレーションを含み、
    　前記温度を記述するパラメータは、ｄｔｅｍｐを含む、
    　請求項１０に記載のシミュレーション方法。     The circuit simulation includes a Spice simulation.
    The parameters describing the temperature include dtemp;
    The simulation method according to claim 10.
  12. 　前記複数のチップのうちの少なくとも一部のチップは、互いに積層される、
    　請求項１に記載のシミュレーション方法。     At least some of the chips among the plurality of chips are stacked on one another.
    The simulation method according to claim 1 .
  13. 　前記複数のチップのうちの少なくとも一部のチップは、１つの基板又はパッケージ上に直接設けられる、
    　請求項１に記載のシミュレーション方法。     At least some of the chips among the plurality of chips are provided directly on one substrate or package.
    The simulation method according to claim 1 .
  14. 　前記能動素子は、半導体で構成される電流制御素子を含み、
    　前記電流制御素子は、
    　　電界効果トランジスタ、
    　　バイポーラトランジスタ、
    　　ＰＮ接合ダイオード、
    　及び
    　　サイリスタ
    　の少なくとも１つを含む、
    　請求項１に記載のシミュレーション方法。     the active element includes a current control element made of a semiconductor;
    The current control element is
    Field effect transistors,
    Bipolar transistors,
    PN junction diode,
    and a thyristor;
    The simulation method according to claim 1 .
  15. 　前記能動素子は、ＭＯＳＦＥＴを含む、
    　請求項１に記載のシミュレーション方法。     The active element includes a MOSFET.
    The simulation method according to claim 1 .
  16. 　前記熱分布をシミュレーションすることは、熱分布の経時変化のシミュレーションを含み、
    　前記応力分布をシミュレーションすることは、応力分布の経時変化のシミュレーションを含む、
    　請求項１に記載のシミュレーション方法。     simulating the heat distribution includes simulating a change in the heat distribution over time;
    The simulating of the stress distribution includes simulating a change in the stress distribution over time.
    The simulation method according to claim 1 .
  17. 　集約配置された複数のチップの動作時における消費電力を加味し、前記複数のチップそれぞれのチップ内熱分布をシミュレーションし、
    　前記熱分布のシミュレーション結果に基づいて、前記複数のチップそれぞれのチップ内応力分布をシミュレーションし、
    　前記応力分布のシミュレーション結果を、前記複数のチップそれぞれの回路シミュレーションに反映させる、
    　処理部を備える、
    　情報処理装置。     Taking into account the power consumption during operation of the multiple chips arranged in a concentrated manner, a simulation is performed for a heat distribution within each of the multiple chips;
    simulating a stress distribution within each of the plurality of chips based on a result of the simulation of the heat distribution;
    reflecting a result of the simulation of the stress distribution in a circuit simulation of each of the plurality of chips;
    A processing unit is provided.
    Information processing device.
  18. 　コンピュータに、
    　集約配置された複数のチップの動作時における消費電力を加味し、前記複数のチップそれぞれのチップ内熱分布をシミュレーションし、
    　前記熱分布のシミュレーション結果に基づいて、前記複数のチップそれぞれのチップ内応力分布をシミュレーションし、
    　前記応力分布のシミュレーション結果を、前記複数のチップそれぞれの回路シミュレーションに反映させる、
    　処理を実行させる、
    　情報処理プログラム。     On the computer,
    Taking into account the power consumption during operation of the multiple chips arranged in a concentrated manner, a simulation is performed for a heat distribution within each of the multiple chips;
    simulating a stress distribution within each of the plurality of chips based on a result of the simulation of the heat distribution;
    reflecting a result of the simulation of the stress distribution in a circuit simulation of each of the plurality of chips;
    Execute the process,
    Information processing program.
PCT/JP2023/036944 2022-11-04 2023-10-12 Simulation method, information processing device, and information processing program WO2024095727A1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080104553A1 (en) * 2006-10-16 2008-05-01 Mostafa Rassaian Method and apparatus for integrated hierarchical electronics analysis
US20080127005A1 (en) * 2006-09-07 2008-05-29 Synopsys, Inc. Method of Correlating Silicon Stress to Device Instance Parameters for Circuit Simulation
JP2009087169A (en) * 2007-10-01 2009-04-23 Nec Electronics Corp Circuit simulation method, circuit simulation device, and program
US20160048622A1 (en) * 2014-08-18 2016-02-18 Jongwook JEON Simulation system estimating self-heating characteristic of circuit and design method thereof
CN107391836A (en) * 2017-07-18 2017-11-24 西安电子科技大学 Circuit sequence optimization method based on silicon hole thermal stress
CN110245414A (en) * 2019-06-11 2019-09-17 南方电网科学研究院有限责任公司 Crimping type IGBT module multi-physical field coupling simulation method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080127005A1 (en) * 2006-09-07 2008-05-29 Synopsys, Inc. Method of Correlating Silicon Stress to Device Instance Parameters for Circuit Simulation
US20080104553A1 (en) * 2006-10-16 2008-05-01 Mostafa Rassaian Method and apparatus for integrated hierarchical electronics analysis
JP2009087169A (en) * 2007-10-01 2009-04-23 Nec Electronics Corp Circuit simulation method, circuit simulation device, and program
US20160048622A1 (en) * 2014-08-18 2016-02-18 Jongwook JEON Simulation system estimating self-heating characteristic of circuit and design method thereof
CN107391836A (en) * 2017-07-18 2017-11-24 西安电子科技大学 Circuit sequence optimization method based on silicon hole thermal stress
CN110245414A (en) * 2019-06-11 2019-09-17 南方电网科学研究院有限责任公司 Crimping type IGBT module multi-physical field coupling simulation method

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