WO2024089892A1 - Optical circuit and method for producing optical circuit - Google Patents

Optical circuit and method for producing optical circuit Download PDF

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Publication number
WO2024089892A1
WO2024089892A1 PCT/JP2022/040490 JP2022040490W WO2024089892A1 WO 2024089892 A1 WO2024089892 A1 WO 2024089892A1 JP 2022040490 W JP2022040490 W JP 2022040490W WO 2024089892 A1 WO2024089892 A1 WO 2024089892A1
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Prior art keywords
waveguide
optical circuit
light
chip
face
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PCT/JP2022/040490
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French (fr)
Japanese (ja)
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裕士 藤原
里美 片寄
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日本電信電話株式会社
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Priority to PCT/JP2022/040490 priority Critical patent/WO2024089892A1/en
Publication of WO2024089892A1 publication Critical patent/WO2024089892A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method

Definitions

  • the present invention relates to optical circuits, and more specifically to the end structure of optical circuits and the manufacturing method thereof.
  • PLCs silica-based planar lightwave circuits
  • optical waveguides are formed on flat substrates such as silicon wafers by patterning using photolithography and reactive ion etching.
  • Optical waveguides are formed by first creating a core and then surrounding it with cladding, which has a lower refractive index than the core.
  • PLCs are characterized by their high transmittance, and by combining multiple basic optical circuits such as directional couplers and Mach-Zehnder interferometers, low-loss optical functional circuits can be realized.
  • PLCs have high transparency even in the visible light band and have small propagation losses, making it possible to mass-produce low-loss, highly functional optical circuits.
  • Non-Patent Document 1 An example of the application of PLC in visible light is a circuit element that combines the three primary colors of visible light (R, G, B) for use in small projectors for eyewear displays and head-up displays. Quartz-based PLCs are also increasingly being used as optical circuits for ultra-small analyzers for the bio-life sciences (Non-Patent Document 1).
  • PLCs with zirconia (ZrO 2 ) added to the core PLCs with non-doped SiO 2 as the core
  • ZrO 2 zirconia
  • non-doped core PLCs have attracted attention.
  • Non-doped core PLCs are expected to have high resistance to visible light, but there are still issues to be addressed.
  • a waveguide is composed of a core and a cladding with a lower refractive index than the core.
  • boron-doped SiO2 or fluorine-doped SiO2 with a lower refractive index is used for the cladding.
  • These glass materials are known to be hygroscopic, and combine with water vapor in the atmosphere, causing the refractive index of the cladding to change over time. Therefore, in order to put non-doped core PLCs into practical use, it is expected that the PLC will be covered with a gas barrier film to prevent it from combining with water vapor.
  • the gas barrier film is formed on the top surface of the wafer before it is chipped, so the chip end faces cannot be protected by the gas barrier film. Because the chip end faces are exposed, there is a problem in that the refractive index changes over time, causing changes in the shape of the emitted light. Furthermore, in order to remove stray light emitted from the chip, it is necessary to separately mount light-shielding components such as absorbers and apertures, which also increases mounting costs (Patent Document 2).
  • the present invention has been developed in consideration of these problems, and provides an end face structure for an optical circuit that prevents deterioration over time in the quality of emitted light in a PLC that handles visible light.
  • One embodiment of the present invention is an optical circuit formed on a substrate, the optical circuit comprising a clad layer on the substrate, a waveguide composed of a core formed in the clad layer, a light-shielding film covering the end face of the chip including the cross section of the core of the waveguide and having an opening that exposes the area including the cross section of the core, and a gas barrier film covering the top face and all end faces of the chip.
  • Another embodiment of the present invention is a method for manufacturing an optical circuit, comprising the steps of: creating a groove on a wafer that will become an end face of the optical circuit in which a waveguide is formed; creating a self-forming waveguide on an extension of the waveguide in the groove; forming a light-shielding film around the self-forming waveguide and on the wafer; removing the self-forming waveguide to form an opening including a core cross section of the waveguide on the end face of the optical circuit; forming a gas barrier film on the wafer; and cutting the groove to produce the optical circuit in chip form.
  • the optical circuit disclosed herein can prevent deterioration of the quality of the light emitted from the PLC over time and can also eliminate stray light.
  • FIG. 1A and 1B are a perspective view and a cross-sectional view of the vicinity of a chip end portion of an optical circuit according to a first embodiment.
  • 1A to 1C are diagrams illustrating a procedure for fabricating an end face structure of an optical circuit according to the present disclosure.
  • FIG. 1 is a diagram for explaining the positions and functions of chips and grooves in a wafer state.
  • 11 is a diagram showing the configuration of an optical circuit chip using a silica-based PLC according to a second embodiment.
  • FIG. FIG. 13 is a diagram showing an optical circuit chip using a silica-based PLC according to a modified example of the second embodiment.
  • the optical circuit disclosed herein has an opening in the light-shielding film at the end face of the waveguide of the optical circuit, which opens up an area including the core cross section. It further includes a gas barrier film that covers the top and end faces of the chip of the optical circuit.
  • the gas barrier film that covers the end faces as well as the top face of the chip can prevent the shape of the emitted light from deteriorating over time due to moisture absorption.
  • the light-shielding film can remove stray light from inside the chip. It presents a novel structure of the chip end face in an optical circuit including a PLC.
  • the present invention also has an aspect of a method for manufacturing an optical circuit. Below, an embodiment of the optical circuit of the present invention will be described in detail with reference to the drawings.
  • FIG. 1 shows a perspective view and a cross-sectional view of the vicinity of the chip end of the optical circuit of the first embodiment.
  • FIG. 1(a) is a perspective view of the end face of the optical circuit chip 50, in which the core cross-section of the input end or output end of the waveguide appears on the chip end face. In order to show the structure in the vicinity of the core cross-section, the front and back faces perpendicular to the chip end face including the core cross-section are shown cut.
  • FIG. 1(b) is a cross-sectional view cut along a plane that includes the Ib-Ib line and vertically cuts the core 3 of the waveguide. Both are schematic views, and unlike the actual size relationship of each part, the size of the core 3 is drawn significantly larger. It should also be noted that the actual cladding layer 2 is much thinner than the support substrate 1.
  • the optical circuit 50 in FIG. 1 is a quartz-based PLC with a typical embedded waveguide constructed on a support substrate 1.
  • the core 3 is surrounded by a cladding layer 2, and the end faces and top face of the chip are covered with a light-shielding film 4, except for a circular region 6 at the center of the core cross section.
  • a gas barrier film 5 is formed to cover the entire surface of the light-shielding film 4.
  • the circular region 6 serves as an opening for the light entering the core or the light exiting the core. At the same time, it acts to prevent stray light from within the chip from mixing with and interfering with the exiting light. Since the gas barrier film 5 covers all ends of the chip, even at the end faces of the PLC, there is no change in the refractive index of the cladding over time due to moisture absorption by the cladding.
  • the optical circuit of the present disclosure can therefore be implemented as an optical circuit 50 formed on a substrate 1, comprising a cladding layer 2 on the substrate, a waveguide composed of a core 3 formed within the cladding layer, a light-shielding film 4 covering the end face of the chip including the core cross-section of the waveguide and having an opening 6 that exposes the area including the core cross-section, and a gas barrier film 5 covering the top face and all end faces of the chip.
  • a non-doped core PLC of a general embedded type waveguide in a PLC is composed of the following procedure. First, an undercladding layer made of fluorine-doped SiO 2 glass or boron-doped SiO 2 glass with a thickness of 20 ⁇ m and a core layer made of non-doped SiO 2 glass with a thickness of 2.5 ⁇ m are formed on a Si substrate in this order. As an example, the refractive index difference ⁇ between the core and the cladding is set to 1.1%.
  • the core layer is processed by general photolithography and dry etching techniques to form the core 3 of the waveguide.
  • the core width is set to approximately 1.7 ⁇ m.
  • an overcladding layer made of fluorine-doped SiO 2 glass or boron-doped SiO 2 glass like the undercladding layer is formed on the core 3 to form a buried type waveguide.
  • the above is a procedure for manufacturing a general buried type waveguide.
  • a procedure for manufacturing the chip end surface structure of the optical circuit 50 of the present disclosure shown in FIG. 1 will be described.
  • FIG. 2 is a diagram explaining the procedure for fabricating the end face structure of the optical circuit of the present disclosure. All of (a) to (f) in FIG. 2 are cross-sectional views taken along a plane that passes through the center of the core of the fabricated embedded waveguide and is perpendicular to the substrate surface. Steps (a) 1 to (f) 6 will be explained in this order with reference to FIG. 3 described later.
  • a groove is formed in a wafer containing a quartz-based PLC, which will form the chip end face where the cross section of the waveguide appears after cutting into a chip shape.
  • the diagram of step 1 shows a state in which a groove 10 is formed perpendicular to the core 3. Since this groove 10 becomes the chip end face, when connecting an optical fiber to a PLC chip, a groove with a depth of more than half the diameter of the optical fiber is dug. The width of the groove is also set to be greater than the thickness of the blade used for dicing. This prevents the blade from coming into contact with the chip end face when cutting the chip from the wafer.
  • the quartz-based glass can be dug by conventional dry etching technology, just like when forming the core.
  • the Si substrate 1, which is the supporting substrate, can be dug by the Bosch process or the like.
  • the PLC is divided into a main circuit 50 and a dummy circuit 51.
  • the main circuit 50 is the part that will become the optical circuit after being cut into chips, and emits light in the direction of the arrow 21.
  • the waveguide core 52 included in the dummy circuit 51 is integral with the core 3 of the main circuit 50 and is a part of the core 3 before the grooves 10 are formed.
  • the entire process in FIG. 2 can be better understood by referring to the structure of the grooves 10 in the wafer state.
  • Figure 3 is a diagram explaining the position and function of the PLC chip and the grooves in the wafer state.
  • Figure 3 (a) shows a wafer 60 in a state in which four grooves 10a to 10d have been formed by process 1 before the optical circuits are cut out.
  • the surface of the wafer 60 contains a total of 12 main circuits 50, indicated by dotted lines, arranged in two rows of six.
  • grooves 10a and 10b By forming grooves 10a and 10b, the six optical circuits in the left row are partitioned, and the area of the main circuits 50 and dummy circuits 51 indicated by dotted lines is formed.
  • Figure 3 shows an example in which the main circuits 50 after being cut out into chips have the input end face or output end face of the waveguide on the two left and right sides.
  • the bottom end of the wafer has a terminal 53 for inputting visible light to harden the resin in order to create a self-forming waveguide, which will be described later.
  • the waveguide branches into four from the terminal 53, and each of these branches further into five to form the dummy waveguides 52.
  • the waveguide core 3 of each main circuit and the dummy waveguide core 52 of the dummy circuit are formed coaxially and face each other.
  • the embedded waveguide, which was originally connected as a single piece, is cut by the groove, so that the dummy waveguide 52 is formed coaxially with the input/output waveguide 3 of the main circuit.
  • the branching parts of the dummy waveguide are designed so that the light is branched evenly.
  • the core width of the dummy waveguide is 1.7 ⁇ m.
  • a self-forming waveguide 11 is formed between the dummy waveguide 52 of the dummy circuit 51 and the waveguide 5 of the main circuit. More specifically, a photocurable resin 7 is first applied to the entire wafer by spin coating. Next, visible light is input from the dummy waveguide 52 side to harden the resin 7. That is, as shown in FIG. 3(b), visible light 23 is input from the input waveguide terminal 53 of the wafer and branched, and then visible light 22 propagates through the resin 7 in the groove from the left and right of each of all optical circuits toward the main circuit.
  • a self-forming waveguide 11 is formed between the dummy waveguide 52 and the waveguide 5. In this embodiment, a visible light source with a wavelength of 405 nm and a power of 30 mW to the input waveguide terminal 53 is prepared.
  • the intensity of the light input into the dummy waveguide 52 is monitored by detecting the branched monitor light 24 with a photodiode 55.
  • the input visible light 23 propagates from the dummy waveguide 52 to the chip end face of each main circuit 50, and is irradiated onto the photocurable resin 7 filled in the groove 10.
  • This forms a self-forming waveguide 11 along the optical path from the end face of the dummy waveguide 52 to the input/output end of the main circuit.
  • a structure is formed in which the cores 3 and 52 of the two waveguides are connected by a self-forming waveguide. After that, the photocurable resin 7 other than the self-forming waveguide 11 is removed. Under the manufacturing conditions for the optical circuit of this embodiment, a self-forming waveguide with a diameter of about 5 ⁇ m was formed.
  • step 3 in FIG. 2(c) electroless plating was used to form a light-shielding film 4 over the entire wafer.
  • Plating is more suitable for forming this light-shielding film 4 than deposition methods such as sputtering and vapor deposition.
  • a thin gold film with a thickness of about 500 nm was fabricated as the light-shielding film 4.
  • the self-formed waveguide 11 is removed. After cleaning with a general organic solvent, ashing is performed using oxygen plasma. The columnar self-formed waveguide 11 is removed by the ashing step, and the waveguide core 3 of this circuit, which was covered by the self-formed waveguide 11, is exposed. Since the self-formed waveguide 11 is made of an organic material, only the self-formed waveguide 11 is removed by ashing. As a result, a light-shielding film 4 is formed on the chip end face of this circuit 50, except for the circular area 6 around the core 3. By steps 1 to 4, a light-shielding film 4 with an opening can be formed all at once on the chip end faces of all of the circuits on the wafer.
  • a gas barrier film 5 is further deposited on the light-shielding film 4.
  • a SiN film with a thickness of about 100 nm is deposited using the plasma CVD (Chemical Vapor Deposition) method.
  • step 6 of FIG. 2(f) dicing is performed to separate each circuit on the wafer, obtaining chip-shaped optical circuits.
  • a blade that is sufficiently thinner than the width of the groove 10 is used to protect the chip end faces.
  • the present invention can therefore also be implemented as a method for manufacturing an optical circuit, comprising the steps of: creating a groove 10 on a wafer 60 that will become an end face of the optical circuit in which a waveguide is formed; creating a self-forming waveguide 11 on an extension of the waveguide in the groove; forming a light-shielding film 4 around the self-forming waveguide and on the wafer; removing the self-forming waveguide to form an opening 6 including a core cross section of the waveguide on the end face of the optical circuit; forming a gas barrier film 5 on the wafer; and cutting the groove to create the chip-shaped optical circuit 50.
  • the end face structure of the optical circuit 50 of the present disclosure which is fabricated by the procedure of FIG. 1 and FIG. 2, allows a gas barrier film to be formed all at once on the chip end face in addition to the upper face of the chip. Furthermore, the opening 6 can be formed all at once on the chip end face on a wafer basis.
  • the configuration of the optical circuit 50 can simultaneously suppress the deterioration of the shape of the emitted light caused by the change in the refractive index of the cladding due to moisture absorption, and the inclusion of stray light in the emitted light.
  • the diameter of the opening 6 is determined by the diameter of the self-forming waveguide. Therefore, the inner diameter of the opening 6 can be controlled to some extent by the amount of light irradiation that grows the self-forming waveguide.
  • the diameter of the self-forming waveguide is set to about 5 ⁇ m, but if the diameter is about 10 ⁇ m or less, the self-forming waveguide can be formed by the series of steps shown in FIG. 2.
  • the diameter of the opening 6 can also be controlled by the core diameter of the dummy waveguide 52. In order to obtain the effect of removing stray light, the diameter (inner diameter) of the opening 6 is appropriately about twice the mode field diameter of the core.
  • the material of the light-shielding film is not limited to gold.
  • the material of the light-shielding film may be any material that can be handled by a method capable of forming a film that follows the unevenness of the surface, such as a plating method.
  • the gas barrier film 5 may be made of alumina, quartz glass, niobium oxide, cerium oxide, or other resin materials in addition to SiN.
  • the grooves 10a to 10d are formed along the two left and right sides of the two rows of the region 50 of the main circuit. However, the grooves may be dug along the four sides, including the top and bottom sides of the chip of the main circuit 50. When forming grooves on the four sides of the main circuit, it is recommended to leave about 100 ⁇ m of the bottom side of the support substrate 1 uncut. In the series of steps of the procedure described in FIG. 2, the groove 10 is formed leaving the bottom side of the substrate, but a groove that completely separates it to the bottom side of the support substrate 1 may be formed. Even if grooves are formed on the two left and right sides of the region of the main circuit 50 as shown in FIG. 3, the main circuit will not fall out of the wafer 60, and steps 1 to 6 can be performed collectively for each wafer.
  • the light-shielding film 4 is formed on the entire top surface of the chip and on the end surfaces of the chip except for the openings.
  • the effect of removing stray light is achieved by forming the light-shielding film 4 together with the openings 6 at least on the chip end surfaces where the cross-section of the waveguide core is present.
  • the light-shielding film 4 is formed on the top surface of the chip and all of the chip end surfaces.
  • FIG. 2 an example is shown in which the light input end or output end is located on two opposing sides of the rectangular chip shape, and the grooves 10 are formed on both sides of the circuit 50.
  • grooves may also be created on the sides corresponding to the chip end surfaces where there is no cross-section of the waveguide core of the optical circuit, and the light-shielding film 4 and gas barrier film 5 may be formed.
  • the center position of the opening 6 on the end face of the chip coincides with the center position of the core cross section in terms of preventing the output of stray light.
  • the cross section of the core is exemplified by a rectangular embedded waveguide, but a rib waveguide or a slot waveguide may also be used.
  • Fig. 4 is a diagram showing the configuration of an optical circuit chip using a silica-based PLC according to embodiment 2.
  • the optical circuit 100 in Fig. 4 is an RGB multiplexer, also called an RGB combiner or RGB coupler.
  • Fig. 4(a) is a top view of the chip, (b) is a side view looking at end face B, (c) is a side view looking at end face C, and (d) is a cross-sectional view of a surface passing through line IVd-IVd near end face C and perpendicular to the substrate surface.
  • the R, G, and B input lights to the R input waveguide 101, G input waveguide 102, and B input waveguide 103 are combined by a combiner 107 composed of an embedded waveguide, and output from the opposite end of the waveguide 102.
  • the three input waveguides are equipped with monitor waveguides 104, 105, and 106, which are also composed of embedded waveguides.
  • monitor waveguides 104, 105, and 106 which are also composed of embedded waveguides.
  • FIG. 4 at end face B and end face C, there is a cross section of the waveguide core in an opening where no light-shielding film is formed.
  • a gas barrier film is formed so as to cover the upper surface and end face of the chip.
  • the cross-sectional configuration of (d) of FIG. 4 is exactly the same as that of (b) of FIG. 1.
  • the core film thickness of each waveguide is 2.5 ⁇ m, the core width is 1.7 ⁇ m, and the relative refractive index difference ⁇ between the core and the clad is 1.1%.
  • the multiplexer 107 is designed to multiplex three wavelengths corresponding to visible light red (R: wavelength 640 nm), green (G: 520 nm), and blue (B: 445 nm) into one waveguide.
  • the input power of visible light input to the three waveguides 101, 102, and 103 is monitored by the monitor waveguides 104, 105, and 106 in FIG. 4.
  • the structure of the opening at the chip end of the optical circuit disclosed herein can significantly suppress stray light output from the output end of the monitor waveguide.
  • the inclusion of stray light in the multiplexed output light can also be significantly suppressed.
  • the RGB multiplexer 100 shown in FIG. 4 can be further modified to further improve stray light in the monitor light.
  • FIG. 5 is a diagram showing the configuration of an optical circuit chip using a silica-based PLC, which is a modified version of the second embodiment.
  • the optical circuit 200 in FIG. 5 is a modified version of the RGB multiplexer 100 in the second embodiment, and differs from the RGB multiplexer 100 only in the configuration of the three monitor waveguides.
  • FIG. 5 (a) is a top view of the chip, (b) is a side view looking at end face B, (c) is a side view looking at end face C, (d) is a side view looking at end face D, and (e) is a side view looking at end face E.
  • the R, G, and B input lights to the R input waveguide 201, G input waveguide 202, and B input waveguide 203 are combined by a combiner 207 made of an embedded waveguide, and output from the opposite end of the waveguide 202.
  • the three input waveguides are equipped with monitor waveguides 204, 205, and 206, which are also made of embedded waveguides.
  • the monitor waveguide has output ends not at end face C where the combined light is output, but at end faces D and E on the chip side relative to end face C.
  • the output ends of the monitor waveguides are provided on the chip end faces perpendicular to the light traveling direction of the combiner, which further suppresses stray light to the monitor light and the combined light.
  • the structure of the openings around the cross section of the core shown in Figure 1 can significantly suppress stray light output from the output ends of the monitor waveguides and the output ends of the combined light.
  • This invention can be used in optical instruments.

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Abstract

An optical circuit according to the present disclosure comprises, in the end face of a waveguide of the optical circuit, an opening (6) of a light-shielding film (4) in a region including the cross-section of a core (3). Additionally, the optical circuit comprises a gas barrier film (5) that covers the top face and end face of a chip (50) of the optical circuit. As a result of the gas barrier film (5) covering the end face of the chip (50), it is possible to prevent the shape of emitted light from deteriorating due to moisture absorption. The light-shielding film (4) is capable of removing stray light originating from inside the chip (50). The present invention presents a novel structure for the chip (50) end face in optical circuits such as PLCs. Also disclosed is a novel method for producing an optical circuit utilizing a self-written waveguide.

Description

光回路および光回路の製造方法Optical circuit and method for manufacturing the optical circuit
　本発明は光回路に関し、具体的には光回路の端部構造およびその製造方法に関する。 The present invention relates to optical circuits, and more specifically to the end structure of optical circuits and the manufacturing method thereof.
　主として光通信の分野で発展してきた石英系平面光波回路（Planar Lightwave Circuit：ＰＬＣ）を、可視光に適用する技術が注目されている。ＰＬＣは、Ｓｉウェハなどの平面上の基板に、フォトリソグラフィなどによるパターニング、反応性イオンエッチング加工により、光導波路を形成する。光導波路は、まずコアを作製し、コアよりも屈折率の低いクラッドで周りを埋め込むことで形成される。ＰＬＣは、光導波路の高い透過率が特徴であり、方向性結合器、マッハ・ツェンダ干渉計など複数の基本的な光回路を組み合わせることで、低損失な光機能回路を実現できる。ＰＬＣは、可視光帯においても高い透明性を持ち、伝搬損失が小さいことから、低損失で高機能な光回路を量産することが可能である。 The technology of applying silica-based planar lightwave circuits (PLCs), which have been developed mainly in the field of optical communications, to visible light is attracting attention. In PLCs, optical waveguides are formed on flat substrates such as silicon wafers by patterning using photolithography and reactive ion etching. Optical waveguides are formed by first creating a core and then surrounding it with cladding, which has a lower refractive index than the core. PLCs are characterized by their high transmittance, and by combining multiple basic optical circuits such as directional couplers and Mach-Zehnder interferometers, low-loss optical functional circuits can be realized. PLCs have high transparency even in the visible light band and have small propagation losses, making it possible to mass-produce low-loss, highly functional optical circuits.
　可視光におけるＰＬＣの応用例は、アイウェア型ディスプレイやヘッドアップディスプレイ向けの小型プロジェクタに用いる可視光３原色(Ｒ、Ｇ、Ｂ)を合波する回路素子である。またバイオ・ライフサイエンス向け超小型分析器向けの光回路としても、石英系ＰＬＣの利用が進んでいる（非特許文献１）。 An example of the application of PLC in visible light is a circuit element that combines the three primary colors of visible light (R, G, B) for use in small projectors for eyewear displays and head-up displays. Quartz-based PLCs are also increasingly being used as optical circuits for ultra-small analyzers for the bio-life sciences (Non-Patent Document 1).
　上述のような可視光を用いる光学機器向けの光回路を石英系ＰＬＣで構成する際には、可視光によって生じるガラス材料の劣化を抑制する必要がある。従来の石英系ＰＬＣでは、導波路を構成するコアには、屈折率を高めるためのドーパントとしてゲルマニア（ＧｅＯ2）が一般的に使用されていた。しかしながら、ゲルマニアを添加したコアは、特に青色に近い波長（４００～４９０ｎｍ）の光が入力されると屈折率が変動することが知られている（非特許文献２）。近年、可視光向け石英系ＰＬＣの需要の高まりに応じて、より可視光耐性の高い導波路構造がいくつか提案されている。例えば、コアにジルコニア（ＺｒＯ2）を添加したものや（特許文献１）、ノンドープＳｉＯ2をコアに用いたもの、すなわちノンドープコアＰＬＣが注目されている。 When constructing an optical circuit for optical devices using visible light as described above using a quartz-based PLC, it is necessary to suppress the deterioration of glass materials caused by visible light. In conventional quartz-based PLCs, germania (GeO 2 ) was generally used as a dopant to increase the refractive index in the core that constitutes the waveguide. However, it is known that the refractive index of a core doped with germania fluctuates when light with a wavelength close to blue (400 to 490 nm) is input (Non-Patent Document 2). In recent years, in response to the increasing demand for quartz-based PLCs for visible light, several waveguide structures with higher visible light resistance have been proposed. For example, PLCs with zirconia (ZrO 2 ) added to the core (Patent Document 1) and PLCs using non-doped SiO 2 as the core, i.e., non-doped core PLCs, have attracted attention.
特開２０１７－１８７７１９号公報JP 2017-187719 A 特開２０２０－２０４６４２号公報JP 2020-204642 A
　ノンドープコアＰＬＣは可視光に対する高い耐性が期待されるが、未だ課題が残されている。一般的に導波路は、コアおよびコアより低い屈折率を持つクラッドで構成される。ノンドープコアＰＬＣの場合、クラッドにはより低い屈折率を持つホウ素ドープＳｉＯ2やフッ素ドープＳｉＯ2が用いられる。これらのガラス材料は吸湿性を持つことが知られており、雰囲気中の水蒸気と結合して、クラッドの屈折率が経時的に変化してしまう。よってノンドープコアＰＬＣを実用するためには、水蒸気との結合を防ぐため、ＰＬＣをガスバリア膜で覆うことが想定されている。 Non-doped core PLCs are expected to have high resistance to visible light, but there are still issues to be addressed. Generally, a waveguide is composed of a core and a cladding with a lower refractive index than the core. In the case of non-doped core PLCs, boron-doped SiO2 or fluorine-doped SiO2 with a lower refractive index is used for the cladding. These glass materials are known to be hygroscopic, and combine with water vapor in the atmosphere, causing the refractive index of the cladding to change over time. Therefore, in order to put non-doped core PLCs into practical use, it is expected that the PLC will be covered with a gas barrier film to prevent it from combining with water vapor.
　しかしながら従来技術のＰＬＣのウェハプロセスにおいては、ウェハ上面にガスバリア膜を成膜したのちにチップ化を行うため、チップ端面をガスバリア膜では保護できていなかった。チップ端面が露出しているため、屈折率の経時的変化が生じて、出射光の形状が変化する問題があった。さらにチップから出射する迷光を除去するために、吸収体やアパーチャなどの遮光部品などを別途実装する必要があり、実装コスト増大も招いていた（特許文献２）。 However, in conventional PLC wafer processes, the gas barrier film is formed on the top surface of the wafer before it is chipped, so the chip end faces cannot be protected by the gas barrier film. Because the chip end faces are exposed, there is a problem in that the refractive index changes over time, causing changes in the shape of the emitted light. Furthermore, in order to remove stray light emitted from the chip, it is necessary to separately mount light-shielding components such as absorbers and apertures, which also increases mounting costs (Patent Document 2).
　本発明はこのような問題に鑑みなされたものであって、可視光を扱うＰＬＣにおける出射光の経時的な品質劣化を防ぐ光回路の端面構造を提供する。 The present invention has been developed in consideration of these problems, and provides an end face structure for an optical circuit that prevents deterioration over time in the quality of emitted light in a PLC that handles visible light.
　本発明の１つの実施態様は、基板に形成された光回路であって、前記基板の上のクラッド層、および、前記クラッド層内に形成されたコアで構成された導波路と、前記導波路のコア断面を含むチップの端面を覆い、前記コア断面を含む領域を開けた開口部を有する、遮光膜と、前記チップの上面およびすべての端面を覆うガスバリア膜とを備えた光回路である。 One embodiment of the present invention is an optical circuit formed on a substrate, the optical circuit comprising a clad layer on the substrate, a waveguide composed of a core formed in the clad layer, a light-shielding film covering the end face of the chip including the cross section of the core of the waveguide and having an opening that exposes the area including the cross section of the core, and a gas barrier film covering the top face and all end faces of the chip.
　本発明のもう１つの実施態様は、光回路の製造方法であって、ウェハ上に、導波路が形成された光回路の端面となる溝を作成するステップと、前記溝内の前記導波路の延長上に、自己形成導波路を作製するステップと、前記自己形成導波路の周囲および前記ウェハ上に、遮光膜を形成するステップと、前記自己形成導波路を除去して、光回路の前記端面の上に、前記導波路のコア断面を含む開口部を形成するステップと、前記ウェハ上に、ガスバリア膜を形成するステップと、前記溝を切断して、チップ状の前記光回路を作製するステップとを備える製造方法である。 Another embodiment of the present invention is a method for manufacturing an optical circuit, comprising the steps of: creating a groove on a wafer that will become an end face of the optical circuit in which a waveguide is formed; creating a self-forming waveguide on an extension of the waveguide in the groove; forming a light-shielding film around the self-forming waveguide and on the wafer; removing the self-forming waveguide to form an opening including a core cross section of the waveguide on the end face of the optical circuit; forming a gas barrier film on the wafer; and cutting the groove to produce the optical circuit in chip form.
　本開示の光回路により、ＰＬＣからの出射光の経時的な品質劣化を防ぐとともに、迷光の除去をすることもできる。 The optical circuit disclosed herein can prevent deterioration of the quality of the light emitted from the PLC over time and can also eliminate stray light.
実施形態１の光回路のチップ端部付近の斜視図および断面図を示す。1A and 1B are a perspective view and a cross-sectional view of the vicinity of a chip end portion of an optical circuit according to a first embodiment. 本開示の光回路の端面構造を作製する手順を説明する図である。1A to 1C are diagrams illustrating a procedure for fabricating an end face structure of an optical circuit according to the present disclosure. ウェハ状態におけるチップと溝の位置および機能を説明する図である。FIG. 1 is a diagram for explaining the positions and functions of chips and grooves in a wafer state. 実施形態２の石英系ＰＬＣによる光回路チップの構成を示す図である。11 is a diagram showing the configuration of an optical circuit chip using a silica-based PLC according to a second embodiment. FIG. 実施形態２の変形例の石英系ＰＬＣによる光回路チップを示す図である。FIG. 13 is a diagram showing an optical circuit chip using a silica-based PLC according to a modified example of the second embodiment.
　本開示の光回路は、光回路の導波路の端面において、コア断面を含む領域を開けた、遮光膜の開口部を持つ。さらに、光回路のチップの上面および端面を覆う、ガスバリア膜を備える。チップの上面に加えて端面も覆うガスバリア膜によって、吸湿に起因して、出射する光の形状が経時的に劣化するのを防ぐことができる。遮光膜は、チップ内部からの迷光を除去可能である。ＰＬＣを含む光回路におけるチップ端面の新規な構造を提示する。本発明は、光回路の製造方法の側面も持っている。以下、図面を参照しながら、本発明の光回路の実施形態について詳細に説明する。 The optical circuit disclosed herein has an opening in the light-shielding film at the end face of the waveguide of the optical circuit, which opens up an area including the core cross section. It further includes a gas barrier film that covers the top and end faces of the chip of the optical circuit. The gas barrier film that covers the end faces as well as the top face of the chip can prevent the shape of the emitted light from deteriorating over time due to moisture absorption. The light-shielding film can remove stray light from inside the chip. It presents a novel structure of the chip end face in an optical circuit including a PLC. The present invention also has an aspect of a method for manufacturing an optical circuit. Below, an embodiment of the optical circuit of the present invention will be described in detail with reference to the drawings.
　[実施形態１]
　図１は、実施形態１の光回路のチップ端部付近の斜視図および断面図を示す。図１の（ａ）は光回路のチップ５０の端面の斜視図であって、導波路の入力端または出力端のコア断面がチップ端面上に現れている。コア断面の近傍の構造を示すため、コア断面を含むチップ端面に垂直な、手前と奥の面は切断して示されている。図１の（ｂ）は、Ｉｂ－Ｉｂ線を含み導波路のコア３を縦断する面で切った断面図である。いずれも模式図であって、各部の実際のサイズ関係とは異なり、コア３のサイズは著しく大きく描かれている。また実際のクラッド層２は支持基板１よりも遥かに薄いことに留意されたい。 [Embodiment 1]
FIG. 1 shows a perspective view and a cross-sectional view of the vicinity of the chip end of the optical circuit of the first embodiment. FIG. 1(a) is a perspective view of the end face of the optical circuit chip 50, in which the core cross-section of the input end or output end of the waveguide appears on the chip end face. In order to show the structure in the vicinity of the core cross-section, the front and back faces perpendicular to the chip end face including the core cross-section are shown cut. FIG. 1(b) is a cross-sectional view cut along a plane that includes the Ib-Ib line and vertically cuts the core 3 of the waveguide. Both are schematic views, and unlike the actual size relationship of each part, the size of the core 3 is drawn significantly larger. It should also be noted that the actual cladding layer 2 is much thinner than the support substrate 1.
　図１の光回路５０は石英系ＰＬＣであって、支持基板１の上に構成された一般的な埋め込み型導波路を備える。コア３の周囲はクラッド層２によって埋め込まれており、コア断面の中心とした円形の領域６を除いて、チップの端面および上面は、遮光膜４で覆われている。さらに、遮光膜４の全面を覆うようにガスバリア膜５が形成されている。円形の領域６は、コアへの入射光またはコアからの出射光に対して開口部となる。同時に、チップ内からの迷光に対しては、迷光の出射光への混入、干渉を防ぐように働く。ＰＬＣの端面においても、ガスバリア膜５がチップのすべての端部を覆っているため、クラッドの吸湿による、クラッドの屈折率の経時的な変化は生じない。 The optical circuit 50 in FIG. 1 is a quartz-based PLC with a typical embedded waveguide constructed on a support substrate 1. The core 3 is surrounded by a cladding layer 2, and the end faces and top face of the chip are covered with a light-shielding film 4, except for a circular region 6 at the center of the core cross section. In addition, a gas barrier film 5 is formed to cover the entire surface of the light-shielding film 4. The circular region 6 serves as an opening for the light entering the core or the light exiting the core. At the same time, it acts to prevent stray light from within the chip from mixing with and interfering with the exiting light. Since the gas barrier film 5 covers all ends of the chip, even at the end faces of the PLC, there is no change in the refractive index of the cladding over time due to moisture absorption by the cladding.
　したがって本開示の光回路は、基板１に形成された光回路５０であって、前記基板の上のクラッド層２、および、前記クラッド層内に形成されたコア３で構成された導波路と、前記導波路のコア断面を含むチップの端面を覆い、前記コア断面を含む領域を開けた開口部６を有する、遮光膜４と、前記チップの上面およびすべての端面を覆うガスバリア膜５とを備えたものとして実施できる。 The optical circuit of the present disclosure can therefore be implemented as an optical circuit 50 formed on a substrate 1, comprising a cladding layer 2 on the substrate, a waveguide composed of a core 3 formed within the cladding layer, a light-shielding film 4 covering the end face of the chip including the core cross-section of the waveguide and having an opening 6 that exposes the area including the core cross-section, and a gas barrier film 5 covering the top face and all end faces of the chip.
　図１に示したチップ端面構造を有するＰＬＣの作製手順は以下の通りである。ＰＬＣにおける一般的な埋め込み型導波路のノンドープコアＰＬＣは、以下の手順で構成される。まずＳｉ基板上に、厚さ２０μｍのフッ素ドープＳｉＯ2ガラスやホウ素ドープＳｉＯ2ガラスで構成されたアンダークラッド層と、厚さ２．５μｍのノンドープＳｉＯ2ガラスで構成されたコア層を、この順に成膜する。一例を挙げれば、コアとクラッドの間の屈折率差Δを１．１％とした。一般的なフォトリソグラフィおよびドライエッチング技術により、コア層を加工し、導波路のコア３を形成する。コア幅をおよそ１．７μｍとした。その後、アンダークラッド層と同じくフッ素ドープＳｉＯ2ガラスやホウ素ドープＳｉＯ2ガラスで構成されたオーバークラッド層をコア３の上に成膜し、埋め込み型導波路が形成される。ここまでは、一般的な埋め込み型導波路を作製する手順である。続いて、図１に示した本開示の光回路５０のチップ端面構造を作製する手順を説明する。 The manufacturing procedure of a PLC having the chip end surface structure shown in FIG. 1 is as follows. A non-doped core PLC of a general embedded type waveguide in a PLC is composed of the following procedure. First, an undercladding layer made of fluorine-doped SiO 2 glass or boron-doped SiO 2 glass with a thickness of 20 μm and a core layer made of non-doped SiO 2 glass with a thickness of 2.5 μm are formed on a Si substrate in this order. As an example, the refractive index difference Δ between the core and the cladding is set to 1.1%. The core layer is processed by general photolithography and dry etching techniques to form the core 3 of the waveguide. The core width is set to approximately 1.7 μm. Then, an overcladding layer made of fluorine-doped SiO 2 glass or boron-doped SiO 2 glass like the undercladding layer is formed on the core 3 to form a buried type waveguide. The above is a procedure for manufacturing a general buried type waveguide. Next, a procedure for manufacturing the chip end surface structure of the optical circuit 50 of the present disclosure shown in FIG. 1 will be described.
　図２は、本開示の光回路の端面構造を作製する手順を説明する図である。図２の（ａ）～（ｆ）のいずれの図も、作製された埋め込み型導波路のコアの中心を通り、基板面に垂直な面で切った断面図である。後述する図３も参照しながら、（ａ）工程１～（ｆ）工程６の順に説明する。 FIG. 2 is a diagram explaining the procedure for fabricating the end face structure of the optical circuit of the present disclosure. All of (a) to (f) in FIG. 2 are cross-sectional views taken along a plane that passes through the center of the core of the fabricated embedded waveguide and is perpendicular to the substrate surface. Steps (a) 1 to (f) 6 will be explained in this order with reference to FIG. 3 described later.
　図２の（ａ）の工程１では、石英系ＰＬＣを含むウェハに対して、チップ形状に切り出した後で、導波路の断面が現れるチップ端面を形成することになる溝が形成される。工程１の図では、コア３に垂直に溝１０が形成された状態を示している。この溝１０がチップの端面になるため、光ファイバとＰＬＣのチップを接続する場合は、光ファイバの直径の半分以上の深さの溝を掘ることとする。また溝の幅は、ダイシングに用いるブレードの厚み以上とする。これによって、チップをウェハから切り出す際にブレードがチップ端面に接触することを防ぐことができる。工程１において、石英系ガラスはコア形成時と同じように従来技術のドライエッチングで掘ることができる。支持基板であるＳｉ基板１は、ボッシュプロセスなどで掘り進めることが可能である。 In step 1 in FIG. 2(a), a groove is formed in a wafer containing a quartz-based PLC, which will form the chip end face where the cross section of the waveguide appears after cutting into a chip shape. The diagram of step 1 shows a state in which a groove 10 is formed perpendicular to the core 3. Since this groove 10 becomes the chip end face, when connecting an optical fiber to a PLC chip, a groove with a depth of more than half the diameter of the optical fiber is dug. The width of the groove is also set to be greater than the thickness of the blade used for dicing. This prevents the blade from coming into contact with the chip end face when cutting the chip from the wafer. In step 1, the quartz-based glass can be dug by conventional dry etching technology, just like when forming the core. The Si substrate 1, which is the supporting substrate, can be dug by the Bosch process or the like.
　溝１０を形成することで、ＰＬＣは本回路５０とダミー回路５１とに区画される。図２では本回路５０は、チップ状に切出した後で、光回路となる部分であって、矢印２１の方向で光が出射するものとする。一方で、ダミー回路５１に含まれる導波路のコア５２は、溝１０を形成する前は、本回路５０のコア３と一体のものでありコア３の一部である。ここで、ウェハ状態における溝１０の構造を参照することで、図２の工程全体がより良く理解できるだろう。 By forming the grooves 10, the PLC is divided into a main circuit 50 and a dummy circuit 51. In FIG. 2, the main circuit 50 is the part that will become the optical circuit after being cut into chips, and emits light in the direction of the arrow 21. Meanwhile, the waveguide core 52 included in the dummy circuit 51 is integral with the core 3 of the main circuit 50 and is a part of the core 3 before the grooves 10 are formed. Here, the entire process in FIG. 2 can be better understood by referring to the structure of the grooves 10 in the wafer state.
　図３は、ウェハ状態におけるＰＬＣチップと溝の位置および機能を説明する図である。図３の（ａ）は、光回路が切り出される前であって、工程１によって４本の溝１０ａ～１０ｄが形成された状態のウェハ６０を示している。ウェハ６０の面内には、２列に６個ずつ配置された全１２個の、点線で示した本回路５０が含まれている。溝１０ａ、１０ｂを形成することによって、左の列にある６個の光回路が区画され、点線で示した本回路５０とダミー回路５１の領域が形成される。同様に、溝１０ｃ、１ｃ０ｄを形成することによって、右の列にある６個の光回路が区画され、本回路５０とダミー回路５１の領域が形成される。図３では、チップに切出した後の本回路５０が、それぞれ、左右の２辺に導波路の入射端面または出射端面を有することになる例を示している。ウェハの下端には、後述する自己形成導波路を作製するための、樹脂を硬化させる可視光を入力する端子５３を有する。 Figure 3 is a diagram explaining the position and function of the PLC chip and the grooves in the wafer state. Figure 3 (a) shows a wafer 60 in a state in which four grooves 10a to 10d have been formed by process 1 before the optical circuits are cut out. The surface of the wafer 60 contains a total of 12 main circuits 50, indicated by dotted lines, arranged in two rows of six. By forming grooves 10a and 10b, the six optical circuits in the left row are partitioned, and the area of the main circuits 50 and dummy circuits 51 indicated by dotted lines is formed. Similarly, by forming grooves 10c and 10d, the six optical circuits in the right row are partitioned, and the area of the main circuits 50 and dummy circuits 51 is formed. Figure 3 shows an example in which the main circuits 50 after being cut out into chips have the input end face or output end face of the waveguide on the two left and right sides. The bottom end of the wafer has a terminal 53 for inputting visible light to harden the resin in order to create a self-forming waveguide, which will be described later.
　図３の（ａ）のチップ配列の場合は、端子５３から、導波路が４本に分岐し、さらに各々が５本に分岐して、ダミー導波路５２となる。各々の本回路の導波路コア３とダミー回路のダミー導波路コア５２が同軸に形成され、向かい合う状態になる。元々１本につながっていた埋め込み型導波路が溝によって切断されるため、ダミー導波路５２と、本回路の入出力導波路３と同軸に形成されることになる。ダミー導波路の分岐部分はそれぞれ光が均等に分岐されるように設計される。ダミー導波路のコア幅を、１．７μｍとした。 In the case of the chip arrangement in Figure 3(a), the waveguide branches into four from the terminal 53, and each of these branches further into five to form the dummy waveguides 52. The waveguide core 3 of each main circuit and the dummy waveguide core 52 of the dummy circuit are formed coaxially and face each other. The embedded waveguide, which was originally connected as a single piece, is cut by the groove, so that the dummy waveguide 52 is formed coaxially with the input/output waveguide 3 of the main circuit. The branching parts of the dummy waveguide are designed so that the light is branched evenly. The core width of the dummy waveguide is 1.7 μm.
　再び図２に戻ると、図２の（ｂ）の工程２では、ダミー回路５１のダミー導波路５２と本回路の導波路５の間に、自己形成導波路１１が形成される。より具体的には、まず光硬化性の樹脂７をスピンコートによりウェハ全体に塗布する。次に、ダミー導波路５２の側から樹脂７を硬化させるための可視光が入力される。すなわち図３の（ｂ）に示したように、ウェハの入力導波路端子５３から可視光２３が入力されて、分岐された後、すべての光回路の各々の左右から、可視光２２が本回路に向かって溝内の樹脂７を伝搬する。ダミー導波路５２と導波路５との間に自己形成導波路１１が形成される。本実施形態では、波長が４０５ｎｍで、入力導波路端子５３へのパワーは３０ｍＷの可視光光源を用意した。 Returning to FIG. 2, in step 2 in FIG. 2(b), a self-forming waveguide 11 is formed between the dummy waveguide 52 of the dummy circuit 51 and the waveguide 5 of the main circuit. More specifically, a photocurable resin 7 is first applied to the entire wafer by spin coating. Next, visible light is input from the dummy waveguide 52 side to harden the resin 7. That is, as shown in FIG. 3(b), visible light 23 is input from the input waveguide terminal 53 of the wafer and branched, and then visible light 22 propagates through the resin 7 in the groove from the left and right of each of all optical circuits toward the main circuit. A self-forming waveguide 11 is formed between the dummy waveguide 52 and the waveguide 5. In this embodiment, a visible light source with a wavelength of 405 nm and a power of 30 mW to the input waveguide terminal 53 is prepared.
　後述する工程３で樹脂７を硬化させる時、ダミー導波路５２中に入力される光の強度は、分岐されたモニタ光２４をフォトダイオード５５で検出することでモニタされる。入力された可視光２３は、ダミー導波路５２から各本回路５０のチップ端面まで伝搬し、溝１０の中に充填された光硬化性樹脂７に照射されることになる。これによりダミー導波路５２の端面から本回路の入出力端へ向かう光路に沿って自己形成導波路１１が形成される。２つの導波路のコア３、５２が自己形成導波路でつながれたような構造ができる。その後、自己形成導波路１１以外の光硬化性の樹脂７が取り除かれる。本実施形態の光回路における作製条件では、直径５μｍ程度の自己形成導波路が形成された。 When the resin 7 is cured in step 3 described below, the intensity of the light input into the dummy waveguide 52 is monitored by detecting the branched monitor light 24 with a photodiode 55. The input visible light 23 propagates from the dummy waveguide 52 to the chip end face of each main circuit 50, and is irradiated onto the photocurable resin 7 filled in the groove 10. This forms a self-forming waveguide 11 along the optical path from the end face of the dummy waveguide 52 to the input/output end of the main circuit. A structure is formed in which the cores 3 and 52 of the two waveguides are connected by a self-forming waveguide. After that, the photocurable resin 7 other than the self-forming waveguide 11 is removed. Under the manufacturing conditions for the optical circuit of this embodiment, a self-forming waveguide with a diameter of about 5 μm was formed.
　続く図２の（ｃ）の工程３では、無電解メッキを用いてウェハ全体に遮光膜４を形成した。図１に示した開口部を形成するためには、工程２で形成した柱状の自己形成導波路１１の側面にも回り込むように、本回路のチップ端面全体に遮光膜４を形成する必要がある。この遮光膜４の成膜には、スパッタリングや蒸着法のような成膜方法よりも、メッキ法が適している。本実施形態の光回路では、遮光膜４として膜厚５００ｎｍ程度の金の薄膜を作製した。 In the next step 3 in FIG. 2(c), electroless plating was used to form a light-shielding film 4 over the entire wafer. To form the opening shown in FIG. 1, it is necessary to form the light-shielding film 4 over the entire chip end face of this circuit, so that it also wraps around the side of the columnar self-forming waveguide 11 formed in step 2. Plating is more suitable for forming this light-shielding film 4 than deposition methods such as sputtering and vapor deposition. In the optical circuit of this embodiment, a thin gold film with a thickness of about 500 nm was fabricated as the light-shielding film 4.
　続く図２の（ｄ）の工程４では、自己形成導波路１１が除去される。一般的な有機溶媒を用いた洗浄の後に、酸素プラズマを用いてアッシングを行った。アッシング工程により、柱状の自己形成導波路１１が除去され、自己形成導波路１１に覆われていた本回路の導波路のコア３が露出する。自己形成導波路１１は有機物で構成されているため、アッシングによって自己形成導波路１１のみが除去される。結果としてコア３周辺の円形の領域６を除いた本回路５０のチップ端面に、遮光膜４が形成される。工程１～工程４によって、ウェハ上のすべての本回路のチップ端面に、一括して開口部を伴う遮光膜４を形成することができる。 In the next step 4 in FIG. 2(d), the self-formed waveguide 11 is removed. After cleaning with a general organic solvent, ashing is performed using oxygen plasma. The columnar self-formed waveguide 11 is removed by the ashing step, and the waveguide core 3 of this circuit, which was covered by the self-formed waveguide 11, is exposed. Since the self-formed waveguide 11 is made of an organic material, only the self-formed waveguide 11 is removed by ashing. As a result, a light-shielding film 4 is formed on the chip end face of this circuit 50, except for the circular area 6 around the core 3. By steps 1 to 4, a light-shielding film 4 with an opening can be formed all at once on the chip end faces of all of the circuits on the wafer.
　次の図２の（ｅ）の工程５では、遮光膜４の上にさらにガスバリア膜５を成膜する。チップ端面となる溝１０の側壁へガスバリア膜５を形成するため、プラズマＣＶＤ（Chemical Vapor Deposition）法を用いて膜厚１００ｎｍ程度のＳｉＮを成膜した。 In the next step 5 in FIG. 2(e), a gas barrier film 5 is further deposited on the light-shielding film 4. To form the gas barrier film 5 on the side walls of the grooves 10 that form the chip end faces, a SiN film with a thickness of about 100 nm is deposited using the plasma CVD (Chemical Vapor Deposition) method.
　最後に図２の（ｆ）の工程６では、ダイシングを行いウェハ上の各本回路を分離して、チップ形状の光回路を得る。前述したように、チップ端面を保護するために、溝１０の幅より十分に薄いブレードを使用する。 Finally, in step 6 of FIG. 2(f), dicing is performed to separate each circuit on the wafer, obtaining chip-shaped optical circuits. As mentioned above, a blade that is sufficiently thinner than the width of the groove 10 is used to protect the chip end faces.
　したがって本発明は、光回路の製造方法であって、ウェハ６０上に、導波路が形成された光回路の端面となる溝１０を作成するステップと、前記溝内の前記導波路の延長上に、自己形成導波路１１を作製するステップと、前記自己形成導波路の周囲および前記ウェハ上に、遮光膜４を形成するステップと、前記自己形成導波路を除去して、光回路の前記端面の上に、前記導波路のコア断面を含む開口部６を形成するステップと、前記ウェハ上に、ガスバリア膜５を形成するステップと、前記溝を切断して、チップ状の前記光回路５０を作製するステップとを備えるものとしても実施できる。 The present invention can therefore also be implemented as a method for manufacturing an optical circuit, comprising the steps of: creating a groove 10 on a wafer 60 that will become an end face of the optical circuit in which a waveguide is formed; creating a self-forming waveguide 11 on an extension of the waveguide in the groove; forming a light-shielding film 4 around the self-forming waveguide and on the wafer; removing the self-forming waveguide to form an opening 6 including a core cross section of the waveguide on the end face of the optical circuit; forming a gas barrier film 5 on the wafer; and cutting the groove to create the chip-shaped optical circuit 50.
　図１および図２の手順で作製された本開示の光回路５０の端面構造により、チップの上面に加えてチップ端面まで一括してガスバリア膜を形成できる。さらに、チップ端面への開口部６の形成がウェハ単位で一括して可能になる。光回路５０の構成によって、吸湿によりクラッドの屈折率が変化して生じる出射光の形状の劣化と、出射光への迷光の混入を同時に抑制することができる。またて開口部６の直径は、自己形成導波路の直径によって決まる。このため、開口部６の内径を、自己形成導波路を成長させる光の照射量によってある程度制御することができる。本実施形態の光回路では、自己形成導波路の直径を５μｍ程度としたが、おおむね１０μｍ以下の直径であれば図２に示した一連の工程によって自己形成導波路を形成可能である。ダミー導波路５２のコア径によって、開口部６の直径を制御することもできる。迷光除去の効果を得るために、開口部６の直径（内径）は、コアのモードフィールド径の２倍程度が適当である。 The end face structure of the optical circuit 50 of the present disclosure, which is fabricated by the procedure of FIG. 1 and FIG. 2, allows a gas barrier film to be formed all at once on the chip end face in addition to the upper face of the chip. Furthermore, the opening 6 can be formed all at once on the chip end face on a wafer basis. The configuration of the optical circuit 50 can simultaneously suppress the deterioration of the shape of the emitted light caused by the change in the refractive index of the cladding due to moisture absorption, and the inclusion of stray light in the emitted light. The diameter of the opening 6 is determined by the diameter of the self-forming waveguide. Therefore, the inner diameter of the opening 6 can be controlled to some extent by the amount of light irradiation that grows the self-forming waveguide. In the optical circuit of this embodiment, the diameter of the self-forming waveguide is set to about 5 μm, but if the diameter is about 10 μm or less, the self-forming waveguide can be formed by the series of steps shown in FIG. 2. The diameter of the opening 6 can also be controlled by the core diameter of the dummy waveguide 52. In order to obtain the effect of removing stray light, the diameter (inner diameter) of the opening 6 is appropriately about twice the mode field diameter of the core.
　本実施形態の光回路では、遮光膜４に金を用いたが、遮光膜の材料は金だけに限定されない。遮光膜の材料は、メッキ法に代表されるような表面の凹凸に追従して膜形成が可能な手法で取り扱うことのできる材料であれば良い。またガスバリア膜５についても、ＳｉＮの他にアルミナや石英系ガラス、酸化ニオブ、酸化セリウム、その他の樹脂材料でも良い。 In the optical circuit of this embodiment, gold is used for the light-shielding film 4, but the material of the light-shielding film is not limited to gold. The material of the light-shielding film may be any material that can be handled by a method capable of forming a film that follows the unevenness of the surface, such as a plating method. Also, the gas barrier film 5 may be made of alumina, quartz glass, niobium oxide, cerium oxide, or other resin materials in addition to SiN.
　図３に示したウェハにおける光回路の配置図では、溝１０ａ～１０ｄは、２列の本回路の領域５０の左右の２辺に沿うように形成されていた。しかしながら、本回路５０のチップの上下２辺をさらに含み、４辺に沿うように溝を掘っても良い。本回路の４辺に溝を形成する場合、支持基板１の下面側を１００μｍ程度削り残しておくと良い。尚、図２で説明した手順の一連の工程でも、溝１０は基板の下面側を残して形成されているが、支持基板１の下面まで完全に分離する溝を形成しても良い。図３に示したように本回路５０の領域の左右の２辺に溝を形成しても、本回路がウェハ６０から抜け落ちることは無く、ウェハごとに一括して工程１～工程６を実施できるからである。 In the layout diagram of the optical circuit on the wafer shown in FIG. 3, the grooves 10a to 10d are formed along the two left and right sides of the two rows of the region 50 of the main circuit. However, the grooves may be dug along the four sides, including the top and bottom sides of the chip of the main circuit 50. When forming grooves on the four sides of the main circuit, it is recommended to leave about 100 μm of the bottom side of the support substrate 1 uncut. In the series of steps of the procedure described in FIG. 2, the groove 10 is formed leaving the bottom side of the substrate, but a groove that completely separates it to the bottom side of the support substrate 1 may be formed. Even if grooves are formed on the two left and right sides of the region of the main circuit 50 as shown in FIG. 3, the main circuit will not fall out of the wafer 60, and steps 1 to 6 can be performed collectively for each wafer.
　上述の工程１～工程６によれば、遮光膜４はチップの上面の全面と、開口部を除いたチップの端面に形成されている。迷光除去の効果は、少なくとも導波路コアの断面があるチップ端面上に、開口部６とともに遮光膜４が形成されていれば良い。予期せぬ迷光の影響を最小化するためには、チップ上面およびすべてのチップ端面上に遮光膜４が形成されているのが好ましい。図２の作製手順では、矩形のチップ形状の向かい合う２辺に、光の入射端または出射端を有している例を示しており、溝１０は本回路５０の両側に作製していた。しかしながら、光回路の導波路コアの断面が無いチップ端面に対応する辺にも、溝を作成して、遮光膜４およびガスバリア膜５を形成しても良い。 According to the above-mentioned steps 1 to 6, the light-shielding film 4 is formed on the entire top surface of the chip and on the end surfaces of the chip except for the openings. The effect of removing stray light is achieved by forming the light-shielding film 4 together with the openings 6 at least on the chip end surfaces where the cross-section of the waveguide core is present. In order to minimize the effect of unexpected stray light, it is preferable that the light-shielding film 4 is formed on the top surface of the chip and all of the chip end surfaces. In the manufacturing procedure of FIG. 2, an example is shown in which the light input end or output end is located on two opposing sides of the rectangular chip shape, and the grooves 10 are formed on both sides of the circuit 50. However, grooves may also be created on the sides corresponding to the chip end surfaces where there is no cross-section of the waveguide core of the optical circuit, and the light-shielding film 4 and gas barrier film 5 may be formed.
　図１に示した光回路の構成および図２に示した工程では、遮光膜４の上にガスバリア膜５を成膜する構成を示したが、これら２つの層を製膜する順序が逆で、ガスバリア層の上に遮光膜が形成されていても良い。この場合は、図２の一部の工程の順序を入れ変えるだけで良い。具体的には図２において、工程１の溝の形成、工程５のガスバリア膜５の成膜、工程２の自己形成導波路の形成、工程３の遮光膜４の形成、工程４のアッシングによる開口部の形成、工程６のダイシングによるチップ切断の順に手順を修正するだけで良い。 In the optical circuit configuration shown in FIG. 1 and the process shown in FIG. 2, a configuration in which a gas barrier film 5 is formed on a light-shielding film 4 is shown, but the order of forming these two layers may be reversed, with the light-shielding film being formed on the gas barrier layer. In this case, it is only necessary to change the order of some of the processes in FIG. 2. Specifically, in FIG. 2, it is only necessary to modify the order of the groove formation in process 1, the deposition of the gas barrier film 5 in process 5, the formation of the self-forming waveguide in process 2, the formation of the light-shielding film 4 in process 3, the formation of an opening by ashing in process 4, and the chip cutting by dicing in process 6.
　本開示の光回路では、チップの端面上において、開口部６の中心位置と、コア断面の中心位置とが一致しているのが、迷光の出力防止の点から最も好ましい。またコアの断面形状は、埋め込み型導波路の矩形状のものを例に示したが、リブ型導波路やスロット導波路でも良い。 In the optical circuit disclosed herein, it is most preferable that the center position of the opening 6 on the end face of the chip coincides with the center position of the core cross section in terms of preventing the output of stray light. In addition, the cross section of the core is exemplified by a rectangular embedded waveguide, but a rib waveguide or a slot waveguide may also be used.
　[実施形態２]
　図４は、実施形態２の石英系ＰＬＣによる光回路チップの構成を示す図である。図４の光回路１００は、ＲＧＢ合波器であって、ＲＧＢコンバイナ、ＲＧＢカプラとも呼ばれる。図４の（ａ）はチップの上面図であり、（ｂ）は端面Ｂを見た側面図、（ｃ）は端面Ｃを見た側面図、（ｄ）は端面Ｃ近傍でＩＶｄ－ＩＶｄ線を通り基板面に垂直な面の断面図である。 [Embodiment 2]
Fig. 4 is a diagram showing the configuration of an optical circuit chip using a silica-based PLC according to embodiment 2. The optical circuit 100 in Fig. 4 is an RGB multiplexer, also called an RGB combiner or RGB coupler. Fig. 4(a) is a top view of the chip, (b) is a side view looking at end face B, (c) is a side view looking at end face C, and (d) is a cross-sectional view of a surface passing through line IVd-IVd near end face C and perpendicular to the substrate surface.
　光回路１００は、Ｒ入力導波路１０１、Ｇ入力導波路１０２、Ｂ入力導波路１０３へのＲ、Ｇ、Ｂの各入力光を、埋め込み型導波路で構成された合波器１０７で合成して、導波路１０２の反対側の端部から出力する。３つの入力導波路には、同じく埋め込み型導波路で構成されたモニタ用導波路１０４、１０５、１０６を備える。図４の（ｂ）および（ｃ）に示したように、端面Ｂおよび端面Ｃでは、それぞれ、遮光膜の形成されていない開口部内に導波路コアの断面がある。遮光膜の上は、チップ上面およびチップ端面を覆うように成膜されたガスバリア膜が構成されている。図４の（ｄ）の断面図の構成は、図１の（ｂ）と全く同じである。 In the optical circuit 100, the R, G, and B input lights to the R input waveguide 101, G input waveguide 102, and B input waveguide 103 are combined by a combiner 107 composed of an embedded waveguide, and output from the opposite end of the waveguide 102. The three input waveguides are equipped with monitor waveguides 104, 105, and 106, which are also composed of embedded waveguides. As shown in (b) and (c) of FIG. 4, at end face B and end face C, there is a cross section of the waveguide core in an opening where no light-shielding film is formed. On top of the light-shielding film, a gas barrier film is formed so as to cover the upper surface and end face of the chip. The cross-sectional configuration of (d) of FIG. 4 is exactly the same as that of (b) of FIG. 1.
　各導波路のコア膜厚は２．５μｍ、コア幅は１．７μｍとし、コアとクラッドの比屈折率差Δは１．１％とした。合波器１０７は、可視光の赤(Ｒ：波長６４０ｎｍ)、緑（Ｇ：５２０ｎｍ）、青（Ｂ：４４５ｎｍ）に相当する３波長を１つの導波路に合波するように設計した。図４のモニタ導波路１０４、１０５、１０６によって、３つの導波路１０１、１０２、１０３へ入力された可視光の入力パワーをモニタする。本開示の光回路のチップ端部の開口部の構造によって、モニタ用導波路の出力端から出力する迷光を大幅に抑制することができる。また、合波された出力光に対する迷光の混入も大幅に抑制できる。図４に示したＲＧＢ合波器１００は、モニタ光への迷光をさらに改善するためさらに変形することができる。 The core film thickness of each waveguide is 2.5 μm, the core width is 1.7 μm, and the relative refractive index difference Δ between the core and the clad is 1.1%. The multiplexer 107 is designed to multiplex three wavelengths corresponding to visible light red (R: wavelength 640 nm), green (G: 520 nm), and blue (B: 445 nm) into one waveguide. The input power of visible light input to the three waveguides 101, 102, and 103 is monitored by the monitor waveguides 104, 105, and 106 in FIG. 4. The structure of the opening at the chip end of the optical circuit disclosed herein can significantly suppress stray light output from the output end of the monitor waveguide. In addition, the inclusion of stray light in the multiplexed output light can also be significantly suppressed. The RGB multiplexer 100 shown in FIG. 4 can be further modified to further improve stray light in the monitor light.
　図５は、実施形態２の変形例の石英系ＰＬＣによる光回路チップの構成を示す図である。図５の光回路２００は、実施形態２のＲＧＢ合波器１００を変形したものであって、３本のモニタ導波路の構成のみ、ＲＧＢ合波器１００と相違している。図５の（ａ）はチップの上面図であり、（ｂ）は端面Ｂを見た側面図、（ｃ）は端面Ｃを見た側面図、（ｄ）は端面Ｄを見た側面図、（ｅ）は端面Ｅを見た側面図である。 FIG. 5 is a diagram showing the configuration of an optical circuit chip using a silica-based PLC, which is a modified version of the second embodiment. The optical circuit 200 in FIG. 5 is a modified version of the RGB multiplexer 100 in the second embodiment, and differs from the RGB multiplexer 100 only in the configuration of the three monitor waveguides. FIG. 5 (a) is a top view of the chip, (b) is a side view looking at end face B, (c) is a side view looking at end face C, (d) is a side view looking at end face D, and (e) is a side view looking at end face E.
　光回路２００は、Ｒ入力導波路２０１、Ｇ入力導波路２０２、Ｂ入力導波路２０３へのＲ、Ｇ、Ｂの各入力光を、埋め込み型導波路で構成された合波器２０７で合成して、導波路２０２の反対側の端部から出力する。３つの入力導波路には、同じく埋め込み型導波路で構成されたモニタ用導波路２０４、２０５、２０６を備える。本変形例では、モニタ導波路は、合波光が出力される端面Ｃではなくて、端面Ｃに対してチップ側面の端面Ｄおよび端面Ｅに出力端を有する。モニタ用導波路の出力端を、合波器の光の進行方向と直交するチップ端面に設けた構成によって、モニタ光および合波光それぞれへの迷光がさらに抑制される。図１に示したコアの断面の周囲の開口部の構造によって、モニタ用導波路の出力端、合波光の出力端から出力される迷光を大幅に抑制することができる。 In the optical circuit 200, the R, G, and B input lights to the R input waveguide 201, G input waveguide 202, and B input waveguide 203 are combined by a combiner 207 made of an embedded waveguide, and output from the opposite end of the waveguide 202. The three input waveguides are equipped with monitor waveguides 204, 205, and 206, which are also made of embedded waveguides. In this modified example, the monitor waveguide has output ends not at end face C where the combined light is output, but at end faces D and E on the chip side relative to end face C. The output ends of the monitor waveguides are provided on the chip end faces perpendicular to the light traveling direction of the combiner, which further suppresses stray light to the monitor light and the combined light. The structure of the openings around the cross section of the core shown in Figure 1 can significantly suppress stray light output from the output ends of the monitor waveguides and the output ends of the combined light.
　本発明は、光学機器に利用できる。 This invention can be used in optical instruments.

Claims (8)

  1. 　基板に形成された光回路であって、
    　前記基板の上のクラッド層、および、前記クラッド層内に形成されたコアで構成された導波路と、
    　前記導波路のコア断面を含むチップの端面を覆い、前記コア断面を含む領域を開けた開口部を有する、遮光膜と、
    　前記チップの上面およびすべての端面を覆うガスバリア膜と
    　を備えた光回路。     An optical circuit formed on a substrate,
    a cladding layer on the substrate and a waveguide comprising a core formed within the cladding layer;
    a light-shielding film covering an end face of the chip including a core cross section of the waveguide and having an opening that exposes an area including the core cross section;
    and a gas barrier film covering the top surface and all end surfaces of the chip.
  2. 　前記遮光膜の上に、前記ガスバリア膜が形成されている請求項１に記載の光回路。 The optical circuit according to claim 1, wherein the gas barrier film is formed on the light-shielding film.
  3. 　前記ガスバリア膜の上に、前記遮光膜が形成されている請求項１に記載の光回路。 The optical circuit according to claim 1, wherein the light-shielding film is formed on the gas barrier film.
  4. 　異なる波長の可視光が入力される２本以上の入力導波路と、前記異なる波長の可視光の合波器と、合波光の出力導波路を備え、
    　前記入力導波路および前記出力導波路の各端部が前記開口部を有する請求項１に記載の光回路。     The optical fiber includes two or more input waveguides to which visible light of different wavelengths is input, a multiplexer for the visible light of the different wavelengths, and an output waveguide for multiplexed light,
    2. The optical circuit of claim 1, wherein each end of said input waveguide and said output waveguide has said opening.
  5. 　前記開口部の直径は１０μｍ以下である請求項１に記載の光回路。 The optical circuit of claim 1, wherein the diameter of the opening is 10 μm or less.
  6. 　前記コアは、ジルコニウム（ＺｒＯ2）ドープＳｉＯ2またはノンドープＳｉＯ2で構成されている請求項１乃至５いずれかに記載の光回路。 6. The optical circuit according to claim 1, wherein the core is made of zirconium ( ZrO2 )-doped SiO2 or non-doped SiO2 .
  7. 　前記クラッド層は、ホウ素ドープＳｉＯ2またはフッ素ドープＳｉＯ2で構成されている請求項１乃至５いずれかに記載の光回路。 6. The optical circuit according to claim 1, wherein the cladding layer is made of boron-doped SiO2 or fluorine-doped SiO2 .
  8. 　光回路の製造方法であって、
    　ウェハ上に、導波路が形成された光回路の端面となる溝を作成するステップと、
    　前記溝内の前記導波路の延長上に、自己形成導波路を作製するステップと、
    　前記自己形成導波路の周囲および前記ウェハ上に、遮光膜を形成するステップと、
    　前記自己形成導波路を除去して、光回路の前記端面の上に、前記導波路のコア断面を含む開口部を形成するステップと、
    　前記ウェハ上に、ガスバリア膜を形成するステップと、
    　前記溝を切断して、チップ状の前記光回路を作製するステップと
    　を備える製造方法。     A method for manufacturing an optical circuit, comprising the steps of:
    forming a groove on a wafer to become an end face of an optical circuit having a waveguide formed therein;
    creating a self-forming waveguide on the extension of the waveguide within the trench;
    forming a light-shielding film around the self-written waveguide and on the wafer;
    removing the self-written waveguide to form an opening on the end face of an optical circuit that includes a core cross-section of the waveguide;
    forming a gas barrier film on the wafer;
    and cutting the groove to fabricate the optical circuit in a chip form.
PCT/JP2022/040490 2022-10-28 2022-10-28 Optical circuit and method for producing optical circuit WO2024089892A1 (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001350043A (en) * 2000-06-05 2001-12-21 Minolta Co Ltd Optical waveguide device and its manufacturing method
JP2003131064A (en) * 2001-10-29 2003-05-08 Ibiden Co Ltd Method for manufacturing optical waveguide
JP2004295118A (en) * 2003-03-12 2004-10-21 Sanyo Electric Co Ltd Optical waveguide
WO2008157469A1 (en) * 2007-06-20 2008-12-24 Texas Instruments Incorporated Illumination source and method
JP2014002282A (en) * 2012-06-19 2014-01-09 Nippon Telegr & Teleph Corp <Ntt> Optical module
WO2021005723A1 (en) * 2019-07-09 2021-01-14 日本電信電話株式会社 Optical multiplexing circuit
JP2021039241A (en) * 2019-09-03 2021-03-11 古河電気工業株式会社 Optical waveguide circuit, light source module, and manufacturing method for optical waveguide circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001350043A (en) * 2000-06-05 2001-12-21 Minolta Co Ltd Optical waveguide device and its manufacturing method
JP2003131064A (en) * 2001-10-29 2003-05-08 Ibiden Co Ltd Method for manufacturing optical waveguide
JP2004295118A (en) * 2003-03-12 2004-10-21 Sanyo Electric Co Ltd Optical waveguide
WO2008157469A1 (en) * 2007-06-20 2008-12-24 Texas Instruments Incorporated Illumination source and method
JP2014002282A (en) * 2012-06-19 2014-01-09 Nippon Telegr & Teleph Corp <Ntt> Optical module
WO2021005723A1 (en) * 2019-07-09 2021-01-14 日本電信電話株式会社 Optical multiplexing circuit
JP2021039241A (en) * 2019-09-03 2021-03-11 古河電気工業株式会社 Optical waveguide circuit, light source module, and manufacturing method for optical waveguide circuit

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