WO2024088942A1 - Method for producing a high-resistivity semiconductor stack and associated stack - Google Patents

Method for producing a high-resistivity semiconductor stack and associated stack Download PDF

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Publication number
WO2024088942A1
WO2024088942A1 PCT/EP2023/079435 EP2023079435W WO2024088942A1 WO 2024088942 A1 WO2024088942 A1 WO 2024088942A1 EP 2023079435 W EP2023079435 W EP 2023079435W WO 2024088942 A1 WO2024088942 A1 WO 2024088942A1
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layer
silicon carbide
support layer
cavities
annealing
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PCT/EP2023/079435
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French (fr)
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Emmanuel Augendre
Christine LAURANT
Shay Reboh
Eric VANDERMOLEN
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Commissariat A L'energie Atomique Et Aux Energies Alternatives
Soitec
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Publication of WO2024088942A1 publication Critical patent/WO2024088942A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • TITLE METHOD FOR MANUFACTURING A HIGHLY RESISTIVE SEMICONDUCTOR STACK AND ASSOCIATED STACK
  • the technical field of the invention is that of semiconductor stacks intended to form silicon on insulator substrates, also called “SOI” substrates for “Silicon On Insulator” in English, and more particularly SOI substrates used in the field of radio frequencies.
  • Highly resistive semiconductor stacks such as silicon-on-insulator, or SOI, substrates, are widely used for radio frequency applications because they promote the integrity of the signals circulating in devices made on their surface.
  • An SOI substrate comprises a first semiconductor layer, made of silicon, called a “support layer” or “base”, a second semiconductor layer, made of silicon, called “active layer”.
  • the active layer is intended to accommodate microelectronic components, manufactured in or on the active layer. We also speak in this case of “initial” or “front end” components, also “FEOL” for “Front End Of Line” in English.
  • the active layer is separated from the support layer by an insulating layer, for example made of silicon oxide, placed between the support layer and the active layer, and more particularly under the active layer.
  • the insulating layer is then called “buried” or “BOX” for “Burned OXide”.
  • the insulating layer makes it possible to confine the majority charge carriers in the active layer, which makes it possible to envisage a high operating frequency of the front end components, for example up to several tens of gigahertz.
  • the charge carriers are then trapped at the grain boundaries, where the dangling silicon bonds are located.
  • the trapping layer is deposited in low pressure vapor phase (also called “LPCVD” for “Low Pressure Chemical Vapor Deposition” in English), followed by rapid annealing at a temperature of 1000 ° C, so as to form the grains of silicon.
  • the effectiveness of the trapping layer is based on the density of pendant silicon bonds and therefore on the density of grain boundaries.
  • the heat treatments implemented during the manufacturing of microelectronic components at the active layer tend to reduce the number of grains and therefore reduce the number of grain boundaries.
  • the polycrystalline silicon trapping layer therefore imposes a restricted thermal budget.
  • Another approach to trapping charge carriers consists of forming bubbles in the support layer, in the vicinity of the interface between the support layer and the insulating layer. The pendant bonds at the free surface of each bubble then allow the trapping of the charge carriers.
  • the article “Chemical and electrical properties of cavities in silicon and germanium”, SM Myers, DM Follstaedt, GA Petersen, CH Seager, HJ Stein & WR Wampler, Nuclear instruments and Methods in Physics Research B 106 (1995) 379-385 ] describes a process for forming bubbles in a silicon layer by implantation of helium ions. However, the bubbles formed are approximately 200 nm away from the interface between the support layer and the insulating layer.
  • the maximum bubble density is located at a distance from the interface of between 1000 nm and 1500 nm.
  • the trapping capacity at the interface level is therefore limited.
  • modulating the implantation energy to bring the bubbles closer to the interface could cause exfoliation of the insulating layer.
  • the implantation time can be long (of the order of 20 min to implant ions in a substrate of 300 mm in diameter, under an implantation current of 10 mA and a dose of 10 17 cm' 2 ).
  • Another known solution is described in document FR3091011 A1 which discloses an SOI substrate comprising a layer of polycrystalline silicon carbide extending on the surface of the support layer.
  • the carbide layer is preferably polycrystalline and thus makes it possible to trap the charge carriers, in the same way as a polycrystalline silicon trapping layer.
  • the growth of the carbide layer is carried out by growth from the support layer using a carbon precursor or by CVD.
  • the thickness of the disclosed carbide layer is limited to 5 nm.
  • the carbide layer is chemically fragile and can be contaminated by species brought during additional manufacturing stages (such as the manufacturing of the insulating layer and/or the active layer) and having migrated up to the carbide layer.
  • the invention relates to a method of manufacturing a semiconductor stack, comprising, from a first layer of silicon, called support layer: the formation of a layer of silicon carbide, extending over the layer support, having a thickness, measured from the support layer, greater than 5 nm, a fraction of carbon atoms of the silicon carbide layer, less than 20 nm from the support layer, being strictly greater than 50%; and annealing the support layer and the silicon carbide layer until forming cavities, each cavity extending into the support layer, from the silicon carbide layer, an oxygen concentration in contact with the silicon carbide layer.
  • silicon carbide during the annealing step, being less than 10 ppm and preferably less than 5 ppm, or even zero.
  • the silicon atoms of the support layer migrate towards the carbide layer thus forming, from the carbide layer, cavities, that is to say hollow zones located in the support layer.
  • the cavities formed in the support layer provide pendant silicon bonds and thus make it possible to trap the charge carriers in the support layer.
  • the arrangement of the cavities makes it possible to effectively trap the charge carriers as close as possible to the interface between the support layer and the carbide layer.
  • the silicon carbide present is a semiconductor having an indirect band gap whose deviation is greater than 2 eV, or even 3 eV.
  • the carbide layer thus prevents the circulation of charge carriers in the vicinity of the insulating layer.
  • the stack since trapping does not rely on the presence of grain boundaries, which are sensitive to temperature, the stack then has improved morphological stability. Furthermore, during heat treatment, the temperature involving the coalescence of cavities is significantly higher than the temperature involving the coalescence of grains in a polycrystalline structure. The temperature involving the coalescence of the cavities is also higher than the temperatures used during additional manufacturing stages. Moreover, while the coalescence of the grains is accompanied by a disappearance of traps, the possible coalescence of the cavities takes place at a constant surface.
  • the silicon carbide layer being richer in carbon, it makes it possible to activate the migration of the silicon atoms from the support layer during annealing and effectively form the cavities.
  • the thickness of the silicon carbide layer greater than 5 nm improves its robustness, particularly chemical, with respect to additional manufacturing steps (such as the manufacturing of “front end” components). In fact, it is less affected by contaminants that can migrate.
  • the silicon carbide layer can undergo oxidation by pitting (also known as pitting) when it is annealed in an environment comprising oxygen. Pitting damages the silicon carbide layer and can slow down the migration of silicon atoms and therefore the formation of cavities. Annealing carried out in an atmosphere poor in oxygen limits the appearance of pitting and therefore improves the reproducibility of the process.
  • Annealing can be carried out for a period of between 15 min and 2 h at a temperature of between 900°C and 1100°C.
  • the layer of silicon carbide resulting from the formation step is advantageously amorphous and the annealing of the layers is advantageously carried out so as to crystallize the layer of silicon carbide in a polycrystalline arrangement.
  • the support layer is advantageously oriented in a plane.
  • the thickness of the silicon carbide layer is preferably less than 500 nm.
  • Each cavity may have facets, each facet being preferably oriented parallel to a crystallographic plane forming, for example, part of the family of crystallographic planes ⁇ 111 ⁇ or part of the family of crystallographic planes ⁇ 113 ⁇ .
  • the cavities extend over a distance, measured perpendicular to the plane and from the layer of silicon carbide, preferably between 5 nm and 100 nm.
  • the method preferably comprises the formation of an insulating layer extending over the layer of silicon carbide.
  • the insulating layer is advantageously intended to form a “buried” layer called “BOX” for “Burned OXide” in English.
  • the formation of the insulating layer is carried out by deposition, before said annealing.
  • the annealing of the support layer, the silicon carbide layer and the insulating layer can be carried out under an atmosphere comprising an oxygen concentration of less than 1%.
  • the formation of the insulating layer is carried out by transfer from a donor substrate, after annealing of the layers.
  • the method can include the formation of a second crystalline layer, extending over the insulating layer.
  • the insulating layer then forms a “BOX” layer.
  • Another aspect of the invention relates to a semiconductor stack comprising: a first silicon layer, called the support layer; a layer of silicon carbide, extending over the support layer, having a thickness, measured from the support layer, greater than 5 nm; and cavities, each cavity extending into the support layer from the silicon carbide layer.
  • the silicon carbide layer is advantageously polycrystalline.
  • the support layer is oriented in a plane and the cavities extend over a distance, measured perpendicular to the plane and from the silicon carbide layer, of between 5 nm and 100 nm.
  • each cavity when the cavities extend over a distance, measured perpendicular to the plane and from the layer of silicon carbide, greater than 15 nm, then each cavity has facets, each facet being oriented parallel to a crystallographic plane.
  • each cavity has a pyramidal shape and has a base aligned with the interface between the support layer and the silicon carbide layer.
  • the top of the pyramid extends into the support layer.
  • the cavities are only located at the interface between the support layer and the silicon carbide layer. In other words, each cavity extends only into the support layer from the silicon carbide layer.
  • the silicon carbide layer is non-porous.
  • each cavity has a free surface surrounding an interior volume, at least one portion of the free surface separating said interior volume from the support layer and at least one other portion of the free surface separating the interior volume from the layer of silicon carbide.
  • each portion of the free surface separating the interior volume of the cavity of the support layer comprises silicon atoms, at least part of which has a pendant bond.
  • FIG. 1 schematically represents a first embodiment of a semiconductor stack according to the invention.
  • FIG. 2 schematically represents a first mode of implementation of a manufacturing process according to the invention.
  • FIG. 3a schematically represents a first example of a first step of the manufacturing process according to the invention.
  • FIG. 3b schematically represents a second example of the first step of the manufacturing process according to the invention.
  • FIG. 4 schematically represents a second step of the manufacturing process according to the invention.
  • FIG. 5 schematically represents a third step of the manufacturing process according to the invention.
  • FIG. 6 schematically represents a fourth step of the manufacturing process according to the invention.
  • FIG. 8 schematically represents a fifth step of the manufacturing process according to the invention.
  • FIG. 9 represents an image obtained by transmission microscopy of a semiconductor stack manufactured using the manufacturing process according to the invention.
  • the invention aims to improve the semiconductor stacks intended to form an SOI substrate and in particular a substrate intended for radio frequency applications.
  • FIG. 1 schematically represents a first embodiment of a semiconductor stack 10 according to the invention.
  • the stack 10 comprises a first silicon layer 11, called the support layer; a layer of silicon carbide 12; and cavities 13.
  • the support layer 11 extends for example along a given plane P. This is, for example, the plane of a silicon wafer from which an SOI substrate will be formed.
  • the support layer 11 is advantageously a resistive support, that is to say having a resistivity greater than 1 k ⁇ cm.
  • the silicon carbide layer 12 (also called SiC layer) extends over the support layer 11 along the given plane P.
  • the SiC layer 12 is directly in contact with the support layer 11, thus forming an interface 112 between the two layers.
  • the stack 10 is remarkable in that it comprises a plurality of cavities 13 extending into the support layer 11.
  • Each cavity 13 is hollow, that is to say empty of any solid or liquid material. They may include a species in gaseous form having a low partial pressure. They are, however preferably completely empty.
  • Each cavity 13 extends into the support layer 11, from the SiC layer 12. That is to say that each cavity 13 extends into the support layer 11 from the interface 112.
  • Each cavity 13 then presents a free surface 131, 132 surrounding an interior volume 130 of the cavity 13. At least one portion 131 of the free surface separates said interior volume 130 from the support layer 11 and at least one other portion 132 of the free surface separates the interior volume 130 from the cavity of the SiC layer 12.
  • the portion(s) 131 of the free surface separating the interior volume 130 from the cavity of the support layer 11 are formed of silicon atoms, at least part of which has a dangling bond.
  • dangling bond we mean an atomic orbital not involved in a chemical bond with other elements.
  • the pendant connections make it possible to trap the charge carriers circulating in the support layer 11 and in the vicinity of the SiC layer 12.
  • the pendant bonds and the cavities also make it possible to trap impurities, such as hydrogen ions or atoms, helium atoms or metals such as lithium or copper, having migrated into the support layer 11 during, for example, additional manufacturing steps (such as the manufacturing of “front end” components).
  • impurities such as hydrogen ions or atoms, helium atoms or metals such as lithium or copper
  • the resistivity of the support layer 11 is therefore not degraded by additional manufacturing steps.
  • thermodynamic stability of the cavities 13 and their formation by diffusion tend to favor faceting of the cavities.
  • Portions 131 of the free surface 131, 132 of each cavity 13 then align preferentially along crystallographic planes of the support layer 11.
  • the cavities 13 can be faceted by presenting portions parallel to crystallographic planes of the family of planes ⁇ 111 ⁇ (that is to say the planes (111), (-111), (1 -11) and (-1 -11)) or of the family of planes ⁇ 113 ⁇ (that is to say the planes (113), (-113), (1 -13) and (-1 -13)).
  • the cavities 13 can then have the shape of an inverted pyramid, with a square base or a triangular base, said base of which coincides with the interface between the support layer 11 and the SiC layer 12.
  • the faceting does not necessarily depend on the plane at the interface 112 of the support layer 11 with the SiC layer 12.
  • Other families of crystallographic planes are possible. [0061] In order to determine the orientation of the crystallographic planes, it is advantageous to consider the cavities 13 extending over a distance 133, measured perpendicular to the plane P, greater than 15 nm. Indeed, beyond that, it can be difficult to distinguish the families of plans ⁇ 113 ⁇ .
  • FIG. 1 represents by arrows the directions [111] and [001], normal to the crystallographic planes (001) and (111).
  • Each cavity 13 preferably extends from the SiC layer 12 over a distance 133 of between 5 nm and 100 nm. Said distance 133 is measured perpendicular to the plane P in which the layer of SiC 12 extends, that is to say along [001] in the present example. Said distance 133 is measured from the carbide layer 12, that is to say from the interface 112 separating the support layer 11 and the carbide layer 12.
  • the stack 10 also comprises an insulating layer 14 and an active layer 15.
  • the stack 10 forms an SOI substrate.
  • the insulating layer 14 extends over the SiC layer 12. It advantageously has a thickness of between 100 nm and 1000 nm. It comprises, for example, an oxide, such as silicon oxide Si ⁇ 2.
  • the active layer 15 comprises a crystalline or polycrystalline semiconductor and extends over the insulating layer 14. The insulating layer 14 thus separates the SiC layer 12 and the active layer 15. It is said to be “buried” under the active layer 15.
  • active layer 15 advantageously has a thickness of between 50 nm and 500 nm and comprises for example crystalline silicon or polycrystalline silicon or another crystalline semiconductor material used in the field of radio frequencies, such as indium phosphide or gallium nitride .
  • the SiC 12 layer is advantageously polycrystalline. Thus, it contributes to the trapping of charge carriers, in the same way as a polycrystalline silicon trapping layer, as described in the prior art.
  • the charge carriers are trapped by the dangling bonds located at the grain boundaries of the polycrystalline arrangement.
  • FIG. 2 schematically represents a manufacturing process according to the invention, making it possible to manufacture the stack 10.
  • the manufacturing method 20 comprises, from a support layer 11, a step 22 of forming a layer of silicon carbide 12 (called SiC layer), extending over the support layer 11.
  • SiC layer silicon carbide 12
  • Two Examples of silicon carbide layer 12 obtained are illustrated in [Fig. 3a] and [Fig. 3b],
  • the SiC layer 12 is for example formed 22 by vapor phase deposition, also called “CVD” for "Chemical Vapor Deposition” in English, from the support layer 11. It is for example a plasma-assisted CVD deposition (or “PECVD” for “Plasma Enhanced CVD” in English).
  • the SiC 12 layer is for example obtained by PECVD deposition of a carbon precursor, such as tetramethylsilane Si(CH3)4, also called “TMS”.
  • TMS tetramethylsilane
  • the support layer 11 extends in a plane P. It preferably has a crystallographic plane (001) in the plane P.
  • the SiC layer 12 has a thickness 121, measured from the support layer 11 and perpendicular to the plane P. , greater than 5 nm and advantageously less than 500 nm.
  • the method 20 further comprises a step 23 of annealing the support layer 11 and the SiC layer 12 until forming cavities 13 extending into the support layer 11, as illustrated in [Fig. 4], Each cavity 13 then extends into the support layer 11, from the SiC layer 12.
  • the temperature increases the mobility of the silicon atoms of the support layer 11 and a part of these atoms, in particular those close to the SiC layer 12.
  • the difference in fractions of silicon atoms between the support layer 11 and the SiC layer 12 tends to direct the migration of the silicon atoms from the support layer 11 towards the SiC layer 12, thus digging several cavities 13 in the support layer 11.
  • the formation of each cavity 13 finds its starting point at the interface between the support layer 11 and the SiC layer 12.
  • Each cavity 13 then extends into the support layer 11 in a direction substantially perpendicular to the plane P
  • substantially perpendicular we mean perpendicular to within 20°.
  • the annealing 23 of the support layer 11 and the SiC layer 12 is preferably simultaneous.
  • each cavity 13 finds its starting point at the interface between the support layer 11 and the SiC layer 12, the method only forms cavities extending from the interface between the support layer 11 and the SiC layer 12. In other words, the method does not make it possible to form cavities distant from said interface between the support layer 11 and the SiC layer 12 (these cavities distant from the interface can be called pores or bubbles).
  • the support layer 11 includes defects such as amorphous zones or grain boundaries, these defects can assist or facilitate the migration of silicon atoms towards the SiC layer 12.
  • the annealing temperature 23 making it possible to form cavities 13 is advantageously between 900°C and 1100°C. Below 900°C, the mobility of the silicon atoms is not sufficient to form cavities 13 in a duration that can be compatible with an industrial rate. Beyond 1100°C, the mobility of the silicon atoms is such that it allows the migration of atoms between cavities 13, tending to form cavities that are few in number but of very large sizes (i.e. extending beyond 100 nm from the SiC layer 12). The trapping of charge carriers is improved when the density of cavities 13 (i.e. the number of cavities 13 per unit surface of the interface 112) increases. On the other hand, trapping deteriorates when the density of cavities 13 decreases.
  • the SiC 12 layer is advantageously formed at a temperature between 300°C and 500°C. In this way, it presents, before annealing 23, an amorphous phase.
  • Annealing 23 of the layers, and in particular of the SiC layer 12, between 900°C and 1100°C has the effect of crystallizing the SiC layer 12 in a polycrystalline arrangement.
  • This crystallization has two beneficial effects. Initially, the grain boundaries of the polycrystalline arrangement contribute to the trapping of the charge carriers, reinforcing the trapping achieved by the cavities 13. Secondly, the crystallization also accelerates the migration of the silicon atoms of the support layer 11 towards the SiC layer 12, in a manner similar to a pumping of silicon atoms, having the effect of accelerating the kinetics of formation of the cavities 13.
  • the SiC 12 layer is, before and after annealing, non-porous.
  • the SiC 12 layer is polycrystalline (for example after annealing)
  • the non-porosity is provided by the grain boundaries of the SiC 12 layer.
  • Annealing 23 is advantageously carried out for a period of between 15 min and 2 h, so that the migration of the silicon atoms of the support layer 11 makes it possible to obtain cavities 13 extending at least 5 nm from the SiC 12 layer and at most 100 nm from this layer.
  • the dimension of the cavities 13 (measured perpendicular to the plane P and from the SiC layer 12) is proportional to the duration of the annealing 23.
  • An annealing duration of the order of 15 min is compatible with an industrial rate.
  • An annealing time of the order of 2 h makes it possible to form cavities 13 of large sizes, close to 100 nm, extending the coverage of the trapping of the charge carriers in the support layer 11.
  • the annealing time of around 2 hours is also compatible with an industrial rate. Indeed, annealing can be carried out in an oven, making it possible to treat several plates simultaneously, for example several dozen.
  • the ion implantation that can be implemented in the prior art carries out treatment plate by plate.
  • the migration of silicon atoms, and therefore the kinetics of formation of cavities 13, is accelerated when the SiC layer 12 has a fraction of carbon atoms (also called carbon fraction) which is, before annealing 23, at least equal to the fraction of silicon atoms.
  • the SiC layer 12 thus has, before annealing 23, a carbon fraction greater than 50% and advantageously less than 70%.
  • the fraction of silicon in the SiC layer 12 is thus, before annealing 23, less than 50.
  • the kinetics of formation of the cavities 13 is especially accelerated when the difference in fractions between the carbon and silicon atoms is significant in the vicinity of the interface 112 between said SiC layer 12 and the support layer 11.
  • the fraction carbon of the SiC layer 12 beyond 20 nm of the support layer 11 does not, however, show any significant impact on the kinetics of formation of the cavities 13.
  • the SiC layer 12 has a greater thickness 121 at 20 nm (measured perpendicular to the plane P and from the interface 112 with the support layer 11), as illustrated by [Fig. 3a]
  • it presents a part, extending at least 20 nm from the support layer 11 and in which the carbon fraction is greater than 50% and advantageously less than or equal to 70%.
  • the SiC layer 12 When the SiC layer 12 has a thickness 121 less than or equal to 20 nm, as illustrated by [Fig. 3b], it then presents, over its entire thickness 121, a carbon fraction greater than 50% and advantageously less than or equal to 70 %.
  • the carbon fraction of the SiC layer 12, less than 20 nm from the support layer 11 (measured perpendicular to the plane P and from the interface 112), is advantageously between 50% and 70%. .
  • the SiC 12 layer reacts with oxygen and can oxidize, for example by pitting.
  • Annealing 23 is therefore carried out by minimizing the contact of oxygen with the SiC layer 12.
  • Annealing 23 of the stack 10 is carried out by maintaining a concentration of oxygen in contact with the SiC layer 12 which is less than 10 ppm, preferably less than 5 ppm, or even zero.
  • Annealing 23 is for example carried out in a neutral atmosphere, comprising for example at least one neutral gas such as nitrogen or argon.
  • the neutral atmosphere is then sized so that it then has an oxygen concentration of less than 10 ppm, or even less, at least for the duration of annealing 23.
  • Method 20, according to the mode of implementation of [Fig. 2], can also include a step of forming 25 of an insulating layer 14 and a step of forming 26 of an active semiconductor layer 15 so that the final stack 10 forms an SOI substrate, as illustrated by [ Fig. 1],
  • the formation 25 of the insulating layer 14, illustrated by [Fig. 6], is advantageously carried out by transfer from a donor substrate 30.
  • the principle of transfer from a donor substrate 30 is known under the name SmartCut(TM).
  • the formation 26 of the active layer 15 is advantageously also carried out by transfer from a donor substrate and if possible from the same donor substrate 30.
  • the formation 25, 26 of the two aforementioned layers is carried out simultaneously.
  • the method 20 comprises, before the formation 25 of the insulating layer 14, a step of smoothing 24 of said surface 122.
  • Smoothing 24, illustrated by [Fig. 5] can be carried out by chemical-mechanical planarization or CMP for “Chemical Mechanical Polishing” in English.
  • CMP Chemical-mechanical planarization
  • the smoothing 24 is carried out so that the SiC layer 12 has a surface roughness less than or equal to 5 A. Surface roughness is also called average roughness or “RMS” roughness for “Root Mean Square” in English.
  • the roughness of the surface 122 of the SiC layer can be evaluated using an atomic force microscope, or “AFM” for “Atomic Force Microscope” in English. The roughness can be evaluated on a portion of the surface 122 of approximately 1 pm 2
  • the simultaneous formations 25, 26 of the insulating and active layers 14, 15 by transfer can be produced from the same donor substrate 30, the latter then comprising a semiconductor layer 35, for example made of crystalline or polycrystalline silicon or of crystalline indium phosphide or crystalline gallium nitride, over which extends an insulating layer 34, for example made of silicon oxide.
  • the insulating layer 34 has, for example, a thickness of between 100 nm and 1000 nm.
  • the underlying semiconductor layer 35 has for example a thickness greater than 50 nm, or even greater than 500 nm.
  • the simultaneous formations 25, 26 can then comprise a sub-step of implanting light ions (for example hydrogen or helium ions) in the semiconductor layer 35 of the donor substrate 30 to a depth of between 50 nm and 500 nm under the insulating layer 34.
  • the implantation is for example carried out at a dose of a few 10 16 /cm 2 and at an energy of a few tens of keV.
  • the simultaneous formations 25, 26 then comprise a sub-step of cleaning the free surface 341 of the insulating layer 34 of the donor substrate 30, in order to allow direct bonding between said insulating layer 34 of said donor substrate 30 and the layer of SiC 12 from the stack 10.
  • the cleaning of the free surface 341 of the insulating layer 34 advantageously involves known recipes from silicon technologies such as the so-called “RCA” recipe (for “Radio Corporation of America” in English) or another recipe called CARO, comprising a mixture of hydrogen peroxide and sulfuric acid.
  • the bonding is then followed by an annealing called “separation annealing”, aimed at separating the semiconductor layer 35 of the donor substrate 30 in two parts, following a plane comprising the light ions previously implanted.
  • the stack 10 thus comprises, after separation annealing, an insulating layer 14, as illustrated by [Fig. 1], extends over the SiC 12 layer (because it is stuck on the latter).
  • the semiconductor layer 35 forms the active layer 15 of the stack 10.
  • a planarization of the active layer 15 and/or a complementary annealing of the stack 10 can be carried out to prepare the active layer 15 and/or improve the adhesion of the layers of the stack 10.
  • FIG. 7 schematically represents a second mode of implementation of the method 20.
  • the step of forming 25 of the insulating layer 14 occurs before the step of annealing 23 of the stack 10.
  • This inversion of the steps makes it possible to simplify the annealing step 23 in that the neutral atmosphere, previously described, no longer needs to have an oxygen concentration less than 10 ppm. It can be less than 1% only.
  • the manufacturing process 20 is thus simpler to implement, particularly with industrial equipment.
  • the insulating layer 14 is formed on the SiC layer 12, as illustrated by [Fig. 8], It forms a barrier making it possible to reduce or even stop the diffusion of species coming from the surrounding atmosphere towards the SiC layer 12.
  • the stack 10 can then simply be annealed 23 in a neutral atmosphere having a concentration of oxygen less than 1%.
  • the formation 25 of the insulating layer 14 before annealing is preferably carried out by CVD deposition, for example of a tetraethyl orthosilicate precursor Si(OCH2CH3)4 (also called “TEOS”).
  • the CVD deposition is advantageously assisted by plasma (called PECVD) to produce, from the precursor, a layer of silicon dioxide SiO2.
  • PECVD plasma
  • This deposition can be carried out at a temperature between 300°C and 500 °C, so as not to anticipate the annealing 23 of the stack 10.
  • the deposition is carried out so as to form an insulating layer 14 having a thickness 121, measured perpendicular to the plane P, between 100 nm and 1000 nm.
  • the formation 25 of the insulating layer 14 is advantageously carried out in the same equipment as that used to form the SiC layer 12. This makes it possible to prevent water vapor coming from the external atmosphere (for example example of the clean room), is not deposited on the SiC 12 layer (at the risk of oxidizing the latter).
  • the method 20 can also include, to manufacture a stack 10 of the SOI substrate type, the formation 26 of the active layer 15. Unlike the mode of implementation of [Fig. 2], the method 20 according to [Fig. 7] only forms the active layer 15 after annealing 23.
  • the active layer 15 can be formed by transfer from a donor substrate 30 as illustrated by [Fig. 6], The donor substrate 30, however, here only comprises the crystalline or polycrystalline semiconductor layer 35.
  • the formation 25 of the insulating layer 14 before the annealing 23 thus makes it possible to simplify the step 26 of forming the active layer 15 by transfer, in that there is only one layer which is transferred.
  • the formation 26 of the active layer 15 by transfer preferably comprises an implantation of light ions, as described above. However, the implantation depth is adjusted in order to transfer, onto the stack 10, an active layer 15 having a thickness of between 50 nm and 500 nm.
  • the bonding of the donor substrate 30 is also preferably prepared as described above. The free surface of the donor substrate 30 is in particular also activated by means of an oxygen or nitrogen plasma in order to improve bonding.
  • the insulating layer 14 of the stack 10 may also comprise, before the formation 26 of the active layer 15, a smoothing 24 of a surface 141 of the insulating layer intended to receive the active layer 15.
  • the smoothing 24 is advantageously similar to the smoothing described with reference to [Fig. 5],
  • the method 20 can also include, in a manner common to the embodiments of [Fig. 2] and [Fig. 7], a step of supplying 21 of the support layer 11, prior to the step of forming the SiC layer 12.
  • the supply of the support layer 11, the supply step 21 can include the preparation of the support layer 11 so as to allow, or even promote, during annealing 23, the diffusion of the silicon atoms of the support layer 11 towards the SiC layer 12.
  • the preparation may include the removal of organic or metallic contaminants, dopants or particles.
  • Removal can be done by implementing known recipes such as a wet recipe called “CARO” (aimed at removing organic contaminants) or sequences of the “RCA” recipe, including for example a cleaning called “HF” ( aimed at removing dopants), so-called “SC1” cleaning (aimed at removing organic contaminants and particles) and/or so-called “SC2” cleaning (aimed at removing metallic contaminants).
  • CARO wet recipe
  • HF cleaning
  • SC1 aimed at removing organic contaminants and particles
  • SC2 so-called “SC2” cleaning
  • FIG. 9 presents an image obtained by transmission electron microscopy (called “TEM” for “Transmission Electron Microscopy” in English) in bright field, of a semiconductor stack 10 according to the invention.
  • This stack was obtained by means of the method according to the present invention.
  • the stack 10 comprises a support layer 11 of monocrystalline silicon, a polycrystalline SiC layer 12 and a plurality of cavities 13 extending in the support layer 11, from the interface 112 between the support layer 11 and the SiC layer 12
  • the support layer 11 has a plane [001] at the interface 112 with the SiC layer 12 so that the cavities have facets extending along crystallographic planes ⁇ 111 ⁇ (represented by an arrow oriented in the direction [111). ], normal to the planes (111)).
  • the SiC layer also has different crystal structures, for example a majority of grains crystallized according to the 3C polytype and a minority of grains in other polytypes including 4H and 6H. This difference in structure also contributes to the appearance of the SiC 12 layer observed in [Fig. 9],
  • the SiC 12 layer is non-porous.
  • the support layer 11 is also non-porous.
  • the height of the cavities 13 is between 10 nm and 40 nm. This height is measured perpendicular to the plane P and from the SiC 12 layer.
  • Each cavity 13 has a pyramidal shape and has a base aligned with the interface between the support layer 11 and the SiC layer 12. In other words, the base of the pyramid coincides with this interface.
  • the top of the pyramid is located in the support layer 11, at varying depths depending on the size of the cavities 13.
  • the cavities 13 are located only at the interface between the support layer 11 and the SiC layer 12.

Abstract

One aspect of the invention relates to a method for producing a semiconductor stack (10), comprising, from a first silicon layer (11), referred to as a support layer, the following steps: - forming a silicon carbide layer (12), extending over the support layer (11); and - annealing the layers until cavities (13) are formed, each cavity (13) extending into the support layer (11), from the silicon carbide layer (12).

Description

DESCRIPTION DESCRIPTION
TITRE : PROCÉDÉ DE FABRICATION D’UN EMPILEMENT SEMICONDUCTEUR HAUTEMENT RÉSISTIF ET EMPILEMENT ASSOCIÉTITLE: METHOD FOR MANUFACTURING A HIGHLY RESISTIVE SEMICONDUCTOR STACK AND ASSOCIATED STACK
DOMAINE TECHNIQUE DE L’INVENTION TECHNICAL FIELD OF THE INVENTION
[0001] Le domaine technique de l’invention est celui des empilements semiconducteurs destinés à former des substrats de silicium sur isolant, aussi appelé substrats « SOI » pour « Silicon On Insulator » en anglais, et plus particulièrement des substrats SOI mis en œuvre dans le domaine des radiofréquences. [0001] The technical field of the invention is that of semiconductor stacks intended to form silicon on insulator substrates, also called “SOI” substrates for “Silicon On Insulator” in English, and more particularly SOI substrates used in the field of radio frequencies.
ARRIÈRE-PLAN TECHNOLOGIQUE DE L’INVENTION TECHNOLOGICAL BACKGROUND OF THE INVENTION
[0002] Les empilements semiconducteurs hautement résistifs, tels que des substrats de silicium sur isolant, ou SOI, sont très utilisés pour des applications radiofréquences car ils favorisent l’intégrité des signaux circulant dans des dispositifs réalisés à leur surface. [0002] Highly resistive semiconductor stacks, such as silicon-on-insulator, or SOI, substrates, are widely used for radio frequency applications because they promote the integrity of the signals circulating in devices made on their surface.
[0003] Un substrat SOI comporte une première couche semiconductrice, en silicium, appelée « couche support » ou « socle », une deuxième couche semiconductrice, en silicium, appelée « couche active ». La couche active est destinée à accueillir des composants microélectroniques, fabriqués dans ou sur la couche active. On parle d’ailleurs dans ce cas de composants « initiaux » ou « front end » encore « FEOL » pour « Front End Of Line » en anglais. La couche active est séparée de la couche support par une couche isolante, par exemple en oxyde de silicium, disposée entre la couche support et la couche active, et plus particulièrement sous la couche active. La couche isolante est alors dite « enterrée » ou « BOX » pour « Burned OXide ». La couche isolante permet de confiner les porteurs de charge majoritaires dans la couche active ce qui permet d’envisager une fréquence de fonctionnement des composants front end qui soit élevée, par exemple jusqu’à plusieurs dizaines de gigahertz. [0003] An SOI substrate comprises a first semiconductor layer, made of silicon, called a “support layer” or “base”, a second semiconductor layer, made of silicon, called “active layer”. The active layer is intended to accommodate microelectronic components, manufactured in or on the active layer. We also speak in this case of “initial” or “front end” components, also “FEOL” for “Front End Of Line” in English. The active layer is separated from the support layer by an insulating layer, for example made of silicon oxide, placed between the support layer and the active layer, and more particularly under the active layer. The insulating layer is then called “buried” or “BOX” for “Burned OXide”. The insulating layer makes it possible to confine the majority charge carriers in the active layer, which makes it possible to envisage a high operating frequency of the front end components, for example up to several tens of gigahertz.
[0004] Toutefois, des porteurs de charges peuvent s’accumuler dans la couche support, au voisinage de la couche isolante, créant une sous-couche conductrice qui pénalise fortement la conduction dans la couche active. Il existe donc un besoin de réduire la circulation de porteurs de charges dans la couche support, au voisinage de la couche isolante. [0005] L’article [« RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate », Dimitri Lederer and Jean-Pierre Raskin, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 7, JULY 2008] apporte une solution à ce problème en formant une couche de piégeage, disposée entre la couche support et la couche isolante, dont le rôle est de piéger les porteurs de charges. La couche de piégeage comprend du silicium polycristallin. Le piégeage des porteurs de charges s’effectue alors au niveau des joints de grains, où sont localisées les liaisons pendantes du silicium. La couche de piégeage est déposée en phase vapeur basse pression (aussi appelée « LPCVD » pour « Low Pressure Chemical Vapor Deposition » en anglais), suivi d’un recuit rapide à une température de 1000 °C, de manière à former les grains de silicium. However, charge carriers can accumulate in the support layer, in the vicinity of the insulating layer, creating a conductive sublayer which strongly penalizes conduction in the active layer. There is therefore a need to reduce the circulation of charge carriers in the support layer, in the vicinity of the insulating layer. [0005] The article [“RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate”, Dimitri Lederer and Jean-Pierre Raskin, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 7, JULY 2008] provides a solution to this problem by forming a trapping layer, placed between the support layer and the insulating layer, the role of which is to trap the charge carriers. The trapping layer includes polycrystalline silicon. The charge carriers are then trapped at the grain boundaries, where the dangling silicon bonds are located. The trapping layer is deposited in low pressure vapor phase (also called “LPCVD” for “Low Pressure Chemical Vapor Deposition” in English), followed by rapid annealing at a temperature of 1000 ° C, so as to form the grains of silicon.
[0006] L’efficacité de la couche de piégeage repose sur la densité de liaisons pendantes du silicium et donc sur la densité de joints de grains. Or les traitements thermiques mis en œuvre pendant la fabrication des composants microélectroniques au niveau de la couche active tendent à réduire le nombre de grains et donc réduire le nombre de joints de grains. La couche de piégeage en silicium polycristallin impose donc un budget thermique restreint. [0006] The effectiveness of the trapping layer is based on the density of pendant silicon bonds and therefore on the density of grain boundaries. However, the heat treatments implemented during the manufacturing of microelectronic components at the active layer tend to reduce the number of grains and therefore reduce the number of grain boundaries. The polycrystalline silicon trapping layer therefore imposes a restricted thermal budget.
[0007] Une autre approche du piégeage des porteurs de charges consiste à former des bulles dans la couche support, au voisinage de l’interface entre la couche support et la couche isolante. Les liaisons pendantes au niveau de la surface libre de chaque bulle permettent alors le piégeage des porteurs de charges. L’article [« Chemical and electrical properties of cavities in silicon and germanium », S.M. Myers, D.M. Follstaedt, G.A. Petersen, C.H. Seager, H.J. Stein & W.R. Wampler, Nuclear instruments and Methods in Physics Research B 106 (1995) 379-385] décrit un procédé de formation de bulles dans une couche de silicium par implantation d’ions d’hélium. Toutefois, les bulles formées sont éloignées d’environ 200 nm de l’interface entre la couche support et la couche isolante. De plus, la densité maximale de bulles se trouve localisée à une distance de l’interface comprise entre 1000 nm et 1500 nm. La capacitée de piégeage au niveau de l’interface est donc limitée. De plus, moduler l’énergie d’implantation pour rapprocher les bulles de l’interface pourrait provoquer une exfoliation de la couche isolante. En outre, le temps d’implantation peut être long (de l’ordre de 20 min pour implanter des ions à dans un substrat de 300 mm de diamètre, sous un courant d’implantation de 10 mA et une dose de 1017 cm’2). [0008] Une autre solution connue est décrite dans le document FR3091011 A1 qui divulgue un substrat SOI comprenant une couche de carbure de silicium polycristallin s’étendant à la surface de la couche support. La couche de carbure est préférentiellement polycristalline et permet ainsi de piéger les porteurs de charges, de la même façon qu’une couche de piégeage en silicium polycristallin. La croissance de la couche de carbure est réalisée par croissance à partir de la couche support au moyen d’un précurseur carboné ou par CVD. Toutefois, l’épaisseur de la couche de carbure divulguée est limitée à 5 nm. Or à faible épaisseur, la couche de carbure est fragile chimiquement et peut être contaminée par des espèces apportées lors des étapes de fabrication complémentaires (telles que la fabrication de la couche isolante et/ou de la couche active) et ayant migrées jusqu’à la couche de carbure. [0007] Another approach to trapping charge carriers consists of forming bubbles in the support layer, in the vicinity of the interface between the support layer and the insulating layer. The pendant bonds at the free surface of each bubble then allow the trapping of the charge carriers. The article [“Chemical and electrical properties of cavities in silicon and germanium”, SM Myers, DM Follstaedt, GA Petersen, CH Seager, HJ Stein & WR Wampler, Nuclear instruments and Methods in Physics Research B 106 (1995) 379-385 ] describes a process for forming bubbles in a silicon layer by implantation of helium ions. However, the bubbles formed are approximately 200 nm away from the interface between the support layer and the insulating layer. In addition, the maximum bubble density is located at a distance from the interface of between 1000 nm and 1500 nm. The trapping capacity at the interface level is therefore limited. Furthermore, modulating the implantation energy to bring the bubbles closer to the interface could cause exfoliation of the insulating layer. In addition, the implantation time can be long (of the order of 20 min to implant ions in a substrate of 300 mm in diameter, under an implantation current of 10 mA and a dose of 10 17 cm' 2 ). Another known solution is described in document FR3091011 A1 which discloses an SOI substrate comprising a layer of polycrystalline silicon carbide extending on the surface of the support layer. The carbide layer is preferably polycrystalline and thus makes it possible to trap the charge carriers, in the same way as a polycrystalline silicon trapping layer. The growth of the carbide layer is carried out by growth from the support layer using a carbon precursor or by CVD. However, the thickness of the disclosed carbide layer is limited to 5 nm. However, at a low thickness, the carbide layer is chemically fragile and can be contaminated by species brought during additional manufacturing stages (such as the manufacturing of the insulating layer and/or the active layer) and having migrated up to the carbide layer.
[0009] Il existe donc un besoin de fournir un empilement semiconducteur permettant de piéger efficacement les porteurs de charges dans la couche support qui soit également robuste vis-à-vis des étapes complémentaires de fabrication (telles que la fabrication de la couche isolante, de la couche active ou encore des composants « front end »). [0009] There is therefore a need to provide a semiconductor stack making it possible to effectively trap the charge carriers in the support layer which is also robust with respect to complementary manufacturing steps (such as the manufacturing of the insulating layer, the active layer or even “front end” components).
RÉSUMÉ DE L’INVENTION SUMMARY OF THE INVENTION
[0010] L’invention concerne un procédé de fabrication d’un empilement semiconducteur, comprenant, à partir d’une première couche de silicium, dite couche support : la formation d’une couche en carbure de silicium, s’étendant sur la couche support, présentant une épaisseur, mesurée depuis la couche support, supérieure à 5 nm, une fraction d’atomes de carbone de la couche de carbure de silicium, à moins de 20 nm de la couche support, étant strictement supérieure à 50 % ; et le recuit de la couche support et de la couche en carbure de silicium jusqu’à former des cavités, chaque cavité s’étendant dans la couche support, depuis la couche en carbure de silicium, une concentration en oxygène au contact de la couche de carbure de silicium, lors de l’étape de recuit, étant inférieure à 10 ppm et de préférence inférieure à 5 ppm, voire nulle. [0011] Lors du recuit, les atomes de silicium de la couche support migrent vers la couche de carbure formant ainsi, depuis la couche de carbure, des cavités, c’est-à- dire des zones creuses localisées dans la couche support. [0010] The invention relates to a method of manufacturing a semiconductor stack, comprising, from a first layer of silicon, called support layer: the formation of a layer of silicon carbide, extending over the layer support, having a thickness, measured from the support layer, greater than 5 nm, a fraction of carbon atoms of the silicon carbide layer, less than 20 nm from the support layer, being strictly greater than 50%; and annealing the support layer and the silicon carbide layer until forming cavities, each cavity extending into the support layer, from the silicon carbide layer, an oxygen concentration in contact with the silicon carbide layer. silicon carbide, during the annealing step, being less than 10 ppm and preferably less than 5 ppm, or even zero. [0011] During annealing, the silicon atoms of the support layer migrate towards the carbide layer thus forming, from the carbide layer, cavities, that is to say hollow zones located in the support layer.
[0012] Les cavités formées dans la couche support apportent des liaisons pendantes de silicium et permettent ainsi de piéger les porteurs de charges dans la couche support. L’agencement des cavités permet de piéger efficacement les porteurs de charge au plus près de l’interface entre la couche support et la couche de carbure. [0012] The cavities formed in the support layer provide pendant silicon bonds and thus make it possible to trap the charge carriers in the support layer. The arrangement of the cavities makes it possible to effectively trap the charge carriers as close as possible to the interface between the support layer and the carbide layer.
[0013] De plus, le carbure de silicium présente est un semiconducteur présentant une bande interdite indirecte dont l’écart est supérieur à 2 eV, voire 3 eV. La couche de carbure empêche ainsi la circulation de porteurs de charges au voisinage de la couche isolante. [0013] Furthermore, the silicon carbide present is a semiconductor having an indirect band gap whose deviation is greater than 2 eV, or even 3 eV. The carbide layer thus prevents the circulation of charge carriers in the vicinity of the insulating layer.
[0014] Puisque le piégeage, ne repose pas sur la présence de joints de grains, qui sont sensibles à la température, l’empilement présente alors une stabilité morphologique améliorée. De plus, lors d’un traitement thermique, la température impliquant la coalescence des cavités est nettement supérieure à la température impliquant la coalescence des grains dans une structure polycristalline. La température impliquant la coalescence des cavités est d’ailleurs supérieure aux températures mises en œuvre lors d’étapes de fabrication complémentaires. De plus, alors, que la coalescence des grains s’accompagne d’une disparition de pièges, la coalescence éventuelle des cavités se fait à surface constante. [0014] Since trapping does not rely on the presence of grain boundaries, which are sensitive to temperature, the stack then has improved morphological stability. Furthermore, during heat treatment, the temperature involving the coalescence of cavities is significantly higher than the temperature involving the coalescence of grains in a polycrystalline structure. The temperature involving the coalescence of the cavities is also higher than the temperatures used during additional manufacturing stages. Moreover, while the coalescence of the grains is accompanied by a disappearance of traps, the possible coalescence of the cavities takes place at a constant surface.
[0015] La couche en carbure de silicium étant plus riche en carbone, elle permet d’activer la migration des atomes de silicium de la couche support lors du recuit et former efficacement les cavités. [0015] The silicon carbide layer being richer in carbon, it makes it possible to activate the migration of the silicon atoms from the support layer during annealing and effectively form the cavities.
[0016] L’épaisseur de la couche de carbure de silicium supérieure à 5 nm améliore sa robustesse, notamment chimique, vis-à-vis des étapes complémentaires de fabrication (telles que la fabrication des composants « front end »). En effet, elle est moins affectée par les contaminants pouvant migrer. [0016] The thickness of the silicon carbide layer greater than 5 nm improves its robustness, particularly chemical, with respect to additional manufacturing steps (such as the manufacturing of “front end” components). In fact, it is less affected by contaminants that can migrate.
[0017] La couche de carbure de silicium peut subir une oxydation par piqûres (dit également par piqûration ou « pitting » en anglais) lorsqu’elle est recuite dans un environnement comprenant de l’oxygène. Le pitting endommage la couche de carbure de silicium et peut freiner la migration des atomes de silicium et donc la formation des cavités. Le recuit réalisé dans une atmosphère pauvre en oxygène permet de limiter l’apparition de pitting et permet donc d’améliorer la reproductibilité du procédé. [0017] The silicon carbide layer can undergo oxidation by pitting (also known as pitting) when it is annealed in an environment comprising oxygen. Pitting damages the silicon carbide layer and can slow down the migration of silicon atoms and therefore the formation of cavities. Annealing carried out in an atmosphere poor in oxygen limits the appearance of pitting and therefore improves the reproducibility of the process.
[0018] Enfin, le procédé ne s’appuie pas sur l’implantation d’ions pour former les cavités, simplifiant sa mise en œuvre. [0018] Finally, the process does not rely on the implantation of ions to form the cavities, simplifying its implementation.
[0019] Le recuit peut être réalisé pendant une durée comprise entre 15 min et 2 h à une température comprise entre 900 °C et 1100 °C. [0019] Annealing can be carried out for a period of between 15 min and 2 h at a temperature of between 900°C and 1100°C.
[0020] La couche de carbure de silicium issue de l’étape de formation est avantageusement amorphe et le recuit des couches est avantageusement réalisé de manière à cristalliser la couche de carbure de silicium selon un arrangement polycristallin. The layer of silicon carbide resulting from the formation step is advantageously amorphous and the annealing of the layers is advantageously carried out so as to crystallize the layer of silicon carbide in a polycrystalline arrangement.
[0021] La couche support est avantageusement orientée dans un plan. The support layer is advantageously oriented in a plane.
[0022] Une fraction d’atomes de carbone de la couche de carbure de silicium, à moins de 20 nm de la couche support, mesuré perpendiculairement au plan, est avantageusement inférieure ou égale à 70 %. [0022] A fraction of carbon atoms of the silicon carbide layer, less than 20 nm from the support layer, measured perpendicular to the plane, is advantageously less than or equal to 70%.
[0023] L’épaisseur de la couche de carbure de silicium est préférentiellement inférieure à 500 nm. The thickness of the silicon carbide layer is preferably less than 500 nm.
[0024] Chaque cavité peut présenter des facettes, chaque facette étant préférentiellement orientée parallèlement à un plan cristallographique faisant, par exemple, partie de la famille de plans cristallographiques {111} ou partie de la famille de plans cristallographiques {113}. [0024] Each cavity may have facets, each facet being preferably oriented parallel to a crystallographic plane forming, for example, part of the family of crystallographic planes {111} or part of the family of crystallographic planes {113}.
[0025] Les cavités s’étendent sur une distance, mesurée perpendiculairement au plan et depuis la couche de carbure de silicium, comprise préférentiellement entre 5 nm et 100 nm. The cavities extend over a distance, measured perpendicular to the plane and from the layer of silicon carbide, preferably between 5 nm and 100 nm.
[0026] Le procédé comprend préférentiellement la formation d’une couche isolante s’étendant sur la couche de carbure de silicium. La couche isolante est avantageusement destinée à former une couche « enterrée » dite « BOX » pour « Burned OXide » en anglais. The method preferably comprises the formation of an insulating layer extending over the layer of silicon carbide. The insulating layer is advantageously intended to form a “buried” layer called “BOX” for “Burned OXide” in English.
[0027] Selon un premier mode de mise en œuvre, la formation de la couche isolante est réalisée par dépôt, avant ledit recuit. [0028] Le recuit de de la couche support, de la couche en carbure de silicium et de la couche isolante peut être réalisé sous une atmosphère comprenant une concentration en oxygène inférieure à 1 %. According to a first mode of implementation, the formation of the insulating layer is carried out by deposition, before said annealing. [0028] The annealing of the support layer, the silicon carbide layer and the insulating layer can be carried out under an atmosphere comprising an oxygen concentration of less than 1%.
[0029] Selon un deuxième mode de mise en œuvre, la formation de la couche isolante est réalisée par transfert à partir d’un substrat donneur, après le recuit des couches. According to a second mode of implementation, the formation of the insulating layer is carried out by transfer from a donor substrate, after annealing of the layers.
[0030] De manière commune aux deux modes de mise en œuvre précités, le procédé peut comprendre la formation d’une deuxième couche cristalline, s’étendant sur la couche isolante. La couche isolante forme alors une couche « BOX ». [0030] Common to the two aforementioned implementation modes, the method can include the formation of a second crystalline layer, extending over the insulating layer. The insulating layer then forms a “BOX” layer.
[0031] Un autre aspect de l’invention concerne un empilement semiconducteur comprenant : une première couche en silicium, dite couche support ; une couche de carbure de silicium, s’étendant sur la couche support, présentant une épaisseur, mesurée depuis la couche support, supérieure à 5 nm ; et des cavités, chaque cavité s’étendant dans la couche support depuis la couche de carbure de silicium. Another aspect of the invention relates to a semiconductor stack comprising: a first silicon layer, called the support layer; a layer of silicon carbide, extending over the support layer, having a thickness, measured from the support layer, greater than 5 nm; and cavities, each cavity extending into the support layer from the silicon carbide layer.
[0032] La couche de carbure de silicium est avantageusement polycristalline. The silicon carbide layer is advantageously polycrystalline.
[0033] Avantageusement, la couche support est orientée dans un plan et les cavités s’étendent sur une distance, mesurée perpendiculairement au plan et depuis la couche de carbure de silicium, comprise entre 5 nm et 100 nm. Advantageously, the support layer is oriented in a plane and the cavities extend over a distance, measured perpendicular to the plane and from the silicon carbide layer, of between 5 nm and 100 nm.
[0034] Avantageusement, lorsque les cavités s’étendent sur une distance, mesurée perpendiculairement au plan et depuis la couche de carbure de silicium, supérieure à 15 nm, alors chaque cavité présente des facettes, chaque facette étant orientée parallèlement à un plan cristallographique. Advantageously, when the cavities extend over a distance, measured perpendicular to the plane and from the layer of silicon carbide, greater than 15 nm, then each cavity has facets, each facet being oriented parallel to a crystallographic plane.
[0035] Avantageusement, chaque cavité présente une forme pyramidale et présente une base alignée avec l’interface entre la couche support et la couche de carbure de silicium. Advantageously, each cavity has a pyramidal shape and has a base aligned with the interface between the support layer and the silicon carbide layer.
[0036] Avantageusement, Le sommet de la pyramide s’étend dans la couche support. [0037] Avantageusement, les cavités sont uniquement situées à l’interface entre la couche support et la couche de carbure de silicium. Autrement dit, chaque cavité s’étend uniquement dans la couche support depuis la couche de carbure de silicium. Advantageously, the top of the pyramid extends into the support layer. Advantageously, the cavities are only located at the interface between the support layer and the silicon carbide layer. In other words, each cavity extends only into the support layer from the silicon carbide layer.
[0038] Avantageusement, la couche de carbure de silicium est non-poreuse. Advantageously, the silicon carbide layer is non-porous.
[0039] Avantageusement, chaque cavité présente une surface libre entourant un volume intérieur, au moins une portion de la surface libre séparant ledit volume intérieur de la couche support et au moins une autre portion de la surface libre séparant le volume intérieur de la couche de carbure de silicium. Advantageously, each cavity has a free surface surrounding an interior volume, at least one portion of the free surface separating said interior volume from the support layer and at least one other portion of the free surface separating the interior volume from the layer of silicon carbide.
[0040] Avantageusement, chaque portion de la surface libre séparant le volume intérieur de la cavité de la couche support comprend des atomes de silicium dont une partie au moins présente une liaison pendante. Advantageously, each portion of the free surface separating the interior volume of the cavity of the support layer comprises silicon atoms, at least part of which has a pendant bond.
[0041] L’invention et ses différentes applications seront mieux comprises à la lecture de la description qui suit et à l’examen des figures qui l’accompagnent. [0041] The invention and its various applications will be better understood on reading the following description and examining the accompanying figures.
BRÈVE DESCRIPTION DES FIGURES BRIEF DESCRIPTION OF THE FIGURES
[0042] Les figures sont présentées à titre indicatif et nullement limitatif de l’invention. Sauf précision contraire, un même élément apparaissant sur des figures différentes présente une référence unique. [0042] The figures are presented for information purposes only and in no way limit the invention. Unless otherwise specified, the same element appearing in different figures presents a unique reference.
[0043] [Fig. 1 ] représente schématiquement un premier mode de réalisation d’un empilement semiconducteur selon l’invention. [0043] [Fig. 1] schematically represents a first embodiment of a semiconductor stack according to the invention.
[0044] [Fig. 2] représente schématiquement un premier mode de mise en œuvre d’un procédé de fabrication selon l’invention. [0044] [Fig. 2] schematically represents a first mode of implementation of a manufacturing process according to the invention.
[0045] [Fig. 3a] représente schématiquement un premier exemple d’une première étape du procédé de fabrication selon l’invention. [0045] [Fig. 3a] schematically represents a first example of a first step of the manufacturing process according to the invention.
[0046] [Fig. 3b] représente schématiquement un deuxième exemple de la première étape du procédé de fabrication selon l’invention. [0046] [Fig. 3b] schematically represents a second example of the first step of the manufacturing process according to the invention.
[0047] [Fig. 4] représente schématiquement une deuxième étape du procédé de fabrication selon l’invention. [0047] [Fig. 4] schematically represents a second step of the manufacturing process according to the invention.
[0048] [Fig. 5] représente schématiquement une troisième étape du procédé de fabrication selon l’invention. [0049] [Fig. 6] représente schématiquement une quatrième étape du procédé de fabrication selon l’invention. [0048] [Fig. 5] schematically represents a third step of the manufacturing process according to the invention. [0049] [Fig. 6] schematically represents a fourth step of the manufacturing process according to the invention.
[0050] [Fig. 7] représente schématiquement un deuxième mode de mise en œuvre d’un procédé de fabrication selon l’invention. [0050] [Fig. 7] schematically represents a second mode of implementation of a manufacturing process according to the invention.
[0051] [Fig. 8] représente schématiquement une cinquième étape du procédé de fabrication selon l’invention. [0051] [Fig. 8] schematically represents a fifth step of the manufacturing process according to the invention.
[0052] [Fig. 9] représente une image obtenue par microscopie en transmission d’un empilement semiconducteur fabriqué au moyen du procédé de fabrication selon l’invention. [0052] [Fig. 9] represents an image obtained by transmission microscopy of a semiconductor stack manufactured using the manufacturing process according to the invention.
DESCRIPTION DÉTAILLÉE DETAILED DESCRIPTION
[0053] L’invention se propose d’améliorer les empilements semiconducteurs destinés à former un substrat SOI et notamment un substrat destiné aux applications radiofréquences. [0053] The invention aims to improve the semiconductor stacks intended to form an SOI substrate and in particular a substrate intended for radio frequency applications.
[0054] La [Fig. 1 ] représente schématiquement un premier mode de réalisation d’un empilement semiconducteur 10 selon l’invention. L’empilement 10 comprend une première couche en silicium 11 , dite couche support ; une couche de carbure de silicium 12 ; et des cavités 13. [0054] [Fig. 1] schematically represents a first embodiment of a semiconductor stack 10 according to the invention. The stack 10 comprises a first silicon layer 11, called the support layer; a layer of silicon carbide 12; and cavities 13.
[0055] La couche support 11 s’étend par exemple selon un plan P donné. Il s’agit par exemple du plan d’une tranche de silicium à partir de laquelle va être formée un substrat SOI. La couche support 11 est avantageusement un support résistif, c’est à dire présentant une résistivité supérieure à 1 kQ cm. The support layer 11 extends for example along a given plane P. This is, for example, the plane of a silicon wafer from which an SOI substrate will be formed. The support layer 11 is advantageously a resistive support, that is to say having a resistivity greater than 1 kΩ cm.
[0056] La couche de carbure de silicium 12 (également appelée couche de SiC) s’étend sur la couche support 11 selon le plan P donné. La couche de SiC 12 est directement au contact de la couche support 11 , formant ainsi une interface 112 entre les deux couches. The silicon carbide layer 12 (also called SiC layer) extends over the support layer 11 along the given plane P. The SiC layer 12 is directly in contact with the support layer 11, thus forming an interface 112 between the two layers.
[0057] L’empilement 10 est remarquable en ce qu’il comprend une pluralité de cavité 13 s’étendant dans la couche support 11 . Chaque cavité 13 est creuse, c’est à dire vide de tout matériau solide ou liquide. Elles peuvent comprendre une espèce sous forme gazeuse présentant une pression partielle faible. Elles sont toutefois préférentiellement complètement vides. Chaque cavité 13 s’étend dans la couche support 11 , depuis la couche de SiC 12. C’est à dire que chaque cavité 13 s’étend dans la couche support 11 depuis l’interface 112. Chaque cavité 13 présente alors une surface libre 131 , 132 entourant un volume intérieur 130 de la cavité 13. Au moins une portion 131 de la surface libre sépare ledit volume intérieur 130 de la couche support 11 et au moins une autre portion 132 de la surface libre sépare le volume intérieur 130 de la cavité de la couche de SiC 12. The stack 10 is remarkable in that it comprises a plurality of cavities 13 extending into the support layer 11. Each cavity 13 is hollow, that is to say empty of any solid or liquid material. They may include a species in gaseous form having a low partial pressure. They are, however preferably completely empty. Each cavity 13 extends into the support layer 11, from the SiC layer 12. That is to say that each cavity 13 extends into the support layer 11 from the interface 112. Each cavity 13 then presents a free surface 131, 132 surrounding an interior volume 130 of the cavity 13. At least one portion 131 of the free surface separates said interior volume 130 from the support layer 11 and at least one other portion 132 of the free surface separates the interior volume 130 from the cavity of the SiC layer 12.
[0058] La ou les portions 131 de la surface libre séparant le volume intérieur 130 de la cavité de la couche support 11 sont formées d’atomes de silicium dont une partie au moins présente une liaison pendante (« dangling bonds » en anglais). Par liaison pendante, on entend une orbitale atomique non impliquée dans une liaison chimique avec d’autres éléments. Les liaisons pendantes permettent des piéger les porteurs de charges circulant dans la couche support 11 et au voisinage de la couche de SiC 12. The portion(s) 131 of the free surface separating the interior volume 130 from the cavity of the support layer 11 are formed of silicon atoms, at least part of which has a dangling bond. By dangling bond we mean an atomic orbital not involved in a chemical bond with other elements. The pendant connections make it possible to trap the charge carriers circulating in the support layer 11 and in the vicinity of the SiC layer 12.
[0059] Les liaisons pendantes et les cavités permettent également de piéger des impuretés, telles que des ions ou atomes d’hydrogène, des atomes d’hélium ou des métaux comme le lithium ou le cuivre, ayant migrées dans la couche support 11 lors, par exemple, d’étapes de fabrication additionnelles (telles que la fabrication de composants « front end »). La résistivité de la couche support 11 n’est donc pas dégradée par lors d’étapes de fabrication additionnelles. [0059] The pendant bonds and the cavities also make it possible to trap impurities, such as hydrogen ions or atoms, helium atoms or metals such as lithium or copper, having migrated into the support layer 11 during, for example, additional manufacturing steps (such as the manufacturing of “front end” components). The resistivity of the support layer 11 is therefore not degraded by additional manufacturing steps.
[0060] La stabilité thermodynamique des cavités 13 et leur formation par diffusion tendent à favoriser un facettage des cavités. Des portions 131 de la surface libre 131 , 132 de chaque cavité 13 s’alignent alors préférentiellement selon des plans cristallographiques de la couche support 11. Par exemple, lorsque la couche support 11 présente un plan (001 ), au niveau de l’interface 112 avec la couche de SiC 12 (c’est à dire que le plan (001 ) et le plan P coïncident), les cavités 13 peuvent être facettées en présentant des portions parallèles à des plans cristallographies de la famille de plans {111 } (c’est à dire les plans (111 ), (-111 ), (1 -11 ) et (-1 -11 )) ou de la famille de plans {113} (c’est à dire les plans (113), (-113), (1 -13) et (-1 -13)). Les cavités 13 peuvent alors présenter une forme de pyramide inversée, à base carrée ou à base triangulaire, dont ladite base coïncide avec l’interface entre la couche support 11 et la couche de SiC 12. Toutefois, le facettage ne dépend pas nécessairement du plan au niveau de l’interface 112 de la couche support 11 avec la couche de SiC 12. D’autres familles de plans cristallographiques sont envisageables. [0061] Afin de déterminer l’orientation des plans cristallographiques, il est avantageux de considérer les cavités 13 s’étendant sur une distance 133, mesurée perpendiculairement au plan P, supérieure à 15 nm. En effet, au-deçà, il peut être difficile de distinguer les familles de plans {113}. [0060] The thermodynamic stability of the cavities 13 and their formation by diffusion tend to favor faceting of the cavities. Portions 131 of the free surface 131, 132 of each cavity 13 then align preferentially along crystallographic planes of the support layer 11. For example, when the support layer 11 has a plane (001), at the level of the interface 112 with the SiC layer 12 (that is to say that the plane (001) and the plane P coincide), the cavities 13 can be faceted by presenting portions parallel to crystallographic planes of the family of planes {111} ( that is to say the planes (111), (-111), (1 -11) and (-1 -11)) or of the family of planes {113} (that is to say the planes (113), (-113), (1 -13) and (-1 -13)). The cavities 13 can then have the shape of an inverted pyramid, with a square base or a triangular base, said base of which coincides with the interface between the support layer 11 and the SiC layer 12. However, the faceting does not necessarily depend on the plane at the interface 112 of the support layer 11 with the SiC layer 12. Other families of crystallographic planes are possible. [0061] In order to determine the orientation of the crystallographic planes, it is advantageous to consider the cavities 13 extending over a distance 133, measured perpendicular to the plane P, greater than 15 nm. Indeed, beyond that, it can be difficult to distinguish the families of plans {113}.
[0062] La [Fig. 1 ] représente par des flèches les directions [111 ] et [001 ], normales aux plans cristallographiques (001 ) et (111 ). [0062] [Fig. 1] represents by arrows the directions [111] and [001], normal to the crystallographic planes (001) and (111).
[0063] Chaque cavité 13 s’étend préférentiellement depuis la couche de SiC 12 sur une distance 133 comprise entre 5 nm et 100 nm. Ladite distance 133 est mesurée perpendiculairement au plan P dans lequel s’étend la couche de SiC 12, c’est à dire selon [001 ] dans l’exemple présent. Ladite distance 133 est mesurée depuis la couche de carbure 12, c’est à dire depuis l’interface 112 séparant la couche support 11 et la couche de carbure 12. [0063] Each cavity 13 preferably extends from the SiC layer 12 over a distance 133 of between 5 nm and 100 nm. Said distance 133 is measured perpendicular to the plane P in which the layer of SiC 12 extends, that is to say along [001] in the present example. Said distance 133 is measured from the carbide layer 12, that is to say from the interface 112 separating the support layer 11 and the carbide layer 12.
[0064] Dans l’exemple de la [Fig. 1], l’empilement 10 comprend également une couche isolante 14 et une couche active 15. De la sorte, l’empilement 10 forme un substrat SOI. La couche isolante 14 s’étend sur la couche de SiC 12. Elle présente avantageusement une épaisseur comprise entre 100 nm et 1000 nm. Elle comprend par exemple un oxyde, tel que de l’oxyde de silicium SiÛ2. La couche active 15 comprend un semiconducteur cristallin ou polycristallin et s’étend sur la couche isolante 14. La couche isolante 14 sépare ainsi la couche de SiC 12 et la couche active 15. Elle est dite « enterrée » sous la couche active 15. La couche active 15 présente avantageusement une épaisseur comprise entre 50 nm et 500 nm et comprend par exemple du silicium cristallin ou du silicium polycristallin ou un autre matériau semiconducteur cristallin utilisé dans le domaine des radiofréquences, tel que le phosphure d’indium ou le nitrure de gallium. [0064] In the example of [Fig. 1], the stack 10 also comprises an insulating layer 14 and an active layer 15. In this way, the stack 10 forms an SOI substrate. The insulating layer 14 extends over the SiC layer 12. It advantageously has a thickness of between 100 nm and 1000 nm. It comprises, for example, an oxide, such as silicon oxide SiÛ2. The active layer 15 comprises a crystalline or polycrystalline semiconductor and extends over the insulating layer 14. The insulating layer 14 thus separates the SiC layer 12 and the active layer 15. It is said to be “buried” under the active layer 15. active layer 15 advantageously has a thickness of between 50 nm and 500 nm and comprises for example crystalline silicon or polycrystalline silicon or another crystalline semiconductor material used in the field of radio frequencies, such as indium phosphide or gallium nitride .
[0065] La couche de SiC 12 est avantageusement polycristalline. Ainsi, elle contribue ainsi au piégeage des porteurs de charges, de la même manière qu’une couche de piégeage en silicium polycristallin, tel que décrit dans l’art antérieur. Les porteurs de charges sont piégés par les liaisons pendantes localisées au niveau des joints de grains de l’arrangement polycristallin. The SiC 12 layer is advantageously polycrystalline. Thus, it contributes to the trapping of charge carriers, in the same way as a polycrystalline silicon trapping layer, as described in the prior art. The charge carriers are trapped by the dangling bonds located at the grain boundaries of the polycrystalline arrangement.
[0066] La [Fig. 2] représente schématiquement un procédé de fabrication selon l’invention, permettant de fabriquer l’empilement 10. [0067] Le procédé 20 de fabrication comprend, à partir d’une couche support 11 , une étape de formation 22 d’une couche en carbure de silicium 12 (dite couche de SiC), s’étendant sur la couche support 11. Deux exemples de couche de carbure de silicium 12 obtenue sont illustrés en [Fig. 3a] et [Fig. 3b], [0066] [Fig. 2] schematically represents a manufacturing process according to the invention, making it possible to manufacture the stack 10. [0067] The manufacturing method 20 comprises, from a support layer 11, a step 22 of forming a layer of silicon carbide 12 (called SiC layer), extending over the support layer 11. Two Examples of silicon carbide layer 12 obtained are illustrated in [Fig. 3a] and [Fig. 3b],
[0068] La couche de SiC 12 est par exemple formée 22 par dépôt en phase vapeur, aussi appelée « CVD » pour « Chemical Vapor Deposition » en anglais, à partir de la couche support 11. Il s’agit par exemple d’un dépôt CVD assisté par plasma (ou « PECVD » pour « Plasma Enhanced CVD » en anglais). La couche de SiC 12 est par exemple obtenue par dépôt PECVD d’un précurseur carboné, tel que le tétraméthylsilane Si(CH3)4, aussi appelé « TMS ». La couche de SiC 12 produite s’étend alors sur la couche support 11 . [0068] The SiC layer 12 is for example formed 22 by vapor phase deposition, also called "CVD" for "Chemical Vapor Deposition" in English, from the support layer 11. It is for example a plasma-assisted CVD deposition (or “PECVD” for “Plasma Enhanced CVD” in English). The SiC 12 layer is for example obtained by PECVD deposition of a carbon precursor, such as tetramethylsilane Si(CH3)4, also called “TMS”. The SiC layer 12 produced then extends over the support layer 11.
[0069] La couche support 11 s’étend dans un plan P. Elle présente préférentiellement un plan cristallographique (001 ) dans le plan P. La couche de SiC 12 présente une épaisseur 121 , mesurée depuis la couche support 11 et perpendiculairement au plan P, supérieure à 5 nm et avantageusement inférieure à 500 nm. [0069] The support layer 11 extends in a plane P. It preferably has a crystallographic plane (001) in the plane P. The SiC layer 12 has a thickness 121, measured from the support layer 11 and perpendicular to the plane P. , greater than 5 nm and advantageously less than 500 nm.
[0070] Le procédé 20 comprend en outre une étape de recuit 23 de la couche support 11 et de la couche de SiC 12 jusqu’à former des cavités 13 s’étendant dans la couche support 11 , telles qu’illustrées en [Fig. 4], Chaque cavité 13 s’étend alors dans la couche support 11 , depuis la couche en SiC 12. Lors du recuit 23, la température augmente la mobilité des atomes de silicium de la couche support 11 et une partie de ces atomes, notamment ceux proches de la couche de SiC 12. La différence de fractions d’atomes de silicium entre la couche support 11 et la couche de SiC 12 tend à orienter la migration des atomes de silicium de la couche support 11 vers la couche de SiC 12, creusant ainsi plusieurs cavités 13 dans la couche support 11 . La formation de chaque cavité 13 trouve alors son point de départ au niveau de l’interface entre la couche support 11 et la couche de SiC 12. Chaque cavité 13 s’étend ensuite dans la couche support 11 selon une direction sensiblement perpendiculaire au plan P. Par sensiblement perpendiculaire, on entend perpendiculaire à 20° près. Le recuit 23 de la couche support 11 et de la couche de SiC 12 est préférentiellement simultané. [0070] The method 20 further comprises a step 23 of annealing the support layer 11 and the SiC layer 12 until forming cavities 13 extending into the support layer 11, as illustrated in [Fig. 4], Each cavity 13 then extends into the support layer 11, from the SiC layer 12. During annealing 23, the temperature increases the mobility of the silicon atoms of the support layer 11 and a part of these atoms, in particular those close to the SiC layer 12. The difference in fractions of silicon atoms between the support layer 11 and the SiC layer 12 tends to direct the migration of the silicon atoms from the support layer 11 towards the SiC layer 12, thus digging several cavities 13 in the support layer 11. The formation of each cavity 13 then finds its starting point at the interface between the support layer 11 and the SiC layer 12. Each cavity 13 then extends into the support layer 11 in a direction substantially perpendicular to the plane P By substantially perpendicular, we mean perpendicular to within 20°. The annealing 23 of the support layer 11 and the SiC layer 12 is preferably simultaneous.
[0071] Puisque la formation de chaque cavité 13 trouve son point de départ au niveau de l’interface entre la couche support 11 et la couche de SiC 12, le procédé forme uniquement des cavités s’étendant depuis l’interface entre la couche support 11 et la couche de SiC 12. Autrement dit, le procédé ne permet pas de former des cavités distantes de ladite interface entre la couche support 11 et la couche de SiC 12 (ces cavités distantes de l’interface pouvant être appelées pores ou bulles). [0071] Since the formation of each cavity 13 finds its starting point at the interface between the support layer 11 and the SiC layer 12, the method only forms cavities extending from the interface between the support layer 11 and the SiC layer 12. In other words, the method does not make it possible to form cavities distant from said interface between the support layer 11 and the SiC layer 12 (these cavities distant from the interface can be called pores or bubbles).
[0072] Lorsque la couche support 11 comprend des défauts tels que des zones amorphes ou des joints de grains, ces défauts peuvent assister ou faciliter la migration des atomes de silicium vers la couche de SiC 12. When the support layer 11 includes defects such as amorphous zones or grain boundaries, these defects can assist or facilitate the migration of silicon atoms towards the SiC layer 12.
[0073] La température de recuit 23 permettant de former des cavités 13 est avantageusement comprise 900 °C et 1100 °C. En deçà de 900 °C, la mobilité des atomes de silicium n’est pas suffisante pour former des cavités 13 dans une durée qui puisse être compatible avec une cadence industrielle. Au-delà de 1100 °C, la mobilité des atomes de silicium est telle qu’elle permet la migration d’atomes entre cavités 13, tendant à former des cavités peu nombreuses mais de très grandes tailles (c’est à dire s’étendant au-delà de 100 nm de la couche de SiC 12). Le piégeage des porteurs de charge est amélioré lorsque la densité de cavités 13 (c’est à dire le nombre de cavités 13 par unité de surface de l’interface 112) croît. Le piégeage est en revanche détérioré lorsque la densité de cavités 13 décroît. [0073] The annealing temperature 23 making it possible to form cavities 13 is advantageously between 900°C and 1100°C. Below 900°C, the mobility of the silicon atoms is not sufficient to form cavities 13 in a duration that can be compatible with an industrial rate. Beyond 1100°C, the mobility of the silicon atoms is such that it allows the migration of atoms between cavities 13, tending to form cavities that are few in number but of very large sizes (i.e. extending beyond 100 nm from the SiC layer 12). The trapping of charge carriers is improved when the density of cavities 13 (i.e. the number of cavities 13 per unit surface of the interface 112) increases. On the other hand, trapping deteriorates when the density of cavities 13 decreases.
[0074] La couche de SiC 12 est avantageusement formée à une température comprise entre 300 °C et 500 °C. De la sorte, elle présente, avant recuit 23, une phase amorphe. Le recuit 23 des couches, et notamment de la couche de SiC 12, entre 900 °C et 1100 °C a pour effet de cristalliser la couche de SiC 12 selon un arrangement polycristallin. Cette cristallisation présente deux effets bénéfiques. Dans un premier temps, les joints de grains de l’arrangement polycristallin apportent une contribution au piégeage des porteurs de charges, renforçant le piégeage réalisé par les cavités 13. Dans un second temps, la cristallisation accélère également la migration des atomes de silicium de la couche support 11 vers la couche de SiC 12, de manière similaire à un pompage d’atomes de silicium, ayant pour effet d’accélérer la cinétique de formation des cavités 13. [0074] The SiC 12 layer is advantageously formed at a temperature between 300°C and 500°C. In this way, it presents, before annealing 23, an amorphous phase. Annealing 23 of the layers, and in particular of the SiC layer 12, between 900°C and 1100°C has the effect of crystallizing the SiC layer 12 in a polycrystalline arrangement. This crystallization has two beneficial effects. Initially, the grain boundaries of the polycrystalline arrangement contribute to the trapping of the charge carriers, reinforcing the trapping achieved by the cavities 13. Secondly, the crystallization also accelerates the migration of the silicon atoms of the support layer 11 towards the SiC layer 12, in a manner similar to a pumping of silicon atoms, having the effect of accelerating the kinetics of formation of the cavities 13.
[0075] La couche de SiC 12 est, avant comme après recuit, non-poreuse. Par exemple, lorsque la couche de SiC 12 est polycristalline (par exemple après recuit), la non-porosité est apportée par les joints de grains de la couche de SiC 12. [0076] Le recuit 23 est avantageusement réalisé pendant une durée comprise entre 15 min et 2 h, de sorte que la migration des atomes de silicium de la couche support 11 permet d’obtenir des cavités 13 s’étendant à au moins 5 nm de la couche de SiC 12 et à au plus 100 nm de cette couche. La dimension des cavités 13 (mesurée perpendiculairement au plan P et depuis la couche de SiC 12) est proportionnelle à la durée du recuit 23. Une durée de recuit de l’ordre de 15 min est compatible avec une cadence industrielle. Une durée de recuit de l’ordre de 2 h permet de former des cavités 13 de grandes tailles, proches de 100 nm, étendant la couverture du piégeage des porteurs de charges dans la couche support 11 . La durée de recuit de l’ordre de 2 h est également compatible avec une cadence industrielle. En effet, le recuit est réalisable en four, permettant de traiter de manière simultanée plusieurs plaques, par exemple plusieurs dizaines. Par contraste, l’implantation ionique pouvant être mise en œuvre dans l’art antérieur réalise un traitement plaque par plaque. The SiC 12 layer is, before and after annealing, non-porous. For example, when the SiC 12 layer is polycrystalline (for example after annealing), the non-porosity is provided by the grain boundaries of the SiC 12 layer. [0076] Annealing 23 is advantageously carried out for a period of between 15 min and 2 h, so that the migration of the silicon atoms of the support layer 11 makes it possible to obtain cavities 13 extending at least 5 nm from the SiC 12 layer and at most 100 nm from this layer. The dimension of the cavities 13 (measured perpendicular to the plane P and from the SiC layer 12) is proportional to the duration of the annealing 23. An annealing duration of the order of 15 min is compatible with an industrial rate. An annealing time of the order of 2 h makes it possible to form cavities 13 of large sizes, close to 100 nm, extending the coverage of the trapping of the charge carriers in the support layer 11. The annealing time of around 2 hours is also compatible with an industrial rate. Indeed, annealing can be carried out in an oven, making it possible to treat several plates simultaneously, for example several dozen. In contrast, the ion implantation that can be implemented in the prior art carries out treatment plate by plate.
[0077] La migration des atomes de silicium, et donc la cinétique de formation des cavités 13, est accélérée lorsque la couche de SiC 12 présente une fraction d’atomes de carbone (aussi appelée fraction de carbone) qui soit, avant recuit 23, au moins égale à la fraction d’atomes de silicium. La couche de SiC 12 présente ainsi, avant recuit 23, une fraction de carbone supérieure à 50 % et avantageusement inférieure à 70 %. La fraction de silicium dans la couche de SiC 12 est ainsi, avant recuit 23, inférieure à 50. [0077] The migration of silicon atoms, and therefore the kinetics of formation of cavities 13, is accelerated when the SiC layer 12 has a fraction of carbon atoms (also called carbon fraction) which is, before annealing 23, at least equal to the fraction of silicon atoms. The SiC layer 12 thus has, before annealing 23, a carbon fraction greater than 50% and advantageously less than 70%. The fraction of silicon in the SiC layer 12 is thus, before annealing 23, less than 50.
[0078] La cinétique de formation des cavités 13 est surtout accélérée lorsque la différence de fractions entre les atomes de carbone et de silicium est importante au voisinage de l’interface 112 entre ladite couche de SiC 12 et la couche support 1 1. La fraction de carbone de la couche de SiC 12 au-delà de 20 nm de la couche support 11 ne montre en revanche pas d’impact significatif sur la cinétique de formation des cavités 13. Aussi, lorsque la couche de SiC 12 présente une épaisseur 121 supérieure à 20 nm (mesurée perpendiculairement au plan P et depuis l’interface 112 avec la couche support 11 ), telle qu’illustrée par la [Fig. 3a], elle présente alors une partie, s’étendant au moins sur 20 nm depuis la couche support 11 et dans laquelle la fraction de carbone est supérieure à 50 % et avantageusement inférieure ou égale à 70 %. Lorsque la couche de SiC 12 présente une épaisseur 121 inférieure ou égale à 20 nm, telle qu’illustrée par la [Fig. 3b], elle présente alors, sur toute son épaisseur 121 , une fraction de carbone supérieure à 50 % et avantageusement inférieure ou égale à 70 %. En d’autres termes, la fraction de carbone de la couche de SiC 12, à moins de 20 nm de la couche support 11 (mesurée perpendiculairement au plan P et depuis l’interface 112), est avantageusement comprise entre 50 % et 70 %. [0078] The kinetics of formation of the cavities 13 is especially accelerated when the difference in fractions between the carbon and silicon atoms is significant in the vicinity of the interface 112 between said SiC layer 12 and the support layer 11. The fraction carbon of the SiC layer 12 beyond 20 nm of the support layer 11 does not, however, show any significant impact on the kinetics of formation of the cavities 13. Also, when the SiC layer 12 has a greater thickness 121 at 20 nm (measured perpendicular to the plane P and from the interface 112 with the support layer 11), as illustrated by [Fig. 3a], it then presents a part, extending at least 20 nm from the support layer 11 and in which the carbon fraction is greater than 50% and advantageously less than or equal to 70%. When the SiC layer 12 has a thickness 121 less than or equal to 20 nm, as illustrated by [Fig. 3b], it then presents, over its entire thickness 121, a carbon fraction greater than 50% and advantageously less than or equal to 70 %. In other words, the carbon fraction of the SiC layer 12, less than 20 nm from the support layer 11 (measured perpendicular to the plane P and from the interface 112), is advantageously between 50% and 70%. .
[0079] La couche de SiC 12 réagit avec l’oxygène et peut s’oxyder, par exemple par piqûres (« pitting » en anglais). Le recuit 23 est donc réalisé en minimisant le contact d’oxygène avec la couche de SiC 12. Le recuit 23 de l’empilement 10 est réalisé en maintenant une concentration d’oxygène en contact avec la couche de SiC 12 qui soit inférieure à 10 ppm, de préférence inférieure à 5 ppm, voire nulle. The SiC 12 layer reacts with oxygen and can oxidize, for example by pitting. Annealing 23 is therefore carried out by minimizing the contact of oxygen with the SiC layer 12. Annealing 23 of the stack 10 is carried out by maintaining a concentration of oxygen in contact with the SiC layer 12 which is less than 10 ppm, preferably less than 5 ppm, or even zero.
[0080] Le recuit 23 est par exemple réalisé dans une atmosphère neutre, comprenant par exemple au moins un gaz neutre tel que l’azote ou l’argon. L’atmosphère neutre est alors dimensionnée de sorte qu’elle présente alors une concentration d’oxygène inférieure à 10 ppm, voire moins, au moins pendant la durée du recuit 23. Annealing 23 is for example carried out in a neutral atmosphere, comprising for example at least one neutral gas such as nitrogen or argon. The neutral atmosphere is then sized so that it then has an oxygen concentration of less than 10 ppm, or even less, at least for the duration of annealing 23.
[0081] Le procédé 20, selon le mode de mise en œuvre de la [Fig. 2], peut également comprendre une étape de formation 25 d’une couche isolante 14 et une étape de formation 26 d’une couche active 15 semiconductrice de sorte que l’empilement 10 final forme un substrat SOI, tel qu’illustré par la [Fig. 1], [0081] Method 20, according to the mode of implementation of [Fig. 2], can also include a step of forming 25 of an insulating layer 14 and a step of forming 26 of an active semiconductor layer 15 so that the final stack 10 forms an SOI substrate, as illustrated by [ Fig. 1],
[0082] La formation 25 de la couche isolante 14, illustrée par la [Fig. 6], est avantageusement réalisée par transfert à partir d’un substrat donneur 30. Le principe du transfert depuis un substrat donneur 30 est connu sous le nom SmartCut(TM). Lorsque la formation 25 de la couche isolante 14 est réalisée par transfert, la formation 26 de la couche active 15 est avantageusement également réalisée par transfert à partir d’un substrat donneur et si possible à partir du même substrat donneur 30. De manière avantageuse, la formation 25, 26 des deux couches précitées est réalisée simultanément. [0082] The formation 25 of the insulating layer 14, illustrated by [Fig. 6], is advantageously carried out by transfer from a donor substrate 30. The principle of transfer from a donor substrate 30 is known under the name SmartCut(TM). When the formation 25 of the insulating layer 14 is carried out by transfer, the formation 26 of the active layer 15 is advantageously also carried out by transfer from a donor substrate and if possible from the same donor substrate 30. Advantageously, the formation 25, 26 of the two aforementioned layers is carried out simultaneously.
[0083] Avant de réaliser la formation 25 de la couche isolante 14, il peut être nécessaire de préparer une surface 122 de la couche de SiC 12, destinée à accueillir la couche isolante 14. Dans ce cas, le procédé 20 comprend, avant la formation 25 de la couche isolante 14, une étape de lissage 24 de ladite surface 122. Le lissage 24, illustré par la [Fig. 5], peut être réalisé par planarisation mécano-chimique ou CMP pour « Chemical Mechanical Polishing » en anglais. Le lissage 24 est réalisé de sorte que la couche de SiC 12 présente une rugosité de surface inférieure ou égale à 5 A. La rugosité de surface est aussi appelée rugosité moyenne ou rugosité « RMS » pour « Root Mean Square » en anglais. La rugosité de la surface 122 de la couche de SiC pourra être évaluée au moyen d’une microscope à force atomique, ou « AFM » pour « Atomic Force Microscope » en anglais. La rugosité peut être évaluée sur une portion de la surface 122 d’environ 1 pm2 [0083] Before forming the insulating layer 14, it may be necessary to prepare a surface 122 of the SiC layer 12, intended to accommodate the insulating layer 14. In this case, the method 20 comprises, before the formation 25 of the insulating layer 14, a step of smoothing 24 of said surface 122. Smoothing 24, illustrated by [Fig. 5], can be carried out by chemical-mechanical planarization or CMP for “Chemical Mechanical Polishing” in English. The smoothing 24 is carried out so that the SiC layer 12 has a surface roughness less than or equal to 5 A. Surface roughness is also called average roughness or “RMS” roughness for “Root Mean Square” in English. The roughness of the surface 122 of the SiC layer can be evaluated using an atomic force microscope, or “AFM” for “Atomic Force Microscope” in English. The roughness can be evaluated on a portion of the surface 122 of approximately 1 pm 2
[0084] Les formations 25, 26 simultanées des couches isolante et active 14, 15 par transfert peuvent être réalisées à partir d’un même substrat donneur 30, ce dernier comprenant alors une couche semiconductrice 35, par exemple en silicium cristallin ou polycristallin ou en phosphure d’indium cristallin ou en nitrure de gallium cristallin, sur laquelle s’étend une couche isolante 34, par exemple en oxyde de silicium. La couche isolante 34 présente par exemple une épaisseur comprise entre 100 nm et 1000 nm. La couche semiconductrice 35 sous-jacente présente par exemple une épaisseur supérieure à 50 nm, voire supérieure à 500 nm. [0084] The simultaneous formations 25, 26 of the insulating and active layers 14, 15 by transfer can be produced from the same donor substrate 30, the latter then comprising a semiconductor layer 35, for example made of crystalline or polycrystalline silicon or of crystalline indium phosphide or crystalline gallium nitride, over which extends an insulating layer 34, for example made of silicon oxide. The insulating layer 34 has, for example, a thickness of between 100 nm and 1000 nm. The underlying semiconductor layer 35 has for example a thickness greater than 50 nm, or even greater than 500 nm.
[0085] Les formations 25, 26 simultanées peuvent alors comprendre une sous- étape d’implantation d’ions légers (par exemple d’ions hydrogène ou hélium) dans la couche semiconductrice 35 du substrat donneur 30 jusqu’à une profondeur comprise entre 50 nm et 500 nm sous la couche isolante 34. L’implantation est par exemple réalisée à une dose de quelques 1016/cm2 et à une énergie de quelques dizaines de keV. [0085] The simultaneous formations 25, 26 can then comprise a sub-step of implanting light ions (for example hydrogen or helium ions) in the semiconductor layer 35 of the donor substrate 30 to a depth of between 50 nm and 500 nm under the insulating layer 34. The implantation is for example carried out at a dose of a few 10 16 /cm 2 and at an energy of a few tens of keV.
[0086] Les formations 25, 26 simultanées comprennent ensuite une sous-étape de nettoyage de la surface libre 341 de la couche isolante 34 du substrat donneur 30, afin de permettre un collage direct entre ladite couche isolante 34 dudit substrat donneur 30 et la couche de SiC 12 de l’empilement 10. Le nettoyage de la surface libre 341 de la couche isolante 34 fait avantageusement intervenir des recettes connues des technologies silicium telles que la recette dite « RCA » (pour « Radio Corporation of America » en anglais) ou encore une recette dite CARO, comprenant un mélange de peroxyde d’hydrogène et d’acide sulfurique. [0086] The simultaneous formations 25, 26 then comprise a sub-step of cleaning the free surface 341 of the insulating layer 34 of the donor substrate 30, in order to allow direct bonding between said insulating layer 34 of said donor substrate 30 and the layer of SiC 12 from the stack 10. The cleaning of the free surface 341 of the insulating layer 34 advantageously involves known recipes from silicon technologies such as the so-called “RCA” recipe (for “Radio Corporation of America” in English) or another recipe called CARO, comprising a mixture of hydrogen peroxide and sulfuric acid.
[0087] Il est toutefois avantageux, pour permettre une bonne adhésion de la couche isolante 34 sur la couche de SiC 12, que le nettoyage soit également suivi d’une activation de la surface libre 341 de la couche isolante 34 du substrat donneur 34. Ladite activation est par exemple réalisée au moyen d’un plasma, par exemple d’oxygène ou d’azote. [0088] Les formations 25, 26 simultanées des couches isolante et active 14, 15 par transfert comprennent une sous-étape de collage du substrat donneur 30 sur l’empilement 10, tel qu’illustré par la [Fig. 6], la couche libre 341 de la couche isolante 34 du substrat donneur 34 étant pressée contre la couche de SiC 12 de l’empilement 10. Le collage est ensuite suivi d’un recuit dit « recuit de séparation », visant à séparer la couche semiconductrice 35 du substrat donneur 30 en deux parties, suivant un plan comprenant les ions légers précédemment implantés. L’empilement 10 comprend ainsi, après recuit de séparation, une couche isolante 14, telle qu’illustrée par la [Fig. 1], s’étend sur la couche de SiC 12 (car collée sur cette dernière). La couche semiconductrice 35 forme la couche active 15 de l’empilement 10. [0087] It is however advantageous, to allow good adhesion of the insulating layer 34 on the SiC layer 12, for cleaning to also be followed by activation of the free surface 341 of the insulating layer 34 of the donor substrate 34. Said activation is for example carried out by means of a plasma, for example oxygen or nitrogen. [0088] The simultaneous formations 25, 26 of the insulating and active layers 14, 15 by transfer comprise a sub-step of bonding the donor substrate 30 to the stack 10, as illustrated by [Fig. 6], the free layer 341 of the insulating layer 34 of the donor substrate 34 being pressed against the SiC layer 12 of the stack 10. The bonding is then followed by an annealing called “separation annealing”, aimed at separating the semiconductor layer 35 of the donor substrate 30 in two parts, following a plane comprising the light ions previously implanted. The stack 10 thus comprises, after separation annealing, an insulating layer 14, as illustrated by [Fig. 1], extends over the SiC 12 layer (because it is stuck on the latter). The semiconductor layer 35 forms the active layer 15 of the stack 10.
[0089] Une planarisation de la couche active 15 et/ou un recuit complémentaire de l’empilement 10 peut être réalisé pour préparer la couche active 15 et/ou améliorer l’adhésion des couches de l’empilement 10. [0089] A planarization of the active layer 15 and/or a complementary annealing of the stack 10 can be carried out to prepare the active layer 15 and/or improve the adhesion of the layers of the stack 10.
[0090] La [Fig. 7] représente schématiquement un deuxième mode de mise en œuvre du procédé 20. Selon ce mode de mise en œuvre, l'étape de formation 25 de la couche isolante 14 intervient avant l’étape de recuit 23 de l’empilement 10. Cette inversion des étapes permet de simplifier l’étape de recuit 23 en ce que l’atmosphère neutre, précédemment décrite, n’a plus besoin d’avoir une concentration d’oxygène inférieure à 10 ppm. Elle peut être, inférieure à 1 % seulement. Le procédé 20 de fabrication est ainsi plus simple à mettre en œuvre et notamment avec des équipements industriels. [0090] [Fig. 7] schematically represents a second mode of implementation of the method 20. According to this mode of implementation, the step of forming 25 of the insulating layer 14 occurs before the step of annealing 23 of the stack 10. This inversion of the steps makes it possible to simplify the annealing step 23 in that the neutral atmosphere, previously described, no longer needs to have an oxygen concentration less than 10 ppm. It can be less than 1% only. The manufacturing process 20 is thus simpler to implement, particularly with industrial equipment.
[0091] Selon ce mode de mise en œuvre, la couche isolante 14 est formée sur la couche de SiC 12, telle qu’illustrée par la [Fig. 8], Elle forme une barrière permettant de réduire, voire stopper la diffusion d’espèces provenant de l’atmosphère environnante vers la couche de SiC 12. L’empilement 10 peut alors simplement être recuit 23 dans une atmosphère neutre présentant une concentration d’oxygène inférieure à 1 %. [0091] According to this mode of implementation, the insulating layer 14 is formed on the SiC layer 12, as illustrated by [Fig. 8], It forms a barrier making it possible to reduce or even stop the diffusion of species coming from the surrounding atmosphere towards the SiC layer 12. The stack 10 can then simply be annealed 23 in a neutral atmosphere having a concentration of oxygen less than 1%.
[0092] La formation 25 de la couche isolante 14 avant recuit est préférentiellement réalisée par dépôt CVD, par exemple d’un précurseur d’orthosilicate de tétraéthyle Si(OCH2CH3)4 (aussi appelé « TEOS »). Le dépôt CVD est avantageusement assisté par plasma (dit PECVD) pour produire, à partir du précurseur, une couche de dioxyde de silicium SiÛ2. Ce dépôt peut être réalisé à une température comprise entre 300 °C et 500 °C, afin de ne pas anticiper le recuit 23 de l’empilement 10. Le dépôt est réalisé de manière à former une couche isolante 14 présentant une épaisseur 121 , mesurée perpendiculairement au plan P, comprise entre 100 nm et 1000 nm. [0092] The formation 25 of the insulating layer 14 before annealing is preferably carried out by CVD deposition, for example of a tetraethyl orthosilicate precursor Si(OCH2CH3)4 (also called “TEOS”). The CVD deposition is advantageously assisted by plasma (called PECVD) to produce, from the precursor, a layer of silicon dioxide SiO2. This deposition can be carried out at a temperature between 300°C and 500 °C, so as not to anticipate the annealing 23 of the stack 10. The deposition is carried out so as to form an insulating layer 14 having a thickness 121, measured perpendicular to the plane P, between 100 nm and 1000 nm.
[0093] La formation 25 de la couche isolante 14 est avantageusement réalisée dans le même équipement que celui utilisé pour former la couche de SiC 12. Ceci permet d’éviter que de la vapeur d’eau, provenant de l’atmosphère extérieure (par exemple de la salle blanche), ne se dépose sur la couche de SiC 12 (au risque d’oxyder cette dernière). [0093] The formation 25 of the insulating layer 14 is advantageously carried out in the same equipment as that used to form the SiC layer 12. This makes it possible to prevent water vapor coming from the external atmosphere (for example example of the clean room), is not deposited on the SiC 12 layer (at the risk of oxidizing the latter).
[0094] Le procédé 20 peut également comprendre, pour fabriquer un empilement 10 de type substrat SOI, la formation 26 de la couche active 15. À la différence du mode de mise en œuvre de la [Fig. 2], le procédé 20 selon la [Fig. 7] ne forme que la couche active 15 après le recuit 23. La couche active 15 peut être formée par transfert à partir d’un substrat donneur 30 tel qu’illustré par la [Fig. 6], Le substrat donneur 30 ne comporte toutefois ici que la couche semiconductrice 35 cristalline ou polycristalline. La formation 25 de la couche isolante 14 avant le recuit 23 permet ainsi de simplifier l’étape de formation 26 de la couche active 15 par transfert, en ce qu’il n’y a qu’une seule couche qui soit transférée. [0094] The method 20 can also include, to manufacture a stack 10 of the SOI substrate type, the formation 26 of the active layer 15. Unlike the mode of implementation of [Fig. 2], the method 20 according to [Fig. 7] only forms the active layer 15 after annealing 23. The active layer 15 can be formed by transfer from a donor substrate 30 as illustrated by [Fig. 6], The donor substrate 30, however, here only comprises the crystalline or polycrystalline semiconductor layer 35. The formation 25 of the insulating layer 14 before the annealing 23 thus makes it possible to simplify the step 26 of forming the active layer 15 by transfer, in that there is only one layer which is transferred.
[0095] La formation 26 de la couche active 15 par transfert comprend préférentiellement une implantation d’ions légers, telle que décrite précédemment. Toutefois, la profondeur d’implantation est ajustée afin de transférer, sur l’empilement 10, une couche active 15 présentant une épaisseur comprise entre 50 nm et 500 nm. Le collage du substrat donneur 30 est également préférentiellement préparé tel que décrit précédemment. La surface libre du substrat donneur 30 est notamment également activée au moyen d’un plasma d’oxygène ou d’azote afin d’améliorer le collage. The formation 26 of the active layer 15 by transfer preferably comprises an implantation of light ions, as described above. However, the implantation depth is adjusted in order to transfer, onto the stack 10, an active layer 15 having a thickness of between 50 nm and 500 nm. The bonding of the donor substrate 30 is also preferably prepared as described above. The free surface of the donor substrate 30 is in particular also activated by means of an oxygen or nitrogen plasma in order to improve bonding.
[0096] La couche isolante 14 de l’empilement 10 peut également comprendre, avant la formation 26 de la couche active 15, un lissage 24 d’une surface 141 de la couche isolante destinée à recevoir la couche active 15. Le lissage 24 est avantageusement similaire au lissage décrit en référence à la [Fig. 5], [0096] The insulating layer 14 of the stack 10 may also comprise, before the formation 26 of the active layer 15, a smoothing 24 of a surface 141 of the insulating layer intended to receive the active layer 15. The smoothing 24 is advantageously similar to the smoothing described with reference to [Fig. 5],
[0097] Le procédé 20 peut également comprendre, de manière commune aux modes de réalisation des [Fig. 2] et [Fig. 7], une étape de fourniture 21 de la couche support 11 , antérieure à l’étape de formation de la couche de SiC 12. Outre l’approvisionnement de la couche support 11 , l’étape de fourniture 21 peut comprendre la préparation de la couche support 11 de manière à permettre, voire favoriser, lors du recuit 23, la diffusion des atomes de silicium de la couche support 11 vers la couche de SiC 12. La préparation peut comprendre le retrait de contaminants organiques ou métalliques, des dopants ou des particules. Le retrait peut se faire en mettant en œuvre des recettes connues telles qu’une recette humide dite « CARO » (visant à retirer les contaminants organiques) ou des séquences de la recette « RCA », comprenant par exemple un nettoyage dit « HF » (visant à retirer les dopants), un nettoyage dit « SC1 » (visant à retirer les contaminants organiques et les particules) et/ou un nettoyage dit « SC2 » (visant à retirer les contaminants métalliques). Lorsque la couche support 11 comprend un oxyde natif, il est alors avantageux de procéder à son retrait par exemple au moyen d’un plasma, préférentiellement dans la chambre qui accueillera la formation 22 de la couche de SiC 12, voire le recuit 23 de l’empilement 10. [0097] The method 20 can also include, in a manner common to the embodiments of [Fig. 2] and [Fig. 7], a step of supplying 21 of the support layer 11, prior to the step of forming the SiC layer 12. In addition the supply of the support layer 11, the supply step 21 can include the preparation of the support layer 11 so as to allow, or even promote, during annealing 23, the diffusion of the silicon atoms of the support layer 11 towards the SiC layer 12. The preparation may include the removal of organic or metallic contaminants, dopants or particles. Removal can be done by implementing known recipes such as a wet recipe called “CARO” (aimed at removing organic contaminants) or sequences of the “RCA” recipe, including for example a cleaning called “HF” ( aimed at removing dopants), so-called “SC1” cleaning (aimed at removing organic contaminants and particles) and/or so-called “SC2” cleaning (aimed at removing metallic contaminants). When the support layer 11 comprises a native oxide, it is then advantageous to remove it for example by means of a plasma, preferably in the chamber which will accommodate the formation 22 of the SiC layer 12, or even the annealing 23 of the stack 10.
[0098] La [Fig. 9] présente une image obtenue par microscopie électronique en transmission (dite « TEM » pour « Transmission Electron Microscopy » en anglais) en champ clair, d’un empilement semiconducteur 10 selon l’invention. Cet empilement a été obtenu au moyen du procédé selon la présente invention. L’empilement 10 comprend une couche support 11 en silicium monocristallin, une couche de SiC 12 polycristalline et une pluralité de cavités 13 s’étendant dans la couche support 11 , depuis l’interface 112 entre la couche support 11 et la couche de SiC 12. La couche support 11 présente un plan [001 ] à l’interface 112 avec la couche SiC 12 si bien que les cavités présentent des facettes s’étendant selon des plans cristallographiques {111 } (représentée par une flèche orientée selon la direction [111 ], normale aux plans (111 )). [0098] [Fig. 9] presents an image obtained by transmission electron microscopy (called “TEM” for “Transmission Electron Microscopy” in English) in bright field, of a semiconductor stack 10 according to the invention. This stack was obtained by means of the method according to the present invention. The stack 10 comprises a support layer 11 of monocrystalline silicon, a polycrystalline SiC layer 12 and a plurality of cavities 13 extending in the support layer 11, from the interface 112 between the support layer 11 and the SiC layer 12 The support layer 11 has a plane [001] at the interface 112 with the SiC layer 12 so that the cavities have facets extending along crystallographic planes {111} (represented by an arrow oriented in the direction [111). ], normal to the planes (111)).
[0099] Les différentes orientations des grains de SiC dans la couche de SiC 12 induisent une grande différence de contraste au sein de cette couche. Cette différence de contraste ne doit toutefois pas être interprétée comme la présence de pores, de bulles ou de lacunes. Dans le cas particulier de la [Fig. 9], la couche de SiC présente également différente de structures cristallines, par exemple une majorité de grains cristallisés suivant le polytype 3C et une minorité de grains dans d’autres polytypes dont 4H et 6H. Cette différence de structure contribue également à l’aspect de la couche de SiC 12 observée en dans la [Fig. 9], La couche de SiC 12 est non-poreuse. La couche support 11 est également non-poreuse. [00100] Sur cette image, la hauteur des cavités 13 est comprise entre 10 nm et 40 nm. Cette hauteur est mesurée perpendiculairement au plan P et depuis la couche de SiC 12. The different orientations of the SiC grains in the SiC 12 layer induce a large difference in contrast within this layer. This difference in contrast should not, however, be interpreted as the presence of pores, bubbles or gaps. In the particular case of [Fig. 9], the SiC layer also has different crystal structures, for example a majority of grains crystallized according to the 3C polytype and a minority of grains in other polytypes including 4H and 6H. This difference in structure also contributes to the appearance of the SiC 12 layer observed in [Fig. 9], The SiC 12 layer is non-porous. The support layer 11 is also non-porous. [00100] In this image, the height of the cavities 13 is between 10 nm and 40 nm. This height is measured perpendicular to the plane P and from the SiC 12 layer.
[00101] Chaque cavité 13 présente une forme pyramidale et présente une base alignée avec l’interface entre la couche support 11 et la couche de SiC 12. Autrement dit, la base de la pyramide est confondue avec cette interface. Le sommet de la pyramide est situé dans la couche support 11 , à des profondeurs variables selon la taille des cavités 13. [00101] Each cavity 13 has a pyramidal shape and has a base aligned with the interface between the support layer 11 and the SiC layer 12. In other words, the base of the pyramid coincides with this interface. The top of the pyramid is located in the support layer 11, at varying depths depending on the size of the cavities 13.
[00102] Comme on peut le constater sur la [Fig. 9], les cavités 13 sont localisées uniquement à l’interface entre la couche support 11 et la couche de SiC 12. [00102] As can be seen in [Fig. 9], the cavities 13 are located only at the interface between the support layer 11 and the SiC layer 12.

Claims

REVENDICATIONS
[Revendication 1 ] Procédé (20) de fabrication d’un empilement semiconducteur (10), comprenant, à partir d’une première couche de silicium (11 ), dite couche support : [Claim 1] Method (20) for manufacturing a semiconductor stack (10), comprising, from a first silicon layer (11), called support layer:
- la formation (22) d’une couche en carbure de silicium (12), s’étendant sur la couche support (11 ), présentant une épaisseur (121 ), mesurée depuis la couche support (11 ), supérieure à 5 nm, une fraction d’atomes de carbone de la couche de carbure de silicium (12), à moins de 20 nm de la couche support (11 ), étant strictement supérieure à 50 % ; et- the formation (22) of a silicon carbide layer (12), extending over the support layer (11), having a thickness (121), measured from the support layer (11), greater than 5 nm, a fraction of carbon atoms of the silicon carbide layer (12), less than 20 nm from the support layer (11), being strictly greater than 50%; And
- le recuit (23) de la couche support (11 ) et de la couche en carbure de silicium (12) jusqu’à former des cavités (13), chaque cavité (13) s’étendant dans la couche support (11 ) depuis la couche en carbure de silicium (12), une concentration en oxygène au contact de la couche de carbure de silicium (12), lors de l’étape de recuit (23), étant inférieure à 10 ppm. - annealing (23) of the support layer (11) and the silicon carbide layer (12) until forming cavities (13), each cavity (13) extending into the support layer (11) from the silicon carbide layer (12), an oxygen concentration in contact with the silicon carbide layer (12), during the annealing step (23), being less than 10 ppm.
[Revendication 2] Procédé (20) selon la revendication précédente, dans lequel le recuit (23) est réalisé pendant une durée comprise entre 15 min et 2 h à une température comprise entre 900 °C et 1100 °C. [Claim 2] Method (20) according to the preceding claim, in which the annealing (23) is carried out for a period of between 15 min and 2 h at a temperature of between 900 °C and 1100 °C.
[Revendication 3] Procédé (20) selon l’une des revendications précédentes, dans lequel la couche de carbure de silicium (12) issue de l’étape de formation (22) est amorphe, le recuit (23) des couches étant réalisé de manière à cristalliser la couche de carbure de silicium (12) selon un arrangement polycristallin. [Claim 3] Method (20) according to one of the preceding claims, in which the layer of silicon carbide (12) resulting from the formation step (22) is amorphous, the annealing (23) of the layers being carried out by so as to crystallize the silicon carbide layer (12) in a polycrystalline arrangement.
[Revendication 4] Procédé (20) selon l’une des revendications précédentes, dans lequel la couche support (11 ) est orientée dans un plan (P) et dans lequel une fraction d’atomes de carbone de la couche de carbure de silicium (12), à moins de 20 nm de la couche support (11 ), est inférieure ou égale à 70 %. [Claim 4] Method (20) according to one of the preceding claims, in which the support layer (11) is oriented in a plane (P) and in which a fraction of carbon atoms of the silicon carbide layer ( 12), less than 20 nm from the support layer (11), is less than or equal to 70%.
[Revendication 5] Procédé (20) selon l’une des revendications précédentes, dans lequel l’épaisseur (121 ) de la couche de carbure de silicium (12) est inférieure à 500 nm. [Claim 5] Method (20) according to one of the preceding claims, in which the thickness (121) of the silicon carbide layer (12) is less than 500 nm.
[Revendication 6] Procédé (20) selon l’une des revendications précédentes, dans lequel la couche support (11 ) est orientée dans un plan (P) et dans lequel les cavités (13) s’étendent sur une distance (133), mesurée perpendiculairement au plan (P) et depuis la couche de carbure de silicium (12), comprise entre 5 nm et 100 nm. [Claim 6] Method (20) according to one of the preceding claims, in which the support layer (11) is oriented in a plane (P) and in which the cavities (13) extend over a distance (133), measured perpendicular to the plane (P) and from the silicon carbide layer (12), of between 5 nm and 100 nm.
[Revendication 7] Procédé (20) selon l’une des revendications précédentes, comprenant la formation (25) d’une couche isolante (14) s’étendant sur la couche de carbure de silicium (12). [Claim 7] Method (20) according to one of the preceding claims, comprising the formation (25) of an insulating layer (14) extending over the silicon carbide layer (12).
[Revendication 8] Procédé (20) selon la revendication précédente, dans lequel la formation (25) de la couche isolante (14) est réalisée par dépôt, avant ledit recuit (23). [Claim 8] Method (20) according to the preceding claim, in which the formation (25) of the insulating layer (14) is carried out by deposition, before said annealing (23).
[Revendication 9] Procédé (20) selon l’une des deux revendications précédentes, dans lequel le recuit (23) de la couche support (11 ), de la couche en carbure de silicium (12) et de la couche isolante (14) est réalisé sous une atmosphère comprenant une concentration en oxygène inférieure à 1 %. [Claim 9] Method (20) according to one of the two preceding claims, in which the annealing (23) of the support layer (11), of the silicon carbide layer (12) and of the insulating layer (14) is carried out under an atmosphere comprising an oxygen concentration of less than 1%.
[Revendication 10] Empilement semiconducteur (10) comprenant : [Claim 10] Semiconductor stack (10) comprising:
- une première couche en silicium (11 ), dite couche support ; - a first silicon layer (11), called support layer;
- une couche de carbure de silicium (12), s’étendant sur la couche support (11 ), présentant une épaisseur (121 ), mesurée depuis la couche support (11 ), supérieure à 5 nm ; et - a layer of silicon carbide (12), extending over the support layer (11), having a thickness (121), measured from the support layer (11), greater than 5 nm; And
- des cavités (13), chaque cavité (13) s’étendant dans la couche support (11 ) depuis la couche de carbure de silicium (12). - cavities (13), each cavity (13) extending into the support layer (11) from the silicon carbide layer (12).
[Revendication 11 ] Empilement semiconducteur (10) selon la revendication précédente, dans lequel la couche support (11 ) est orientée dans un plan (P) et dans lequel les cavités (13) s’étendent sur une distance (133), mesurée perpendiculairement au plan (P) et depuis la couche de carbure de silicium (12), comprise entre 5 nm et 100 nm. [Claim 11] Semiconductor stack (10) according to the preceding claim, in which the support layer (11) is oriented in a plane (P) and in which the cavities (13) extend over a distance (133), measured perpendicularly to the plane (P) and from the silicon carbide layer (12), between 5 nm and 100 nm.
[Revendication 12] Empilement semiconducteur (10) selon la revendication précédente, dans lequel lorsque les cavités (13) s’étendent sur une distance (133), mesurée perpendiculairement au plan (P) et depuis la couche de carbure de silicium (12), supérieure à 15 nm, alors chaque cavité (13) présente des facettes, chaque facette étant orientée parallèlement à un plan cristallographique. [Claim 12] Semiconductor stack (10) according to the preceding claim, in which when the cavities (13) extend over a distance (133), measured perpendicular to the plane (P) and from the silicon carbide layer (12) , greater than 15 nm, then each cavity (13) has facets, each facet being oriented parallel to a crystallographic plane.
[Revendication 13] Empilement semiconducteur (10) selon l’une des revendications 10 à 12, dans lequel chaque cavité (13) présente une forme pyramidale et présente une base alignée avec l’interface entre la couche support (11 ) et la couche de carbure de silicium (12). [Claim 13] Semiconductor stack (10) according to one of claims 10 to 12, in which each cavity (13) has a pyramidal shape and has a base aligned with the interface between the support layer (11) and the silicon carbide layer (12).
[Revendication 14] Empilement semiconducteur (10) selon l’une des revendications[Claim 14] Semiconductor stack (10) according to one of the claims
10 à 13, dans lequel les cavités (13) sont uniquement situées à l’interface entre la couche support (11 ) et la couche de carbure de silicium (12). 10 to 13, in which the cavities (13) are only located at the interface between the support layer (11) and the silicon carbide layer (12).
[Revendication 15] Empilement semiconducteur (10) selon l’une des revendications 10 à 14, dans lequel la couche de carbure de silicium (12) est non-poreuse. [Claim 15] Semiconductor stack (10) according to one of claims 10 to 14, in which the silicon carbide layer (12) is non-porous.
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