WO2024087780A1

WO2024087780A1 - Semiconductor structure and manufacturing method therefor

Info

Publication number: WO2024087780A1
Application number: PCT/CN2023/110764
Authority: WO
Inventors: 黄猛
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-10-25
Filing date: 2023-08-02
Publication date: 2024-05-02
Also published as: CN117979688A

Abstract

Disclosed in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, which comprises a core region and a stepped region; at least one set of active pillar stacked structures located in the core region, wherein each active pillar stacked structure comprises a plurality of active pillars, which are distributed in a stacked manner; and at least one set of bit line connection line laminated structures located in the stepped region, wherein each bit line connection line laminated structure comprises a plurality of bit line connection lines, which are distributed in a stacked manner, and one bit line connection line is correspondingly electrically connected to one active pillar. At least one bit line connection line comprises an inclined section, and an included angle is formed between the extension direction of the inclined section and a horizontal direction.

Description

一种半导体结构及其制造方法A semiconductor structure and a method for manufacturing the same

相关申请的交叉引用CROSS-REFERENCE TO RELATED APPLICATIONS

本公开基于申请号为202211313989.2、申请日为2022年10月25日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。This disclosure is based on the Chinese patent application with application number 202211313989.2 and application date October 25, 2022, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference.

技术领域Technical Field

本公开涉及但不限于一种半导体结构及其制造方法。The present disclosure relates to, but is not limited to, a semiconductor structure and a method for manufacturing the same.

背景技术Background technique

随着半导体工业的不断发展，需要越来越高集成度的半导体器件，以满足消费者对优越性能和低廉价格的需求。在二维半导体器件的制造中，通过改进处理技术或优化电路设计等，可以将平面存储单元缩放到更小的尺寸。然而，随着平面存储单元的特征尺寸接近下限，平面存储单元的存储密度也接近上限。目前，三维存储器架构可以解决平面存储单元中的存储密度限制，但三维存储器的集成度还有待进一步提高。With the continuous development of the semiconductor industry, more and more highly integrated semiconductor devices are needed to meet consumers' demand for superior performance and low prices. In the manufacture of two-dimensional semiconductor devices, planar memory cells can be scaled to smaller sizes by improving processing technology or optimizing circuit design. However, as the characteristic size of planar memory cells approaches the lower limit, the storage density of planar memory cells also approaches the upper limit. At present, three-dimensional memory architecture can solve the storage density limitation in planar memory cells, but the integration of three-dimensional memory needs to be further improved.

发明内容Summary of the invention

有鉴于此，本公开实施例为解决背景技术中存在的技术问题而提供一种半导体结构及其制造方法。In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same in order to solve the technical problems existing in the background technology.

根据本公开实施例的第一方面，提供了一种半导体结构，包括：According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, including:

衬底，所述衬底包括核心区域和阶梯区域；A substrate, the substrate comprising a core region and a step region;

位于所述核心区域的至少一组有源柱堆叠结构，所述有源柱堆叠结构包括沿竖直方向依次堆叠分布的多个有源柱，所述有源柱沿第一方向延伸，所述第一方向与水平面平行；At least one group of active pillar stacking structures located in the core area, the active pillar stacking structure comprising a plurality of active pillars stacked and distributed in sequence along a vertical direction, the active pillars extending along a first direction, the first direction being parallel to a horizontal plane;

位于所述阶梯区域的至少一组位线连接线叠层结构，所述位线连接线叠层结构包括沿竖直方向依次堆叠分布的多条位线连接线，一条所述位线连接线对应电连接一个所述有源柱；其中，At least one group of bit line connection line stacked structures located in the step region, the bit line connection line stacked structure includes a plurality of bit line connection lines stacked and distributed in sequence along a vertical direction, and one of the bit line connection lines is electrically connected to one of the active pillars; wherein,

至少一条所述位线连接线包括倾斜区段，所述倾斜区段的延伸方向与水平方向之间具有夹角。At least one of the bit line connection lines comprises an inclined section, and an extending direction of the inclined section forms an angle with a horizontal direction.

在一些实施例中，所述夹角的范围为15度至65度。In some embodiments, the angle ranges from 15 degrees to 65 degrees.

在一些实施例中，所述位线连接线还包括水平区段，所述水平区段沿第一方向延伸，所述水平区段电连接所述倾斜区段的底端和与该条位线连接线对应的所述有源柱的一端。In some embodiments, the bit line connection line further includes a horizontal section extending along a first direction, the horizontal section electrically connecting a bottom end of the inclined section and one end of the active pillar corresponding to the bit line connection line.

在一些实施例中，所述半导体结构还包括至少一个位线插塞，所述位线插塞的底端电连接所述倾斜区段的顶端。In some embodiments, the semiconductor structure further includes at least one bit line plug, a bottom end of the bit line plug is electrically connected to a top end of the inclined section.

在一些实施例中，所述核心区域上包括多组所述有源柱堆叠结构，所述阶梯区域上包括多组所述位线连接线叠层结构；In some embodiments, the core region includes a plurality of groups of active pillar stack structures, and the step region includes a plurality of groups of bit line connection line stack structures;

所述半导体结构还包括：The semiconductor structure further comprises:

多条位线，所述位线沿第二方向延伸，所述第二方向平行于水平面且与所述第一方向相交；一条所述位线与多组所述位线连接线叠层结构中位于同一层的所述位线连接线电连接。A plurality of bit lines are provided, wherein the bit lines extend along a second direction, the second direction is parallel to a horizontal plane and intersects with the first direction; and one of the bit lines is electrically connected to the bit line connection lines located at the same layer in a plurality of groups of the bit line connection line stacked structures.

在一些实施例中，所述有源柱包括沟道区；所述半导体结构还包括：In some embodiments, the active pillar includes a channel region; and the semiconductor structure further includes:

至少一条字线，所述字线沿竖直方向延伸，且所述字线围绕一组所述有源柱堆叠结构中的所述沟道区。At least one word line extends in a vertical direction and surrounds the channel region in a group of the active pillar stack structures.

在一些实施例中，所述半导体结构还包括至少一个电容，所述电容的一个极板电连接一个所述有源柱。In some embodiments, the semiconductor structure further comprises at least one capacitor, one plate of which is electrically connected to one of the active pillars.

在一些实施例中，一组所述位线连接线叠层结构中的每个所述位线连接线均包括倾斜区段。In some embodiments, each of the bit line connection lines in a set of the bit line connection line stack structures comprises an inclined section.

在一些实施例中，每组所述位线连接线叠层结构中相邻的所述位线连接线之间的间距与所述位线连接线的厚度的比值范围为2到4。In some embodiments, a ratio of a spacing between adjacent bit line connection lines in each group of the bit line connection line stacked structures to a thickness of the bit line connection lines ranges from 2 to 4.

在一些实施例中，一组所述位线连接线叠层结构中，相邻所述位线连接线的倾斜区段之间的间距小于等于所述有源柱堆叠结构中沿竖直方向相邻的所述有源柱之间的间距。In some embodiments, in a group of the bit line connection line stacked structures, the spacing between the inclined sections of adjacent bit line connection lines is less than or equal to the spacing between the active pillars adjacent to each other in the vertical direction in the active pillar stacked structure.

根据本公开实施例的第二方面，提供了一种半导体结构的制造方法，包括：According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

提供衬底，所述衬底包括阶梯区域和核心区域；Providing a substrate, the substrate comprising a step region and a core region;

在所述衬底上方形成材料堆叠层，所述材料堆叠层包括多个沿竖直方向依次交替堆叠的半导体层和牺牲层，所述材料堆叠层包括第一子区、第二子区和第三子区，所述第一子区与所述第二子区位于所述阶梯区域，所述第三子区位于所述核心区域；所述第二子区与所述第三子区中的所述半导体层与所述牺牲层沿水平方向延伸，所述第一子区包括倾斜面，所述倾斜面与水平面之间存在夹角；A material stacking layer is formed above the substrate, the material stacking layer comprising a plurality of semiconductor layers and sacrificial layers alternately stacked in sequence along a vertical direction, the material stacking layer comprising a first sub-region, a second sub-region and a third sub-region, the first sub-region and the second sub-region are located in the step region, and the third sub-region is located in the core region; the semiconductor layers and the sacrificial layers in the second sub-region and the third sub-region extend in a horizontal direction, the first sub-region comprises an inclined surface, and an angle exists between the inclined surface and a horizontal plane;

至少对所述第一子区与所述第二子区执行刻蚀工艺，形成若干条沿第一方向延伸的第二沟槽，所述第一方向与水平面平行，从而将所述第一子区与所述第二子区中的所述材料堆叠层刻蚀为多组位线连接线待形成层堆叠结构，所述位线连接线待形成层堆叠结构包括多层位线连接线待形成层；Performing an etching process on at least the first sub-region and the second sub-region to form a plurality of second grooves extending in a first direction, wherein the first direction is parallel to a horizontal plane, thereby etching the material stacking layer in the first sub-region and the second sub-region into a plurality of bit line connection line to-be-formed layer stacking structures, wherein the bit line connection line to-be-formed layer stacking structures include a plurality of bit line connection line to-be-formed layers;

对所述位线连接线待形成层进行处理以形成位线连接线。The layer to be formed with the bit line connection line is processed to form a bit line connection line.

在一些实施例中，保留所述牺牲层在半导体结构中，或者，在形成所述位线连接线待形成层堆叠结构之后，且在形成所述位线连接线之前，去除所述位线连接线待形成层堆叠结构中的所述牺牲层。In some embodiments, the sacrificial layer is retained in the semiconductor structure, or the sacrificial layer in the bit line connection line to be formed layer stack structure is removed after forming the bit line connection line to be formed layer stack structure and before forming the bit line connection line.

在一些实施例中，当保留所述牺牲层在半导体结构中时，对所述位线连接线待形成层进行处理包括：对暴露在所述第二沟槽内的所述位线连接线待形成层的侧壁进行金属硅化处理以形成金属硅化物；当在形成所述位线连接线待形成层堆叠结构之后，且在形成所述位线连接线之前去除所述牺牲层时，所述位线连接线待形成层的侧壁全部裸露，对所述位线连接线待形成层进行处理包括：对所述位线连接线待形成层进行处理包括：对所述位线连接线待形成层的裸露侧壁进行金属硅化处理以形成金属硅化物。In some embodiments, when the sacrificial layer is retained in the semiconductor structure, processing the layer to be formed for the bit line connection line includes: performing metal silicide treatment on the side walls of the layer to be formed for the bit line connection line exposed in the second trench to form a metal silicide; when the sacrificial layer is removed after forming the stacked structure of the layer to be formed for the bit line connection line and before forming the bit line connection line, the side walls of the layer to be formed for the bit line connection line are completely exposed, and processing the layer to be formed for the bit line connection line includes: processing the layer to be formed for the bit line connection line includes: performing metal silicide treatment on the exposed side walls of the layer to be formed for the bit line connection line to form a metal silicide.

在一些实施例中，提供衬底，包括：In some embodiments, a substrate is provided, comprising:

提供基底，所述基底包括第一分区、第二分区和第三分区；providing a substrate, the substrate comprising a first partition, a second partition, and a third partition;

刻蚀所述第二分区与所述第三分区，使得所述第三分区的上表面低于所述第一分区的上表面，所述第二分区的上表面成为倾斜表面，所述倾斜表面的上端连接所述第一分区的上表面，下端连接所述第三分区的上表面。The second partition and the third partition are etched so that the upper surface of the third partition is lower than the upper surface of the first partition, and the upper surface of the second partition becomes an inclined surface, the upper end of the inclined surface is connected to the upper surface of the first partition, and the lower end is connected to the upper surface of the third partition.

在一些实施例中，在所述衬底上方形成材料堆叠层，包括：In some embodiments, forming a material stack layer above the substrate includes:

在所述衬底上方共形地形成初始材料堆叠层，所述初始材料堆叠层包括多个沿竖直方向依次交替堆叠的半导体层与牺牲层，位于所述核心区域上方的所述初始材料堆叠层的上表面不高于所述第一分区的上表面；Conformally forming an initial material stacking layer above the substrate, the initial material stacking layer comprising a plurality of semiconductor layers and sacrificial layers alternately stacked in sequence along a vertical direction, wherein an upper surface of the initial material stacking layer above the core region is not higher than an upper surface of the first subarea;

对所述初始材料堆叠层进行平坦化工艺，去除位于所述第一分区上方的所述初始材料堆叠层，并使得位于所述第二分区和所述第三分区上方的所述初始材料堆叠层的上表面齐平。A planarization process is performed on the initial material stack layer to remove the initial material stack layer located above the first partition and to make the upper surface of the initial material stack layer located above the second partition and the third partition flush.

在一些实施例中，所述半导体层的材料为单晶硅，所述牺牲层的材料为硅锗，所述半导体层与所述牺牲层采用外延工艺形成；或者，In some embodiments, the semiconductor layer is made of single crystal silicon, the sacrificial layer is made of silicon germanium, and the semiconductor layer and the sacrificial layer are formed by an epitaxial process; or,

所述半导体层的材料为多晶硅或铟镓锌氧化物，所述牺牲层的材料为介电层，所述半导体层与所述牺牲层采用沉积工艺形成。The material of the semiconductor layer is polysilicon or indium gallium zinc oxide, the material of the sacrificial layer is a dielectric layer, and the semiconductor layer and the sacrificial layer are formed by a deposition process.

在一些实施例中，在对所述第一子区与所述第二子区执行刻蚀工艺的同一步骤中刻蚀所述第三子区，形成若干沿所述第一方向延伸的第一沟槽，所述第一沟槽与所述第二沟槽连通，从而将位于所述第三子区的所述材料堆叠层刻蚀为多组有源柱堆叠结构，每组所述有源柱堆叠结构包括多层有源柱。In some embodiments, the first sub-region and the second sub-region are etched in the same step of performing an etching process. The third sub-region forms a plurality of first grooves extending along the first direction, and the first grooves are connected to the second grooves, so that the material stack layer located in the third sub-region is etched into a plurality of groups of active column stack structures, each group of the active column stack structures includes multiple layers of active columns.

在一些实施例中，形成多个沿第一方向延伸的第一沟槽之后，去除所述牺牲层之前，所述方法还包括：In some embodiments, after forming a plurality of first trenches extending along the first direction and before removing the sacrificial layer, the method further includes:

形成第一介质层，所述第一介质层填充所述第一沟槽并覆盖所述材料堆叠层的上表面；forming a first dielectric layer, wherein the first dielectric layer fills the first trench and covers an upper surface of the material stack layer;

对所述第三子区进行刻蚀工艺，去除所述第一沟槽内的部分所述第一介质层，形成多个第三沟槽和多个第四沟槽，多个所述第三沟槽沿第二方向排列，多个所述第四沟槽沿所述第二方向排列，所述第二方向平行于水平面且与所述第一方向相交；Performing an etching process on the third sub-region to remove a portion of the first dielectric layer in the first trench to form a plurality of third trenches and a plurality of fourth trenches, wherein the plurality of third trenches are arranged along a second direction, and the plurality of fourth trenches are arranged along the second direction, wherein the second direction is parallel to a horizontal plane and intersects with the first direction;

去除暴露于所述第三沟槽与所述第四沟槽内的所述牺牲层，使得所述第三沟槽在所述第二方向上连通形成第一网状沟槽，所述第四沟槽在所述第二方向上连通形成第二网状沟槽；removing the sacrificial layer exposed in the third trench and the fourth trench, so that the third trench is connected in the second direction to form a first mesh-shaped trench, and the fourth trench is connected in the second direction to form a second mesh-shaped trench;

通过所述第一网状沟槽与所述第二网状沟槽对所述半导体层执行掺杂工艺，以使暴露于所述第一网状沟槽内的所述半导体层形成源区，暴露于所述第二网状沟槽内的所述半导体层形成漏区；Performing a doping process on the semiconductor layer through the first mesh grooves and the second mesh grooves, so that the semiconductor layer exposed in the first mesh grooves forms a source region, and the semiconductor layer exposed in the second mesh grooves forms a drain region;

形成第二介质层，填充于所述第一网状沟槽内的所述第二介质层构成第一网状支撑结构，填充于所述第二网状沟槽内的所述第二介质层构成第二网状支撑结构。A second dielectric layer is formed. The second dielectric layer filled in the first mesh-shaped grooves constitutes a first mesh-shaped support structure. The second dielectric layer filled in the second mesh-shaped grooves constitutes a second mesh-shaped support structure.

在一些实施例中，形成所述第一网状支撑结构与所述第二网状支撑结构之后，所述方法还包括：In some embodiments, after forming the first mesh support structure and the second mesh support structure, the method further includes:

去除所述第一网状支撑结构与所述第二网状支撑结构之间的所述第一介质层，形成多个沿所述第二方向排布的开口；removing the first dielectric layer between the first mesh support structure and the second mesh support structure to form a plurality of openings arranged along the second direction;

去除暴露于所述开口内的所述牺牲层，使得所述有源柱堆叠结构中的有源柱悬空。The sacrificial layer exposed in the opening is removed, so that the active pillars in the active pillar stack structure are suspended.

在一些实施例中，对所述位线连接线待形成层处理形成所述位线连接线之后，所述方法还包括：In some embodiments, after processing the layer to be formed of the bit line connection line to form the bit line connection line, the method further comprises:

形成第四介质层，所述第四介质层填充所述位线连接线之间的间隙并覆盖所述位线连接线的上表面；forming a fourth dielectric layer, wherein the fourth dielectric layer fills the gaps between the bit line connection lines and covers the upper surfaces of the bit line connection lines;

对位于所述第一沟槽内的第三介质层执行刻蚀工艺，形成沿第二方向排布的多个隔离通孔，所述第二方向平行于水平面且与所述第一方向相交，所述隔离通孔沿竖直方向延伸，且所述隔离通孔位于相邻两组所述有源柱堆叠结构之间；Performing an etching process on the third dielectric layer located in the first trench to form a plurality of isolation through holes arranged along a second direction, wherein the second direction is parallel to a horizontal plane and intersects with the first direction, the isolation through holes extend along a vertical direction, and the isolation through holes are located between two adjacent groups of the active pillar stack structures;

采用隔离介质层填充所述隔离通孔形成多个隔离结构。An isolation dielectric layer is used to fill the isolation through holes to form a plurality of isolation structures.

在一些实施例中，在形成多个所述隔离结构之后，所述方法还包括：In some embodiments, after forming a plurality of the isolation structures, the method further comprises:

刻蚀去除相邻所述隔离结构之间的所述第三介质层形成字线通孔，所述字线通孔沿竖直方向延伸，一组所述有源柱堆叠结构中的所有有源柱的沟道区暴露于一个所述字线通孔中；Etching and removing the third dielectric layer between adjacent isolation structures to form a word line through hole, wherein the word line through hole extends in a vertical direction, and the channel regions of all active pillars in a group of active pillar stack structures are exposed in one word line through hole;

在所述字线通孔内形成包覆所述有源柱的沟道区的栅介质层与栅极，一组所述有源柱堆叠结构中的所有有源柱的栅极连接在一起形成一条字线。A gate dielectric layer and a gate electrode covering a channel region of the active column are formed in the word line through hole, and the gate electrodes of all active columns in a group of active column stacking structures are connected together to form a word line.

在一些实施例中，在形成所述位线连接线之后，所述方法还包括：In some embodiments, after forming the bit line connection line, the method further includes:

在所述位线连接线上方形成至少一个位线插塞，一个所述位线插塞对应电连接一条所述位线连接线；forming at least one bit line plug above the bit line connection line, wherein one bit line plug is electrically connected to one bit line connection line;

在所述位线插塞上方形成位线材料层；forming a bit line material layer over the bit line plug;

刻蚀所述位线材料层，形成至少一条位线，所述位线沿第二方向延伸，所述第二方向平行于水平面且与所述第一方向相交，且一条所述位线与同一组的所述位线插塞电连接，其中，连接同一层的所述位线连接线的多个所述位线插塞定义为同一组的所述位线插塞；或者，Etching the bit line material layer to form at least one bit line, wherein the bit line extends along a second direction, the second direction is parallel to the horizontal plane and intersects the first direction, and one bit line is electrically connected to the bit line plugs of the same group, wherein a plurality of bit line plugs connected to the bit line connection lines of the same layer are defined as the bit line plugs of the same group; or,

在形成所述位线连接线之后，所述方法还包括： After forming the bit line connection line, the method further includes:

在所述位线连接线上方形成位线材料层；forming a bit line material layer above the bit line connection line;

刻蚀所述位线材料层，形成至少一条位线，所述位线沿所述第二方向延伸，且一条所述位线电连接位于同一层的所有所述位线连接线。The bit line material layer is etched to form at least one bit line, wherein the bit line extends along the second direction, and one bit line is electrically connected to all the bit line connection lines located in the same layer.

本公开实施例提供了一种半导体结构及其制造方法，包括：衬底，所述衬底包括核心区域和阶梯区域；位于所述核心区域的至少一组有源柱堆叠结构，所述有源柱堆叠结构包括沿竖直方向依次堆叠分布的多个有源柱，所述有源柱沿第一方向延伸，所述第一方向与水平面平行；位于所述阶梯区域的至少一组位线连接线叠层结构，所述位线连接线叠层结构包括沿竖直方向依次堆叠分布的多条位线连接线，一条所述位线连接线对应电连接一个所述有源柱；其中，至少一条所述位线连接线包括倾斜区段，所述倾斜区段的延伸方向与水平方向之间具有夹角。An embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same, comprising: a substrate, the substrate comprising a core region and a step region; at least one group of active column stacking structures located in the core region, the active column stacking structure comprising a plurality of active columns stacked and distributed in sequence along a vertical direction, the active columns extending along a first direction, the first direction being parallel to a horizontal plane; at least one group of bit line connection line stacking structures located in the step region, the bit line connection line stacking structure comprising a plurality of bit line connection lines stacked and distributed in sequence along a vertical direction, one bit line connection line being electrically connected to one active column; wherein at least one bit line connection line comprises an inclined section, the extension direction of the inclined section having an angle with the horizontal direction.

在相关技术的三维存储器结构中，位线连接线的端部通常包括水平台阶结构，为了制备位线接触插塞，通常需要在位线连接线构成的台阶面上留出足够的空间，因此水平台阶结构占据较大的空间，这限制了三维存储器集成度的提高。本公开提供的半导体结构中的位线连接线包括具有倾斜区段的位线阶梯结构，相比于上述水平延伸的位线阶梯结构，具有倾斜区段的位线阶梯结构占用的面积更小，增加了空间利用率，可进一步提高集成度，并且制作工艺简单，且能够与现有的具有多层水平存储单元层的三维存储器的工艺流程兼容，工艺成本低。In the three-dimensional memory structure of the related art, the end of the bit line connection line usually includes a horizontal step structure. In order to prepare the bit line contact plug, it is usually necessary to leave enough space on the step surface formed by the bit line connection line, so the horizontal step structure occupies a large space, which limits the improvement of the integration of the three-dimensional memory. The bit line connection line in the semiconductor structure provided by the present disclosure includes a bit line step structure with an inclined section. Compared with the above-mentioned horizontally extended bit line step structure, the bit line step structure with an inclined section occupies a smaller area, increases the space utilization rate, can further improve the integration, and has a simple manufacturing process, and can be compatible with the existing process flow of a three-dimensional memory with multiple horizontal memory cell layers, and has a low process cost.

本公开附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

图1为本公开一实施例的半导体结构的三维立体示意图；FIG1 is a three-dimensional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

图2为本公开一实施例的半导体结构的俯视图；FIG2 is a top view of a semiconductor structure according to an embodiment of the present disclosure;

图3为本公开一实施例的半导体结构沿图2中的a-a’、b-b’、c-c’、d-d’和e-e’线的垂直剖面示意图；FIG3 is a schematic vertical cross-sectional view of a semiconductor structure along lines a-a′, b-b′, c-c′, d-d′ and e-e′ in FIG2 according to an embodiment of the present disclosure;

图4为本公开一实施例的半导体结构的制造方法的流程图；FIG4 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

图5至图16为本公开一实施例的半导体结构在制造过程中的结构示意图，其中，每一附图中包含沿图2中的a-a’、b-b’、c-c’、d-d’和e-e’线的垂直剖面示意图。Figures 5 to 16 are schematic diagrams of the structure of a semiconductor structure during the manufacturing process of an embodiment of the present disclosure, wherein each figure includes a vertical cross-sectional schematic diagram along the a-a’, b-b’, c-c’, d-d’ and e-e’ lines in Figure 2.

附图标记：
10-衬底；101-第一分区；102-第二分区；103-第三分区；104-倾斜表面；11-阶梯区域；
12-核心区域；13-材料堆叠层；131-第一子区；132-第二子区；133-第三子区；14-半导体层；15-牺牲层；16-倾斜面；17-初始材料堆叠层；18-第一沟槽；19-第一介质层；20-第二沟槽；21-第三沟槽；A-第一网状沟槽；B-第二网状沟槽；241-第一网状支撑结构；242-第二网状支撑结构；25-位线连接线待形成层堆叠结构；251-位线连接线待形成层；26-有源柱堆叠结构；27-有源柱；28-第三介质层；29-位线连接线；30-第四介质层；31-隔离通孔；32-隔离结构；33-字线通孔；35-栅介质层；36-栅极；37-字线；38-位线插塞待形成结构；39-位线插塞；40-第五介质层；41-位线；42-位线连接线叠层结构；43-倾斜区段；44-水平区段；45-电容；451-第一电极层；452-电容介质层；453-第二电极层。Reference numerals:
10-substrate; 101-first partition; 102-second partition; 103-third partition; 104-inclined surface; 11-step region;
12-core region; 13-material stacking layer; 131-first sub-region; 132-second sub-region; 133-third sub-region; 14-semiconductor layer; 15-sacrificial layer; 16-inclined surface; 17-initial material stacking layer; 18-first groove; 19-first dielectric layer; 20-second groove; 21-third groove; A-first mesh groove; B-second mesh groove; 241-first mesh support structure; 242-second mesh support structure; 25-bit line connection line to be formed layer stacking structure; 251-bit line connection line to be formed layer; 26 -active pillar stacking structure; 27-active pillar; 28-third dielectric layer; 29-bit line connection line; 30-fourth dielectric layer; 31-isolation through hole; 32-isolation structure; 33-word line through hole; 35-gate dielectric layer; 36-gate; 37-word line; 38-bit line plug to be formed structure; 39-bit line plug; 40-fifth dielectric layer; 41-bit line; 42-bit line connection line stacking structure; 43-inclined section; 44-horizontal section; 45-capacitor; 451-first electrode layer; 452-capacitor dielectric layer; 453-second electrode layer.

具体实施方式Detailed ways

下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said/the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and/or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and/or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and/or groups. When used herein, the term "and/or" includes any and all combinations of the relevant listed items.

本公开一实施例提供了一种半导体结构，附图1是半导体结构的三维立体示意图，附图2是半导体结构的俯视示意图，附图3是半导体结构沿附图2中的a-a’、b-b’、c-c’、d-d’和e-e’线的垂直剖面示意图。结合附图1至附图3所示，半导体结构包括：An embodiment of the present disclosure provides a semiconductor structure, FIG1 is a three-dimensional schematic diagram of the semiconductor structure, FIG2 is a top view schematic diagram of the semiconductor structure, and FIG3 is a vertical cross-sectional schematic diagram of the semiconductor structure along lines a-a', b-b', c-c', d-d', and e-e' in FIG2. In combination with FIG1 to FIG3, the semiconductor structure includes:

衬底10，衬底10包括核心区域12和阶梯区域11；A substrate 10, the substrate 10 comprising a core region 12 and a step region 11;

位于核心区域12的多组有源柱堆叠结构26，有源柱堆叠结构26包括沿竖直方向依次堆叠分布的多个有源柱27，有源柱27沿第一方向延伸，第一方向与水平面平行；A plurality of active pillar stacking structures 26 located in the core region 12, the active pillar stacking structures 26 comprising a plurality of active pillars 27 stacked and distributed in sequence along a vertical direction, the active pillars 27 extending along a first direction, the first direction being parallel to a horizontal plane;

位于阶梯区域11的多组位线连接线叠层结构42，位线连接线叠层结构42包括沿竖直方向依次堆叠分布的多条位线连接线29，一条位线连接线29对应电连接一个有源柱27；其中，A plurality of bit line connection line stack structures 42 are located in the step region 11, and the bit line connection line stack structures 42 include a plurality of bit line connection lines 29 stacked and distributed in sequence along the vertical direction, and one bit line connection line 29 is electrically connected to one active pillar 27; wherein,

多条位线连接线29，每条位线连接线29均包括倾斜区段43，倾斜区段43的延伸方向与水平方向之间具有夹角。Each of the plurality of bit line connection lines 29 includes an inclined section 43 , and an angle is formed between an extending direction of the inclined section 43 and a horizontal direction.

上述半导体结构中的位线连接线29具有倾斜区段43，相比于传统的水平延伸的位线阶梯结构，具有倾斜区段43的位线连接线阶梯结构占用的面积更小，增加了空间利用率，可进一步提高集成度，实现更高的存储密度。The bit line connection line 29 in the above semiconductor structure has an inclined section 43. Compared with the traditional horizontally extending bit line step structure, the bit line connection line step structure with the inclined section 43 occupies a smaller area, increases space utilization, and can further improve integration and achieve higher storage density.

在实际操作中，衬底10例如包括但不限于单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。衬底可以是掺杂的或未掺杂的，或者在其中包含掺杂区域和未掺杂区域二者。衬底还可以包括一个或多个掺杂(n-或p-)区域；如果衬底包括多个掺杂区域，则这些区域可以具有相同或者不同的导电性和/或掺杂浓度。这些掺杂区域被称为“阱”，并且可以用于限定各个器件区域。在一具体实施例中，衬底10包括经掺杂或未经掺杂的硅衬底。有源柱27的材料可以包括但不限于单晶硅、多晶硅或铟镓锌的氧化物等，位线连接线29的材料可以包括导电材料，例如金属硅化物材料。In actual operation, the substrate 10 includes, for example, but is not limited to, a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate may be doped or undoped, or contain both doped and undoped regions. The substrate may also include one or more doped (n- or p-) regions; if the substrate includes Multiple doped regions may have the same or different conductivity and/or doping concentration. These doped regions are called "wells" and can be used to define various device regions. In a specific embodiment, the substrate 10 includes a doped or undoped silicon substrate. The material of the active pillar 27 may include but is not limited to single crystal silicon, polycrystalline silicon or indium gallium zinc oxide, and the material of the bit line connection line 29 may include a conductive material, such as a metal silicide material.

在一些实施例中，每组位线连接线叠层结构42中相邻的位线连接线29之间的间距与位线连接线29的厚度的比值范围为2到4。相邻的位线连接线29距离过近，容易产生相互串扰，相邻的位线连接线29距离过远会降低位线连接线29的密度，上述数值范围能够兼顾相互串扰和位线连接线29密度的问题。In some embodiments, the ratio of the spacing between adjacent bit line connection lines 29 in each group of bit line connection line stack structures 42 to the thickness of the bit line connection lines 29 is in a range of 2 to 4. If the adjacent bit line connection lines 29 are too close, mutual crosstalk is likely to occur, and if the adjacent bit line connection lines 29 are too far apart, the density of the bit line connection lines 29 will be reduced. The above numerical range can take into account both the mutual crosstalk and the density of the bit line connection lines 29.

在一些实施例中，一组位线连接线叠层结构42中，相邻位线连接线29的倾斜区段43之间的间距小于等于有源柱堆叠结构26中沿竖直方向相邻的有源柱27之间的间距。In some embodiments, in a group of bit line connection line stack structures 42 , the spacing between the inclined sections 43 of adjacent bit line connection lines 29 is less than or equal to the spacing between the active pillars 27 adjacent to each other in the vertical direction in the active pillar stack structure 26 .

相邻的位线连接线29的倾斜区段43之间的间距小于相邻有源柱27之间的间距，能够使得位线连接线29远离有源柱27的端部在水平面上排布更加密集，最终使得位线41之间的间距减小，实现更加密集的排布。The spacing between the inclined sections 43 of adjacent bit line connection lines 29 is smaller than the spacing between adjacent active pillars 27, which enables the ends of the bit line connection lines 29 away from the active pillars 27 to be arranged more densely on the horizontal plane, ultimately reducing the spacing between the bit lines 41 and achieving a denser arrangement.

本实施例中，水平面是指衬底10所在平面。In this embodiment, the horizontal plane refers to the plane where the substrate 10 is located.

在一些实施例中，夹角的范围为15度至65度，包括端点值，例如27度、35度、45度、55度或60度。In some embodiments, the angle ranges from 15 degrees to 65 degrees, including endpoints, such as 27 degrees, 35 degrees, 45 degrees, 55 degrees, or 60 degrees.

当夹角的角度小于15度时，位线连接线29的倾斜区段43的坡度比较平缓，导致位线连接线29阶梯区域占据的面积较大，不利于集成度的提高；当夹角的角度大于65度时，位线连接线29的倾斜区段43的坡度较大，倾斜区段43与水平区段44连接处比较陡峭，容易导致尖端放电，进而引起击穿现象，从而影响半导体器件的性能。因此，在一些更具体的实施方式中，夹角的角度可以为20度至45度，包括端点值，以使得位线连接线29的倾斜区段43在水平面上的投影具有足够的面积，便于与后续形成的位线插塞形成良好的连接，同时兼顾性能和集成度的提高。When the angle is less than 15 degrees, the slope of the inclined section 43 of the bit line connection line 29 is relatively gentle, resulting in a larger area occupied by the step region of the bit line connection line 29, which is not conducive to the improvement of integration; when the angle is greater than 65 degrees, the slope of the inclined section 43 of the bit line connection line 29 is relatively large, and the connection between the inclined section 43 and the horizontal section 44 is relatively steep, which is easy to cause tip discharge, and then cause breakdown, thereby affecting the performance of the semiconductor device. Therefore, in some more specific embodiments, the angle can be 20 degrees to 45 degrees, including the end value, so that the projection of the inclined section 43 of the bit line connection line 29 on the horizontal plane has enough area, which is convenient for forming a good connection with the bit line plug formed subsequently, while taking into account the improvement of performance and integration.

在一些实施例中，参见附图3，沿远离有源柱27的方向，倾斜区段43的高度逐渐抬升。In some embodiments, referring to FIG. 3 , the height of the inclined section 43 gradually increases in a direction away from the active pillar 27 .

这里，倾斜区段43的高度逐渐抬升，以便于工艺的制备，应当理解的是，沿远离有源柱27的方向，倾斜区段43的高度也可以逐渐下降，最终位线41可设置于位线连接线29的下方。Here, the height of the inclined section 43 is gradually raised to facilitate the preparation of the process. It should be understood that the height of the inclined section 43 may also gradually decrease in the direction away from the active pillar 27 , and finally the bit line 41 may be arranged below the bit line connection line 29 .

在一些实施例中，参见附图3，位线连接线29还包括水平区段44，水平区段44沿第一方向延伸，水平区段44电连接倾斜区段43的底端和与该条位线连接线29对应的有源柱27的一端。In some embodiments, referring to FIG. 3 , the bit line connection line 29 further includes a horizontal section 44 extending along the first direction and electrically connecting the bottom end of the inclined section 43 and one end of the active pillar 27 corresponding to the bit line connection line 29 .

在一些实施例中，参见附图3，半导体结构还包括：In some embodiments, referring to FIG. 3 , the semiconductor structure further includes:

多个位线插塞39，一个位线插塞39的底端电连接一条位线连接线29的倾斜区段43的顶端。There are a plurality of bit line plugs 39 , and a bottom end of one bit line plug 39 is electrically connected to a top end of an inclined section 43 of one bit line connection line 29 .

位线插塞39可以将具有倾斜区段43的位线连接线29引出至半导体器件的表面，便于后续将位线连接线29连接至外部控制电路。The bit line plug 39 can lead the bit line connection line 29 having the inclined section 43 to the surface of the semiconductor device, so as to facilitate the subsequent connection of the bit line connection line 29 to an external control circuit.

在实际操作中，位线插塞39的材料可以包括导电材料，其中位线插塞39的材料与位线连接线29的材料可以相同也可以不同，在一些具体的实施例中，位线连接线29和位线插塞39的材料均可以为金属硅化物，材料相同，接触电阻较小，有利于提升半导体器件的性能。In actual operation, the material of the bit line plug 39 may include a conductive material, wherein the material of the bit line plug 39 may be the same as or different from the material of the bit line connecting line 29. In some specific embodiments, the material of the bit line connecting line 29 and the bit line plug 39 may both be metal silicide. The same material has a small contact resistance, which is beneficial to improving the performance of the semiconductor device.

在一些实施例中，参见附图1和附图3，半导体结构还包括：In some embodiments, referring to FIGS. 1 and 3 , the semiconductor structure further includes:

多条位线41，位线41沿第二方向延伸，第二方向平行于水平面且与第一方向相交；一条位线41与多组位线连接线叠层结构42中位于同一层的位线连接线29电连接。A plurality of bit lines 41 extend along a second direction parallel to the horizontal plane and intersecting the first direction; one bit line 41 is electrically connected to the bit line connection lines 29 in the same layer of the plurality of bit line connection line stack structures 42 .

在一些具体实施方式中，第二方向与第一方向垂直。In some embodiments, the second direction is perpendicular to the first direction.

位线41将位于同一层的位线连接线29连接在一起引出，后续连接至外部控制电路，能够实现同时对多个存储单元进行控制。这里位于同一层的位线连接线29定义为通过同一层半导体层14图形化获得的所有位线连接线29。The bit line 41 connects the bit line connection lines 29 on the same layer and leads out, and is subsequently connected to an external control circuit. It is possible to control multiple memory cells at the same time. Here, the bit line connection lines 29 located in the same layer are defined as all the bit line connection lines 29 obtained by patterning the same semiconductor layer 14 .

在实际操作中，位线41可以包括导电材料，例如金属、含碳材料或金属氮化物等，具体的，例如包括但不限于钨、铜、石墨烯或氮化钛等。In actual operation, the bit line 41 may include a conductive material, such as a metal, a carbon-containing material, or a metal nitride, and specifically includes but is not limited to tungsten, copper, graphene, or titanium nitride.

在一些实施例中，参见附图3，有源柱27包括沟道区(图中未示出)；半导体结构还包括：多条字线37，字线37沿竖直方向延伸，且一条字线37围绕一组有源柱堆叠结构26中的沟道区。In some embodiments, referring to FIG. 3 , the active pillar 27 includes a channel region (not shown); the semiconductor structure also includes: a plurality of word lines 37 , the word lines 37 extend in a vertical direction, and a word line 37 surrounds a channel region in a group of active pillar stack structures 26 .

形成的字线37与沟道区共同构成晶体管，字线37可作为晶体管的栅极提供驱动。单条字线37沿竖直方向延伸，围绕一组有源柱堆叠结构26中的每个有源柱27的沟道区，能够对多个晶体管提供控制。The word line 37 and the channel region together form a transistor, and the word line 37 can be used as a gate of the transistor to provide drive. A single word line 37 extends in a vertical direction, surrounds the channel region of each active pillar 27 in a group of active pillar stack structures 26, and can provide control for multiple transistors.

在实际操作中，字线37与沟道区之间可以设置栅介质层35。栅介质层35的材料可以包括氧化硅、高k介电材料或它们的组合，字线37的材料可以包括多晶硅和/或金属电极(比如钨)等。在一些实施例中，还可以在栅介质层35与字线材料层之间形成一层阻挡层以防止字线材料的扩散，阻挡层的材料例如可以为氮化钛。In actual operation, a gate dielectric layer 35 may be disposed between the word line 37 and the channel region. The material of the gate dielectric layer 35 may include silicon oxide, a high-k dielectric material, or a combination thereof, and the material of the word line 37 may include polysilicon and/or a metal electrode (such as tungsten), etc. In some embodiments, a barrier layer may be formed between the gate dielectric layer 35 and the word line material layer to prevent diffusion of the word line material, and the material of the barrier layer may be, for example, titanium nitride.

在一些实施例中，参见附图3，半导体结构还包括：第一网状支撑结构241和第二网状支撑结构242，字线37位于第一网状支撑结构241与第二网状支撑结构242之间；有源柱27还包括源区(图中未示出)与漏区(图中未示出)，第一网状支撑结构241围绕至少一组有源柱堆叠结构26中的源区，第二网状支撑结构242围绕至少一组有源柱堆叠结构26中的漏区。In some embodiments, referring to FIG3 , the semiconductor structure further includes: a first mesh support structure 241 and a second mesh support structure 242, and the word line 37 is located between the first mesh support structure 241 and the second mesh support structure 242; the active pillar 27 further includes a source region (not shown in the figure) and a drain region (not shown in the figure), and the first mesh support structure 241 surrounds the source region in at least one group of active pillar stacking structures 26, and the second mesh support structure 242 surrounds the drain region in at least one group of active pillar stacking structures 26.

第一网状支撑结构241与第二网状支撑结构242在制造半导体结构的工艺中，对横向延伸的悬空有源柱27以及与有源柱27为连续结构的悬空位线连接线29提供有效的支撑作用，从而方便工艺中对有源柱27的掺杂、形成包围字线37以及位线连接线29金属硅化物反应的顺利执行，防止在制造过程中出现倒塌或者断裂等现象，显著提高了半导体结构在制造过程中的稳定性。During the process of manufacturing the semiconductor structure, the first mesh support structure 241 and the second mesh support structure 242 provide effective support for the laterally extending suspended active pillars 27 and the suspended bit line connection lines 29 which are continuous structures with the active pillars 27, thereby facilitating the doping of the active pillars 27, the formation of the surrounding word lines 37, and the smooth execution of the metal silicide reaction of the bit line connection lines 29, preventing collapse or breakage during the manufacturing process, and significantly improving the stability of the semiconductor structure during the manufacturing process.

在实际操作中，第一网状支撑结构241和第二网状支撑结构242的材料可以包括绝缘材料，例如氧化物、氮化物或氮氧化物，在一具体的实施例中，其材料可以为氮化硅。In actual operation, the materials of the first mesh support structure 241 and the second mesh support structure 242 may include insulating materials, such as oxide, nitride or oxynitride. In a specific embodiment, the material may be silicon nitride.

第一网状支撑结构241和第二网状支撑结构242分别位于源区和漏区，在对有源柱27起到有效的支撑作用的同时，不会对在有源柱27上的沟道区上形成字线37产生影响。The first mesh support structure 241 and the second mesh support structure 242 are respectively located in the source region and the drain region, and while effectively supporting the active pillar 27 , will not affect the formation of the word line 37 on the channel region on the active pillar 27 .

在一些其他实施例中，参见附图3，半导体结构还包括至少一个电容45，电容45的一个极板电连接一个有源柱27。In some other embodiments, referring to FIG. 3 , the semiconductor structure further includes at least one capacitor 45 , and one plate of the capacitor 45 is electrically connected to one active pillar 27 .

电容45包括第一电极层451、电容介质层452以及第二电极层453。单个电容45与对应的有源柱27内的晶体管共同构成一个存储单元。这里，电容45可以为桶状电容或者柱状电容，桶状电容沿垂直于衬底所在平面方向堆叠在有源柱27上，柱状电容包裹有源柱27。The capacitor 45 includes a first electrode layer 451, a capacitor dielectric layer 452, and a second electrode layer 453. A single capacitor 45 and a transistor in a corresponding active column 27 together constitute a storage unit. Here, the capacitor 45 can be a barrel capacitor or a column capacitor, the barrel capacitor is stacked on the active column 27 in a direction perpendicular to the plane of the substrate, and the column capacitor wraps the active column 27.

在第一方向上，一组有源柱堆叠结构26中的一条有源柱27连接一组位线连接线叠层结构42中位于同层的位线连接线29，因而在垂直衬底10所在平面方向上，有源柱堆叠结构26中有源柱27的条数与位线连接线叠层结构42中位线连接线29的条数对应。在第二方向上，有源柱堆叠结构26的组数与位线连接线叠层结构42的组数对应。字线37的条数与有源柱堆叠结构26的组数对应。位线41的条数与一组或多组有源柱堆叠结构26中有源柱27的条数对应。因而，一些实施例中，半导体结构还可以包括一组有源柱堆叠结构26，对应一组位线连接线叠层结构42，一条字线37与多条位线41。上述第一方向与水平面平行，其中，水平面指衬底10所在平面，上述第二方向平行于水平面且与第一方向相交。在一些具体的实施例中，第二方向与第一方向垂直。In the first direction, an active pillar 27 in a group of active pillar stacking structures 26 is connected to a bit line connection line 29 in the same layer in a group of bit line connection line stacking structures 42, so that in the direction perpendicular to the plane where the substrate 10 is located, the number of active pillars 27 in the active pillar stacking structures 26 corresponds to the number of bit line connection lines 29 in the bit line connection line stacking structures 42. In the second direction, the number of groups of active pillar stacking structures 26 corresponds to the number of groups of bit line connection line stacking structures 42. The number of word lines 37 corresponds to the number of groups of active pillar stacking structures 26. The number of bit lines 41 corresponds to the number of active pillars 27 in one or more groups of active pillar stacking structures 26. Therefore, in some embodiments, the semiconductor structure may further include a group of active pillar stacking structures 26, corresponding to a group of bit line connection line stacking structures 42, a word line 37 and a plurality of bit lines 41. The first direction is parallel to the horizontal plane, wherein the horizontal plane refers to the plane where the substrate 10 is located, and the second direction is parallel to the horizontal plane and intersects with the first direction. In some specific embodiments, the second direction is perpendicular to the first direction.

一些实施例中，一组位线连接线叠层结构42中，也可以部分数目条位线连接线29包括倾斜区段43。 In some embodiments, in a set of bit line connection line stack structures 42 , a portion of the bit line connection lines 29 may include inclined sections 43 .

公开实施例还提供了一种半导体结构的制造方法，具体请参见附图4，如图所示，方法包括：The disclosed embodiment further provides a method for manufacturing a semiconductor structure. Please refer to FIG. 4 for details. As shown in the figure, the method includes:

步骤101：提供衬底10，衬底10包括阶梯区域11和核心区域12；Step 101: providing a substrate 10, wherein the substrate 10 includes a step region 11 and a core region 12;

步骤102：在衬底10上方形成材料堆叠层13，材料堆叠层13包括多个沿竖直方向依次交替堆叠的半导体层14和牺牲层15，材料堆叠层13包括第一子区131、第二子区132和第三子区133，第一子区131与第二子区132位于阶梯区域11，第三子区133位于核心区域12；第二子区132与第三子区133中的半导体层14与牺牲层15沿水平方向延伸，第一子区131包括倾斜面16，倾斜面16与水平面之间存在夹角；Step 102: forming a material stacking layer 13 on the substrate 10, the material stacking layer 13 comprising a plurality of semiconductor layers 14 and sacrificial layers 15 alternately stacked in sequence along a vertical direction, the material stacking layer 13 comprising a first sub-region 131, a second sub-region 132 and a third sub-region 133, the first sub-region 131 and the second sub-region 132 being located in the step region 11, and the third sub-region 133 being located in the core region 12; the semiconductor layers 14 and the sacrificial layers 15 in the second sub-region 132 and the third sub-region 133 extending in a horizontal direction, the first sub-region 131 comprising an inclined surface 16, and an angle between the inclined surface 16 and the horizontal plane;

步骤103：至少对第一子区131与第二子区132执行刻蚀工艺，形成若干条沿第一方向延伸的第二沟槽20，第一方向与水平面平行，从而将第一子区131与第二子区132中的材料堆叠层13刻蚀为多组位线连接线待形成层堆叠结构25，位线连接线待形成层堆叠结构25包括多层位线连接线待形成层251；Step 103: performing an etching process on at least the first sub-region 131 and the second sub-region 132 to form a plurality of second trenches 20 extending along a first direction, wherein the first direction is parallel to the horizontal plane, thereby etching the material stacking layer 13 in the first sub-region 131 and the second sub-region 132 into a plurality of bit line connection line to-be-formed layer stacking structures 25, wherein the bit line connection line to-be-formed layer stacking structures 25 include a plurality of bit line connection line to-be-formed layers 251;

步骤104：对位线连接线待形成层251进行处理以形成位线连接线29。Step 104 : Processing the layer 251 for forming the bit line connection line to form the bit line connection line 29 .

下面结合具体实施例对本公开提供的半导体结构的制造方法再作进一步详细的说明。The manufacturing method of the semiconductor structure provided by the present disclosure is further described in detail below in conjunction with specific embodiments.

首先，执行步骤101，参见附图5，提供衬底10，衬底10包括阶梯区域11和核心区域12。First, step 101 is performed. Referring to FIG. 5 , a substrate 10 is provided. The substrate 10 includes a step region 11 and a core region 12 .

这里，阶梯区域11为后续形成台阶状位线的区域，核心区域12为后续形成存储单元的区域，例如晶体管和电容。Here, the step region 11 is a region where a stepped bit line is subsequently formed, and the core region 12 is a region where a memory cell, such as a transistor and a capacitor, is subsequently formed.

在一些实施例中，参见附图5，衬底10可以通过以下方法制备。具体的，提供衬底10，包括：提供基底(图中未示出)，基底包括第一分区101、第二分区102和第三分区103；刻蚀第二分区102与第三分区103，使得第三分区103的上表面低于第一分区101的上表面，第二分区102的上表面成为倾斜表面104，倾斜表面104上端连接第一分区101的上表面，下端连接第三分区103的上表面。In some embodiments, referring to FIG. 5 , the substrate 10 can be prepared by the following method. Specifically, providing the substrate 10 includes: providing a base (not shown in the figure), the base including a first partition 101, a second partition 102 and a third partition 103; etching the second partition 102 and the third partition 103, so that the upper surface of the third partition 103 is lower than the upper surface of the first partition 101, and the upper surface of the second partition 102 becomes an inclined surface 104, the upper end of the inclined surface 104 is connected to the upper surface of the first partition 101, and the lower end is connected to the upper surface of the third partition 103.

这里基底可以为具有水平表面的基体材料，例如，基底包括但不限于单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。在一具体实施例中，基底为经掺杂或未经掺杂的硅衬底。刻蚀基底的第二分区102与第三分区103可以采用干法刻蚀或湿法刻蚀工艺，例如等离子体刻蚀工艺、化学机械研磨工艺(CMP)等。Here, the substrate may be a base material with a horizontal surface, for example, the substrate includes but is not limited to a single semiconductor material substrate (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (for example, a silicon germanium (SiGe) substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GeOI) substrate, etc. In a specific embodiment, the substrate is a doped or undoped silicon substrate. The second partition 102 and the third partition 103 of the substrate may be etched by a dry etching process or a wet etching process, such as a plasma etching process, a chemical mechanical polishing process (CMP), etc.

通过将基底部分刻蚀形成具有倾斜面的阶梯区域11和核心区域12的衬底，为后续在衬底10上共形地形成具有斜坡区域的初始材料堆叠层17提供基础结构。A substrate having a stepped region 11 and a core region 12 with an inclined surface is formed by partially etching the base, thereby providing a basic structure for subsequently conformally forming an initial material stacking layer 17 having a slope region on the substrate 10 .

接下来，执行步骤102，参见附图7，在衬底10上方形成材料堆叠层13，材料堆叠层13包括多个沿竖直方向依次交替堆叠的半导体层14和牺牲层15，材料堆叠层13包括第一子区131、第二子区132和第三子区133，第一子区131与第二子区132位于所述阶梯区域11，第三子区133位于核心区域12；第二子区132与第三子区133中的半导体层14与牺牲层15沿水平方向延伸，第一子区131包括倾斜面16，倾斜面16与水平面之间存在夹角。Next, step 102 is performed, referring to FIG7 , to form a material stack layer 13 above the substrate 10, wherein the material stack layer 13 includes a plurality of semiconductor layers 14 and sacrificial layers 15 alternately stacked in a vertical direction, and the material stack layer 13 includes a first sub-region 131, a second sub-region 132, and a third sub-region 133, wherein the first sub-region 131 and the second sub-region 132 are located in the step region 11, and the third sub-region 133 is located in the core region 12; the semiconductor layers 14 and the sacrificial layers 15 in the second sub-region 132 and the third sub-region 133 extend in a horizontal direction, and the first sub-region 131 includes an inclined surface 16, and there is an angle between the inclined surface 16 and the horizontal plane.

在一些实施例中，第一子区131包括的倾斜面16与水平面之间的夹角的范围为15度至65度，包括端点值。In some embodiments, the angle between the inclined surface 16 included in the first sub-region 131 and the horizontal plane ranges from 15 degrees to 65 degrees, including end points.

当夹角的角度小于15度时，倾斜面16的坡度比较平缓，后续通过刻蚀第一子区131形成的具有倾斜区段的位线连接线29结构中阶梯区域占据的面积较大，不利于集成度的提高。当夹角的角度大于65度时，第一子区131与第二子区132的连接处比较陡峭，后续形成的位线连接线29在上述连接处容易导致尖端放电，进而引起击穿现象，从而影响半导体器件的性能。因此，在一些更具体的实施方式中，上述夹角的角度可以为20度至45度，包括端点值，以使得刻蚀第一子区131后形成的位线连接线29的倾斜区段在水平面上的投影具有足够的面积，便于后续形成连接良好的位线插塞39，同时兼顾性能和集成度的提高。When the angle is less than 15 degrees, the slope of the inclined surface 16 is relatively gentle, and the area occupied by the step region in the structure of the bit line connection line 29 with an inclined section formed by etching the first sub-region 131 is relatively large, which is not conducive to improving the integration. When the angle is greater than 65 degrees, the connection between the first sub-region 131 and the second sub-region 132 is relatively steep, and the subsequently formed bit line connection line 29 is prone to tip discharge at the above connection, thereby causing breakdown, thereby affecting the performance of the semiconductor device. Therefore, in some more specific embodiments, the angle of the above-mentioned angle can be 20 degrees to 45 degrees, including the endpoint value, so that the projection of the inclined section of the bit line connection line 29 formed after etching the first sub-region 131 on the horizontal plane has a sufficient area, which is convenient for the subsequent formation of a well-connected bit line plug 39, while taking into account both performance and integration. degree of improvement.

在实际操作中，夹角的大小控制可以通过增大或减小等离子源与承载基底的基台之间的偏置电压，改变等离子单向性来实现；或者，通过选择刻蚀气体和/或工艺条件，使得刻蚀副产物附着在倾斜表面，从而在刻蚀过程中对其进行保护来实现。In actual operation, the size of the angle can be controlled by increasing or decreasing the bias voltage between the plasma source and the base supporting the substrate, thereby changing the unidirectionality of the plasma; or, by selecting the etching gas and/or process conditions so that the etching by-products adhere to the inclined surface, thereby protecting it during the etching process.

在一些实施方式中，参见附图6和附图7，在衬底10上方形成材料堆叠层13的具体步骤，可以包括：在衬底10上方共形地形成初始材料堆叠层17，初始材料堆叠层17包括多个沿竖直方向依次交替堆叠的半导体层14与牺牲层15，位于核心区域12上方的初始材料堆叠层17的上表面不高于第一分区101的上表面(参见附图6)；对初始材料堆叠层17进行平坦化工艺，去除位于第一分区101上方的初始材料堆叠层17，并使得位于第二分区102和第三分区103上方的初始材料堆叠层17的上表面齐平(参见附图7)。In some embodiments, referring to FIGS. 6 and 7 , the specific steps of forming a material stack layer 13 above the substrate 10 may include: conformally forming an initial material stack layer 17 above the substrate 10, the initial material stack layer 17 including a plurality of semiconductor layers 14 and sacrificial layers 15 stacked alternately in a vertical direction, the upper surface of the initial material stack layer 17 above the core region 12 being no higher than the upper surface of the first partition 101 (see FIG. 6 ); performing a planarization process on the initial material stack layer 17 to remove the initial material stack layer 17 above the first partition 101, and making the upper surfaces of the initial material stack layer 17 above the second partition 102 and the third partition 103 flush (see FIG. 7 ).

通过提供具有阶梯区域11的衬底10，采用共形的方式沉积形成初始材料堆叠层17，可以一次性形成具有斜坡区域和水平延伸区域的材料堆叠层，不需要单独将水平延伸区域和斜坡区域的材料堆叠层分别生长，简化了工艺，且一次性形成的材料堆叠层在各分区的连接更牢固，不易发生脱落或断裂，其次，一次性形成的材料堆叠层各分区的特性差异小，不易对半导体器件的性能产生不利影响。By providing a substrate 10 with a step region 11 and depositing an initial material stacking layer 17 in a conformal manner, a material stacking layer with a slope region and a horizontal extension region can be formed at one time. There is no need to grow the material stacking layers of the horizontal extension region and the slope region separately, thereby simplifying the process. In addition, the material stacking layer formed at one time has a stronger connection between each partition and is less likely to fall off or break. Secondly, the characteristics of each partition of the material stacking layer formed at one time are slightly different, which is less likely to have an adverse effect on the performance of the semiconductor device.

在实际操作中，初始材料堆叠层17可以采用外延生长工艺形成，其中，半导体层14的材料可以包括但不仅限于单晶硅，牺牲层15的材料可以包括但不仅限于硅锗。对初始材料堆叠层17进行平坦化工艺可以采用例如化学机械研磨工艺(CMP)。In actual operation, the initial material stack layer 17 can be formed by an epitaxial growth process, wherein the material of the semiconductor layer 14 can include but is not limited to single crystal silicon, and the material of the sacrificial layer 15 can include but is not limited to silicon germanium. The initial material stack layer 17 can be planarized by, for example, a chemical mechanical polishing process (CMP).

在形成半导体层14与牺牲层15时，由于第二分区102的上表面为倾斜表面104，在形成牺牲层15时，位于倾斜表面104上的牺牲层15的厚度将小于等于位于第二子区132和第三子区133表面的牺牲层15的厚度，这将导致后续形成的结构中，相邻的位线连接线29之间的间距小于等于有源柱27之间的间距。相邻的位线连接线29的倾斜区段43之间的间距小于相邻有源柱27之间的间距，能够使得位线连接线29远离有源柱27的端部在水平面上排布更加密集，最终使得位线41之间的间距减小，实现更加密集的排布。When forming the semiconductor layer 14 and the sacrificial layer 15, since the upper surface of the second sub-region 102 is an inclined surface 104, when forming the sacrificial layer 15, the thickness of the sacrificial layer 15 located on the inclined surface 104 will be less than or equal to the thickness of the sacrificial layer 15 located on the surface of the second sub-region 132 and the third sub-region 133, which will result in that in the subsequently formed structure, the spacing between adjacent bit line connection lines 29 is less than or equal to the spacing between active pillars 27. The spacing between the inclined sections 43 of adjacent bit line connection lines 29 is smaller than the spacing between adjacent active pillars 27, which can make the ends of the bit line connection lines 29 away from the active pillars 27 more densely arranged on the horizontal plane, and finally reduce the spacing between the bit lines 41, thereby achieving a denser arrangement.

需要说明的是，在本公开实施例的附图中，仅示意性的示出了一定数量的半导体层14和牺牲层15堆叠形成材料堆叠层。在实际操作中，材料堆叠层的实际层数不受本公开实施例中附图所示数量的限制，具体的，材料堆叠层的层数可设置为不小于24层，例如：24层、48层、64层、128层、256层等。但不限于此，材料堆叠层的层数还可以为更多或更少的数值，在此不做具体限制，实际操作中，可根据需求灵活确定。It should be noted that in the drawings of the embodiments of the present disclosure, only a certain number of semiconductor layers 14 and sacrificial layers 15 are schematically shown to be stacked to form a material stack layer. In actual operation, the actual number of layers of the material stack layer is not limited by the number shown in the drawings of the embodiments of the present disclosure. Specifically, the number of layers of the material stack layer can be set to be no less than 24 layers, for example: 24 layers, 48 layers, 64 layers, 128 layers, 256 layers, etc. However, it is not limited to this, and the number of layers of the material stack layer can also be more or less values, which is not specifically limited here. In actual operation, it can be flexibly determined according to needs.

此外，交替堆叠的半导体层14与牺牲层15可以为单层半导体层与单层牺牲层依次交替堆叠、多层半导体层与单层牺牲层依次交替堆叠、单层半导体层与多层牺牲层依次交替堆叠或多层半导体层与多层牺牲层依次交替堆叠中的一种或多种组合，在此不作具体限制。In addition, the alternately stacked semiconductor layers 14 and sacrificial layers 15 can be one or more combinations of single-layer semiconductor layers and single-layer sacrificial layers alternately stacked in sequence, multiple-layer semiconductor layers and single-layer sacrificial layers alternately stacked in sequence, single-layer semiconductor layers and multiple-layer sacrificial layers alternately stacked in sequence, or multiple-layer semiconductor layers and multiple-layer sacrificial layers alternately stacked in sequence, and no specific limitation is made here.

接下来，执行步骤103，参见附图10，至少对第一子区131与第二子区132执行刻蚀工艺，形成若干条沿第一方向延伸的第二沟槽20，第一方向与水平面平行，从而将第一子区131与第二子区132中的材料堆叠层13刻蚀为多组位线连接线待形成层堆叠结构25；位线连接线待形成层堆叠结构25包括多层位线连接线待形成层251。Next, execute step 103, refer to Figure 10, and perform an etching process on at least the first sub-region 131 and the second sub-region 132 to form a plurality of second grooves 20 extending along a first direction, wherein the first direction is parallel to the horizontal plane, thereby etching the material stack layer 13 in the first sub-region 131 and the second sub-region 132 into a plurality of groups of bit line connection line to-be-formed layer stack structures 25; the bit line connection line to-be-formed layer stack structures 25 include a plurality of layers of bit line connection line to-be-formed layers 251.

在一些实施例中，首先参见附图8和附图9，在形成第二沟槽20之前，方法还包括：对第三子区133执行刻蚀工艺，形成若干沿第一方向延伸的第一沟槽18，从而将位于第三子区133的半导体层14刻蚀为多组有源柱堆叠结构26(参见附图8)；去除牺牲层15(参见附图9)。In some embodiments, first referring to Figures 8 and 9, before forming the second trench 20, the method also includes: performing an etching process on the third sub-region 133 to form a plurality of first trenches 18 extending along the first direction, thereby etching the semiconductor layer 14 located in the third sub-region 133 into a plurality of groups of active column stacking structures 26 (see Figure 8); and removing the sacrificial layer 15 (see Figure 9).

通过刻蚀形成第一沟槽18将半导体层14刻蚀为多个沿第一方向延伸的半导体柱，为后续形成横向晶体管提供有源区，此外，后续制造步骤中利用第一沟槽18的开口来去除牺牲层15，不需进行其他额外的步骤，使得工艺流程更加简单。The semiconductor layer 14 is etched into a plurality of semiconductor pillars extending along a first direction by etching to form a first groove 18, thereby providing an active area for the subsequent formation of a lateral transistor. In addition, the sacrificial layer 15 is removed by utilizing the opening of the first groove 18 in subsequent manufacturing steps without the need for other additional steps, thereby making the process flow simpler.

在实际操作中，刻蚀第三子区133形成第一沟槽18，可以采用各向异性刻蚀工艺，例如等离子体刻蚀工艺形成。去除牺牲层15可以采用湿法刻蚀工艺，例如采用酸性溶液腐蚀去除。In actual operation, the third sub-region 133 is etched to form the first trench 18, which may be formed by an anisotropic etching process, such as a plasma etching process. The sacrificial layer 15 may be removed by a wet etching process, such as an acid solution etching process. Corrosion removal.

在一些具体的实施例中，参见附图8，形成多个沿第一方向延伸的第一沟槽18之后，去除牺牲层15之前，方法还包括：形成第一介质层19，第一介质层19填充第一沟槽18并覆盖材料堆叠层13的上表面；对第三子区133进行刻蚀工艺，去除第一沟槽18内的部分第一介质层19，形成多个第三沟槽21和多个第四沟槽(第四沟槽与第三沟槽21平行对称分布，与附图8中d-d’方向剖面示意图中示出的第三沟槽21具有类似结构，所以未在图中重复示出)，多个第三沟槽21沿第二方向排列，多个第四沟槽沿第二方向排列，第二方向平行于水平面且与第一方向相交；去除暴露于第三沟槽21与第四沟槽内的牺牲层15，使得第三沟槽21在第二方向上连通形成第一网状沟槽A，第四沟槽在第二方向上连通形成第二网状沟槽B；通过第一网状沟槽A与第二网状沟槽B对半导体层14执行掺杂工艺，以使暴露于第一网状沟槽A内的半导体层14形成源区(图中未示出)，暴露于第二网状沟槽B内的半导体层14形成漏区(图中未示出)；形成第二介质层，填充于第一网状沟槽A内的第二介质层构成第一网状支撑结构241，填充于第二网状沟槽B内的第二介质层构成第二网状支撑结构242。In some specific embodiments, referring to FIG8 , after forming a plurality of first grooves 18 extending along the first direction and before removing the sacrificial layer 15, the method further includes: forming a first dielectric layer 19, the first dielectric layer 19 filling the first groove 18 and covering the upper surface of the material stack layer 13; performing an etching process on the third sub-region 133 to remove a portion of the first dielectric layer 19 in the first groove 18 to form a plurality of third grooves 21 and a plurality of fourth grooves (the fourth grooves are parallel to and symmetrically distributed with the third grooves 21, and have a similar structure to the third grooves 21 shown in the cross-sectional schematic diagram in the d-d′ direction of FIG8 , so they are not repeatedly shown in the figure), the plurality of third grooves 21 are arranged along the second direction, the plurality of fourth grooves are arranged along the second direction, and the second direction is parallel to the third grooves 21. A horizontal plane intersects with the first direction; the sacrificial layer 15 exposed in the third groove 21 and the fourth groove is removed, so that the third groove 21 is connected in the second direction to form a first mesh groove A, and the fourth groove is connected in the second direction to form a second mesh groove B; a doping process is performed on the semiconductor layer 14 through the first mesh groove A and the second mesh groove B, so that the semiconductor layer 14 exposed in the first mesh groove A forms a source region (not shown in the figure), and the semiconductor layer 14 exposed in the second mesh groove B forms a drain region (not shown in the figure); a second dielectric layer is formed, and the second dielectric layer filled in the first mesh groove A constitutes a first mesh support structure 241, and the second dielectric layer filled in the second mesh groove B constitutes a second mesh support structure 242.

在去除牺牲层15之前形成第一网状支撑结构241和第二网状支撑结构242，使得后续去除牺牲层15之后，对横向延伸的悬空有源柱27以及与有源柱27为连续结构的悬空位线连接线待形成层251提供有效的支撑作用，从而方便后续工艺中对有源柱27的掺杂、形成包围字线37以及位线连接线29金属硅化物反应的顺利执行，防止在制造过程中出现倒塌或者断裂等现象，显著提高了半导体结构在制造过程中的稳定性。Before removing the sacrificial layer 15, a first mesh support structure 241 and a second mesh support structure 242 are formed, so that after the subsequent removal of the sacrificial layer 15, effective support is provided for the laterally extended suspended active pillars 27 and the suspended bit line connection line to-be-formed layer 251 which is a continuous structure with the active pillars 27, thereby facilitating the smooth execution of the doping of the active pillars 27, the formation of the surrounding word lines 37 and the metal silicide reaction of the bit line connection lines 29 in the subsequent processes, preventing the occurrence of collapse or breakage during the manufacturing process, and significantly improving the stability of the semiconductor structure during the manufacturing process.

在实际操作中，形成第一介质层19和第二介质层的工艺可采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种，其中，第一介质层19和第二介质层的材料可以包括绝缘材料，例如氧化物、氮化物或氮氧化物等，在一些具体的实施例中，第一介质层19的材料可以为氧化硅，第二介质层的材料可以为氮化硅。刻蚀第三子区133形成多个第三沟槽21与多个第四沟槽可以采用各向异性刻蚀工艺，例如等离子体刻蚀工艺形成。去除暴露于第三沟槽21与第四沟槽内的牺牲层15可以采用湿法刻蚀工艺，例如采用酸性溶液腐蚀去除。In actual operation, the process of forming the first dielectric layer 19 and the second dielectric layer may adopt one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, wherein the materials of the first dielectric layer 19 and the second dielectric layer may include insulating materials, such as oxides, nitrides or oxynitrides, etc. In some specific embodiments, the material of the first dielectric layer 19 may be silicon oxide, and the material of the second dielectric layer may be silicon nitride. Etching the third sub-region 133 to form a plurality of third trenches 21 and a plurality of fourth trenches may adopt an anisotropic etching process, such as a plasma etching process. Removing the sacrificial layer 15 exposed in the third trenches 21 and the fourth trenches may adopt a wet etching process, such as etching with an acidic solution.

在形成上述第一网状支撑结构241和第二网状支撑结构242之后，参见附图9，去除第一网状支撑结构241与第二网状支撑结构242之间的第一介质层19，形成多个沿第二方向排布的开口；去除暴露于开口内的牺牲层15，使得有源柱堆叠结构26中的有源柱27悬空。After forming the above-mentioned first mesh support structure 241 and the second mesh support structure 242, referring to FIG. 9, the first dielectric layer 19 between the first mesh support structure 241 and the second mesh support structure 242 is removed to form a plurality of openings arranged along the second direction; the sacrificial layer 15 exposed in the opening is removed so that the active pillar 27 in the active pillar stacking structure 26 is suspended.

利用去除第一介质层19后形成的开口来去除牺牲层15，不用再额外进行开槽的步骤，因此，简化了工艺，降低了成本。The sacrificial layer 15 is removed by utilizing the opening formed after removing the first dielectric layer 19 , and no additional grooving step is required, thereby simplifying the process and reducing the cost.

在实际操作中，去除第一介质层19可以采用干法刻蚀，如等离子体刻蚀，或湿法刻蚀工艺。去除牺牲层15可以采用湿法刻蚀工艺，例如采用酸性溶液腐蚀去除。In actual operation, the first dielectric layer 19 may be removed by dry etching, such as plasma etching, or wet etching. The sacrificial layer 15 may be removed by wet etching, such as etching with an acidic solution.

在去除牺牲层15之后，参见附图10，对第一子区131与第二子区132执行刻蚀工艺，形成多个沿第一方向延伸的第二沟槽20，包括：形成第三介质层28，第三介质层28填充第一沟槽18、相邻半导体层14之间的间隙并覆盖半导体层14的上表面；刻蚀第一子区131和第二子区132中的半导体层14与第三介质层28，形成多个沿第一方向延伸的第二沟槽20，第二沟槽20与第一沟槽18连通，从而将第一子区131和第二子区132中的半导体层14刻蚀为多组位线连接线待形成层堆叠结构25，其中，位线连接线待形成层251的侧面从第二沟槽20中暴露。After removing the sacrificial layer 15, referring to FIG. 10, an etching process is performed on the first sub-region 131 and the second sub-region 132 to form a plurality of second grooves 20 extending along the first direction, including: forming a third dielectric layer 28, the third dielectric layer 28 filling the first groove 18, the gap between the adjacent semiconductor layer 14 and covering the upper surface of the semiconductor layer 14; etching the semiconductor layer 14 and the third dielectric layer 28 in the first sub-region 131 and the second sub-region 132 to form a plurality of second grooves 20 extending along the first direction, the second grooves 20 being connected to the first grooves 18, thereby etching the semiconductor layer 14 in the first sub-region 131 and the second sub-region 132 into a plurality of groups of bit line connection line to be formed layer stack structures 25, wherein the side surfaces of the bit line connection line to be formed layer 251 are exposed from the second grooves 20.

通过刻蚀工艺将半导体层14刻蚀为条状的位线连接线待形成层251，同时使得位线连接线待形成层251的侧面暴露，后续可通过暴露的侧面对位线连接线待形成层251进行处理，形成位线连接线29，可以省去单独暴露位线连接线待形成层251的工艺，简化了工艺流程。The semiconductor layer 14 is etched into a strip-shaped bit line connection line to be formed layer 251 by an etching process, and the side of the bit line connection line to be formed layer 251 is exposed. The bit line connection line to be formed layer 251 can be processed through the exposed side to form the bit line connection line 29, which can save the process of exposing the bit line connection line to be formed layer 251 separately, simplifying the process. process.

在实际操作中，形成第三介质层28的工艺可采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种，其中，第三介质层28的材料可以包括绝缘材料，例如氧化物、氮化物或氮氧化物等，在一具体的实施例中，第三介质层28的材料可以为氧化硅。刻蚀第一子区131和第二子区132中的半导体层14与第三介质层28形成第二沟槽20可以采用各向异性刻蚀工艺，例如等离子体刻蚀工艺形成。In actual operation, the process of forming the third dielectric layer 28 may adopt one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, wherein the material of the third dielectric layer 28 may include insulating materials, such as oxides, nitrides or oxynitrides, etc. In a specific embodiment, the material of the third dielectric layer 28 may be silicon oxide. Etching the semiconductor layer 14 and the third dielectric layer 28 in the first sub-region 131 and the second sub-region 132 to form the second trench 20 may adopt an anisotropic etching process, such as a plasma etching process.

在一些其他实施方式中，在形成第二沟槽20之后，参见附图11，方法还包括：去除位于第一子区131与第二子区132内的第三介质层28，暴露位线连接线待形成层251。In some other embodiments, after forming the second trench 20 , referring to FIG. 11 , the method further includes: removing the third dielectric layer 28 located in the first sub-region 131 and the second sub-region 132 to expose the layer 251 for forming the bit line connection line.

在该实施方式中，不满足于位线连接线待形成层251仅有侧壁暴露，进一步将位线连接线待形成层251上表面、下表面以及一个端面也使其暴露，由于暴露的表面更多，在后续对位线连接线待形成层251进行金属硅化处理工艺时，能够提高金属硅化处理的效果，进而降低形成的位线连接线29的电阻，从而提高半导体器件的性能。In this embodiment, the present invention is not satisfied with exposing only the side walls of the bit line connection line layer 251, but further exposes the upper surface, the lower surface and one end face of the bit line connection line layer 251. Since more surfaces are exposed, the effect of the metal silicidation treatment can be improved when the bit line connection line layer 251 is subsequently subjected to a metal silicidation treatment process, thereby reducing the resistance of the formed bit line connection line 29, thereby improving the performance of the semiconductor device.

在实际操作中，去除第三介质层28可以采用湿法刻蚀等工艺去除。In actual operation, the third dielectric layer 28 may be removed by using a process such as wet etching.

最后，执行步骤104，参见附图12，对位线连接线待形成层251进行处理以形成位线连接线29。Finally, step 104 is performed, referring to FIG. 12 , in which the layer 251 for forming the bit line connection line is processed to form the bit line connection line 29 .

具体地，包括：在位线连接线待形成层251暴露的表面上形成金属层(图中未示出)；进行第一次热处理工艺，以在位线连接线待形成层251上形成第一金属半导体化合物；去除未反应的金属层；进行第二次热处理工艺，以在位线连接线待形成层251上形成第二金属半导体化合物；其中，第二次热处理工艺的处理温度大于第一次热处理工艺的处理温度。Specifically, it includes: forming a metal layer (not shown in the figure) on the exposed surface of the bit line connection line layer 251 to be formed; performing a first heat treatment process to form a first metal semiconductor compound on the bit line connection line layer 251 to be formed; removing the unreacted metal layer; performing a second heat treatment process to form a second metal semiconductor compound on the bit line connection line layer 251 to be formed; wherein the treatment temperature of the second heat treatment process is greater than the treatment temperature of the first heat treatment process.

通过多次热处理工艺和控制热处理的温度，先形成具有高阻值的金属硅化物，再进一步处理形成低阻值的金属硅化物，最终实现电阻更低的位线连接线29的制造，且位线连接线29具有倾斜区段，相比于传统的水平延伸的位线连接线阶梯结构，具有倾斜区段的位线连接线阶梯结构占用的面积更小，增加了空间利用率，进一步提高了集成度。Through multiple heat treatment processes and controlling the temperature of the heat treatment, a metal silicide with a high resistance is first formed, and then further processed to form a metal silicide with a low resistance, and finally the manufacture of a bit line connection line 29 with a lower resistance is achieved. The bit line connection line 29 has an inclined section. Compared with the traditional horizontally extended bit line connection line step structure, the bit line connection line step structure with an inclined section occupies a smaller area, increases space utilization, and further improves integration.

在实际操作中，金属层的材料可以包括Ti、Co、Ni、Pt等中的一种或多种，在一具体的实施例中，金属层的材料可以为Ti，形成低阻值的金属硅化物作为位线的具体步骤为：首先，在位线连接线待形成层251暴露的表面沉积一层Ti薄膜，接着，再淀积一层TiN薄膜覆盖在Ti薄膜上，淀积TiN薄膜的目的是防止Ti在快速热退火处理时流动；接下来，进行第一次热处理，第一次热处理的温度范围可以为450℃～650℃，包括端点值，例如480℃、500℃、550℃或600℃等，金属Ti与位线连接线待形成层反应形成高阻态的金属硅化物Ti2Si，接着，可以利用选择性湿法刻蚀去除表面的TiN薄膜和没有反应的Ti薄膜；然后，进行第二次热处理，第二次热处理的温度可以在750℃以上，包括端点值，比如，800℃、850℃、900℃或高达950℃，可以将高阻态金属硅化物Ti2Si转化为低阻的金属硅化物TiSi2，金属硅化物TiSi2的热力学特性很好，非常稳定。In actual operation, the material of the metal layer may include one or more of Ti, Co, Ni, Pt, etc. In a specific embodiment, the material of the metal layer may be Ti. The specific steps of forming a low-resistance metal silicide as a bit line are as follows: first, a Ti film is deposited on the exposed surface of the bit line connection line to be formed layer 251, and then a TiN film is deposited to cover the Ti film. The purpose of depositing the TiN film is to prevent Ti from flowing during the rapid thermal annealing process; next, a first heat treatment is performed. The temperature range of the first heat treatment may be 450° C. to 650° C., including the end value, for example, 4 At 80°C, 500°C, 550°C or 600°C, the metal Ti reacts with the layer to be formed of the bit line connection line to form a high-resistance metal silicide Ti2Si. Then, the TiN film and the unreacted Ti film on the surface can be removed by selective wet etching. Then, a second heat treatment is performed. The temperature of the second heat treatment can be above 750°C, including endpoint values, such as 800°C, 850°C, 900°C or as high as 950°C. The high-resistance metal silicide Ti2Si can be converted into a low-resistance metal silicide TiSi2. The metal silicide TiSi2 has good thermodynamic properties and is very stable.

可以理解的是，当金属层的材料选择不同时，金属硅化处理步骤与上述步骤类似，但第一次热处理和第二次热处理的温度范围选择不同，例如，当金属层的材料为Co时，第一次热处理的温度范围可以为300℃～370℃，包括端点值，第二次热处理的温度范围可以为500℃以上，包括端点值，比如700℃。It can be understood that when the material of the metal layer is selected differently, the metal silicidation treatment step is similar to the above steps, but the temperature ranges of the first heat treatment and the second heat treatment are selected differently. For example, when the material of the metal layer is Co, the temperature range of the first heat treatment can be 300°C to 370°C, including the endpoint values, and the temperature range of the second heat treatment can be above 500°C, including the endpoint values, such as 700°C.

在一些实施例中，对位线连接线待形成层251处理形成位线连接线29之后，参见附图12，方法还包括：形成第四介质层30，第四介质层30填充位线连接线29之间的间隙并覆盖位线连接线29的上表面；对位于第一沟槽18内的第三介质层28执行刻蚀工艺，形成沿第二方向排布的多个隔离通孔31，第二方向平行于水平面且与第一方向相交，隔离通孔31沿竖直方向延伸，且隔离通孔31位于相邻两组有源柱堆叠结构26之间；采用隔离介质层填充隔离通孔31形成多个隔离结构32。In some embodiments, after the bit line connection line to-be-formed layer 251 is processed to form the bit line connection line 29, referring to FIG. 12, the method further includes: forming a fourth dielectric layer 30, the fourth dielectric layer 30 fills the gaps between the bit line connection lines 29 and covers the upper surfaces of the bit line connection lines 29; performing an etching process on the third dielectric layer 28 located in the first groove 18 to form a plurality of isolation through holes 31 arranged along a second direction, the second direction is parallel to the horizontal plane and intersects with the first direction, the isolation through holes 31 extend along a vertical direction, and the isolation through holes 31 are located between two adjacent groups of active column stacking structures 26; and filling the isolation through holes 31 with an isolation dielectric layer to form a plurality of isolation structures 32.

形成的隔离结构32可作为后续工艺中形成的字线37的绝缘隔离，进而缓解和降低字线37之间短路的可能性，降低了器件的不良率，从而提高半导体器件的性能稳定性与寿命。The formed isolation structure 32 can be used as an insulation isolation for the word line 37 formed in the subsequent process, thereby alleviating and reducing the word line The possibility of short circuit between the wires 37 is reduced, and the defect rate of the device is reduced, thereby improving the performance stability and life of the semiconductor device.

在实际操作中，形成第四介质层30和采用隔离介质层填充隔离通孔31的工艺可采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种，其中，第四介质层30和隔离介质层的材料可以包括绝缘材料，例如氧化物、氮化物或氮氧化物等，在一具体的实施例中，第四介质层30的材料可以为氧化硅，隔离介质层的材料可以为氮化硅。刻蚀第三介质层28形成隔离通孔31可以采用各向异性刻蚀工艺，例如等离子体刻蚀工艺形成。In actual operation, the process of forming the fourth dielectric layer 30 and filling the isolation through hole 31 with the isolation dielectric layer may adopt one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, wherein the materials of the fourth dielectric layer 30 and the isolation dielectric layer may include insulating materials, such as oxides, nitrides or oxynitrides, etc. In a specific embodiment, the material of the fourth dielectric layer 30 may be silicon oxide, and the material of the isolation dielectric layer may be silicon nitride. Etching the third dielectric layer 28 to form the isolation through hole 31 may adopt an anisotropic etching process, such as a plasma etching process.

在一些实施例中，在形成多个隔离结构32之后，参见附图13，方法还包括：刻蚀去除相邻隔离结构32之间的第三介质层28形成字线通孔33，字线通孔33沿竖直方向延伸，一组有源柱堆叠结构26中的所有有源柱27的沟道区暴露于一个字线通孔33中；In some embodiments, after forming a plurality of isolation structures 32, referring to FIG. 13, the method further includes: etching and removing the third dielectric layer 28 between adjacent isolation structures 32 to form a word line through hole 33, the word line through hole 33 extending in a vertical direction, and the channel regions of all active pillars 27 in a group of active pillar stack structures 26 are exposed in one word line through hole 33;

在字线通孔33内形成包覆有源柱27的沟道区的栅介质层35与栅极36，一组有源柱堆叠结构26中的所有有源柱27的栅极36连接在一起形成一条字线37。A gate dielectric layer 35 and a gate electrode 36 covering the channel region of the active pillar 27 are formed in the word line through hole 33 , and the gate electrodes 36 of all active pillars 27 in a group of active pillar stack structures 26 are connected together to form a word line 37 .

形成的栅极36与沟道区共同构成晶体管，一组有源柱堆叠结构26中的所有有源柱27的栅极36连接在一起形成一条字线37单条字线37沿竖直方向延伸，能够对一组有源柱堆叠结构26中的多个晶体管提供驱动。The formed gate 36 and the channel region together constitute a transistor. The gates 36 of all active pillars 27 in a group of active pillar stack structures 26 are connected together to form a word line 37. The single word line 37 extends in the vertical direction and can provide drive for multiple transistors in a group of active pillar stack structures 26.

在实际操作中，可采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种，沉积栅介质层材料和栅极材料层，其中栅介质层35的材料可以包括氧化硅、高k介电材料或它们的组合，栅极36的材料可以包括多晶硅和/或金属电极(比如钨)等。在一些实施例中，可以在栅介质层35与栅极36之间形成一层阻挡层以防止字线材料的扩散，阻挡层的材料例如可以为氮化钛。In actual operation, one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes may be used to deposit the gate dielectric layer material and the gate material layer, wherein the material of the gate dielectric layer 35 may include silicon oxide, high-k dielectric material or a combination thereof, and the material of the gate 36 may include polysilicon and/or a metal electrode (such as tungsten), etc. In some embodiments, a barrier layer may be formed between the gate dielectric layer 35 and the gate 36 to prevent diffusion of the word line material, and the material of the barrier layer may be, for example, titanium nitride.

在一些实施例中，在形成字线37之后，参见附图14和附图15，在形成位线连接线29之后，方法还包括：在位线连接线29上方形成多个位线插塞39，一个位线插塞39对应电连接一条位线连接线29。In some embodiments, after forming the word line 37 , referring to FIGS. 14 and 15 , after forming the bit line connection line 29 , the method further includes: forming a plurality of bit line plugs 39 above the bit line connection line 29 , one bit line plug 39 correspondingly electrically connected to one bit line connection line 29 .

具体的，如附图14至附图15所示，先形成插塞材料层，刻蚀插塞材料层形成多个位线插塞待形成结构38，每一位线插塞待形成结构38的底端对应连接一条位线连接线29(参见附图14)；在位线插塞待形成结构38上形成金属层；进行第三次热处理工艺，以在位线插塞待形成结构38上形成第三金属半导体化合物；去除未反应的金属层；进行第四次热处理工艺，在位线插塞待形成结构38上形成第四金属半导体化合物，以形成位线插塞39(参见附图15)；其中，第四次热处理工艺的处理温度大于第三次热处理工艺的处理温度。Specifically, as shown in FIGS. 14 and 15 , a plug material layer is first formed, and the plug material layer is etched to form a plurality of bit line plug structures 38 to be formed, wherein the bottom end of each bit line plug structure 38 to be formed is correspondingly connected to a bit line connecting line 29 (see FIG. 14 ); a metal layer is formed on the bit line plug structures 38 to be formed; a third heat treatment process is performed to form a third metal semiconductor compound on the bit line plug structures 38 to be formed; the unreacted metal layer is removed; a fourth heat treatment process is performed to form a fourth metal semiconductor compound on the bit line plug structures 38 to be formed to form bit line plugs 39 (see FIG. 15 ); wherein the treatment temperature of the fourth heat treatment process is greater than the treatment temperature of the third heat treatment process.

通过位线插塞39的制备将位线连接线29引出到半导体器件表面，以方便后续将位线连接线连接至外部的控制电路。此外，经金属硅化处理后，位线插塞39的材料可以与位线连接线29的材料为相同的低阻值金属硅化物，进而可降低位线插塞39与位线连接线29之间的接触电阻，因此，可提高半导体器件的性能。The bit line connection line 29 is led out to the surface of the semiconductor device by preparing the bit line plug 39, so as to facilitate the subsequent connection of the bit line connection line to the external control circuit. In addition, after the metal silicide treatment, the material of the bit line plug 39 can be the same low-resistance metal silicide as the material of the bit line connection line 29, thereby reducing the contact resistance between the bit line plug 39 and the bit line connection line 29, thereby improving the performance of the semiconductor device.

在实际操作中，形成插塞材料层可以采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种，其中，插塞材料层的材料可以包括但不限于硅。刻蚀插塞材料层形成多个位线插塞待形成结构38，可以首先在插塞材料层表面形成图形化的掩膜层，然后以图形化的掩膜层为掩膜进行刻蚀形成。对位线插塞待形成结构38进行金属硅化处理的方法可以参照上述对位线连接线待形成层251进行金属硅化处理的方法步骤，在此不再赘述。In actual operation, the plug material layer may be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, wherein the material of the plug material layer may include but is not limited to silicon. The plug material layer is etched to form a plurality of bit line plug structures to be formed 38. A patterned mask layer may be first formed on the surface of the plug material layer, and then etching is performed using the patterned mask layer as a mask. The method of performing metal silicide treatment on the bit line plug structure to be formed 38 may refer to the above-mentioned method steps for performing metal silicide treatment on the bit line connection line layer to be formed 251, which will not be repeated here.

在一些实施例中，在形成位线插塞39之后，参见附图16，方法还包括：在位线插塞39上方形成位线材料层；刻蚀位线材料层，形成多条位线41，位线41沿第二方向延伸，第二方向平行于水平面且与第一方向相交，且一条位线41与同一组的位线插塞39电连接，其中，连接同一层的位线连接线29的多个位线插塞39定义为同一组的位线插塞39。In some embodiments, after forming the bit line plugs 39, referring to FIG. 16, the method further includes: forming a bit line material layer above the bit line plugs 39; etching the bit line material layer to form a plurality of bit lines 41, the bit lines 41 extending along a second direction, the second direction being parallel to the horizontal plane and intersecting with the first direction, and a bit line 41 being electrically connected to the same group of bit line plugs 39, wherein a plurality of bit line plugs 39 connected to the bit line connection lines 29 of the same layer are defined as the same group of bit line plugs 39.

在一些具体实施方式中，第二方向与第一方向垂直。 In some embodiments, the second direction is perpendicular to the first direction.

具体的，如附图16所示，首先形成第五介质层40，第五介质层40填充相邻位线插塞39之间的间隙；然后，在位线插塞39与第五介质层40上方形成位线材料层；接着，刻蚀位线材料层，使得位线材料层形成至少一条位线41，位线41沿第二方向延伸，且位线41与同一组的位线插塞39电连接，其中，连接同一层的位线连接线29的多个位线插塞39定义为同一组的位线插塞39。Specifically, as shown in FIG. 16 , a fifth dielectric layer 40 is first formed to fill the gaps between adjacent bit line plugs 39; then, a bit line material layer is formed above the bit line plugs 39 and the fifth dielectric layer 40; then, the bit line material layer is etched to form at least one bit line 41 in the bit line material layer, the bit line 41 extends along the second direction, and the bit line 41 is electrically connected to the same group of bit line plugs 39, wherein a plurality of bit line plugs 39 connected to the bit line connection lines 29 of the same layer are defined as the same group of bit line plugs 39.

位线41将位于同一层的位线连接线29连接在一起引出，后续连接至外部控制电路，能够实现同时对多个存储单元进行控制，且位线41可以与***电路中的栅极结构/导电插塞等采用同一材料层一步刻蚀形成，能够显著简化工艺。The bit line 41 connects the bit line connection line 29 located on the same layer and leads out, and is subsequently connected to an external control circuit, so that multiple storage cells can be controlled simultaneously. The bit line 41 can be formed by etching in one step using the same material layer as the gate structure/conductive plug in the peripheral circuit, which can significantly simplify the process.

在实际操作中，形成第五介质层40和位线材料层可以采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种，其中第五介质层40的材料可以包括绝缘材料，例如氧化物、氮化物或氮氧化物等，在一具体的实施例中，第五介质层40的材料可以为氧化硅，位线材料层的材料可以为导电材料，例如氮化钛等。刻蚀位线材料层，形成位线41的方法可以首先在位线材料层表面形成图形化的掩膜层，然后以图形化的掩膜层为掩膜进行刻蚀形成。In actual operation, the fifth dielectric layer 40 and the bit line material layer may be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, wherein the material of the fifth dielectric layer 40 may include insulating materials, such as oxides, nitrides or oxynitrides, etc. In a specific embodiment, the material of the fifth dielectric layer 40 may be silicon oxide, and the material of the bit line material layer may be a conductive material, such as titanium nitride, etc. The method of etching the bit line material layer to form the bit line 41 may first form a patterned mask layer on the surface of the bit line material layer, and then perform etching using the patterned mask layer as a mask.

应当理解的是，附图5至附图16及相关文字示意出的制备方法仅为本公开提供的半导体结构的制备方法的一种实施方式，在上述实施方式中，在形成第一网状支撑结构241和第二网状支撑结构242之后，牺牲层15会被去除。然而，应当理解的是，在一些其他实施方式中，当牺牲层15的材料为介电层，例如包括但不限于氧化硅、氮化硅或氮氧化硅时，却可以被保留在半导体结构中。这里，半导体层14可以为多晶硅或铟镓锌的氧化物。相应地，对于制作方法，步骤102中，半导体层14与牺牲层15可采用沉积工艺形成，例如可以采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种工艺形成。It should be understood that the preparation method illustrated in Figures 5 to 16 and the related text is only one embodiment of the preparation method of the semiconductor structure provided by the present disclosure. In the above embodiment, after the first mesh support structure 241 and the second mesh support structure 242 are formed, the sacrificial layer 15 will be removed. However, it should be understood that in some other embodiments, when the material of the sacrificial layer 15 is a dielectric layer, such as but not limited to silicon oxide, silicon nitride or silicon oxynitride, it can be retained in the semiconductor structure. Here, the semiconductor layer 14 can be an oxide of polycrystalline silicon or indium gallium zinc. Accordingly, for the manufacturing method, in step 102, the semiconductor layer 14 and the sacrificial layer 15 can be formed by a deposition process, for example, one or more processes of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) can be used.

在牺牲层15被保留的实施方式中，将不再出现附图8至附图10及相关文字示意出的去除第一介质层19，以去除第一介质层19形成的开口去除牺牲层15，以及形成第三介质层的步骤。相比于如附图5至附图16及相关文字示意出的制备方法，省略了去除牺牲层15的步骤，简化了工艺步骤，降低了制造成本。In the embodiment where the sacrificial layer 15 is retained, the steps of removing the first dielectric layer 19, removing the sacrificial layer 15 by removing the opening formed by the first dielectric layer 19, and forming the third dielectric layer as shown in FIGS. 8 to 10 and the related text will no longer appear. Compared with the preparation method shown in FIGS. 5 to 16 and the related text, the step of removing the sacrificial layer 15 is omitted, the process steps are simplified, and the manufacturing cost is reduced.

相应地，步骤104中，对位线连接线待形成层251进行处理为对暴露在第二沟槽20内的位线连接线待形成层251侧壁进行金属硅化处理以形成金属硅化物。Accordingly, in step 104 , the bit line connection line to-be-formed layer 251 is processed by performing metal silicide treatment on the sidewalls of the bit line connection line to-be-formed layer 251 exposed in the second trench 20 to form metal silicide.

可以理解的，即使牺牲层15的材料为介电层，在一些其他实施方式中，也可以在形成位线连接线待形成层堆叠结构25之后，且在形成位线连接线29之前，去除位线连接线待形成层堆叠结构25中的牺牲层15。如此，能够使得位线连接线待形成层251的侧壁均全部裸露，那么，对位线连接线待形成层251进行处理将包括对位线连接线待形成层251的所有裸露侧壁进行金属硅化处理从而形成金属硅化物。在该实施方式中，不满足于位线连接线待形成层251仅有侧壁暴露，进一步将位线连接线待形成层251上表面、下表面也使其暴露，由于暴露的表面更多，在后续对位线连接线待形成层251进行金属硅化处理工艺时，能够提高金属硅化处理的效果，进而降低形成的位线连接线29的电阻，从而提高半导体器件的性能。It can be understood that even if the material of the sacrificial layer 15 is a dielectric layer, in some other embodiments, the sacrificial layer 15 in the bit line connection line to be formed layer stacking structure 25 can be removed after forming the bit line connection line to be formed layer stacking structure 25 and before forming the bit line connection line 29. In this way, the side walls of the bit line connection line to be formed layer 251 can be completely exposed, so the treatment of the bit line connection line to be formed layer 251 will include metal silicide treatment of all exposed side walls of the bit line connection line to be formed layer 251 to form metal silicide. In this embodiment, it is not satisfied that only the side walls of the bit line connection line to be formed layer 251 are exposed, and the upper surface and the lower surface of the bit line connection line to be formed layer 251 are further exposed. Since more surfaces are exposed, when the bit line connection line to be formed layer 251 is subsequently subjected to the metal silicide treatment process, the effect of the metal silicide treatment can be improved, thereby reducing the resistance of the formed bit line connection line 29, thereby improving the performance of the semiconductor device.

在附图5至附图16及相关文字示意出的制备方法的一种实施方式中，第一沟槽18与第二沟槽20在两步刻蚀工艺中形成。然而，在一些其他实施方式中，可以在对第一子区131与第二子区132执行刻蚀工艺形成第二沟槽20的同一步骤中也对第三子区133进行刻蚀，从而在形成第二沟槽20的同时形成若干沿第一方向延伸的第一沟槽18，第一沟槽18与第二沟槽20连通，从而将位于第三子区133的材料堆叠层13刻蚀为多组有源柱堆叠结构26，每组有源柱堆叠结构26包括多层有源柱27。In one embodiment of the preparation method illustrated in FIGS. 5 to 16 and the related text, the first trench 18 and the second trench 20 are formed in a two-step etching process. However, in some other embodiments, the third sub-region 133 may be etched in the same step of performing an etching process on the first sub-region 131 and the second sub-region 132 to form the second trench 20, so that a plurality of first trenches 18 extending along the first direction are formed while forming the second trench 20, and the first trenches 18 are connected to the second trenches 20, so that the material stack layer 13 located in the third sub-region 133 is etched into a plurality of groups of active column stack structures 26, each group of active column stack structures 26 including a plurality of active columns 27.

将第一沟槽18与第二沟槽20在同一步刻蚀工艺中执行，能够避免或改善第一沟槽18与第二沟槽20在不同工序中形成时的对准问题。 Performing the first trench 18 and the second trench 20 in the same etching process can avoid or improve the alignment problem when the first trench 18 and the second trench 20 are formed in different processes.

附图5至附图16及相关文字示意出的制备方法仅为本公开提供的半导体结构的制备方法的一种实施方式，在上述实施方式中，在形成位线连接线29之后还需要形成位线插塞39，最终位线41形成在位线插塞39上方。然而，在一些其他实施方式中，在形成位线连接线29之后，方法还包括：在位线连接线29上方形成位线材料层；刻蚀位线材料层，形成多条位线41，位线41沿第二方向延伸，且一条位线41电连接位于同一层的所有位线连接线29。如此，能够省去形成位线插塞39的步骤，缩短工艺流程，降低工艺成本。The preparation method illustrated in Figures 5 to 16 and the related text is only one embodiment of the preparation method of the semiconductor structure provided by the present disclosure. In the above embodiment, after forming the bit line connection line 29, it is also necessary to form a bit line plug 39, and finally the bit line 41 is formed above the bit line plug 39. However, in some other embodiments, after forming the bit line connection line 29, the method further includes: forming a bit line material layer above the bit line connection line 29; etching the bit line material layer to form a plurality of bit lines 41, the bit line 41 extends along the second direction, and one bit line 41 is electrically connected to all the bit line connection lines 29 located in the same layer. In this way, the step of forming the bit line plug 39 can be omitted, the process flow can be shortened, and the process cost can be reduced.

综上所述，本公开提供的半导体结构中，具有包括倾斜区段43的位线连接线阶梯结构，相比于通常具有多层水平存储单元层的三维存储器中的沿水平延伸的位线连接线阶梯结构，具有倾斜区段43的位线连接线阶梯结构占用的面积更小，增加了空间利用率，可进一步提高集成度，且制备工艺能够与现有的具有多层水平存储单元层的三维存储器的工艺流程兼容，流程简化，工艺成本低。In summary, the semiconductor structure provided by the present invention has a bit line connection line step structure including an inclined section 43. Compared with the horizontally extending bit line connection line step structure in a three-dimensional memory device that generally has multiple layers of horizontal memory cell layers, the bit line connection line step structure with the inclined section 43 occupies a smaller area, increases space utilization, and can further improve integration. Moreover, the preparation process is compatible with the existing process flow of a three-dimensional memory device that has multiple layers of horizontal memory cell layers, thereby simplifying the process and reducing the process cost.

需要说明的是，本公开实施例提供的半导体结构的制造方法及半导体结构可以应用于任何包括该结构的集成电路中，例如动态随机存取存储器(DRAM)。各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。It should be noted that the manufacturing method of the semiconductor structure and the semiconductor structure provided in the embodiments of the present disclosure can be applied to any integrated circuit including the structure, such as a dynamic random access memory (DRAM). The technical features in the technical solutions described in the embodiments can be combined arbitrarily without conflict.

以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

工业实用性Industrial Applicability

本公开提供的半导体结构中的位线连接线包括具有倾斜区段的位线阶梯结构，相比于上述水平延伸的位线阶梯结构，具有倾斜区段的位线阶梯结构占用的面积更小，增加了空间利用率，可进一步提高集成度，并且制作工艺简单，且能够与现有的具有多层水平存储单元层的三维存储器的工艺流程兼容，工艺成本低。 The bit line connection line in the semiconductor structure provided by the present invention includes a bit line ladder structure with an inclined section. Compared with the above-mentioned horizontally extending bit line ladder structure, the bit line ladder structure with an inclined section occupies a smaller area, increases space utilization, can further improve integration, and has a simple manufacturing process. It is compatible with the existing process flow of a three-dimensional memory with multiple horizontal storage unit layers, and has a low process cost.

Claims

一种半导体结构，包括：A semiconductor structure comprising:

衬底(10)，所述衬底(10)包括核心区域(12)和阶梯区域(11)；A substrate (10), the substrate (10) comprising a core region (12) and a step region (11);

位于所述核心区域(12)的至少一组有源柱堆叠结构(26)，所述有源柱堆叠结构(26)包括沿竖直方向依次堆叠分布的多个有源柱(27)，所述有源柱(27)沿第一方向延伸，所述第一方向与水平面平行；At least one group of active column stacking structures (26) located in the core region (12), the active column stacking structure (26) comprising a plurality of active columns (27) stacked and distributed in sequence along a vertical direction, the active columns (27) extending along a first direction, the first direction being parallel to a horizontal plane;

位于所述阶梯区域(11)的至少一组位线连接线叠层结构(42)，所述位线连接线叠层结构(42)包括沿竖直方向依次堆叠分布的多条位线连接线(29)，一条所述位线连接线(29)对应电连接一个所述有源柱(27)；其中，At least one group of bit line connection line stacked structures (42) located in the step region (11), the bit line connection line stacked structure (42) comprising a plurality of bit line connection lines (29) stacked and distributed in sequence along a vertical direction, one bit line connection line (29) correspondingly electrically connected to one active pillar (27); wherein:

至少一条所述位线连接线(29)包括倾斜区段(43)，所述倾斜区段(43)的延伸方向与水平方向之间具有夹角。At least one of the bit line connection lines (29) comprises an inclined section (43), and an extending direction of the inclined section (43) forms an angle with a horizontal direction.
根据权利要求1所述的半导体结构，其中，所述夹角的范围为15度至65度。The semiconductor structure according to claim 1, wherein the angle ranges from 15 degrees to 65 degrees.
根据权利要求1或2所述的半导体结构，其中，所述位线连接线(29)还包括水平区段(44)，所述水平区段(44)沿第一方向延伸，所述水平区段(44)电连接所述倾斜区段(43)的底端和与该条位线连接线(29)对应的所述有源柱(27)的一端。According to the semiconductor structure of claim 1 or 2, the bit line connection line (29) further includes a horizontal section (44), the horizontal section (44) extends along the first direction, and the horizontal section (44) electrically connects the bottom end of the inclined section (43) and one end of the active pillar (27) corresponding to the bit line connection line (29).
根据权利要求1至3任一项所述的半导体结构，其中，所述半导体结构还包括：The semiconductor structure according to any one of claims 1 to 3, wherein the semiconductor structure further comprises:

至少一个位线插塞(39)，所述位线插塞(39)的底端电连接所述倾斜区段(43)的顶端。At least one bit line plug (39), the bottom end of the bit line plug (39) is electrically connected to the top end of the inclined section (43).
根据权利要求1至4任一项所述的半导体结构，其中，所述核心区域(12)上包括多组所述有源柱堆叠结构(26)，所述阶梯区域(11)上包括多组所述位线连接线叠层结构(42)；The semiconductor structure according to any one of claims 1 to 4, wherein the core region (12) includes a plurality of groups of active pillar stack structures (26), and the step region (11) includes a plurality of groups of bit line connection line stack structures (42);

所述半导体结构还包括：The semiconductor structure further comprises:

多条位线(41)，所述位线(41)沿第二方向延伸，所述第二方向平行于水平面且与所述第一方向相交；一条所述位线(41)与多组所述位线连接线叠层结构(42)中位于同一层的所述位线连接线(29)电连接。A plurality of bit lines (41), the bit lines (41) extending along a second direction, the second direction being parallel to a horizontal plane and intersecting the first direction; one of the bit lines (41) being electrically connected to the bit line connection lines (29) located on the same layer in a plurality of groups of the bit line connection line stacked structures (42).
根据权利要求1至5任一项所述的半导体结构，其中，所述有源柱(27)包括沟道区；所述半导体结构还包括：The semiconductor structure according to any one of claims 1 to 5, wherein the active pillar (27) comprises a channel region; the semiconductor structure further comprises:

至少一条字线(37)，所述字线(37)沿竖直方向延伸，且所述字线(37)围绕一组所述有源柱堆叠结构(26)中的所述沟道区。At least one word line (37), the word line (37) extending in a vertical direction, and the word line (37) surrounding the channel region in a group of the active pillar stack structures (26).
根据权利要求1至6任一项所述的半导体结构，其中，还包括：The semiconductor structure according to any one of claims 1 to 6, further comprising:

至少一个电容(45)，所述电容(45)的一个极板电连接一个所述有源柱(27)。At least one capacitor (45), one plate of the capacitor (45) is electrically connected to one of the active pillars (27).
根据权利要求1至7任一项所述的半导体结构，其中，一组所述位线连接线叠层结构(42)中的每个所述位线连接线(29)均包括倾斜区段(43)。The semiconductor structure according to any one of claims 1 to 7, wherein each of the bit line connection lines (29) in a group of the bit line connection line stack structures (42) comprises an inclined section (43).
根据权利要求1至8任一项所述的半导体结构，其中，每组所述位线连接线叠层结构(42)中相邻的所述位线连接线(29)之间的间距与所述位线连接线(29)的厚度的比值范围为2到4。The semiconductor structure according to any one of claims 1 to 8, wherein the ratio of the spacing between adjacent bit line connection lines (29) in each group of the bit line connection line stacked structures (42) to the thickness of the bit line connection lines (29) ranges from 2 to 4.
根据权利要求1至9任一项所述的半导体结构，其中，一组所述位线连接线叠层结构(42)中，相邻所述位线连接线(29)的倾斜区段(43)之间的间距小于等于所述有源柱堆叠结构(26)中沿竖直方向相邻的所述有源柱(27)之间的间距。A semiconductor structure according to any one of claims 1 to 9, wherein in a group of the bit line connection line stack structures (42), the spacing between the inclined sections (43) of adjacent bit line connection lines (29) is less than or equal to the spacing between the active pillars (27) adjacent to each other in the vertical direction in the active pillar stack structure (26).
一种半导体结构的制备方法，包括：A method for preparing a semiconductor structure, comprising:

提供衬底(10)，所述衬底(10)包括阶梯区域(11)和核心区域(12)；Providing a substrate (10), wherein the substrate (10) comprises a step region (11) and a core region (12);

在所述衬底(10)上方形成材料堆叠层(13)，所述材料堆叠层(13)包括多个沿竖直方向依次交替堆叠的半导体层(14)和牺牲层(15)，所述材料堆叠层(13)包括第一子区(131)、第二子区(132)和第三子区(133)，所述第一子区(131)与所述第二子区(132)位于所述阶梯区域(11)，所述第三子区(133)位于所述核心区域(12)；所述第二子区(132)与所述第三子区(133)中的所述半导体层(14)与所述牺牲层(15)沿水平方向延伸，所述第一子区(131)包括倾斜面(16)，所述倾斜面(16)与水平面之间存在夹角；A material stacking layer (13) is formed above the substrate (10), wherein the material stacking layer (13) comprises a plurality of semiconductor layers (14) and sacrificial layers (15) which are alternately stacked in sequence along a vertical direction, and the material stacking layer (13) comprises a first sub-region (131), a second sub-region (132) and a third sub-region (133), wherein the first sub-region (131) and the second sub-region (132) are located in the step region (11), and the third sub-region (133) is located in the core region (12); the semiconductor layer (14) and the sacrificial layer (15) in the second sub-region (132) and the third sub-region (133) extend in a horizontal direction, and the first sub-region (131) comprises an inclined surface (16), and an angle exists between the inclined surface (16) and the horizontal plane;

至少对所述第一子区(131)与所述第二子区(132)执行刻蚀工艺，形成若干条沿第一方向延伸的第二沟槽(20)，所述第一方向与水平面平行，从而将所述第一子区(131)与所述第二子区(132)中的所述材料堆叠层(13)刻蚀为多组位线连接线待形成层堆叠结构(25)，所述位线连接线待形成层堆叠结构(25)包括多层位线连接线待形成层(251)；Performing an etching process on at least the first sub-region (131) and the second sub-region (132) to form a plurality of second grooves (20) extending along a first direction, wherein the first direction is parallel to a horizontal plane, thereby etching the material stack layer (13) in the first sub-region (131) and the second sub-region (132) into a plurality of groups of bit line connection line to-be-formed layer stack structures (25), wherein the bit line connection line to-be-formed layer stack structures (25) include a plurality of layers of bit line connection line to-be-formed layers (251);

对所述位线连接线待形成层(251)进行处理以形成位线连接线(29)。The layer (251) on which the bit line connection line is to be formed is processed to form a bit line connection line (29).
根据权利要求11所述的半导体结构的制备方法，其中，保留所述牺牲层(15)在半导体结构中，或者，在形成所述位线连接线待形成层堆叠结构(25)之后，且在形成所述位线连接线(29)之前，去除所述位线连接线待形成层堆叠结构(25)中的所述牺牲层(15)。The method for preparing a semiconductor structure according to claim 11, wherein the sacrificial layer (15) is retained in the semiconductor structure, or, after forming the bit line connection line to be formed layer stack structure (25) and before forming the bit line connection line (29), the sacrificial layer (15) in the bit line connection line to be formed layer stack structure (25) is removed.
根据权利要求12所述的半导体结构的制备方法，其中，当保留所述牺牲层(15)在半导体结构中时，对所述位线连接线待形成层(251)进行处理包括：对暴露在所述第二沟槽(20)内的所述位线连接线待形成层(251)的侧壁进行金属硅化处理以形成金属硅化物；当在形成所述位线连接线待形成层堆叠结构(25)之后，且在形成所述位线连接线(29)之前去除所述牺牲层(15)时，所述位线连接线待形成层(251)的侧壁全部裸露，对所述位线连接线待形成层(251)进行处理包括：对所述位线连接线待形成层(251)的裸露侧壁进行金属硅化处理以形成金属硅化物。The method for preparing a semiconductor structure according to claim 12, wherein, when the sacrificial layer (15) is retained in the semiconductor structure, processing the bit line connection line to be formed layer (251) includes: performing metal silicide treatment on the side walls of the bit line connection line to be formed layer (251) exposed in the second groove (20) to form a metal silicide; when the sacrificial layer (15) is removed after forming the bit line connection line to be formed layer stacking structure (25) and before forming the bit line connection line (29), the side walls of the bit line connection line to be formed layer (251) are completely exposed, and processing the bit line connection line to be formed layer (251) includes: performing metal silicide treatment on the exposed side walls of the bit line connection line to be formed layer (251) to form a metal silicide.
根据权利要求11至13任一项所述的半导体结构的制备方法，其中，提供衬底(10)，包括：The method for preparing a semiconductor structure according to any one of claims 11 to 13, wherein providing a substrate (10) comprises:

提供基底，所述基底包括第一分区(101)、第二分区(102)和第三分区(103)；Providing a substrate, the substrate comprising a first partition (101), a second partition (102), and a third partition (103);

刻蚀所述第二分区(102)与所述第三分区(103)，使得所述第三分区(103)的上表面低于所述第一分区(101)的上表面，所述第二分区(102)的上表面成为倾斜表面(104)，所述倾斜表面(104)的上端连接所述第一分区(101)的上表面，下端连接所述第三分区(103)的上表面。The second partition (102) and the third partition (103) are etched so that the upper surface of the third partition (103) is lower than the upper surface of the first partition (101), and the upper surface of the second partition (102) becomes an inclined surface (104), the upper end of the inclined surface (104) is connected to the upper surface of the first partition (101), and the lower end is connected to the upper surface of the third partition (103).
根据权利要求14所述的半导体结构的制备方法，其中，在所述衬底(10)上方形成材料堆叠层(13)，包括：The method for preparing a semiconductor structure according to claim 14, wherein forming a material stack layer (13) above the substrate (10) comprises:

在所述衬底(10)上方共形地形成初始材料堆叠层(17)，所述初始材料堆叠层(17)包括多个沿竖直方向依次交替堆叠的半导体层(14)与牺牲层(15)，位于所述核心区域(12)上方的所述初始材料堆叠层(17)的上表面不高于所述第一分区(101)的上表面；Conformally forming an initial material stacking layer (17) above the substrate (10), the initial material stacking layer (17) comprising a plurality of semiconductor layers (14) and sacrificial layers (15) stacked alternately in sequence along a vertical direction, wherein an upper surface of the initial material stacking layer (17) located above the core region (12) is not higher than an upper surface of the first partition (101);

对所述初始材料堆叠层(17)进行平坦化工艺，去除位于所述第一分区(101)上方的所述初始材料堆叠层(17)，并使得位于所述第二分区(102)和所述第三分区(103)上方的所述初始材料堆叠层(17)的上表面齐平。The initial material stack layer (17) is subjected to a planarization process to remove the initial material stack layer (17) located above the first partition (101), and to make the upper surface of the initial material stack layer (17) located above the second partition (102) and the third partition (103) flush.
根据权利要求15所述的半导体结构的制备方法，其中，The method for preparing a semiconductor structure according to claim 15, wherein:

所述半导体层(14)的材料为单晶硅，所述牺牲层(15)的材料为硅锗，所述半导体层(14)与所述牺牲层(15)采用外延工艺形成；或者，The material of the semiconductor layer (14) is single crystal silicon, the material of the sacrificial layer (15) is silicon germanium, and the semiconductor layer (14) and the sacrificial layer (15) are formed by an epitaxial process; or,

所述半导体层(14)的材料为多晶硅或铟镓锌氧化物，所述牺牲层(15)的材料为介电层，所述半导体层(14)与所述牺牲层(15)采用沉积工艺形成。The material of the semiconductor layer (14) is polycrystalline silicon or indium gallium zinc oxide, the material of the sacrificial layer (15) is a dielectric layer, and the semiconductor layer (14) and the sacrificial layer (15) are formed by a deposition process.
根据权利要求11至16任一项所述的半导体结构的制备方法，其中，在对所述第一子区(131)与所述第二子区(132)执行刻蚀工艺的同一步骤中刻蚀所述第三子区(133)，形成若干沿所述第一方向延伸的第一沟槽(18)，所述第一沟槽(18)与所述第二沟槽(20)连通，从而将位于所述第三子区(133)的所述材料堆叠层(13)刻蚀为多组有源柱堆叠结构(26)，每组所述有源柱堆叠结构(26)包括多层有源柱(27)。The method for preparing a semiconductor structure according to any one of claims 11 to 16, wherein the third sub-region (133) is etched in the same step of performing an etching process on the first sub-region (131) and the second sub-region (132) to form a plurality of first trenches (18) extending along the first direction, the first trenches (18) being connected to the second trenches (20), thereby etching the material stack layer (13) located in the third sub-region (133) into a plurality of groups of active column stacks Structure (26), each group of the active pillar stacking structure (26) includes multiple layers of active pillars (27).
根据权利要求17所述的半导体结构的制备方法，其中，形成多个沿第一方向延伸的第一沟槽(18)之后，去除所述牺牲层(15)之前，所述方法还包括：The method for preparing a semiconductor structure according to claim 17, wherein after forming a plurality of first trenches (18) extending along the first direction and before removing the sacrificial layer (15), the method further comprises:

形成第一介质层(19)，所述第一介质层(19)填充所述第一沟槽(18)并覆盖所述材料堆叠层(13)的上表面；forming a first dielectric layer (19), wherein the first dielectric layer (19) fills the first trench (18) and covers the upper surface of the material stack layer (13);

对所述第三子区(133)进行刻蚀工艺，去除所述第一沟槽(18)内的部分所述第一介质层(19)，形成多个第三沟槽(21)和多个第四沟槽，多个所述第三沟槽(21)沿第二方向排列，多个所述第四沟槽沿所述第二方向排列，所述第二方向平行于水平面且与所述第一方向相交；Performing an etching process on the third sub-region (133) to remove a portion of the first dielectric layer (19) in the first groove (18) to form a plurality of third grooves (21) and a plurality of fourth grooves, wherein the plurality of third grooves (21) are arranged along a second direction, and the plurality of fourth grooves are arranged along the second direction, wherein the second direction is parallel to a horizontal plane and intersects with the first direction;

去除暴露于所述第三沟槽(21)与所述第四沟槽内的所述牺牲层(15)，使得所述第三沟槽(21)在所述第二方向上连通形成第一网状沟槽(A)，所述第四沟槽在所述第二方向上连通形成第二网状沟槽(B)；removing the sacrificial layer (15) exposed in the third groove (21) and the fourth groove, so that the third groove (21) is connected in the second direction to form a first mesh groove (A), and the fourth groove is connected in the second direction to form a second mesh groove (B);

通过所述第一网状沟槽(A)与所述第二网状沟槽(B)对所述半导体层(14)执行掺杂工艺，以使暴露于所述第一网状沟槽(A)内的所述半导体层(14)形成源区，暴露于所述第二网状沟槽(B)内的所述半导体层(14)形成漏区；Performing a doping process on the semiconductor layer (14) through the first mesh-shaped groove (A) and the second mesh-shaped groove (B), so that the semiconductor layer (14) exposed in the first mesh-shaped groove (A) forms a source region, and the semiconductor layer (14) exposed in the second mesh-shaped groove (B) forms a drain region;

形成第二介质层，填充于所述第一网状沟槽(A)内的所述第二介质层构成第一网状支撑结构(241)，填充于所述第二网状沟槽(B)内的所述第二介质层构成第二网状支撑结构(242)。A second dielectric layer is formed, wherein the second dielectric layer filled in the first mesh-shaped groove (A) constitutes a first mesh-shaped support structure (241), and the second dielectric layer filled in the second mesh-shaped groove (B) constitutes a second mesh-shaped support structure (242).
根据权利要求18所述的半导体结构的制备方法，其中，形成所述第一网状支撑结构(241)与所述第二网状支撑结构(242)之后，所述方法还包括：The method for preparing a semiconductor structure according to claim 18, wherein after forming the first mesh support structure (241) and the second mesh support structure (242), the method further comprises:

去除所述第一网状支撑结构(241)与所述第二网状支撑结构(242)之间的所述第一介质层(19)，形成多个沿所述第二方向排布的开口；Removing the first dielectric layer (19) between the first mesh support structure (241) and the second mesh support structure (242) to form a plurality of openings arranged along the second direction;

去除暴露于所述开口内的所述牺牲层(15)，使得所述有源柱堆叠结构(26)中的有源柱(27)悬空。The sacrificial layer (15) exposed in the opening is removed, so that the active pillars (27) in the active pillar stack structure (26) are suspended.
根据权利要求17至19任一项所述的半导体结构的制备方法，其中，对所述位线连接线待形成层(251)处理形成所述位线连接线(29)之后，所述方法还包括：The method for preparing a semiconductor structure according to any one of claims 17 to 19, wherein after the layer (251) to be formed as the bit line connection line is processed to form the bit line connection line (29), the method further comprises:

形成第四介质层(30)，所述第四介质层(30)填充所述位线连接线(29)之间的间隙并覆盖所述位线连接线(29)的上表面；forming a fourth dielectric layer (30), wherein the fourth dielectric layer (30) fills the gaps between the bit line connection lines (29) and covers the upper surfaces of the bit line connection lines (29);

对位于所述第一沟槽(18)内的第三介质层(28)执行刻蚀工艺，形成沿第二方向排布的多个隔离通孔(31)，所述第二方向平行于水平面且与所述第一方向相交，所述隔离通孔(31)沿竖直方向延伸，且所述隔离通孔(31)位于相邻两组所述有源柱堆叠结构(26)之间；Performing an etching process on the third dielectric layer (28) located in the first trench (18) to form a plurality of isolation through holes (31) arranged along a second direction, wherein the second direction is parallel to a horizontal plane and intersects with the first direction, the isolation through holes (31) extend along a vertical direction, and the isolation through holes (31) are located between two adjacent groups of the active column stacking structures (26);

采用隔离介质层填充所述隔离通孔(31)形成多个隔离结构(32)。An isolation dielectric layer is used to fill the isolation through holes (31) to form a plurality of isolation structures (32).
根据权利要求20所述的半导体结构的制备方法，其中，在形成多个所述隔离结构(32)之后，所述方法还包括：The method for preparing a semiconductor structure according to claim 20, wherein after forming a plurality of the isolation structures (32), the method further comprises:

刻蚀去除相邻所述隔离结构(32)之间的所述第三介质层(28)形成字线通孔(33)，所述字线通孔(33)沿竖直方向延伸，一组所述有源柱堆叠结构(26)中的所有有源柱(27)的沟道区暴露于一个所述字线通孔(33)中；Etching and removing the third dielectric layer (28) between adjacent isolation structures (32) to form a word line through hole (33), wherein the word line through hole (33) extends in a vertical direction, and the channel regions of all active pillars (27) in a group of active pillar stack structures (26) are exposed in one of the word line through holes (33);

在所述字线通孔(33)内形成包覆所述有源柱(27)的沟道区的栅介质层(35)与栅极(36)，一组所述有源柱堆叠结构(26)中的所有有源柱(27)的栅极(36)连接在一起形成一条字线(37)。A gate dielectric layer (35) and a gate electrode (36) covering a channel region of the active column (27) are formed in the word line through hole (33); the gate electrodes (36) of all active columns (27) in a group of active column stacking structures (26) are connected together to form a word line (37).
根据权利要求11至21任一项所述的半导体结构的制备方法，其中，在形成所述位线连接线(29)之后，所述方法还包括：The method for preparing a semiconductor structure according to any one of claims 11 to 21, wherein after forming the bit line connection line (29), the method further comprises:

在所述位线连接线(29)上方形成至少一个位线插塞(39)，一个所述位线插塞(39)对应电连接一条所述位线连接线(29)； At least one bit line plug (39) is formed above the bit line connection line (29), and one bit line plug (39) is electrically connected to one bit line connection line (29);

在所述位线插塞(39)上方形成位线材料层；forming a bit line material layer above the bit line plug (39);

刻蚀所述位线材料层，形成至少一条位线(41)，所述位线(41)沿第二方向延伸，所述第二方向平行于水平面且与所述第一方向相交，且一条所述位线(41)与同一组的所述位线插塞(39)电连接，其中，连接同一层的所述位线连接线(29)的多个所述位线插塞(39)定义为同一组的所述位线插塞(39)；或者，Etching the bit line material layer to form at least one bit line (41), wherein the bit line (41) extends along a second direction, the second direction is parallel to a horizontal plane and intersects with the first direction, and one bit line (41) is electrically connected to the bit line plugs (39) of the same group, wherein a plurality of bit line plugs (39) connected to the bit line connection lines (29) of the same layer are defined as the bit line plugs (39) of the same group; or,

在形成所述位线连接线(29)之后，所述方法还包括：After forming the bit line connection line (29), the method further comprises:

在所述位线连接线(29)上方形成位线材料层；forming a bit line material layer above the bit line connection line (29);

刻蚀所述位线材料层，形成至少一条位线，所述位线沿所述第二方向延伸，且一条所述位线电连接位于同一层的所有所述位线连接线(29)。 The bit line material layer is etched to form at least one bit line, wherein the bit line extends along the second direction, and one bit line is electrically connected to all the bit line connection lines (29) located in the same layer.