WO2024084911A1 - Voltage monitoring circuit, semiconductor integrated circuit device, vehicle, control device, switching regulator, and power supply device - Google Patents

Voltage monitoring circuit, semiconductor integrated circuit device, vehicle, control device, switching regulator, and power supply device Download PDF

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Publication number
WO2024084911A1
WO2024084911A1 PCT/JP2023/035185 JP2023035185W WO2024084911A1 WO 2024084911 A1 WO2024084911 A1 WO 2024084911A1 JP 2023035185 W JP2023035185 W JP 2023035185W WO 2024084911 A1 WO2024084911 A1 WO 2024084911A1
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Prior art keywords
voltage
signal
output stage
transistor
switch
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PCT/JP2023/035185
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French (fr)
Japanese (ja)
Inventor
公信 佐藤
和宏 村上
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ローム株式会社
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Publication of WO2024084911A1 publication Critical patent/WO2024084911A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the invention disclosed in this specification relates to a voltage monitoring circuit, a semiconductor integrated circuit device, and a vehicle.
  • the invention disclosed in this specification also relates to a control device, a switching regulator including this control device, and a power supply device including this switching regulator.
  • in-vehicle power supply ICs Integrated Circuits
  • ADAS Advanced Driver-Assistance Systems
  • Patent Document 1 As an example of related prior art, Patent Document 1 can be mentioned.
  • the accuracy of voltage monitoring in a SoC that includes the power supply IC is required to be within the power supply specifications of the SoC. Therefore, there are cases where extremely high-precision voltage monitoring is required.
  • the coil currents of each switch output stage may not match, resulting in an unbalanced state. This may result in the output current of the switching regulator operating in an unbalanced manner, which may lead to reduced efficiency. Furthermore, if the imbalance is relatively large, the protection circuit will cause the switching regulator to malfunction.
  • the voltage monitoring circuit disclosed in this specification comprises a first differential input pair including a first transistor configured to receive a reference voltage and a second transistor configured to receive a monitored voltage, and a second differential input pair including a third transistor configured to receive the first voltage and a fourth transistor configured to receive a second voltage.
  • the output terminal of the first transistor and the output terminal of the third transistor are commonly connected.
  • the output terminal of the second transistor and the output terminal of the fourth transistor are commonly connected.
  • the semiconductor integrated circuit device disclosed in this specification includes a voltage monitoring circuit having the above configuration.
  • the vehicle disclosed in this specification is equipped with a semiconductor integrated circuit device having the above configuration.
  • the control device disclosed in this specification is a control device for a switching regulator configured to generate a desired output voltage from an input voltage by driving at least a first switch output stage and a second switch output stage with a predetermined phase difference.
  • the control device includes a first control circuit and a second control circuit configured to drive the first switch output stage and the second switch output stage, respectively, and a transmission signal having both clock information and duty information of the first switch output stage is transmitted from the first control circuit to the second control circuit.
  • the switching regulator disclosed in this specification is equipped with a control device having the above configuration.
  • the power supply device disclosed in this specification includes a switching regulator having the above configuration.
  • the invention disclosed in this specification makes it possible to achieve highly accurate voltage monitoring.
  • the second control circuit can obtain clock information and duty information of the first switch output stage. By controlling the drive of the second switch output stage based on this clock information and duty information, it is possible to prevent imbalance with the drive of the first switch output stage.
  • FIG. 1 is a diagram showing a comparative example of a switching power supply device.
  • FIG. 2 is a diagram showing a first embodiment of a switching power supply device.
  • FIG. 3 is a diagram showing an example of the configuration of a four-input terminal comparator.
  • FIG. 4 is a diagram showing a second embodiment of a switching power supply device.
  • FIG. 5 is a diagram showing a schematic diagram of the value of the second voltage being switched in a time division manner.
  • FIG. 6 is an external view of the vehicle.
  • FIG. 7 is a block diagram showing the configuration of a power supply device of the comparative example.
  • FIG. 8 is a timing chart showing the first inductor current, the second inductor current, the first switch voltage, and the second switch voltage in the power supply device of the comparative example.
  • FIG. 9 is a diagram showing a schematic configuration of an embodiment of a power supply device according to the present disclosure.
  • FIG. 10 is a timing chart showing the first switch voltage, the second switch voltage, the first inductor current, and the second inductor current.
  • FIG. 11 is a block diagram showing the configuration of the power supply device.
  • FIG. 12 is a timing chart showing the first ramp signal, the second ramp signal, the first error signal, the second error signal, the first comparison signal, the second comparison signal, the first inductor current, and the second inductor current.
  • FIG. 13 is a block diagram showing the details of the matching unit.
  • a switching power supply device 1 of this comparative example generates a desired DC output voltage VOUT from a DC input voltage VIN.
  • the switching power supply device 1 includes a semiconductor integrated circuit device 10, an inductor L1, and an output capacitor COUT.
  • the semiconductor integrated circuit device 10 is a power supply IC that serves as the main controller of the switching power supply device 1.
  • the semiconductor integrated circuit device 10 has multiple terminals (terminals T1 to T4 in this diagram) as a means for establishing electrical connection with the outside of the device.
  • a DC input voltage VIN is applied to terminal T1.
  • a ground voltage is applied to terminal T2.
  • a first end of inductor L1 is connected to terminal T3.
  • a second end of inductor L1 and a first end of output capacitor COUT are connected to terminal T4.
  • a ground voltage is applied to the second end of output capacitor COUT.
  • Inductor L1 and output capacitor COUT convert the pulsed switch voltage VSW output from terminal T3 into a DC output voltage VOUT.
  • the DC output voltage VOUT is applied to terminal T4.
  • the semiconductor integrated circuit device 10 includes a digital data generation circuit 11, a DAC (Digital Analog Converter) 12, a buffer amplifier 13, a switch voltage generation circuit 14, a voltage monitoring circuit 15, and resistors R1 and R2.
  • DAC Digital Analog Converter
  • the digital data generation circuit 11 generates and outputs digital data for the reference voltage. Note that the digital data for the reference voltage generated by the digital data generation circuit 11 may be fixed to one value, or may be switchable between multiple values.
  • DAC12 converts the digital data for the reference voltage into an analog voltage, the reference voltage VREF, and outputs it.
  • the reference voltage VREF output from DAC12 is supplied to the switch voltage generation circuit 14 and the voltage monitoring circuit 15 via the buffer amplifier 13.
  • Resistors R1 and R2 generate a feedback voltage VFB, which is a divided voltage of the DC output voltage VOUT applied to terminal T4, and supply the feedback voltage VFB to the switch voltage generating circuit 14 and the voltage monitoring circuit 15, respectively.
  • the switch voltage generating circuit 14 includes a switching element, and converts the DC input voltage VIN into a switch voltage VSW by switching the switching element with a duty corresponding to the difference between the reference voltage VREF and the feedback voltage VFB, and supplies the switch voltage VSW to the terminal T3.
  • the voltage monitoring circuit 15 includes voltage generating circuits 151 and 152, and comparators 153 and 154.
  • the voltage monitoring circuit 15 monitors whether the feedback voltage VFB is an overvoltage or not, and also monitors whether the feedback voltage VFB is a low voltage or not.
  • the voltage generation circuit 151 includes a constant current circuit and a resistor, and generates a first reference voltage VREF1 from the reference voltage VREF using the constant current and the resistor.
  • the first reference voltage VREF1 is greater than the reference voltage VREF by a first predetermined value.
  • the voltage generating circuit 152 includes a constant current circuit and a resistor, and generates a second reference voltage VREF2 from the reference voltage VREF using the constant current and the resistor.
  • the second reference voltage VREF2 is smaller than the reference voltage VREF by a second predetermined value.
  • the second predetermined value may be the same as the first predetermined value, or may be a value different from the first predetermined value.
  • the non-inverting input terminal of the comparator 153 is supplied with a first reference voltage VREF1.
  • the inverting input terminal of the comparator 154 is supplied with a feedback voltage VFB.
  • the overvoltage detection signal OVD which is the output signal of the comparator 153
  • the second reference voltage VREF2 is supplied to the inverting input terminal of the comparator 154.
  • the feedback voltage VFB is supplied to the non-inverting input terminal of the comparator 154.
  • the feedback voltage VFB is smaller than the second reference voltage VREF2
  • the low voltage detection signal UVD which is the output signal of the comparator 153
  • the accuracy of voltage monitoring can be improved by performing trimming.
  • the temperature characteristics and voltage characteristics of the constant current circuits included in the voltage generation circuits 151 and 152 and the temperature characteristics of the offsets of the comparators 153 and 154 are characteristics that vary depending on the usage environment of the switching power supply device 1, and are a cause of deterioration in accuracy.
  • the voltage monitoring circuit 15 of the comparative example had insufficient voltage monitoring accuracy.
  • ⁇ Switching power supply device (first embodiment)> 2 is a diagram showing a first embodiment of a switching power supply device.
  • the switching power supply device 1 of this embodiment is based on the comparative example (FIG. 1) described above, but includes a constant voltage generating circuit 16 and has a different configuration for the voltage monitoring circuit 15.
  • the constant voltage generation circuit 16 generates a constant voltage VREG from the DC input voltage VIN.
  • the voltage monitoring circuit 15 of this embodiment includes a four-input terminal comparator 155, a resistive voltage divider circuit formed by resistors R3 and R4, and a resistive voltage divider circuit formed by resistors R5 and R6.
  • the resistor voltage divider circuit formed by resistors R3 and R4 outputs a first voltage V1 obtained by dividing the constant voltage VREG by the resistance ratio of resistors R3 and R4.
  • the resistor voltage divider circuit formed by resistors R5 and R6 outputs a second voltage V2 obtained by dividing the constant voltage VREG by the resistance ratio of resistors R5 and R6.
  • the first non-inverting input terminal of the four-input terminal comparator 155 is supplied with a reference voltage VREF.
  • the first inverting input terminal of the four-input terminal comparator 155 is supplied with a feedback voltage VFB.
  • the second non-inverting input terminal of the four-input terminal comparator 155 is supplied with a first voltage V1.
  • the second inverting input terminal of the four-input terminal comparator 155 is supplied with a second voltage V2.
  • the overvoltage detection signal OVD which is the output signal of the four-input terminal comparator 155, is a voltage that corresponds to the sum of the difference between the reference voltage VREF and the feedback voltage VFB and the difference between the first voltage V1 and the second voltage V2 (VREF-VFB+V1-V2).
  • the voltage monitoring circuit 15 of this embodiment can monitor whether the feedback voltage VFB is an overvoltage, similar to the voltage monitoring circuit 15 of the comparative example.
  • the overvoltage detection signal OVD which is the output signal of the four-input terminal comparator 155
  • the overvoltage detection signal OVD which is the output signal of the four-input terminal comparator 155
  • the first voltage V1 and the second voltage V2 do not need to be generated using the reference voltage VREF. This makes it possible to make the first voltage V1 and the second voltage V2 voltages less likely to fluctuate with temperature. Therefore, the voltage monitoring circuit 15 of this embodiment can achieve highly accurate voltage monitoring.
  • the pairing of the two resistors included in the resistive voltage divider circuit is used to make each of the first voltage V1 and the second voltage V2 voltages less likely to fluctuate with temperature. Furthermore, as in this embodiment, by configuring the resistive voltage divider circuit formed by resistors R3 and R4 and the resistive voltage divider circuit formed by resistors R5 and R6 to be supplied with a common constant voltage VREG, it is possible to prevent the difference between the first voltage V1 and the second voltage V2 (V1-V2) from being affected by the temperature characteristics of the constant voltage VREG even if the constant voltage VREG fluctuates with temperature.
  • FIG. 3 is a diagram showing an example configuration of a four-input terminal comparator 155.
  • the four-input terminal comparator 155 of the example configuration shown in FIG. 3 includes transistors M1 to M16, current sources CS1 to CS6, switches SW1 to SW6, and capacitors C1 and C2.
  • Transistors M1 to M6, M15, and M16 are P-channel type MOS field effect transistors.
  • Transistors M7 to M14 are N-channel type MOS field effect transistors.
  • the first differential input pair P1 is formed by transistors M1 and M2.
  • the second differential input pair P2 is formed by transistors M3 and M4.
  • the calibration circuit CAL1 is formed by transistors M5 and M6, capacitors C1 and C2, and switches SW5 and SW6.
  • a constant voltage VREG is applied to the first terminal of each of the current sources CS1 to CS6.
  • the reference voltage VREF is supplied to the gate of transistor M1 and the first terminal of switch SW2.
  • the feedback voltage VFB is supplied to the first terminal of switch SW1.
  • the second terminals of switches SW1 and SW2 are connected to the gate of transistor M2.
  • the second terminal of current source CS1 is connected to the sources of transistors M1 and M2.
  • the first voltage V1 is supplied to the gate of transistor M3 and the first terminal of switch SW4.
  • the second voltage V2 is supplied to the first terminal of switch SW3.
  • the second terminals of switches SW3 and SW4 are connected to the gate of transistor M4.
  • the second terminal of current source CS2 is connected to the sources of transistors M3 and M4.
  • the drain of transistor M1 and the drain of transistor M3 are commonly connected.
  • the drain of transistor M2 and the drain of transistor M4 are commonly connected.
  • the gate of transistor M5 is connected to the first end of switch SW5 and the first end of capacitor C1.
  • the gate of transistor M6 is connected to the first end of switch SW6 and the first end of capacitor C2.
  • the second end of current source CS3 is connected to the sources of transistors M5 and M6. A ground voltage is applied to the second ends of capacitors C1 and C2.
  • the drain of transistor M5 and the second end of switch SW5 are connected to the drain of transistor M1, the drain of transistor M3, the source of transistor M9, and the drain of transistor M10.
  • the drain of transistor M9 is connected to the second end of current source CS5.
  • the drain of transistor M6 and the second end of switch SW6 are connected to the drain of transistor M2, the drain of transistor M4, the source of transistor M11, and the drain of transistor M12.
  • the drain of transistor M11 is connected to the second end of current source CS6.
  • the gates of transistors M7 to M12 are connected to the second end of current source CS4 and the drain of transistor M7.
  • the source of transistor M7 is connected to the drain of transistor M8.
  • a ground voltage is applied to the sources of transistors M8, M10, and M12.
  • a gate signal G14 is supplied to the gate of transistor M14 from the connection node between current source CS5 and transistor M9.
  • a gate signal G13 is supplied to the gate of transistor M13 from the connection node between current source CS6 and transistor M11.
  • a ground voltage is applied to the sources of transistors M13 and M14.
  • a current mirror circuit is formed by transistors M15 and M16.
  • a constant voltage VREG is applied to the sources of transistors M15 and M16.
  • the gates of transistors M15 and M16 and the drain of transistor M15 are connected to the drain of transistor M13.
  • the drain of transistor M16 is connected to the drain of transistor M14.
  • the output signal SOUT of the four-input terminal comparator 155 (overvoltage detection signal OVD in FIG. 1) is output from the connection node between transistors M16 and M14.
  • the four-input terminal comparator 155 in the configuration example shown in FIG. 3 turns on switches SW1 and SW3 during normal operation (during comparison operation) and turns off switches SW2, SW4, SW5, and SW6.
  • the four-input terminal comparator 155 of the configuration example shown in FIG. 3 turns off switches SW1 and SW3 during calibration operation, and turns on switches SW2, SW4, SW5, and SW6. At this time, if the threshold voltage of transistor M1 is equal to the threshold voltage of transistor M2, the drain current Ia2 of transistor M1 is equal to the drain current Ia3 of transistor M2. Similarly, if the threshold voltage of transistor M3 is equal to the threshold voltage of transistor M4, the drain current Ib2 of transistor M3 is equal to the drain current Ib3 of transistor M4.
  • the drain current Ia2 of transistor M1 will be smaller than the drain current Ia3 of transistor M2 and the drain current Ib2 of transistor M3 will be smaller than the drain current Ib3 of transistor M4.
  • the drain voltage V12 of transistors M1 and M3 will be smaller than the drain voltage V13 of transistors M2 and M4.
  • the calibration circuit CAL1 passes the drain current Ic2 of transistor M5 and the drain current Ic3 of transistor M6 in a balance that depends on the drain voltage V12 of transistors M1 and M3 and the drain voltage V13 of transistors M2 and M4.
  • the drain current Ic2 of the transistor M5 becomes larger than the drain current Ic3 of the transistor M6, and the drain voltage V12 of the transistors M1 and M3 and the drain voltage V13 of the transistors M2 and M4 are adjusted to be closer to an equal state. Then, a charge according to the drain voltage V12 of the transistors M1 and M3 is charged to the capacitor C1, and a charge according to the drain voltage V13 of the transistors M2 and M4 is charged to the capacitor C1.
  • the voltage monitoring circuit 15 of this embodiment can achieve even more accurate voltage monitoring by the calibration circuit CAL1.
  • the offsets of the first differential input pair P1 and the second differential input pair P2 vary depending on the environment in which the switching power supply device 1 is used. Therefore, the four-input terminal comparator 155 in the configuration example shown in FIG. 3 alternately repeats a calibration operation and a normal operation.
  • the voltage monitoring circuit 15 of this embodiment can only monitor whether the feedback voltage VFB is an overvoltage, and cannot monitor whether the feedback voltage VFB is an undervoltage. To monitor whether the feedback voltage VFB is an undervoltage, it is necessary to add another set of a four-input terminal comparator 155, a resistive voltage divider circuit formed by resistors R3 and R4, and a resistive voltage divider circuit formed by resistors R5 and R6 to the voltage monitoring circuit 15 of this embodiment for undervoltage monitoring.
  • Comparators including the calibration circuit CAL1 generally tend to be large in circuit size. Therefore, if the voltage monitoring circuit 15 of this embodiment is configured with two sets of a four-input terminal comparator 155, a resistive voltage divider circuit formed by resistors R3 and R4, and a resistive voltage divider circuit formed by resistors R5 and R6, the circuit area will be significantly larger than that of the voltage monitoring circuit 15 of the comparative example.
  • ⁇ Switching power supply device (second embodiment)> 4 is a diagram showing a second embodiment of a switching power supply device.
  • the switching power supply device 1 of this embodiment is based on the first embodiment (FIG. 2) described above, but has a configuration in which the resistive voltage divider circuit formed by resistors R5 and R6 is replaced with a digital data generation circuit 156 and a DAC 157.
  • the voltage monitoring circuit 15 of this embodiment can monitor not only whether the feedback voltage VFB is an overvoltage, but also whether the feedback voltage VFB is a low voltage. Furthermore, since the voltage monitoring circuit 15 of this embodiment does not need to have two four-input terminal comparators 155, an increase in the circuit area can be suppressed.
  • the semiconductor integrated circuit device 10 of this embodiment generates a clock signal CLK internally or receives it from the outside.
  • the digital data generation circuit 156 switches the digital data corresponding to the second voltage V2 between overvoltage data and low voltage data in a time-division manner based on the clock signal CLK.
  • a constant voltage VREG and a ground voltage are applied to the DAC 157.
  • the DAC 157 converts the digital data output from the digital data generation circuit 156 to the second voltage V2, which is an analog voltage, and outputs it based on the constant voltage VREG and the ground voltage. Therefore, as shown in FIG.
  • the second voltage V2 switches between an overvoltage value (OVD VALUE) and a low voltage value (UVD VALUE) in a time-division manner based on the clock signal CLK.
  • the four-input terminal comparator 155 outputs an overvoltage detection signal OVD and a low voltage detection signal UVD in a time-division manner.
  • the resistive voltage divider circuit formed by resistors R5 and R6 is replaced with a digital data generation circuit 156 and a DAC 157, as compared to the voltage monitoring circuit 15 of the first embodiment.
  • the resistive voltage divider circuit formed by resistors R5 and R6 may be replaced with a digital data generation circuit and a DAC.
  • the voltage division ratio of the resistive voltage divider circuit formed by resistors R3 and R4 is fixed, and the voltage division ratio of the resistive voltage divider circuit formed by resistors R5 and R6 is fixed, but at least one of the two resistive voltage divider circuits may be changed to a resistive voltage divider circuit with a variable voltage division ratio.
  • the voltage monitoring circuit 15 modified in this way also does not need to have two four-input terminal comparators 155, and can not only monitor whether the feedback voltage VFB is an overvoltage, but also monitor whether the feedback voltage VFB is an undervoltage.
  • the resistive voltage divider circuit formed by resistors R3 and R4 may be changed to a resistive voltage divider circuit with a variable voltage division ratio.
  • ⁇ Application Examples> 6 is an external view of a vehicle X.
  • the vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving a voltage output from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for convenience of illustration.
  • Electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).
  • engine-related controls injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.
  • the electronic device X12 is a lamp control unit that controls the turning on and off of HID [high intensity discharged lamp] and DRL [daytime running lamp].
  • Electronic device X13 is a transmission control unit that performs control related to the transmission.
  • the electronic device X14 is a braking unit that performs controls related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).
  • ABS anti-lock brake system
  • EPS electric power steering
  • electronic suspension control etc.
  • Electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, etc.
  • Electronic device X16 is an electronic device that is installed in vehicle X at the time of shipment from the factory as standard equipment or manufacturer's option, such as wipers, power door mirrors, power windows, dampers (shock absorbers), power sunroof, and power seats.
  • Electronic device X17 is an electronic device that is optionally installed in vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].
  • vehicle X an electronic device that is optionally installed in vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].
  • Electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.
  • a high-voltage motor such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.
  • the switching power supply device 1 described above can be incorporated into any of the electronic devices X11 to X18. Therefore, the vehicle X is equipped with the semiconductor integrated circuit device 10 described above. Furthermore, the application of the switching power supply device 1 described above is not limited to a power supply mounted on the vehicle X, but may also be a power supply mounted on industrial equipment, for example.
  • ⁇ Comparative example power supply device Y20> The control device of the power supply device Y20 will be described as a comparative example with the power supply device X20 of the present disclosure.
  • Fig. 7 is a block diagram showing the configuration of the power supply device Y20 of the comparative example.
  • Fig. 8 is a timing chart showing the first inductor current IL1, the second inductor current IL2, the first switch voltage Vst1, and the second switch voltage Vst2 of the power supply device Y20 of the comparative example.
  • the power supply device Y20 of the comparative example has a first semiconductor device 301, a second semiconductor device 302, an inductor L21, an inductor L22, a capacitor C21, and a capacitor C22.
  • the first semiconductor device 301 is connected to the application terminal of the input voltage Vi and the ground terminal.
  • the output terminal of the first semiconductor device 301 is connected to the first terminal of the inductor L21.
  • the second terminal of the inductor L21 is commonly connected to the first terminal of the capacitor C21 and the application terminal of the output voltage Vo.
  • the second terminal of the capacitor C21 is connected to the ground terminal.
  • the first semiconductor device 301, the inductor L21, and the capacitor C21 form a step-down first output stage that generates a first switch voltage Vst1 from the input voltage Vi and rectifies and smoothes the first switch voltage Vst1.
  • the first semiconductor device 301 controls the switching of the first inductor current IL1 flowing through the inductor L21 based on a first clock signal (not shown).
  • the second semiconductor device 302 is connected to the application terminal of the input voltage Vi and the ground terminal.
  • the output terminal of the second semiconductor device 302 is connected to the first terminal of the inductor L22.
  • the second terminal of the inductor L22 is commonly connected to the first terminal of the capacitor C22 and the application terminal of the output voltage Vo.
  • the second terminal of the capacitor C22 is connected to the ground terminal.
  • the second semiconductor device 302, the inductor L21, and the capacitor C22 form a step-down second output stage that generates a second switch voltage Vst2 from the input voltage Vi and rectifies and smoothes the second switch voltage Vst2.
  • the second semiconductor device 302 controls the switching of the second inductor current IL2 flowing through the inductor L22 based on a second clock signal (not shown).
  • a load Z20 is connected to the output terminal of the output voltage Vo.
  • An output current Io flows through the load Z20 according to the output voltage Vo and the resistance value of the load Z20.
  • the average value A1 of the first inductor current IL1 and the average value A2 of the second inductor current IL2 are approximately equal.
  • the balance between the value of the first inductor current IL1 and the value of the second inductor current IL2 may be lost.
  • the average value A1 of the first inductor current IL1 and the average value A2 of the second inductor current IL2 do not match, resulting in an imbalance between the first inductor current IL1 and the second inductor current IL2.
  • the second semiconductor device 302 may receive a clock signal and an error signal from the first semiconductor device 301, and may control the second inductor current IL2 based on these.
  • the error signal is a signal generated according to the error between the output voltage Vo and its target value (details will be described later).
  • the power supply device Y20 may adopt a configuration in which it monitors the output current Io and feeds it back to the first semiconductor device 301 and the second semiconductor device 302, thereby controlling the first inductor current IL1 and the second inductor current IL2 to achieve a balance.
  • Fig. 9 is a diagram showing a schematic configuration of an embodiment of the power supply device X20 of the present disclosure.
  • Fig. 10 is a timing chart showing the first switch voltage Vst1, the second switch voltage Vst2, the first inductor current IL1, and the second inductor current IL2 of the power supply device X20 of the present disclosure.
  • the power supply device X20 is a switching regulator configured to generate a desired output voltage Vo from an input voltage Vi.
  • a load Z20 is connected to the output terminal of the power supply device X20.
  • the power supply device X20 has a control device 250, inductors L21 and L22, and capacitors C21 and C22.
  • the control device 250 controls the drive of the power supply device X20.
  • the control device 250 has a first semiconductor device 201 and a second semiconductor device 202.
  • Inductors L21 and L22 and capacitors C21 and C22 are discrete components external to the control device 250.
  • the first semiconductor device 201 is connected to the application terminal of the input voltage Vi and the ground terminal.
  • the output terminal of the first semiconductor device 201 is connected to the first terminal of the inductor L21.
  • the first terminal of the capacitor C21 is commonly connected to the second terminal of the inductor L21, the application terminal of the first semiconductor device 201, and the application terminal of the output voltage Vo.
  • the second terminal of the capacitor C21 is connected to the ground terminal.
  • the first semiconductor device 201 is configured to internally generate a first clock signal CL1 and a first error signal Vc1.
  • the first error signal Vc1 is generated according to the error between the output voltage Vo and its target value.
  • the first semiconductor device 201 performs switching control of the first inductor current IL1 by pulse driving the first switch voltage Vst1 based on the first clock signal CL1 and the first error signal Vc1. In this way, the first semiconductor device 201 forms a step-down first output stage that generates the first switch voltage Vst1 from the input voltage Vi. The duty of the first output stage is determined according to the first error signal Vc1.
  • the second semiconductor device 202 is connected to the application terminal of the input voltage Vi and the ground terminal.
  • the output terminal of the second semiconductor device 202 is connected to the first terminal of the inductor L22.
  • the first terminal of the capacitor C22 is commonly connected to the second terminal of the inductor L22, the application terminal of the second semiconductor device 202, and the application terminal of the output voltage Vo.
  • the second terminal of the capacitor C22 is connected to the ground terminal.
  • the first semiconductor device 201 and the second semiconductor device 202 are connected to each other by a transmission path 228.
  • a first end of the transmission path 228 is connected to one application terminal of the first semiconductor device 201.
  • a second end of the transmission path 228 is connected to one application terminal of the second semiconductor device 202.
  • the first semiconductor device 201 transmits a transmission signal Vt and a first error signal Vc1 to the second semiconductor device 202.
  • the second semiconductor device 202 internally generates a second clock signal CL2 based on a transmission signal Vt that includes frequency information of the first clock signal CL1.
  • the second semiconductor device 202 also internally generates a second error signal Vc2 by correcting the first error signal Vc1 based on the transmission signal Vt that includes duty information of the first output stage.
  • the second semiconductor device 202 pulse-drives the second switch voltage Vst2 based on the second clock signal CL2 and the second error signal Vc2, thereby controlling the switching of the second inductor current IL2. In this way, the second semiconductor device 202 forms a step-down second output stage that generates the second switch voltage Vst2 from the input voltage Vi.
  • the second semiconductor device 202 can obtain duty information of the first output stage and clock information of the first clock signal CL1. Therefore, the second semiconductor device 202 can control the switching of the second inductor current IL2 based on the duty information of the first output stage and the clock information of the first clock signal CL1.
  • the first end of the transmission path 228 is connected to one application end of the first semiconductor device 201, and the second end of the transmission path 228 is connected to one application end of the second semiconductor device 202. Therefore, the number of terminals used in the first semiconductor device 201 and the second semiconductor device 202 can be reduced compared to the case where the clock information of the first clock signal CL1 contained in the transmission signal Vt and the duty information of the first output stage are transmitted from the first semiconductor device 201 to the second semiconductor device 202 via separate paths.
  • Figure 11 is a block diagram showing the configuration of the power supply device X20.
  • the first semiconductor device 201 is a monolithic semiconductor integrated circuit device (a so-called multi-phase switching regulator IC) in which a first switch output stage 203 and a first control circuit 204 are integrated into a single package.
  • a monolithic semiconductor integrated circuit device a so-called multi-phase switching regulator IC
  • the first switch output stage 203 includes a high-side transistor and a low-side transistor (not shown) and a first driver (not shown).
  • the high-side transistor and the low-side transistor are MOSFETs connected to each other to form a half bridge.
  • the first driver drives and controls the high-side transistor and the low-side transistor.
  • the first switch output stage 203 drives the first inductor current IL1 by turning the high-side transistor and the low-side transistor on and off.
  • the first control circuit 204 includes an error amplifier circuit 205 and a switch control circuit 206.
  • the error amplifier circuit 205 is configured to generate a first error signal Vc1 that corresponds to the error between the output voltage Vo and its target value.
  • the error amplifier circuit 205 includes resistors R21 and R22, a voltage source E3, and an error amplifier 207.
  • a first end of the resistor R21 is connected to a first end of the load Z20.
  • a second end of the resistor R21, together with a first end of the resistor R22, is connected to the non-inverting input terminal of the error amplifier 207.
  • a second end of the resistor R22 is connected to the ground terminal.
  • the first terminal of the voltage source E3 is connected to the inverting input terminal of the error amplifier 207.
  • the second terminal of the voltage source E3 is connected to the ground terminal.
  • the output terminal of the error amplifier 207 is connected to the input terminal of the switch control circuit 206 (the non-inverting input terminal of the first comparator 212 described later).
  • the functional block corresponding to the matching circuit 217 of the second semiconductor device 202 is disabled as shown by the dashed line in the figure. Therefore, the first error signal Vc1 is input directly to the non-inverting input terminal of the first comparator 212.
  • the switch control circuit 206 generates a first clock signal CL1 and a first comparison signal Va1 and outputs them to the first switch output stage 203.
  • the first clock signal CL1 is a signal that defines the switching frequency of the first switch output stage 203 (hereinafter referred to as the "first switching frequency").
  • the above-mentioned clock information is timing information of the rising or falling edge of the first clock signal CL1.
  • the switch control circuit 206 includes a first oscillator 208, a first PLL [Phase Locked Loop] 209, a first selector 210, a first ramp signal generating unit 211, a first comparator 212, and an adder 213.
  • the first oscillator 208 and the first PLL 209 are both connected to the input terminal of the first selector 210.
  • the first semiconductor device 201 is the master.
  • the first oscillator 208 is electrically connected to the first switch output stage 203 and the input terminal of the first ramp signal generating unit 211 via the first selector 210.
  • the first PLL 209 is electrically cut off by the first selector 210 and is in a non-functional state.
  • the first oscillator 208 generates a first clock signal CL1 and inputs it to the first ramp signal generating unit 211.
  • the output terminal of the first ramp signal generating unit 211 is connected to the input terminal of the adder unit 213 together with the first differential line 214 of the first switch output stage 203.
  • the first ramp signal generating unit 211 generates a first ramp signal Vr1 having a sawtooth waveform in response to the first clock signal CL1.
  • the output terminal of the adder 213 is connected to the inverting input terminal of the first comparator 212.
  • the adder 213 adds the first ramp signal Vr1 and the first differential signal Vd1 to generate the first reference signal Vs1.
  • the output terminal of the first comparator 212 is connected to the input terminal (not shown) of the first switch output stage 203.
  • the first comparator 212 compares the first error signal Vc1 with the first reference signal Vs1 to generate a first comparison signal Va1.
  • the first comparison signal Va1 is at a high level when the first reference signal Vs1 is lower than the first error signal Vc1, and conversely, is at a low level when the first reference signal Vs1 is higher than the first error signal Vc1.
  • the first control circuit 204 drives and controls the first switch output stage 203 based on the first clock signal CL1 and the first comparison signal Va1.
  • the second semiconductor device 202 is a monolithic semiconductor integrated circuit device (a so-called multi-phase switching regulator IC) in which the second switch output stage 215 and the second control circuit 216 are integrated into a single package.
  • the second semiconductor device 202 is formed as a package separate from the first semiconductor device 201.
  • the second switch output stage 215 includes a high-side transistor and a low-side transistor (not shown) and a second driver (not shown).
  • the high-side transistor and the low-side transistor are MOSFETs connected to each other to form a half bridge.
  • the second driver drives and controls the high-side transistor and the low-side transistor.
  • the second switch output stage 215 drives the second inductor current IL2 by turning the high-side transistor and the low-side transistor on and off.
  • the second control circuit 216 is configured to drive and control the second switch output stage 215.
  • the second control circuit 216 includes a matching circuit 217, a phase synchronization circuit 218, a second ramp signal generating unit 219, and a second comparator 230.
  • the matching circuit 217 includes a first low-pass filter 220, a second low-pass filter 221, a correction comparator 222, and a matching unit 223.
  • a first end of the first low-pass filter 220 is connected to a first end of the inductor L21.
  • a second end of the first low-pass filter 220 is connected to a non-inverting input terminal of the correction comparator 222.
  • the first low-pass filter 220 smoothes (averages) the first switch voltage Vst1 to generate a first average voltage Vave1 and transmits it to the correction comparator 222.
  • the first end of the second low-pass filter 221 is connected to the first end of the inductor L22.
  • the second end of the second low-pass filter 221 is connected to the inverting input terminal of the correction comparator 222.
  • the second low-pass filter 221 smoothes (averages) the second switch voltage Vst2 to generate a second average voltage Vave2 and transmits it to the correction comparator 222.
  • the output terminal of the correction comparator 222 is connected to the matching unit 223.
  • the correction comparator 222 compares the first average voltage Vave1 with the second average voltage Vave2 to generate a correction signal Vcr, and transmits the correction signal Vcr to the matching unit 223.
  • the output terminal of the matching unit 223 is connected to the non-inverting input terminal of the second comparator 230.
  • the first input terminal of the matching unit 223 is connected to the output terminal of the correction comparator 222.
  • the second input terminal of the matching unit 223 is connected to the output terminal of the error amplifier 207.
  • the matching unit 223 corrects the first error signal Vc1 output from the error amplifier 207 based on the correction signal Vcr output from the correction comparator 222 to generate a second error signal Vc2.
  • the second error signal Vc2 is input to the non-inverting input terminal of the second comparator 230. Note that the functional block corresponding to the error amplifier circuit 205 of the first semiconductor device 201 is disabled as indicated by the dashed line in the figure.
  • the phase-locked loop 218 is configured to generate a second clock signal CL2 based on the transmission signal Vt.
  • the second clock signal CL2 is a signal that defines the switching frequency of the second switch output stage 215 (hereinafter referred to as the "second switching frequency").
  • the phase synchronization circuit 218 includes a second oscillator 224, a second PLL 225, and a second selector 226.
  • the second oscillator 224 and the second PLL 225 are connected to the second selector 226.
  • the output terminal of the second selector 226 is connected to the second ramp signal generating unit 219 together with the second switch output stage 215.
  • the second semiconductor device 202 is the slave.
  • the second selector 226 internally cuts off the connection to the second oscillator 224.
  • the output terminal of the second PLL 225 is electrically connected to the second switch output stage 215 and the second ramp signal generating unit 219 via the second selector 226.
  • the input end of the second PLL 225 is connected to the first end of the inductor L21 via the transmission path 228. That is, the second PLL 225 generates the second clock signal CL2 based on the first switch voltage Vst1 including the clock information of the first clock signal CL1, and inputs the second clock signal CL2 to the second switch output stage 215 and the second ramp signal generating unit 219. From a functional perspective, the second PLL 225 generates the second clock signal CL2 by phase-shifting the first clock signal CL1 and converting it to a high frequency.
  • the output terminal of the second ramp signal generating unit 219 is connected to the input terminal of the adder unit 227 together with the second differential line 229 of the second switch output stage 215.
  • the second ramp signal generating unit 219 generates a second ramp signal Vr2 having a sawtooth waveform in response to the second clock signal CL2.
  • the output terminal of the adder 227 is connected to the inverting input terminal of the second comparator 230.
  • the adder 227 adds the second ramp signal Vr2 and the second differential signal Vd2 to generate the second reference signal Vs2.
  • the output terminal of the second comparator 230 is connected to the input terminal (not shown) of the second switch output stage 215.
  • the second comparator 230 compares the second error signal Vc2 with the second reference signal Vs2 to generate a second comparison signal Va2.
  • the second switch output stage 215 is driven based on the second clock signal CL2 and the second comparison signal Va2.
  • the second control circuit 216 drives and controls the second switch output stage 215 based on the second clock signal CL2 and the second comparison signal Va2.
  • FIG. 12 is a timing chart showing the first ramp signal Vr1, the second ramp signal Vr2, the first error signal Vc1, the second error signal Vc2, the first switch voltage Vst1, the second switch voltage Vst2, the first inductor current IL1, and the second inductor current IL2.
  • the first switch voltage Vst1 when the first switch voltage Vst1 is raised to a high level, the first inductor current IL1 gradually increases. In response to this, the first ramp signal Vr1 begins to rise. When the first ramp signal Vr1 exceeds the first error signal Vc1, the first switch voltage Vst1 is lowered to a low level. Then, the first inductor current IL1 gradually decreases.
  • the second inductor current IL2 gradually increases.
  • the second ramp signal Vr2 begins to rise.
  • the second switch voltage Vst2 is lowered to a low level. Then, the second inductor current IL2 gradually decreases.
  • the second error signal Vc2 is larger than the first error signal Vc1 by the second offset signal S2. This increases the duty ratio of the on-time of the second switch voltage Vst2, and increases the maximum value of the second inductor current IL2.
  • the duty ratio of the on-time of the second switch voltage Vst2 may be smaller than the duty ratio of the on-time of the first switch voltage Vst1 due to manufacturing variations in the device, etc.
  • the average value A2 of the second inductor current IL2 is smaller than the average value A1 of the first inductor current IL1.
  • the second error signal Vc2 becomes larger than the first error signal Vc1, and the second inductor current IL2 becomes larger. Therefore, as shown in FIG. 12, the average value A2 of the second inductor current IL2 becomes approximately equal to the average value A1 of the first inductor current IL1. Therefore, a current balance is achieved between the first inductor current IL1 and the second inductor current IL2, and a decrease in the efficiency of the power supply device X20 can be suppressed.
  • the voltage monitoring circuit 15 is provided in a semiconductor integrated circuit device that is a power supply IC, but it may also be provided in a semiconductor integrated circuit device other than a power supply IC.
  • the first semiconductor device 201 and the second semiconductor device 202 are formed in separate packages, but a configuration in which they are formed in the same package can also be adopted.
  • a configuration using a step-down output stage has been described as an example, but the configuration of the present invention is not limited to this, and a step-up output stage or a step-up/step-down output stage may also be used.
  • first semiconductor device 201 and second semiconductor device 202 have been shown as an example of an embodiment of the present disclosure.
  • a configuration including one or more other semiconductor devices in addition to first semiconductor device 201 and second semiconductor device 202 may also be adopted.
  • this other semiconductor device has the same configuration as the first semiconductor device 201 and the second semiconductor device 202.
  • the first semiconductor device 201 transmits the transmission signal Vt not only to the second semiconductor device 202 but also to the other semiconductor device.
  • This other semiconductor device like the second semiconductor device 202, controls the drive of the switch output stage based on the transmission signal Vt.
  • the first error signal Vc1 and the transmission signal Vt are supplied from one master to multiple slaves.
  • the matching unit 223 of the above embodiment may also have the following configuration (see FIG. 13).
  • FIG. 13 is a block diagram showing the details of the matching unit 223.
  • the matching unit 223 further includes a current balancer 231.
  • the input terminal of the current balancer 231 is connected to the output terminal of the correction comparator 222.
  • the first output terminal of the current balancer 231 is connected to the application terminal of the first comparator 212.
  • the second output terminal of the current balancer 231 is connected to the application terminal of the second comparator 230.
  • the current balancer 231 transmits the first offset signal S1 to the first comparator 212 and the second offset signal S2 to the second comparator 230 in response to the correction signal Vcr.
  • the first comparator 212 adjusts the offset of at least one of the first error signal Vc1, the first ramp signal Vr1, and the first differential signal Vd1 in response to the first offset signal S1.
  • the second comparator 230 adjusts the offset of at least one of the first error signal Vc1, the second ramp signal Vr2, and the second differential signal Vd2 in response to the second offset signal S2.
  • the voltage monitoring circuit (15) disclosed herein comprises a first differential input pair (P1) including a first transistor (M1) configured to receive a reference voltage and a second transistor (M2) configured to receive a voltage to be monitored, and a second differential input pair (P2) including a third transistor (M3) configured to receive a first voltage and a fourth transistor (M4) configured to receive a second voltage, and is configured (first configuration) in which the output terminal of the first transistor and the output terminal of the third transistor are commonly connected, and the output terminal of the second transistor and the output terminal of the fourth transistor are commonly connected.
  • At least one of the first voltage and the second voltage may be the output voltage of a resistor voltage divider circuit (R3 to R6) (second configuration).
  • At least one of the first voltage and the second voltage may be the output voltage of a DAC (157) (third configuration).
  • the value of at least one of the first voltage and the second voltage may be switched in a time-division manner (fourth configuration).
  • the voltage monitoring circuit of any of the first to fourth configurations may be configured (fifth configuration) to include a calibration circuit (CAL1) configured to cancel offsets due to the difference in threshold voltage between the first transistor and the second transistor and the difference in threshold voltage between the third transistor and the fourth transistor.
  • CAL1 calibration circuit
  • the semiconductor integrated circuit device (10) disclosed herein has a configuration (sixth configuration) that includes a voltage monitoring circuit having any of the first to fifth configurations described above.
  • the vehicle (X) disclosed herein is configured (seventh configuration) to include a semiconductor integrated circuit device of the sixth configuration described above.
  • the control device (250) disclosed in the specification is a switching regulator control device (250) configured to generate a desired output voltage (Vo) from an input voltage (Vi) by driving at least the first switch output stage (203) and the second switch output stage (215) with a predetermined phase difference, and includes a first control circuit (204) and a second control circuit (216) configured to drive the first switch output stage (203) and the second switch output stage (215), respectively, and is configured (8th configuration) in which a transmission signal (Vt) having both clock information and duty information of the first switch output stage (203) is transmitted from the first control circuit (204) to the second control circuit (216).
  • control device (250) having the eighth configuration may be configured such that the first control circuit (204) includes an error amplifier circuit (205) configured to generate a first error signal (Vc1) corresponding to the error between the output voltage (Vo) and its target value, and a switch control circuit (206) configured to generate a first clock signal (CL1) that defines a first switching frequency of the first switch output stage (203), and is configured to drive and control the first switch output stage (203) based on the first clock signal (CL1) and the first error signal (Vc1) and transmit the first error signal (Vc1) to the second control circuit (216), the clock information is timing information of the rise or fall of the first clock signal (CL1), and the second control circuit (216) drives and controls the second switch output stage (215) based on the first error signal (Vc1) and the transmission signal (Vt) (ninth configuration).
  • the first control circuit (204) includes an error amplifier circuit (205) configured to generate a first error signal (Vc1) corresponding to the error between the output voltage (Vo) and its target value, and
  • the second control circuit (216) includes a phase synchronization circuit (218) configured to generate a second clock signal (CL2) that defines a second switching frequency of the second switch output stage (215) based on the transmission signal (Vt), and a matching circuit configured to generate a second error signal (Vc2) based on the first error signal (Vc1) and the transmission signal (Vt), and is configured to drive and control the second switch output stage (215) based on the second clock signal (CL2) and the second error signal (Vc2) (tenth configuration).
  • CL2 second clock signal
  • Vc2 second error signal
  • the transmission signal (Vt) is a first switch voltage (Vst1) output by the first switch output stage (203) or a first switch control signal for PWM controlling the first switch output stage (203), and the matching circuit is a first low-pass filter (220) that averages the transmission signal (Vt) to generate a first average voltage (Vave1), and a second switch voltage (Vst2) output by the second switch output stage (215) or a second switch control signal for PWM controlling the second switch output stage (215).
  • the 11th configuration prefferably includes a second low-pass filter (221) that averages the second switch control signal for M control to generate a second average voltage (Vave2), a correction comparator (222) configured to compare the first average voltage (Vave1) and the second average voltage (Vave2) to generate a correction signal (Vcr), and a matching unit (223) configured to correct the first error signal (Vc1) based on the correction signal (Vcr) to generate a second error signal (Vc2).
  • a second low-pass filter (221) that averages the second switch control signal for M control to generate a second average voltage (Vave2)
  • a correction comparator 222
  • Vcr correction signal
  • Vcr correction signal
  • control device (250) having the 11th configuration includes a first control circuit (204) including a first ramp signal generating unit (211) configured to generate a first ramp signal (Vr1) in synchronization with a first clock signal (CL1), and a first comparator (212) configured to compare a first error signal (Vc1) with a first reference signal (Vs1) corresponding to the first ramp signal (Vr1) to generate a first comparison signal (Va1), and performs drive control of a first switch output stage (203) based on the first clock signal (CL1) and the first comparison signal (Va1).
  • a first control circuit (204) including a first ramp signal generating unit (211) configured to generate a first ramp signal (Vr1) in synchronization with a first clock signal (CL1), and a first comparator (212) configured to compare a first error signal (Vc1) with a first reference signal (Vs1) corresponding to the first ramp signal (Vr1) to generate a first comparison signal (Va1), and performs drive control of a first switch
  • the second control circuit (216) includes a second ramp signal generating unit (219) configured to generate a second ramp signal (Vr2) in synchronization with the second clock signal (CL2), and a second comparator (230) configured to compare the second error signal (Vc2) with a second reference signal (Vs2) corresponding to the second ramp signal (Vr2) to generate a second comparison signal (Va2), and is configured to control the drive of the second switch output stage (215) in response to the second clock signal (CL2) and the second comparison signal (Va2) (12th configuration).
  • a second ramp signal generating unit (219) configured to generate a second ramp signal (Vr2) in synchronization with the second clock signal (CL2)
  • a second comparator (230) configured to compare the second error signal (Vc2) with a second reference signal (Vs2) corresponding to the second ramp signal (Vr2) to generate a second comparison signal (Va2), and is configured to control the drive of the second switch output stage (215) in response to the second clock signal (CL2) and
  • the first control circuit (204) and the second control circuit (216) may be configured in the same package (thirteenth configuration).
  • the first control circuit (204) and the second control circuit (216) may be formed in different packages (14th configuration)
  • control device (250) having the 14th configuration may be configured (15th configuration) to include a first semiconductor device (201) having a first external terminal configured to output a transmission signal (Vt) and including a first control circuit (204), a second semiconductor device (202) having a second external terminal configured to input the transmission signal (Vt), and a transmission line electrically connecting the first external terminal and the second external terminal and configured to be a transmission path (228) for the transmission signal (Vt).
  • the switching regulator disclosed in the specification is configured (16th configuration) to include a control device (250) having any of the eighth to twelfth configurations.
  • the power supply device (X20) disclosed in the specification is configured to include a switching regulator having a 16th configuration (17th configuration).
  • the second control circuit (216) can obtain clock information and duty information of the first switch output stage (203). By controlling the drive of the second switch output stage (215) based on this clock information and duty information, it is possible to prevent imbalance with the drive of the first switch output stage (203).
  • the second control circuit (216) controls the drive of the second switch output stage (215) based on the first error signal (Vc1). This makes it possible to more effectively prevent the drive balance between the first switch output stage (203) and the second switch output stage (215) from being lost.
  • the second switch output stage (215) is driven based on the first error signal (Vc1) and the transmission signal (Vt).
  • the clock information contained in the transmission signal (Vt) is timing information of the rising or falling edge of the first clock signal (CL1). Therefore, the second switch output stage (215) is driven based on this timing information and the first error signal (Vc1), and therefore, it is possible to more suitably prevent the drive balance between the first switch output stage (203) and the second switch output stage (215) from being lost.
  • the second switch output stage (215) is driven based on the second clock signal (CL2) and the second error signal (Vc2).
  • the second clock signal (CL2) is generated based on the first clock signal (CL1)
  • the second error signal (Vc2) is generated based on the first error signal (Vc1).
  • the second error signal (Vc2) is generated by correcting the first error signal (Vc1) based on the correction signal (Vcr) generated by comparing the first average voltage (Vave1) and the second average voltage (Vave2). Therefore, it is possible to generate the second error signal (Vc2) that can more suitably suppress the loss of balance in the drive between the first switch output stage (203) and the second switch output stage (215).
  • the second reference signal (Vs2) corresponds to the second ramp signal (Vr2) synchronized with the second clock signal (CL2).
  • the second reference signal (Vs2) is compared with the second error signal (Vc2) to generate the second comparison signal (Va2), and the second switch output stage (215) is driven in response to the second clock signal (CL2) and the second comparison signal (Va2).
  • the second clock signal (CL2) is generated based on the transmission signal (Vt). This makes it possible to more effectively prevent the drive balance between the first switch output stage (203) and the second switch output stage (215) from being lost.
  • the first control circuit (204) and the second control circuit (216) are formed in a single package, which allows the control device (250) to be space-saving.
  • the control device (250) according to the 14th configuration has a relatively simple control circuit formed in one package, making it possible to suppress increases in the manufacturing costs of the control device (250).
  • the external terminals used to connect the transmission line can be limited to the first external terminal and the second external terminal.
  • a transmission signal (Vt) including duty information and clock information is transmitted via this transmission line. Therefore, it is possible to transmit duty information and clock information from the first semiconductor device (201) to the second semiconductor device (202) while suppressing an increase in the number of external terminals used in the first semiconductor device (201) and the second semiconductor device (202).
  • the control device (250) according to the 16th configuration can provide a switching regulator capable of suppressing imbalance in the drive of the first switch output stage (203) and the second switch output stage (215).
  • the control device (250) can provide a power supply device (X20) capable of suppressing imbalance in the drive of the first switch output stage (203) and the second switch output stage (215).
  • Switching power supply device 10 Semiconductor integrated circuit device 11, 156 Digital data generation circuit 12, 157 DAC 13 Buffer amplifier 14 Switch voltage generation circuit 15 Voltage monitoring circuit 16 Constant voltage generation circuit 151, 152 Voltage generation circuit 153, 154 Comparator 155 Four-input terminal comparator C1, C2 Capacitor CAL1 Calibration circuit CS1 to CS6 Current source COUT Output capacitor L1 Inductor M1 to M16 Transistor P1 First differential input pair P2 Second differential input pair R1 to R6 Resistor SW1 to SW6 Switch X Vehicle X11 to X18 Electronic device 201 First semiconductor device 202 Second semiconductor device 203 First switch output stage 204 First control circuit 205 Error amplifier circuit 206 Switch control circuit 207 Error amplifier 208 First oscillator 209 First PLL 210 First selector 211 First ramp signal generating section 212 First comparator 213 Adding section 214 First differential line 215 Second switch output stage 216 Second control circuit 217 Matching circuit 218 Phase locked loop circuit 219 Second ramp

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Abstract

This voltage monitoring circuit comprises: a first differential input pair including a first transistor configured so as to receive a reference voltage and a second transistor configured so as to receive a voltage to be monitored; and a second differential input pair including a third transistor configured so as to receive a first voltage and a fourth transistor configured so as to receive a second voltage. The output end of the first transistor and the output end of the third transistor are connected in common. The output end of the second transistor and the output end of the fourth transistor are connected in common.

Description

電圧監視回路、半導体集積回路装置、車両、制御装置、スイッチングレギュレータ、及び電源装置VOLTAGE MONITORING CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, VEHICLE, CONTROL DEVICE, SWITCHING REGULATOR, AND POWER SUPPLY DEVICE
　本明細書中に開示されている発明は、電圧監視回路、半導体集積回路装置、及び車両に関する。また、本明細書中に開示されている発明は、制御装置、この制御装置を備えるスイッチングレギュレータ、およびこのスイッチングレギュレータを備える電源装置に関する。 The invention disclosed in this specification relates to a voltage monitoring circuit, a semiconductor integrated circuit device, and a vehicle. The invention disclosed in this specification also relates to a control device, a switching regulator including this control device, and a power supply device including this switching regulator.
　例えば車載向けの電源ＩＣ（Integrated　Circuit）では、ＩＳＯ２６２６２規格等で制定されている機能安全、ＡＤＡＳ（Advanced　Driver-Assistance　Systems）対応のために電圧監視機能が必要となる。 For example, in-vehicle power supply ICs (Integrated Circuits) require voltage monitoring functions to comply with the functional safety established in standards such as ISO26262 and ADAS (Advanced Driver-Assistance Systems).
　なお、上記に関連する従来技術の一例としては、特許文献１を挙げることができる。 As an example of related prior art, Patent Document 1 can be mentioned.
　また、スイッチングレギュレータにおいて、単一のスイッチ出力段では電流能力が不足する場合に、複数のスイッチ出力段を並列に接続して所定の位相差で駆動させるＳｔａｃｋ方式（又はマルチフェイズ方式）という駆動方式がある。この駆動方式では、各スイッチ出力段のコイルにそれぞれ流れるコイル電流の値が一致していることが理想的である。 In addition, in switching regulators, when the current capacity of a single switch output stage is insufficient, there is a drive method called the stack method (or multi-phase method) in which multiple switch output stages are connected in parallel and driven with a specified phase difference. With this drive method, it is ideal for the values of the coil currents flowing through the coils of each switch output stage to be the same.
特開２０１１－２０４１６４号公報JP 2011-204164 A 特開２０１８－１６１００８号公報JP 2018-161008 A
　例えば上記電源ＩＣを含むＳｏＣ（System-on-a-Chip）における電圧監視の精度は、上記ＳｏＣの電源仕様内での監視が求められる。そのため、非常に高精度な電圧監視が求められる場合がある。 For example, the accuracy of voltage monitoring in a SoC (System-on-a-Chip) that includes the power supply IC is required to be within the power supply specifications of the SoC. Therefore, there are cases where extremely high-precision voltage monitoring is required.
　また、スイッチングレギュレータにおいて、例えば各スイッチ出力段、これらを駆動するドライバ、またはドライバを制御する制御回路等の特性のばらつきによって、各スイッチ出力段のコイル電流が一致せず、バランスの崩れた状態となることがある。すると、スイッチングレギュレータの出力電流が偏った動作となり、効率の低下につながるおそれがある。また、比較的大きくバランスを崩した場合には、保護回路によって、スイッチングレギュレータが動作不良の状態となる。 In addition, in a switching regulator, for example, due to variations in the characteristics of each switch output stage, the drivers that drive them, or the control circuit that controls the drivers, the coil currents of each switch output stage may not match, resulting in an unbalanced state. This may result in the output current of the switching regulator operating in an unbalanced manner, which may lead to reduced efficiency. Furthermore, if the imbalance is relatively large, the protection circuit will cause the switching regulator to malfunction.
　本明細書中に開示されている電圧監視回路は、基準電圧を受け取るように構成された第１トランジスタ及び監視対象電圧を受け取るように構成された第２トランジスタを含む第１差動入力対と、第１電圧を受け取るように構成された第３トランジスタ及び第２電圧を受け取るように構成された第４トランジスタを含む第２差動入力対と、を備える。前記第１トランジスタの出力端と前記第３トランジスタの出力端とが共通接続される。前記第２トランジスタの出力端と前記第４トランジスタの出力端とが共通接続される。 The voltage monitoring circuit disclosed in this specification comprises a first differential input pair including a first transistor configured to receive a reference voltage and a second transistor configured to receive a monitored voltage, and a second differential input pair including a third transistor configured to receive the first voltage and a fourth transistor configured to receive a second voltage. The output terminal of the first transistor and the output terminal of the third transistor are commonly connected. The output terminal of the second transistor and the output terminal of the fourth transistor are commonly connected.
　本明細書中に開示されている半導体集積回路装置は、上記構成の電圧監視回路を備える。 The semiconductor integrated circuit device disclosed in this specification includes a voltage monitoring circuit having the above configuration.
　本明細書中に開示されている車両は、上記構成の半導体集積回路装置を備える。 The vehicle disclosed in this specification is equipped with a semiconductor integrated circuit device having the above configuration.
　本明細書中に開示されている制御装置は、少なくとも第１スイッチ出力段及び第２スイッチ出力段を所定の位相差で駆動することにより入力電圧から所望の出力電圧を生成するように構成されたスイッチングレギュレータの制御装置である。制御装置は、第１スイッチ出力段及び第２スイッチ出力段をそれぞれ駆動するように構成された第１制御回路および第２制御回路を含み、第１制御回路から第２制御回路へ、第１スイッチ出力段のクロック情報とDuty情報を併せ持つ伝送信号が伝送される。 The control device disclosed in this specification is a control device for a switching regulator configured to generate a desired output voltage from an input voltage by driving at least a first switch output stage and a second switch output stage with a predetermined phase difference. The control device includes a first control circuit and a second control circuit configured to drive the first switch output stage and the second switch output stage, respectively, and a transmission signal having both clock information and duty information of the first switch output stage is transmitted from the first control circuit to the second control circuit.
　本明細書中に開示されているスイッチングレギュレータは、上記構成の制御装置を備える。 The switching regulator disclosed in this specification is equipped with a control device having the above configuration.
　本明細書中に開示されている電源装置は、上記構成のスイッチングレギュレータを備える。 The power supply device disclosed in this specification includes a switching regulator having the above configuration.
　本明細書中に開示されている発明によれば、高精度な電圧監視を実現することができる。 The invention disclosed in this specification makes it possible to achieve highly accurate voltage monitoring.
　本明細書中に開示されている制御装置によれば、第２制御回路は、第１スイッチ出力段のクロック情報およびDuty情報を得ることができる。このクロック情報およびDuty情報に基づいて第２スイッチ出力段を駆動制御することで、第１スイッチ出力段の駆動とのバランスが崩れるのを抑制することができる。 According to the control device disclosed in this specification, the second control circuit can obtain clock information and duty information of the first switch output stage. By controlling the drive of the second switch output stage based on this clock information and duty information, it is possible to prevent imbalance with the drive of the first switch output stage.
図１は、スイッチング電源装置の比較例を示す図である。FIG. 1 is a diagram showing a comparative example of a switching power supply device. 図２は、スイッチング電源装置の第１実施形態を示す図である。FIG. 2 is a diagram showing a first embodiment of a switching power supply device. 図３は、４入力端子コンパレータの構成例を示す図である。FIG. 3 is a diagram showing an example of the configuration of a four-input terminal comparator. 図４は、スイッチング電源装置の第２実施形態を示す図である。FIG. 4 is a diagram showing a second embodiment of a switching power supply device. 図５は、第２電圧の値が時分割で切り替えられることを模式的に示す図である。FIG. 5 is a diagram showing a schematic diagram of the value of the second voltage being switched in a time division manner. 図６は、車両の外観図である。FIG. 6 is an external view of the vehicle. 図７は、比較例の電源装置の構成を示すブロック図である。FIG. 7 is a block diagram showing the configuration of a power supply device of the comparative example. 図８は、比較例の電源装置に係る第１インダクタ電流、第２インダクタ電流、第１スイッチ電圧、および第２スイッチ電圧、を示すタイミングチャートである。FIG. 8 is a timing chart showing the first inductor current, the second inductor current, the first switch voltage, and the second switch voltage in the power supply device of the comparative example. 図９は、本開示の電源装置の実施形態の概略構成を示す図である。FIG. 9 is a diagram showing a schematic configuration of an embodiment of a power supply device according to the present disclosure. 図１０は、第１スイッチ電圧、第２スイッチ電圧、第１インダクタ電流、および第２インダクタ電流を示すタイミングチャートである。FIG. 10 is a timing chart showing the first switch voltage, the second switch voltage, the first inductor current, and the second inductor current. 図１１は、電源装置の構成を示すブロック図である。FIG. 11 is a block diagram showing the configuration of the power supply device. 図１２は、第１ランプ信号、第２ランプ信号、第１誤差信号、第２誤差信号、第１比較信号、第２比較信号、第１インダクタ電流、および第２インダクタ電流を示すタイミングチャートである。FIG. 12 is a timing chart showing the first ramp signal, the second ramp signal, the first error signal, the second error signal, the first comparison signal, the second comparison signal, the first inductor current, and the second inductor current. 図１３は、整合部の詳細を示すブロック図である。FIG. 13 is a block diagram showing the details of the matching unit.
＜スイッチング電源装置（比較例）＞
　図１は、スイッチング電源装置の比較例（＝後出の実施形態と対比される一般的な構成）を示す図である。本比較例のスイッチング電源装置１は、直流入力電圧ＶＩＮから所望の直流出力電圧ＶＯＵＴを生成する。 <Switching power supply device (comparison example)>
1 is a diagram showing a comparative example of a switching power supply device (= a general configuration to be compared with the embodiments described later). A switching power supply device 1 of this comparative example generates a desired DC output voltage VOUT from a DC input voltage VIN.
　スイッチング電源装置１は、半導体集積回路装置１０と、インダクタＬ１と、出力コンデンサＣＯＵＴと、を備える。半導体集積回路装置１０は、スイッチング電源装置１の制御主体となる電源ＩＣである。 The switching power supply device 1 includes a semiconductor integrated circuit device 10, an inductor L1, and an output capacitor COUT. The semiconductor integrated circuit device 10 is a power supply IC that serves as the main controller of the switching power supply device 1.
　半導体集積回路装置１０は、装置外部との電気的な接続を確立するための手段として、複数の端子（本図では端子Ｔ１～Ｔ４）を備える。 The semiconductor integrated circuit device 10 has multiple terminals (terminals T1 to T4 in this diagram) as a means for establishing electrical connection with the outside of the device.
　端子Ｔ１には、直流入力電圧ＶＩＮが印加される。端子Ｔ２には、グラウンド電圧が印加される。端子Ｔ３には、インダクタＬ１の第１端が接続される。インダクタＬ１の第２端及び出力コンデンサＣＯＵＴの第１端は、端子Ｔ４に接続される。出力コンデンサＣＯＵＴの第２端には、グラウンド電圧が印加される。 A DC input voltage VIN is applied to terminal T1. A ground voltage is applied to terminal T2. A first end of inductor L1 is connected to terminal T3. A second end of inductor L1 and a first end of output capacitor COUT are connected to terminal T4. A ground voltage is applied to the second end of output capacitor COUT.
　インダクタＬ１及び出力コンデンサＣＯＵＴは、端子Ｔ３から出力されるパルス状のスイッチ電圧ＶＳＷを直流出力電圧ＶＯＵＴに変換する。端子Ｔ４には、直流出力電圧ＶＯＵＴが印加される。 Inductor L1 and output capacitor COUT convert the pulsed switch voltage VSW output from terminal T3 into a DC output voltage VOUT. The DC output voltage VOUT is applied to terminal T4.
　半導体集積回路装置１０は、デジタルデータ生成回路１１と、ＤＡＣ（Digital　Analog　Converter）１２と、バッファアンプ１３と、スイッチ電圧生成回路１４と、電圧監視回路１５と、抵抗Ｒ１及びＲ２と、を備える。 The semiconductor integrated circuit device 10 includes a digital data generation circuit 11, a DAC (Digital Analog Converter) 12, a buffer amplifier 13, a switch voltage generation circuit 14, a voltage monitoring circuit 15, and resistors R1 and R2.
　デジタルデータ生成回路１１は、基準電圧用のデジタルデータを生成して出力する。なお、デジタルデータ生成回路１１によって生成される基準電圧用のデジタルデータは、１つの値に固定されていてもよく、複数の値に切り替え可能であってもよい。 The digital data generation circuit 11 generates and outputs digital data for the reference voltage. Note that the digital data for the reference voltage generated by the digital data generation circuit 11 may be fixed to one value, or may be switchable between multiple values.
　ＤＡＣ１２は、基準電圧用のデジタルデータを、アナログ電圧である基準電圧ＶＲＥＦに変換して出力する。ＤＡＣ１２から出力される基準電圧ＶＲＥＦは、バッファアンプ１３を経由して、スイッチ電圧生成回路１４及び電圧監視回路１５それぞれに供給される。 DAC12 converts the digital data for the reference voltage into an analog voltage, the reference voltage VREF, and outputs it. The reference voltage VREF output from DAC12 is supplied to the switch voltage generation circuit 14 and the voltage monitoring circuit 15 via the buffer amplifier 13.
　抵抗Ｒ１及びＲ２は、端子Ｔ４に印加される直流出力電圧ＶＯＵＴの分圧である帰還電圧ＶＦＢを生成し、帰還電圧ＶＦＢをスイッチ電圧生成回路１４及び電圧監視回路１５それぞれに供給する。 Resistors R1 and R2 generate a feedback voltage VFB, which is a divided voltage of the DC output voltage VOUT applied to terminal T4, and supply the feedback voltage VFB to the switch voltage generating circuit 14 and the voltage monitoring circuit 15, respectively.
　スイッチ電圧生成回路１４は、スイッチング素子を含み、基準電圧ＶＲＥＦと帰還電圧ＶＦＢとの差に応じたデューティでスイッチング素子をスイッチングすることによって、直流入力電圧ＶＩＮをスイッチ電圧ＶＳＷに変換し、スイッチ電圧ＶＳＷを端子Ｔ３に供給する。 The switch voltage generating circuit 14 includes a switching element, and converts the DC input voltage VIN into a switch voltage VSW by switching the switching element with a duty corresponding to the difference between the reference voltage VREF and the feedback voltage VFB, and supplies the switch voltage VSW to the terminal T3.
　電圧監視回路１５は、電圧生成回路１５１及び１５２と、コンパレータ１５３及び１５４と、を備える。電圧監視回路１５は、帰還電圧ＶＦＢが過電圧であるか否かを監視するとともに、帰還電圧ＶＦＢが低電圧であるか否かを監視する。 The voltage monitoring circuit 15 includes voltage generating circuits 151 and 152, and comparators 153 and 154. The voltage monitoring circuit 15 monitors whether the feedback voltage VFB is an overvoltage or not, and also monitors whether the feedback voltage VFB is a low voltage or not.
　電圧生成回路１５１は、定電流回路及び抵抗を含み、定電流と抵抗を用いて基準電圧ＶＲＥＦから第１基準電圧ＶＲＥＦ１を生成する。第１基準電圧ＶＲＥＦ１は、基準電圧ＶＲＥＦより第１所定値だけ大きい。 The voltage generation circuit 151 includes a constant current circuit and a resistor, and generates a first reference voltage VREF1 from the reference voltage VREF using the constant current and the resistor. The first reference voltage VREF1 is greater than the reference voltage VREF by a first predetermined value.
　電圧生成回路１５２は、定電流回路及び抵抗を含み、定電流と抵抗を用いて基準電圧ＶＲＥＦから第２基準電圧ＶＲＥＦ２を生成する。第２基準電圧ＶＲＥＦ２は、基準電圧ＶＲＥＦより第２所定値だけ小さい。なお、第２所定値は、第１所定値と同じ値であってもよく、第１所定値と異なる値であってもよい。 The voltage generating circuit 152 includes a constant current circuit and a resistor, and generates a second reference voltage VREF2 from the reference voltage VREF using the constant current and the resistor. The second reference voltage VREF2 is smaller than the reference voltage VREF by a second predetermined value. Note that the second predetermined value may be the same as the first predetermined value, or may be a value different from the first predetermined value.
　コンパレータ１５３の非反転入力端子には、第１基準電圧ＶＲＥＦ１が供給される。コンパレータ１５４の反転入力端子には、帰還電圧ＶＦＢが供給される。帰還電圧ＶＦＢが第１基準電圧ＶＲＥＦ１より大きいとき、すなわち帰還電圧ＶＦＢが過電圧であるとき、コンパレータ１５３の出力信号である過電圧検出信号ＯＶＤは、ＬＯＷレベルになる。一方、帰還電圧ＶＦＢが過電圧でないとき、コンパレータ１５３の出力信号である過電圧検出信号ＯＶＤは、ＨＩＧＨレベルになる。 The non-inverting input terminal of the comparator 153 is supplied with a first reference voltage VREF1. The inverting input terminal of the comparator 154 is supplied with a feedback voltage VFB. When the feedback voltage VFB is greater than the first reference voltage VREF1, that is, when the feedback voltage VFB is an overvoltage, the overvoltage detection signal OVD, which is the output signal of the comparator 153, becomes a LOW level. On the other hand, when the feedback voltage VFB is not an overvoltage, the overvoltage detection signal OVD, which is the output signal of the comparator 153, becomes a HIGH level.
　コンパレータ１５４の反転入力端子には、第２基準電圧ＶＲＥＦ２が供給される。コンパレータ１５４の非反転入力端子には、帰還電圧ＶＦＢが供給される。帰還電圧ＶＦＢが第２基準電圧ＶＲＥＦ２より小さいとき、すなわち帰還電圧ＶＦＢが低電圧であるとき、コンパレータ１５３の出力信号である低電圧検出信号ＵＶＤは、ＬＯＷレベルになる。一方、帰還電圧ＶＦＢが低電圧でないとき、コンパレータ１５３の出力信号である低電圧検出信号ＵＶＤは、ＨＩＧＨレベルになる。 The second reference voltage VREF2 is supplied to the inverting input terminal of the comparator 154. The feedback voltage VFB is supplied to the non-inverting input terminal of the comparator 154. When the feedback voltage VFB is smaller than the second reference voltage VREF2, that is, when the feedback voltage VFB is a low voltage, the low voltage detection signal UVD, which is the output signal of the comparator 153, becomes a LOW level. On the other hand, when the feedback voltage VFB is not a low voltage, the low voltage detection signal UVD, which is the output signal of the comparator 153, becomes a HIGH level.
　電圧監視回路１５では、トリミングを実施することで電圧監視の精度を向上させることができる。 In the voltage monitoring circuit 15, the accuracy of voltage monitoring can be improved by performing trimming.
　しかしながら、電圧生成回路１５１及び１５２に含まれる定電流回路の温度特性及び電圧特性と、コンパレータ１５３及び１５４のオフセットの温度特性とは、スイッチング電源装置１の使用環境によって変動する特性であり、精度悪化の要因となっていた。つまり、比較例の電圧監視回路１５は、電圧監視の精度が不十分であった。 However, the temperature characteristics and voltage characteristics of the constant current circuits included in the voltage generation circuits 151 and 152 and the temperature characteristics of the offsets of the comparators 153 and 154 are characteristics that vary depending on the usage environment of the switching power supply device 1, and are a cause of deterioration in accuracy. In other words, the voltage monitoring circuit 15 of the comparative example had insufficient voltage monitoring accuracy.
　上記の考察に鑑み、以下では、高精度な電圧監視を実現することができる新規な実施形態を提案する。 In light of the above considerations, we propose a new embodiment below that can achieve highly accurate voltage monitoring.
＜スイッチング電源装置（第１実施形態）＞
　図２は、スイッチング電源装置の第１実施形態を示す図である。本実施形態のスイッチング電源装置１は、先出の比較例（図１）を基本としつつ、定電圧生成回路１６を備え、電圧監視回路１５の構成が異なっている。 <Switching power supply device (first embodiment)>
2 is a diagram showing a first embodiment of a switching power supply device. The switching power supply device 1 of this embodiment is based on the comparative example (FIG. 1) described above, but includes a constant voltage generating circuit 16 and has a different configuration for the voltage monitoring circuit 15.
　定電圧生成回路１６は、直流入力電圧ＶＩＮから定電圧ＶＲＥＧを生成する。 The constant voltage generation circuit 16 generates a constant voltage VREG from the DC input voltage VIN.
　本実施形態の電圧監視回路１５は、４入力端子コンパレータ１５５と、抵抗Ｒ３及びＲ４によって構成される抵抗分圧回路と、抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路と、を備える。 The voltage monitoring circuit 15 of this embodiment includes a four-input terminal comparator 155, a resistive voltage divider circuit formed by resistors R3 and R4, and a resistive voltage divider circuit formed by resistors R5 and R6.
　抵抗Ｒ３及びＲ４によって構成される抵抗分圧回路は、定電圧ＶＲＥＧを抵抗Ｒ３及びＲ４の抵抗値比で分圧して得られる第１電圧Ｖ１を出力する。抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路は、定電圧ＶＲＥＧを抵抗Ｒ５及びＲ６の抵抗値比で分圧して得られる第２電圧Ｖ２を出力する。 The resistor voltage divider circuit formed by resistors R3 and R4 outputs a first voltage V1 obtained by dividing the constant voltage VREG by the resistance ratio of resistors R3 and R4. The resistor voltage divider circuit formed by resistors R5 and R6 outputs a second voltage V2 obtained by dividing the constant voltage VREG by the resistance ratio of resistors R5 and R6.
　４入力端子コンパレータ１５５の第１非反転入力端子には基準電圧ＶＲＥＦが供給される。４入力端子コンパレータ１５５の第１反転入力端子には帰還電圧ＶＦＢが供給される。４入力端子コンパレータ１５５の第２非反転入力端子には第１電圧Ｖ１が供給される。４入力端子コンパレータ１５５の第２反転入力端子には第２電圧Ｖ２が供給される。 The first non-inverting input terminal of the four-input terminal comparator 155 is supplied with a reference voltage VREF. The first inverting input terminal of the four-input terminal comparator 155 is supplied with a feedback voltage VFB. The second non-inverting input terminal of the four-input terminal comparator 155 is supplied with a first voltage V1. The second inverting input terminal of the four-input terminal comparator 155 is supplied with a second voltage V2.
　４入力端子コンパレータ１５５の出力信号である過電圧検出信号ＯＶＤは、基準電圧ＶＲＥＦと帰還電圧ＶＦＢとの差及び第１電圧Ｖ１と第２電圧Ｖ２との差の合計（ＶＲＥＦ－ＶＦＢ＋Ｖ１－Ｖ２）に応じた電圧になる。 The overvoltage detection signal OVD, which is the output signal of the four-input terminal comparator 155, is a voltage that corresponds to the sum of the difference between the reference voltage VREF and the feedback voltage VFB and the difference between the first voltage V1 and the second voltage V2 (VREF-VFB+V1-V2).
　したがって、第１電圧Ｖ１と第２電圧Ｖ２との差（Ｖ１－Ｖ２）が上述した第１所定値に設定されることで、本実施形態の電圧監視回路１５は、比較例の電圧監視回路１５と同様に、帰還電圧ＶＦＢが過電圧であるか否かを監視することができる。帰還電圧ＶＦＢが過電圧であるとき、４入力端子コンパレータ１５５の出力信号である過電圧検出信号ＯＶＤは、ＬＯＷレベルになる。一方、帰還電圧ＶＦＢが過電圧でないとき、４入力端子コンパレータ１５５の出力信号である過電圧検出信号ＯＶＤは、ＨＩＧＨレベルになる。 Therefore, by setting the difference (V1-V2) between the first voltage V1 and the second voltage V2 to the above-mentioned first predetermined value, the voltage monitoring circuit 15 of this embodiment can monitor whether the feedback voltage VFB is an overvoltage, similar to the voltage monitoring circuit 15 of the comparative example. When the feedback voltage VFB is an overvoltage, the overvoltage detection signal OVD, which is the output signal of the four-input terminal comparator 155, becomes a LOW level. On the other hand, when the feedback voltage VFB is not an overvoltage, the overvoltage detection signal OVD, which is the output signal of the four-input terminal comparator 155, becomes a HIGH level.
　第１電圧Ｖ１及び第２電圧Ｖ２それぞれは、基準電圧ＶＲＥＦを用いて生成される必要がない。このため、第１電圧Ｖ１及び第２電圧Ｖ２それぞれを温度によって変動し難い電圧にすることができる。したがって、本実施形態の電圧監視回路１５は、高精度な電圧監視を実現することができる。 The first voltage V1 and the second voltage V2 do not need to be generated using the reference voltage VREF. This makes it possible to make the first voltage V1 and the second voltage V2 voltages less likely to fluctuate with temperature. Therefore, the voltage monitoring circuit 15 of this embodiment can achieve highly accurate voltage monitoring.
　本実施形態では、抵抗分圧回路に含まれる２つの抵抗のペア性を利用して、第１電圧Ｖ１及び第２電圧Ｖ２それぞれを温度によって変動し難い電圧にしている。また、本実施形態のように、抵抗Ｒ３及びＲ４によって構成される抵抗分圧回路と、抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路とに共通の定電圧ＶＲＥＧが供給される構成にすることで、仮に定電圧ＶＲＥＧが温度によって変動しても第１電圧Ｖ１と第２電圧Ｖ２との差（Ｖ１－Ｖ２）が定電圧ＶＲＥＧの温度特性の影響を受けないようにすることができる。 In this embodiment, the pairing of the two resistors included in the resistive voltage divider circuit is used to make each of the first voltage V1 and the second voltage V2 voltages less likely to fluctuate with temperature. Furthermore, as in this embodiment, by configuring the resistive voltage divider circuit formed by resistors R3 and R4 and the resistive voltage divider circuit formed by resistors R5 and R6 to be supplied with a common constant voltage VREG, it is possible to prevent the difference between the first voltage V1 and the second voltage V2 (V1-V2) from being affected by the temperature characteristics of the constant voltage VREG even if the constant voltage VREG fluctuates with temperature.
　図３は、４入力端子コンパレータ１５５の構成例を示す図である。図３に示す構成例の４入力端子コンパレータ１５５は、トランジスタＭ１～Ｍ１６と、電流源ＣＳ１～ＣＳ６と、スイッチＳＷ１～ＳＷ６と、コンデンサＣ１及びＣ２と、を備える。トランジスタＭ１～Ｍ６、Ｍ１５、及びＭ１６は、Ｐチャネル型ＭＯＳ電界効果トランジスタである。トランジスタＭ７～Ｍ１４は、Ｎチャネル型ＭＯＳ電界効果トランジスタである。 FIG. 3 is a diagram showing an example configuration of a four-input terminal comparator 155. The four-input terminal comparator 155 of the example configuration shown in FIG. 3 includes transistors M1 to M16, current sources CS1 to CS6, switches SW1 to SW6, and capacitors C1 and C2. Transistors M1 to M6, M15, and M16 are P-channel type MOS field effect transistors. Transistors M7 to M14 are N-channel type MOS field effect transistors.
　トランジスタＭ１及びＭ２によって第１差動入力対Ｐ１が構成される。トランジスタＭ３及びＭ４によって第２差動入力対Ｐ２が構成される。トランジスタＭ５及びＭ６とコンデンサＣ１及びＣ２とスイッチＳＷ５及びＳＷ６とによってキャリブレーション回路ＣＡＬ１が構成される。 The first differential input pair P1 is formed by transistors M1 and M2. The second differential input pair P2 is formed by transistors M3 and M4. The calibration circuit CAL1 is formed by transistors M5 and M6, capacitors C1 and C2, and switches SW5 and SW6.
　電流源ＣＳ１～ＣＳ６の各第１端には定電圧ＶＲＥＧが印加される。 A constant voltage VREG is applied to the first terminal of each of the current sources CS1 to CS6.
　基準電圧ＶＲＥＦは、トランジスタＭ１のゲート及びスイッチＳＷ２の第１端に供給される。帰還電圧ＶＦＢは、スイッチＳＷ１の第１端に供給される。スイッチＳＷ１及びＳＷ２の各第２端は、トランジスタＭ２のゲートに接続される。電流源ＣＳ１の第２端は、トランジスタＭ１及びＭ２の各ソースに接続される。 The reference voltage VREF is supplied to the gate of transistor M1 and the first terminal of switch SW2. The feedback voltage VFB is supplied to the first terminal of switch SW1. The second terminals of switches SW1 and SW2 are connected to the gate of transistor M2. The second terminal of current source CS1 is connected to the sources of transistors M1 and M2.
　第１電圧Ｖ１は、トランジスタＭ３のゲート及びスイッチＳＷ４の第１端に供給される。第２電圧Ｖ２は、スイッチＳＷ３の第１端に供給される。スイッチＳＷ３及びＳＷ４の各第２端は、トランジスタＭ４のゲートに接続される。電流源ＣＳ２の第２端は、トランジスタＭ３及びＭ４の各ソースに接続される。 The first voltage V1 is supplied to the gate of transistor M3 and the first terminal of switch SW4. The second voltage V2 is supplied to the first terminal of switch SW3. The second terminals of switches SW3 and SW4 are connected to the gate of transistor M4. The second terminal of current source CS2 is connected to the sources of transistors M3 and M4.
　トランジスタＭ１のドレインとトランジスタＭ３のドレインとは共通接続される。トランジスタＭ２のドレインとトランジスタＭ４のドレインとは共通接続される。 The drain of transistor M1 and the drain of transistor M3 are commonly connected. The drain of transistor M2 and the drain of transistor M4 are commonly connected.
　トランジスタＭ５のゲートは、スイッチＳＷ５の第１端及びコンデンサＣ１の第１端に接続される。トランジスタＭ６のゲートは、スイッチＳＷ６の第１端及びコンデンサＣ２の第１端に接続される。電流源ＣＳ３の第２端は、トランジスタＭ５及びＭ６の各ソースに接続される。コンデンサＣ１及びＣ２の各第２端には、グラウンド電圧が印加される。 The gate of transistor M5 is connected to the first end of switch SW5 and the first end of capacitor C1. The gate of transistor M6 is connected to the first end of switch SW6 and the first end of capacitor C2. The second end of current source CS3 is connected to the sources of transistors M5 and M6. A ground voltage is applied to the second ends of capacitors C1 and C2.
　トランジスタＭ５のドレイン及びスイッチＳＷ５の第２端は、トランジスタＭ１のドレインと、トランジスタＭ３のドレインと、トランジスタＭ９のソースと、トランジスタＭ１０のドレインと、に接続される。トランジスタＭ９のドレインは、電流源ＣＳ５の第２端に接続される。 The drain of transistor M5 and the second end of switch SW5 are connected to the drain of transistor M1, the drain of transistor M3, the source of transistor M9, and the drain of transistor M10. The drain of transistor M9 is connected to the second end of current source CS5.
　トランジスタＭ６のドレイン及びスイッチＳＷ６の第２端は、トランジスタＭ２のドレインと、トランジスタＭ４のドレインと、トランジスタＭ１１のソースと、トランジスタＭ１２のドレインと、に接続される。トランジスタＭ１１のドレインは、電流源ＣＳ６の第２端に接続される。 The drain of transistor M6 and the second end of switch SW6 are connected to the drain of transistor M2, the drain of transistor M4, the source of transistor M11, and the drain of transistor M12. The drain of transistor M11 is connected to the second end of current source CS6.
　トランジスタＭ７～Ｍ１２の各ゲートは、電流源ＣＳ４の第２端及びトランジスタＭ７のドレインに接続される。トランジスタＭ７のソースは、トランジスタＭ８のドレインに接続される。トランジスタＭ８、Ｍ１０、及びＭ１２の各ソースには、グラウンド電圧が印加される。電流源ＣＳ５とトランジスタＭ９との接続ノードからトランジスタＭ１４のゲートにゲート信号Ｇ１４が供給される。電流源ＣＳ６とトランジスタＭ１１との接続ノードからトランジスタＭ１３のゲートにゲート信号Ｇ１３が供給される。トランジスタＭ１３及びＭ１４の各ソースは、グラウンド電圧が印加される。トランジスタＭ１５及びＭ１６によってカレントミラー回路が構成される。トランジスタＭ１５及びＭ１６の各ソースには、定電圧ＶＲＥＧが印加される。トランジスタＭ１５及びＭ１６の各ゲート並びにトランジスタＭ１５のドレインは、トランジスタＭ１３のドレインに接続される。トランジスタＭ１６のドレインは、トランジスタＭ１４のドレインに接続される。トランジスタＭ１６とトランジスタＭ１４との接続ノードから４入力端子コンパレータ１５５の出力信号ＳＯＵＴ（図１における過電圧検出信号ＯＶＤ）が出力される。 The gates of transistors M7 to M12 are connected to the second end of current source CS4 and the drain of transistor M7. The source of transistor M7 is connected to the drain of transistor M8. A ground voltage is applied to the sources of transistors M8, M10, and M12. A gate signal G14 is supplied to the gate of transistor M14 from the connection node between current source CS5 and transistor M9. A gate signal G13 is supplied to the gate of transistor M13 from the connection node between current source CS6 and transistor M11. A ground voltage is applied to the sources of transistors M13 and M14. A current mirror circuit is formed by transistors M15 and M16. A constant voltage VREG is applied to the sources of transistors M15 and M16. The gates of transistors M15 and M16 and the drain of transistor M15 are connected to the drain of transistor M13. The drain of transistor M16 is connected to the drain of transistor M14. The output signal SOUT of the four-input terminal comparator 155 (overvoltage detection signal OVD in FIG. 1) is output from the connection node between transistors M16 and M14.
　図３に示す構成例の４入力端子コンパレータ１５５は、通常動作時（比較動作時）にスイッチＳＷ１及びスイッチＳＷ３をオンにし、スイッチＳＷ２、ＳＷ４、ＳＷ５、及びＳＷ６をオフにする。 The four-input terminal comparator 155 in the configuration example shown in FIG. 3 turns on switches SW1 and SW3 during normal operation (during comparison operation) and turns off switches SW2, SW4, SW5, and SW6.
　図３に示す構成例の４入力端子コンパレータ１５５は、キャリブレーション動作時にスイッチＳＷ１及びスイッチＳＷ３をオフにし、スイッチＳＷ２、ＳＷ４、ＳＷ５、及びＳＷ６をオンにする。このとき、トランジスタＭ１の閾値電圧とトランジスタＭ２の閾値電圧が等しければ、トランジスタＭ１のドレイン電流Ｉa２とトランジスタＭ２のドレイン電流Ｉa３は等しくなる。同様に、トランジスタＭ３の閾値電圧とトランジスタＭ４の閾値電圧が等しければ、トランジスタＭ３のドレイン電流Ｉｂ２とトランジスタＭ４のドレイン電流Ｉｂ３は等しくなる。 The four-input terminal comparator 155 of the configuration example shown in FIG. 3 turns off switches SW1 and SW3 during calibration operation, and turns on switches SW2, SW4, SW5, and SW6. At this time, if the threshold voltage of transistor M1 is equal to the threshold voltage of transistor M2, the drain current Ia2 of transistor M1 is equal to the drain current Ia3 of transistor M2. Similarly, if the threshold voltage of transistor M3 is equal to the threshold voltage of transistor M4, the drain current Ib2 of transistor M3 is equal to the drain current Ib3 of transistor M4.
　しかし、例えばトランジスタＭ１の閾値電圧がトランジスタＭ２の閾値電圧より大きく、且つ、トランジスタＭ３の閾値電圧がトランジスタＭ４の閾値電圧より大きい場合、トランジスタＭ１のドレイン電流Ｉa２がトランジスタＭ２のドレイン電流Ｉa３より小さくなり、且つ、トランジスタＭ３のドレイン電流Ｉｂ２がトランジスタＭ４のドレイン電流Ｉｂ３より小さくなる。その結果、トランジスタＭ１及びＭ３のドレイン電圧Ｖ１２は、トランジスタＭ２及びＭ４のドレイン電圧Ｖ１３より小さくなる。 However, for example, if the threshold voltage of transistor M1 is greater than the threshold voltage of transistor M2 and the threshold voltage of transistor M3 is greater than the threshold voltage of transistor M4, the drain current Ia2 of transistor M1 will be smaller than the drain current Ia3 of transistor M2 and the drain current Ib2 of transistor M3 will be smaller than the drain current Ib3 of transistor M4. As a result, the drain voltage V12 of transistors M1 and M3 will be smaller than the drain voltage V13 of transistors M2 and M4.
　ここで、スイッチＳＷ５及びＳＷ６がオンであるため、キャリブレーション回路ＣＡＬ１は、トランジスタＭ１及びＭ３のドレイン電圧Ｖ１２とトランジスタＭ２及びＭ４のドレイン電圧Ｖ１３とに依存したバランスで、トランジスタＭ５のドレイン電流Ｉｃ２とトランジスタＭ６のドレイン電流Ｉｃ３とを流す。 Now, because switches SW5 and SW6 are on, the calibration circuit CAL1 passes the drain current Ic2 of transistor M5 and the drain current Ic3 of transistor M6 in a balance that depends on the drain voltage V12 of transistors M1 and M3 and the drain voltage V13 of transistors M2 and M4.
　例えば、トランジスタＭ１及びＭ３のドレイン電圧Ｖ１２がトランジスタＭ２及びＭ４のドレイン電圧Ｖ１３より小さいときには、トランジスタＭ５のドレイン電流Ｉｃ２がトランジスタＭ６のドレイン電流Ｉｃ３より大きくなり、トランジスタＭ１及びＭ３のドレイン電圧Ｖ１２とトランジスタＭ２及びＭ４のドレイン電圧Ｖ１３とが等しい状態に近づくように調整される。そして、トランジスタＭ１及びＭ３のドレイン電圧Ｖ１２に応じた電荷がコンデンサＣ１にチャージされ、トランジスタＭ２及びＭ４のドレイン電圧Ｖ１３に応じた電荷がコンデンサＣ１にチャージされる。これより、キャリブレーション動作から通常動作に切り替わったときに、第１差動入力対Ｐ１及び第２差動入力対Ｐ２の各オフセットがキャンセルされる。したがって、本実施形態の電圧監視回路１５は、キャリブレーション回路ＣＡＬ１によってより一層高精度な電圧監視を実現することができる。 For example, when the drain voltage V12 of the transistors M1 and M3 is smaller than the drain voltage V13 of the transistors M2 and M4, the drain current Ic2 of the transistor M5 becomes larger than the drain current Ic3 of the transistor M6, and the drain voltage V12 of the transistors M1 and M3 and the drain voltage V13 of the transistors M2 and M4 are adjusted to be closer to an equal state. Then, a charge according to the drain voltage V12 of the transistors M1 and M3 is charged to the capacitor C1, and a charge according to the drain voltage V13 of the transistors M2 and M4 is charged to the capacitor C1. As a result, when switching from the calibration operation to the normal operation, the offsets of the first differential input pair P1 and the second differential input pair P2 are canceled. Therefore, the voltage monitoring circuit 15 of this embodiment can achieve even more accurate voltage monitoring by the calibration circuit CAL1.
　第１差動入力対Ｐ１及び第２差動入力対Ｐ２の各オフセットは、スイッチング電源装置１の使用環境によって変動する。したがって、図３に示す構成例の４入力端子コンパレータ１５５は、キャリブレーション動作と通常動作とを交互に繰り返すようにする。 The offsets of the first differential input pair P1 and the second differential input pair P2 vary depending on the environment in which the switching power supply device 1 is used. Therefore, the four-input terminal comparator 155 in the configuration example shown in FIG. 3 alternately repeats a calibration operation and a normal operation.
　本実施形態の電圧監視回路１５は、帰還電圧ＶＦＢが過電圧であるか否かを監視することしかできず、帰還電圧ＶＦＢが低電圧であるか否かを監視することができない。帰還電圧ＶＦＢが低電圧であるか否かを監視するためには、本実施形態の電圧監視回路１５に、低電圧監視用として、４入力端子コンパレータ１５５と、抵抗Ｒ３及びＲ４によって構成される抵抗分圧回路と、抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路と、をもう一組追加する必要がある。 The voltage monitoring circuit 15 of this embodiment can only monitor whether the feedback voltage VFB is an overvoltage, and cannot monitor whether the feedback voltage VFB is an undervoltage. To monitor whether the feedback voltage VFB is an undervoltage, it is necessary to add another set of a four-input terminal comparator 155, a resistive voltage divider circuit formed by resistors R3 and R4, and a resistive voltage divider circuit formed by resistors R5 and R6 to the voltage monitoring circuit 15 of this embodiment for undervoltage monitoring.
　キャリブレーション回路ＣＡＬ１を含むコンパレータは、一般的に回路規模が大きくなる傾向にある。したがって、本実施形態の電圧監視回路１５を、４入力端子コンパレータ１５５と、抵抗Ｒ３及びＲ４によって構成される抵抗分圧回路と、抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路と、を二組設ける構成にした場合、比較例の電圧監視回路１５に比べて大幅に回路面積が増大してしまう。 Comparators including the calibration circuit CAL1 generally tend to be large in circuit size. Therefore, if the voltage monitoring circuit 15 of this embodiment is configured with two sets of a four-input terminal comparator 155, a resistive voltage divider circuit formed by resistors R3 and R4, and a resistive voltage divider circuit formed by resistors R5 and R6, the circuit area will be significantly larger than that of the voltage monitoring circuit 15 of the comparative example.
＜スイッチング電源装置（第２実施形態）＞
　図４は、スイッチング電源装置の第２実施形態を示す図である。本実施形態のスイッチング電源装置１は、先出の第１実施形態（図２）を基本としつつ、抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路をデジタルデータ生成回路１５６及びＤＡＣ１５７に置換した構成である。 <Switching power supply device (second embodiment)>
4 is a diagram showing a second embodiment of a switching power supply device. The switching power supply device 1 of this embodiment is based on the first embodiment (FIG. 2) described above, but has a configuration in which the resistive voltage divider circuit formed by resistors R5 and R6 is replaced with a digital data generation circuit 156 and a DAC 157.
　本実施形態の電圧監視回路１５は、帰還電圧ＶＦＢが過電圧であるか否かを監視することのみならず、帰還電圧ＶＦＢが低電圧であるか否かを監視することもできる。そして、本実施形態の電圧監視回路１５は、４入力端子コンパレータ１５５を二つ備える必要がないため、回路面積の増大を抑制することができる。 The voltage monitoring circuit 15 of this embodiment can monitor not only whether the feedback voltage VFB is an overvoltage, but also whether the feedback voltage VFB is a low voltage. Furthermore, since the voltage monitoring circuit 15 of this embodiment does not need to have two four-input terminal comparators 155, an increase in the circuit area can be suppressed.
　本実施形態の半導体集積回路装置１０は、クロック信号ＣＬＫを内部で発生させるか外部から受け取る。デジタルデータ生成回路１５６は、クロック信号ＣＬＫに基づき、第２電圧Ｖ２に対応するデジタルデータを過電圧用データと低電圧用データとに時分割で切り替える。ＤＡＣ１５７には、定電圧ＶＲＥＧ及びグラウンド電圧が印加される。ＤＡＣ１５７は、定電圧ＶＲＥＧ及びグラウンド電圧を基準として、デジタルデータ生成回路１５６から出力されるデジタルデータを、アナログ電圧である第２電圧Ｖ２に変換して出力する。したがって、図５に示すように、第２電圧Ｖ２は、クロック信号ＣＬＫに基づき、過電圧用の値（ＯＶＤ　ＶＡＬＵＥ）と低電圧用の値（ＵＶＤ　ＶＡＬＵＥ）とで時分割に切り替わる。これにより、４入力端子コンパレータ１５５は、過電圧検出信号ＯＶＤと低電圧検出信号ＵＶＤとを時分割で出力する。 The semiconductor integrated circuit device 10 of this embodiment generates a clock signal CLK internally or receives it from the outside. The digital data generation circuit 156 switches the digital data corresponding to the second voltage V2 between overvoltage data and low voltage data in a time-division manner based on the clock signal CLK. A constant voltage VREG and a ground voltage are applied to the DAC 157. The DAC 157 converts the digital data output from the digital data generation circuit 156 to the second voltage V2, which is an analog voltage, and outputs it based on the constant voltage VREG and the ground voltage. Therefore, as shown in FIG. 5, the second voltage V2 switches between an overvoltage value (OVD VALUE) and a low voltage value (UVD VALUE) in a time-division manner based on the clock signal CLK. As a result, the four-input terminal comparator 155 outputs an overvoltage detection signal OVD and a low voltage detection signal UVD in a time-division manner.
　なお、本実施形態の電圧監視回路１５は、第１実施形態の電圧監視回路１５に対して、抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路をデジタルデータ生成回路１５６及びＤＡＣ１５７に置換した構成であったが、抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路のみならず抵抗Ｒ３及びＲ４によって構成される抵抗分圧回路もデジタルデータ生成回路及びＤＡＣに置換した構成であってもよい。 In addition, in the voltage monitoring circuit 15 of the present embodiment, the resistive voltage divider circuit formed by resistors R5 and R6 is replaced with a digital data generation circuit 156 and a DAC 157, as compared to the voltage monitoring circuit 15 of the first embodiment. However, not only the resistive voltage divider circuit formed by resistors R5 and R6 but also the resistive voltage divider circuit formed by resistors R3 and R4 may be replaced with a digital data generation circuit and a DAC.
　第１実施形態の電圧監視回路１５では、抵抗Ｒ３及びＲ４によって構成される抵抗分圧回路の分圧比が固定され、抵抗Ｒ５及びＲ６によって構成される抵抗分圧回路の分圧比が固定されているが、２組の抵抗分圧回路の少なくとも一方を分圧比が可変する抵抗分圧回路に変更してもよい。このような変更を施した電圧監視回路１５も、４入力端子コンパレータ１５５を二つ備える必要がなく、帰還電圧ＶＦＢが過電圧であるか否かを監視することのみならず、帰還電圧ＶＦＢが低電圧であるか否かを監視することもできる。 In the voltage monitoring circuit 15 of the first embodiment, the voltage division ratio of the resistive voltage divider circuit formed by resistors R3 and R4 is fixed, and the voltage division ratio of the resistive voltage divider circuit formed by resistors R5 and R6 is fixed, but at least one of the two resistive voltage divider circuits may be changed to a resistive voltage divider circuit with a variable voltage division ratio. The voltage monitoring circuit 15 modified in this way also does not need to have two four-input terminal comparators 155, and can not only monitor whether the feedback voltage VFB is an overvoltage, but also monitor whether the feedback voltage VFB is an undervoltage.
　また、本実施形態の電圧監視回路１５において、抵抗Ｒ３及びＲ４によって構成される抵抗分圧回路を分圧比が可変する抵抗分圧回路に変更してもよい。 In addition, in the voltage monitoring circuit 15 of this embodiment, the resistive voltage divider circuit formed by resistors R3 and R4 may be changed to a resistive voltage divider circuit with a variable voltage division ratio.
＜適用例＞
　図６は、車両Ｘの外観図である。本構成例の車両Ｘは、不図示のバッテリから出力される電圧の供給を受けて動作する種々の電子機器Ｘ１１～Ｘ１８を搭載している。なお、本図における電子機器Ｘ１１～Ｘ１８の搭載位置は、図示の便宜上、実際とは異なる場合がある。 <Application Examples>
6 is an external view of a vehicle X. The vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving a voltage output from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for convenience of illustration.
　電子機器Ｘ１１は、エンジンに関連する制御（インジェクション制御、電子スロットル制御、アイドリング制御、酸素センサヒータ制御、及び、オートクルーズ制御など）を行うエンジンコントロールユニットである。 Electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).
　電子機器Ｘ１２は、ＨＩＤ［high　intensity　discharged　lamp］やＤＲＬ［daytime　running　lamp］などの点消灯制御を行うランプコントロールユニットである。 The electronic device X12 is a lamp control unit that controls the turning on and off of HID [high intensity discharged lamp] and DRL [daytime running lamp].
　電子機器Ｘ１３は、トランスミッションに関連する制御を行うトランスミッションコントロールユニットである。 Electronic device X13 is a transmission control unit that performs control related to the transmission.
　電子機器Ｘ１４は、車両Ｘの運動に関連する制御（ＡＢＳ［anti-lock　brake　system］制御、ＥＰＳ［electric　power　steering］制御、電子サスペンション制御など）を行う制動ユニットである。 The electronic device X14 is a braking unit that performs controls related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).
　電子機器Ｘ１５は、ドアロックや防犯アラームなどの駆動制御を行うセキュリティコントロールユニットである。 Electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, etc.
　電子機器Ｘ１６は、ワイパー、電動ドアミラー、パワーウィンドウ、ダンパー（ショックアブソーバー）、電動サンルーフ、及び、電動シートなど、標準装備品やメーカーオプション品として、工場出荷段階で車両Ｘに組み込まれている電子機器である。 Electronic device X16 is an electronic device that is installed in vehicle X at the time of shipment from the factory as standard equipment or manufacturer's option, such as wipers, power door mirrors, power windows, dampers (shock absorbers), power sunroof, and power seats.
　電子機器Ｘ１７は、車載Ａ／Ｖ［audio/visual］機器、カーナビゲーションシステム、及び、ＥＴＣ［electronic　toll　collection　system］など、ユーザオプション品として任意で車両Ｘに装着される電子機器である。 Electronic device X17 is an electronic device that is optionally installed in vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].
　電子機器Ｘ１８は、車載ブロア、オイルポンプ、ウォーターポンプ、バッテリ冷却ファンなど、高耐圧系モータを備えた電子機器である。 Electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.
　なお、先に説明したスイッチング電源装置１は、電子機器Ｘ１１～Ｘ１８のいずれにも組み込むことが可能である。したがって、車両Ｘは、先に説明した半導体集積回路装置１０を備える。また、先に説明したスイッチング電源装置１の用途としては、車両Ｘに搭載される電源に限定されず、例えば産業機器に搭載される電源であってもよい。 The switching power supply device 1 described above can be incorporated into any of the electronic devices X11 to X18. Therefore, the vehicle X is equipped with the semiconductor integrated circuit device 10 described above. Furthermore, the application of the switching power supply device 1 described above is not limited to a power supply mounted on the vehicle X, but may also be a power supply mounted on industrial equipment, for example.
＜比較例の電源装置Ｙ２０＞
　電源装置Ｙ２０の制御装置について、本開示の電源装置Ｘ２０との比較例として説明する。図７は、比較例の電源装置Ｙ２０の構成を示すブロック図である。図８は、比較例の電源装置Ｙ２０に係る第１インダクタ電流ＩＬ１、第２インダクタ電流ＩＬ２、第１スイッチ電圧Ｖｓｔ１、および第２スイッチ電圧Ｖｓｔ２を示すタイミングチャートである。 <Comparative example power supply device Y20>
The control device of the power supply device Y20 will be described as a comparative example with the power supply device X20 of the present disclosure. Fig. 7 is a block diagram showing the configuration of the power supply device Y20 of the comparative example. Fig. 8 is a timing chart showing the first inductor current IL1, the second inductor current IL2, the first switch voltage Vst1, and the second switch voltage Vst2 of the power supply device Y20 of the comparative example.
　比較例の電源装置Ｙ２０は、第１半導体装置３０１と、第２半導体装置３０２と、インダクタＬ２１と、インダクタＬ２２と、キャパシタＣ２１と、キャパシタＣ２２と、を有する。 The power supply device Y20 of the comparative example has a first semiconductor device 301, a second semiconductor device 302, an inductor L21, an inductor L22, a capacitor C21, and a capacitor C22.
　第１半導体装置３０１は、入力電圧Ｖｉの印加端、および接地端に接続されている。第１半導体装置３０１の出力端は、インダクタＬ２１の第１端に接続されている。インダクタＬ２１の第２端は、キャパシタＣ２１の第１端と、出力電圧Ｖｏの印加端とに共通に接続されている。キャパシタＣ２１の第２端は、接地端に接続されている。 The first semiconductor device 301 is connected to the application terminal of the input voltage Vi and the ground terminal. The output terminal of the first semiconductor device 301 is connected to the first terminal of the inductor L21. The second terminal of the inductor L21 is commonly connected to the first terminal of the capacitor C21 and the application terminal of the output voltage Vo. The second terminal of the capacitor C21 is connected to the ground terminal.
　第１半導体装置３０１と、インダクタＬ２１と、キャパシタＣ２１とは、入力電圧Ｖｉから第１スイッチ電圧Ｖｓｔ１を生成し、第１スイッチ電圧Ｖｓｔ１を整流及び平滑する降圧型の第１出力段を形成している。第１半導体装置３０１は、第１クロック信号（図示省略）に基づいて、インダクタＬ２１に流れる第１インダクタ電流ＩＬ１をスイッチング制御する。 The first semiconductor device 301, the inductor L21, and the capacitor C21 form a step-down first output stage that generates a first switch voltage Vst1 from the input voltage Vi and rectifies and smoothes the first switch voltage Vst1. The first semiconductor device 301 controls the switching of the first inductor current IL1 flowing through the inductor L21 based on a first clock signal (not shown).
　第２半導体装置３０２は、入力電圧Ｖｉの印加端、および接地端に接続されている。第２半導体装置３０２の出力端は、インダクタＬ２２の第１端に接続されている。インダクタＬ２２の第２端には、キャパシタＣ２２の第１端と出力電圧Ｖｏの印加端とが共通に接続されている。キャパシタＣ２２の第２端は、接地端に接続されている。 The second semiconductor device 302 is connected to the application terminal of the input voltage Vi and the ground terminal. The output terminal of the second semiconductor device 302 is connected to the first terminal of the inductor L22. The second terminal of the inductor L22 is commonly connected to the first terminal of the capacitor C22 and the application terminal of the output voltage Vo. The second terminal of the capacitor C22 is connected to the ground terminal.
　第２半導体装置３０２と、インダクタＬ２１と、キャパシタＣ２２とは、入力電圧Ｖｉから第２スイッチ電圧Ｖｓｔ２を生成し、第２スイッチ電圧Ｖｓｔ２を整流及び平滑する降圧型の第２出力段を形成している。第２半導体装置３０２は、第２クロック信号（図示省略）に基づいて、インダクタＬ２２に流れる第２インダクタ電流ＩＬ２をスイッチング制御する。 The second semiconductor device 302, the inductor L21, and the capacitor C22 form a step-down second output stage that generates a second switch voltage Vst2 from the input voltage Vi and rectifies and smoothes the second switch voltage Vst2. The second semiconductor device 302 controls the switching of the second inductor current IL2 flowing through the inductor L22 based on a second clock signal (not shown).
　出力電圧Ｖｏの出力端には負荷Ｚ２０が接続されている。負荷Ｚ２０には、出力電圧Ｖｏと負荷Ｚ２０の抵抗値に応じた出力電流Ｉｏが流れる。 A load Z20 is connected to the output terminal of the output voltage Vo. An output current Io flows through the load Z20 according to the output voltage Vo and the resistance value of the load Z20.
　図７に示すような電源装置Ｙ２０は、第１インダクタ電流ＩＬ１の平均値Ａ１と第２インダクタ電流ＩＬ２の平均値Ａ２とが略等しくなることが好ましい。 In the power supply device Y20 shown in FIG. 7, it is preferable that the average value A1 of the first inductor current IL1 and the average value A2 of the second inductor current IL2 are approximately equal.
　しかしながら、例えば第１半導体装置３０１、第２半導体装置３０２、インダクタＬ２１、Ｌ２２、キャパシタＣ２１、Ｃ２２の特性のばらつきによって、第１インダクタ電流ＩＬ１の値と第２インダクタ電流ＩＬ２の値とのバランスが崩れた状態となることがある。 However, for example, due to variations in the characteristics of the first semiconductor device 301, the second semiconductor device 302, the inductors L21 and L22, and the capacitors C21 and C22, the balance between the value of the first inductor current IL1 and the value of the second inductor current IL2 may be lost.
　具体的には、図８に示すように、第１インダクタ電流ＩＬ１の平均値Ａ１と第２インダクタ電流ＩＬ２の平均値Ａ２とが一致せず、第１インダクタ電流ＩＬ１と第２インダクタ電流ＩＬ２のバランスが崩れた状態となってしまう。 Specifically, as shown in FIG. 8, the average value A1 of the first inductor current IL1 and the average value A2 of the second inductor current IL2 do not match, resulting in an imbalance between the first inductor current IL1 and the second inductor current IL2.
　このようにバランスが崩れた状態になると、電源装置Ｙ２０の出力電流Ｉｏが偏った動作となり、電源装置Ｙ２０の効率低下につながるおそれがある。また、比較的大きくバランスを崩した場合には、保護回路によって、スイッチングレギュレータが動作不良の状態となる。 When this balance is lost, the output current Io of the power supply device Y20 becomes biased, which may lead to a decrease in the efficiency of the power supply device Y20. Furthermore, when the balance is lost to a relatively large extent, the protection circuit causes the switching regulator to malfunction.
　また、電源装置Ｙ２０では、第２半導体装置３０２は、第１半導体装置３０１からクロック信号と誤差信号とを享受し、これらに基づいて第２インダクタ電流ＩＬ２を駆動制御する構成も考えられる。誤差信号とは、出力電圧Ｖｏとその目標値との誤差に応じて生成される信号である（詳細は後述）。この場合、電源装置Ｙ２０は、出力電流Ｉｏをモニターし、第１半導体装置３０１および第２半導体装置３０２にフィードバックすることで、第１インダクタ電流ＩＬ１と第２インダクタ電流ＩＬ２とのバランスを取るように制御する構成を採用することも考えられる。 Furthermore, in the power supply device Y20, the second semiconductor device 302 may receive a clock signal and an error signal from the first semiconductor device 301, and may control the second inductor current IL2 based on these. The error signal is a signal generated according to the error between the output voltage Vo and its target value (details will be described later). In this case, the power supply device Y20 may adopt a configuration in which it monitors the output current Io and feeds it back to the first semiconductor device 301 and the second semiconductor device 302, thereby controlling the first inductor current IL1 and the second inductor current IL2 to achieve a balance.
　しかしながら、この場合、第１半導体装置３０１と第２半導体装置３０２との間で、第１クロック信号ＣＬ１、第１誤差信号Ｖｃ１、および出力電流Ｉｏに関する電流情報を伝送する必要がある。このため、それぞれに対応する伝送経路を第１半導体装置３０１と第２半導体装置３０２との間に複数接続する必要があり、第１半導体装置３０１および第２半導体装置３０２の端子を多く使用してしまう。 However, in this case, it is necessary to transmit the first clock signal CL1, the first error signal Vc1, and current information related to the output current Io between the first semiconductor device 301 and the second semiconductor device 302. For this reason, it is necessary to connect multiple transmission paths corresponding to each between the first semiconductor device 301 and the second semiconductor device 302, which uses many terminals of the first semiconductor device 301 and the second semiconductor device 302.
＜本開示の電源装置Ｘ２０＞
　次に、本開示の実施形態について説明する。図９は、本開示の電源装置Ｘ２０の実施形態の概略構成を示す図である。図１０は、本開示の電源装置Ｘ２０に係る第１スイッチ電圧Ｖｓｔ１、第２スイッチ電圧Ｖｓｔ２、第１インダクタ電流ＩＬ１、および第２インダクタ電流ＩＬ２を示すタイミングチャートである。 <Power supply device X20 of the present disclosure>
Next, an embodiment of the present disclosure will be described. Fig. 9 is a diagram showing a schematic configuration of an embodiment of the power supply device X20 of the present disclosure. Fig. 10 is a timing chart showing the first switch voltage Vst1, the second switch voltage Vst2, the first inductor current IL1, and the second inductor current IL2 of the power supply device X20 of the present disclosure.
　電源装置Ｘ２０は、入力電圧Ｖｉから所望の出力電圧Ｖｏを生成するように構成されたスイッチングレギュレータである。電源装置Ｘ２０の出力端には、負荷Ｚ２０が接続されている。電源装置Ｘ２０は、制御装置２５０と、インダクタＬ２１、Ｌ２２と、キャパシタＣ２１、Ｃ２２とを有する。制御装置２５０は、電源装置Ｘ２０の駆動制御を行う。 The power supply device X20 is a switching regulator configured to generate a desired output voltage Vo from an input voltage Vi. A load Z20 is connected to the output terminal of the power supply device X20. The power supply device X20 has a control device 250, inductors L21 and L22, and capacitors C21 and C22. The control device 250 controls the drive of the power supply device X20.
　制御装置２５０は、第１半導体装置２０１と、第２半導体装置２０２を有する。インダクタＬ２１、Ｌ２２、およびキャパシタＣ２１、Ｃ２２は、制御装置２５０に外付けされたディスクリート部品である。 The control device 250 has a first semiconductor device 201 and a second semiconductor device 202. Inductors L21 and L22 and capacitors C21 and C22 are discrete components external to the control device 250.
　第１半導体装置２０１は、入力電圧Ｖｉの印加端、および接地端に接続されている。第１半導体装置２０１の出力端は、インダクタＬ２１の第１端に接続されている。キャパシタＣ２１の第１端は、インダクタＬ２１の第２端と、第１半導体装置２０１の印加端と、出力電圧Ｖｏの印加端とに共通に接続されている。キャパシタＣ２１の第２端は、接地端に接続されている。 The first semiconductor device 201 is connected to the application terminal of the input voltage Vi and the ground terminal. The output terminal of the first semiconductor device 201 is connected to the first terminal of the inductor L21. The first terminal of the capacitor C21 is commonly connected to the second terminal of the inductor L21, the application terminal of the first semiconductor device 201, and the application terminal of the output voltage Vo. The second terminal of the capacitor C21 is connected to the ground terminal.
　第１半導体装置２０１は、第１クロック信号ＣＬ１、および第１誤差信号Ｖｃ１を内部で生成するように構成されている。第１誤差信号Ｖｃ１は、出力電圧Ｖｏとその目標値との誤差に応じて生成される。 The first semiconductor device 201 is configured to internally generate a first clock signal CL1 and a first error signal Vc1. The first error signal Vc1 is generated according to the error between the output voltage Vo and its target value.
　第１半導体装置２０１は、第１クロック信号ＣＬ１、および第１誤差信号Ｖｃ１に基づいて第１スイッチ電圧Ｖｓｔ１をパルス駆動することにより、第１インダクタ電流ＩＬ１をスイッチング制御する。このように、第１半導体装置２０１は、入力電圧Ｖｉから第１スイッチ電圧Ｖｓｔ１を生成する降圧型の第１出力段を形成している。なお、第１出力段のDutyは、第１誤差信号Ｖｃ１に応じて決定される。 The first semiconductor device 201 performs switching control of the first inductor current IL1 by pulse driving the first switch voltage Vst1 based on the first clock signal CL1 and the first error signal Vc1. In this way, the first semiconductor device 201 forms a step-down first output stage that generates the first switch voltage Vst1 from the input voltage Vi. The duty of the first output stage is determined according to the first error signal Vc1.
　第２半導体装置２０２は、入力電圧Ｖｉの印加端、および接地端に接続されている。第２半導体装置２０２の出力端は、インダクタＬ２２の第１端に接続されている。キャパシタＣ２２の第１端は、インダクタＬ２２の第２端と、第２半導体装置２０２の印加端と、出力電圧Ｖｏの印加端とに共通に接続されている。キャパシタＣ２２の第２端は、接地端に接続されている。 The second semiconductor device 202 is connected to the application terminal of the input voltage Vi and the ground terminal. The output terminal of the second semiconductor device 202 is connected to the first terminal of the inductor L22. The first terminal of the capacitor C22 is commonly connected to the second terminal of the inductor L22, the application terminal of the second semiconductor device 202, and the application terminal of the output voltage Vo. The second terminal of the capacitor C22 is connected to the ground terminal.
　第１半導体装置２０１と第２半導体装置２０２とは、伝送経路２２８によって互いに接続されている。伝送経路２２８の第１端は第１半導体装置２０１の１つの印加端に接続されている。伝送経路２２８の第２端は第２半導体装置２０２の１つの印加端に接続されている。 The first semiconductor device 201 and the second semiconductor device 202 are connected to each other by a transmission path 228. A first end of the transmission path 228 is connected to one application terminal of the first semiconductor device 201. A second end of the transmission path 228 is connected to one application terminal of the second semiconductor device 202.
　第１半導体装置２０１は、第２半導体装置２０２へ伝送信号Ｖｔと、第１誤差信号Ｖｃ１を送信する。伝送信号Ｖｔは、第１出力段のDuty情報（＝第１出力段のDutyに関する情報）と第１クロック信号ＣＬ１のクロック情報（＝第１出力段のスイッチング周波数に関する情報）を含んでいる。 The first semiconductor device 201 transmits a transmission signal Vt and a first error signal Vc1 to the second semiconductor device 202. The transmission signal Vt includes duty information of the first output stage (=information related to the duty of the first output stage) and clock information of the first clock signal CL1 (=information related to the switching frequency of the first output stage).
　第２半導体装置２０２は、内部で、第１クロック信号ＣＬ１の周波数情報を含む伝送信号Ｖｔに基づいて第２クロック信号ＣＬ２を生成する。また、第２半導体装置２０２は、内部で、第１出力段のDuty情報を含む伝送信号Ｖｔに基づいて第１誤差信号Ｖｃ１を補正することにより第２誤差信号Ｖｃ２を生成する。第２半導体装置２０２は、第２クロック信号ＣＬ２、および第２誤差信号Ｖｃ２に基づいて第２スイッチ電圧Ｖｓｔ２をパルス駆動することにより、第２インダクタ電流ＩＬ２をスイッチング制御する。このように、第２半導体装置２０２は、入力電圧Ｖｉから第２スイッチ電圧をＶｓｔ２生成する降圧型の第２出力段を形成している。 The second semiconductor device 202 internally generates a second clock signal CL2 based on a transmission signal Vt that includes frequency information of the first clock signal CL1. The second semiconductor device 202 also internally generates a second error signal Vc2 by correcting the first error signal Vc1 based on the transmission signal Vt that includes duty information of the first output stage. The second semiconductor device 202 pulse-drives the second switch voltage Vst2 based on the second clock signal CL2 and the second error signal Vc2, thereby controlling the switching of the second inductor current IL2. In this way, the second semiconductor device 202 forms a step-down second output stage that generates the second switch voltage Vst2 from the input voltage Vi.
　第１半導体装置２０１から第２半導体装置２０２に伝送信号Ｖｔが伝送されることで、第２半導体装置２０２は、第１出力段のDuty情報および第１クロック信号ＣＬ１のクロック情報を得ることができる。このため、第２半導体装置２０２が、第１出力段のDuty情報および第１クロック信号ＣＬ１のクロック情報に基づいて第２インダクタ電流ＩＬ２のスイッチング制御することができる。 By transmitting the transmission signal Vt from the first semiconductor device 201 to the second semiconductor device 202, the second semiconductor device 202 can obtain duty information of the first output stage and clock information of the first clock signal CL1. Therefore, the second semiconductor device 202 can control the switching of the second inductor current IL2 based on the duty information of the first output stage and the clock information of the first clock signal CL1.
　これにより、図１０に示すように、駆動開始当初は第１インダクタ電流ＩＬ１と第２インダクタ電流ＩＬ２とのバランスが崩れていたとしても、第１半導体装置２０１から第２半導体装置２０２に供給される伝送信号Ｖｔに基づいて第２インダクタ電流ＩＬ２の駆動制御を補正することで、第１インダクタ電流ＩＬ１と第２インダクタ電流ＩＬ２とのバランスが徐々に整うものとなる。従って、第１インダクタ電流ＩＬ１と第２インダクタ電流ＩＬ２とのバランスが崩れるのを抑制できる。 As a result, as shown in FIG. 10, even if the balance between the first inductor current IL1 and the second inductor current IL2 is lost at the beginning of driving, the balance between the first inductor current IL1 and the second inductor current IL2 is gradually restored by correcting the drive control of the second inductor current IL2 based on the transmission signal Vt supplied from the first semiconductor device 201 to the second semiconductor device 202. Therefore, it is possible to prevent the balance between the first inductor current IL1 and the second inductor current IL2 from being lost.
　また、上述した通り、伝送経路２２８の第１端は第１半導体装置２０１の１つの印加端に接続され、伝送経路２２８の第２端は第２半導体装置２０２の１つの印加端に接続されている。このため、伝送信号Ｖｔに含まれる第１クロック信号ＣＬ１のクロック情報と第１出力段のDuty情報とを別々の経路で第１半導体装置２０１から第２半導体装置２０２へ伝送する場合に比べて、第１半導体装置２０１および第２半導体装置２０２の端子の使用数を削減することができる。 As described above, the first end of the transmission path 228 is connected to one application end of the first semiconductor device 201, and the second end of the transmission path 228 is connected to one application end of the second semiconductor device 202. Therefore, the number of terminals used in the first semiconductor device 201 and the second semiconductor device 202 can be reduced compared to the case where the clock information of the first clock signal CL1 contained in the transmission signal Vt and the duty information of the first output stage are transmitted from the first semiconductor device 201 to the second semiconductor device 202 via separate paths.
　本開示の電源装置Ｘ２０の構成について、さらに詳細に説明する。図１１は、電源装置Ｘ２０の構成を示すブロック図である。 The configuration of the power supply device X20 of the present disclosure will now be described in further detail. Figure 11 is a block diagram showing the configuration of the power supply device X20.
　なお、本図の第１半導体装置２０１と第２半導体装置２０２は、同一の機種であり、全く同様の機能ブロックを備えている。ただし、第１半導体装置２０１と第２半導体装置２０２は、それぞれの主従関係に応じていくつかの機能ブロックの有効／無効が切り替えられる。以下では、第１半導体装置２０１がマスタ（＝誤差信号及び伝送信号を送る側）となり、第２半導体装置２０２がスレーブ（＝誤差信号及び伝送信号を受ける側）となる場合について説明する。 Note that the first semiconductor device 201 and the second semiconductor device 202 in this diagram are the same model and have exactly the same functional blocks. However, the first semiconductor device 201 and the second semiconductor device 202 have some functional blocks that can be enabled or disabled depending on their respective master-slave relationships. Below, we will explain the case where the first semiconductor device 201 is the master (= the side that sends the error signal and transmission signal) and the second semiconductor device 202 is the slave (= the side that receives the error signal and transmission signal).
　図１１に示すように、第１半導体装置２０１は、第１スイッチ出力段２０３と、第１制御回路２０４と、を１つのパッケージ内に集積化したモノリシック半導体集積回路装置（いわゆるマルチフェイズ型スイッチングレギュレータＩＣ）である。 As shown in FIG. 11, the first semiconductor device 201 is a monolithic semiconductor integrated circuit device (a so-called multi-phase switching regulator IC) in which a first switch output stage 203 and a first control circuit 204 are integrated into a single package.
　第１スイッチ出力段２０３は、ハイサイドトランジスタおよびロ―サイドトランジスタ（図示省略）と、第１ドライバと（図示省略）と、を含んで構成される。ハイサイドトランジスタおよびロ―サイドトランジスタは、ハーフブリッジを形成するように互いに接続されたＭＯＳＦＥＴである。第１ドライバは、ハイサイドトランジスタおよびロ―サイドトランジスタを駆動制御する。第１スイッチ出力段２０３は、ハイサイドトランジスタおよびロ―サイドトランジスタをオン／オフすることにより第１インダクタ電流ＩＬ１を駆動する。 The first switch output stage 203 includes a high-side transistor and a low-side transistor (not shown) and a first driver (not shown). The high-side transistor and the low-side transistor are MOSFETs connected to each other to form a half bridge. The first driver drives and controls the high-side transistor and the low-side transistor. The first switch output stage 203 drives the first inductor current IL1 by turning the high-side transistor and the low-side transistor on and off.
　第１制御回路２０４は、誤差増幅回路２０５と、スイッチ制御回路２０６と、を含んで構成されている。誤差増幅回路２０５は、出力電圧Ｖｏとその目標値との誤差に応じた第１誤差信号Ｖｃ１を生成するように構成されている。 The first control circuit 204 includes an error amplifier circuit 205 and a switch control circuit 206. The error amplifier circuit 205 is configured to generate a first error signal Vc1 that corresponds to the error between the output voltage Vo and its target value.
　誤差増幅回路２０５は、抵抗Ｒ２１、Ｒ２２と、電圧源Ｅ３と、誤差増幅アンプ２０７と、を含んで構成されている。抵抗Ｒ２１の第１端は、負荷Ｚ２０の第１端に接続されている。抵抗Ｒ２１の第２端は、抵抗Ｒ２２の第１端と共に誤差増幅アンプ２０７の非反転入力端子に接続されている。抵抗Ｒ２２の第２端は、接地端に接続されている。 The error amplifier circuit 205 includes resistors R21 and R22, a voltage source E3, and an error amplifier 207. A first end of the resistor R21 is connected to a first end of the load Z20. A second end of the resistor R21, together with a first end of the resistor R22, is connected to the non-inverting input terminal of the error amplifier 207. A second end of the resistor R22 is connected to the ground terminal.
　電圧源Ｅ３の第１端は、誤差増幅アンプ２０７の反転入力端子に接続されている。電圧源Ｅ３の第２端は、接地端に接続されている。誤差増幅アンプ２０７の出力端は、スイッチ制御回路２０６の入力端（後述する第１コンパレータ２１２の非反転入力端子）に接続されている。 The first terminal of the voltage source E3 is connected to the inverting input terminal of the error amplifier 207. The second terminal of the voltage source E3 is connected to the ground terminal. The output terminal of the error amplifier 207 is connected to the input terminal of the switch control circuit 206 (the non-inverting input terminal of the first comparator 212 described later).
　なお、第２半導体装置２０２の整合回路２１７に相当する機能ブロックは、図中の破線で示すように無効化されている。従って、第１誤差信号Ｖｃ１は、第１コンパレータ２１２の非反転入力端子にそのまま入力される。 Note that the functional block corresponding to the matching circuit 217 of the second semiconductor device 202 is disabled as shown by the dashed line in the figure. Therefore, the first error signal Vc1 is input directly to the non-inverting input terminal of the first comparator 212.
　スイッチ制御回路２０６は、第１クロック信号ＣＬ１と第１比較信号Ｖａ１を生成して第１スイッチ出力段２０３に出力する。第１クロック信号ＣＬ１は、第１スイッチ出力段２０３のスイッチング周波数（以下「第１スイッチング周波数」と称する）を規定する信号である。上述したクロック情報は、第１クロック信号ＣＬ１の立上がり又は立下りのタイミング情報である。 The switch control circuit 206 generates a first clock signal CL1 and a first comparison signal Va1 and outputs them to the first switch output stage 203. The first clock signal CL1 is a signal that defines the switching frequency of the first switch output stage 203 (hereinafter referred to as the "first switching frequency"). The above-mentioned clock information is timing information of the rising or falling edge of the first clock signal CL1.
　スイッチ制御回路２０６は、第１オシレータ２０８と、第１ＰＬＬ［Phase　Locked　Loop］２０９と、第１セレクタ２１０と、第１ランプ信号生成部２１１と、第１コンパレータ２１２と、加算部２１３と、を含んで構成されている。 The switch control circuit 206 includes a first oscillator 208, a first PLL [Phase Locked Loop] 209, a first selector 210, a first ramp signal generating unit 211, a first comparator 212, and an adder 213.
　第１オシレータ２０８および第１ＰＬＬ２０９は、共に第１セレクタ２１０の入力端に接続されている。なお、本図では、第１半導体装置２０１がマスタとなる。この場合、第１オシレータ２０８は、第１セレクタ２１０を介して第１スイッチ出力段２０３及び第１ランプ信号生成部２１１の入力端に電気的に接続している。第１ＰＬＬ２０９は、第１セレクタ２１０によって電気的に遮断されており、機能しない状態となっている。第１オシレータ２０８は、第１クロック信号ＣＬ１を生成して第１ランプ信号生成部２１１に入力する。 The first oscillator 208 and the first PLL 209 are both connected to the input terminal of the first selector 210. In this diagram, the first semiconductor device 201 is the master. In this case, the first oscillator 208 is electrically connected to the first switch output stage 203 and the input terminal of the first ramp signal generating unit 211 via the first selector 210. The first PLL 209 is electrically cut off by the first selector 210 and is in a non-functional state. The first oscillator 208 generates a first clock signal CL1 and inputs it to the first ramp signal generating unit 211.
　第１ランプ信号生成部２１１の出力端は、第１スイッチ出力段２０３の第１差動ライン２１４と共に加算部２１３の入力端に接続されている。第１ランプ信号生成部２１１は、第１クロック信号ＣＬ１に応じて鋸波形の第１ランプ信号Ｖｒ１を生成する。第１差動ライン２１４は、第１スイッチ出力段２０３の生成した第１差動信号Ｖｄ１（＝第１インダクタ電流ＩＬ１に応じた電流帰還信号）を加算部２１３に伝達する。 The output terminal of the first ramp signal generating unit 211 is connected to the input terminal of the adder unit 213 together with the first differential line 214 of the first switch output stage 203. The first ramp signal generating unit 211 generates a first ramp signal Vr1 having a sawtooth waveform in response to the first clock signal CL1. The first differential line 214 transmits the first differential signal Vd1 (= a current feedback signal corresponding to the first inductor current IL1) generated by the first switch output stage 203 to the adder unit 213.
　加算部２１３の出力端は、第１コンパレータ２１２の反転入力端子に接続されている。加算部２１３は、第１ランプ信号Ｖｒ１と第１差動信号Ｖｄ１とを加算して、第１基準信号Ｖｓ１を生成する。 The output terminal of the adder 213 is connected to the inverting input terminal of the first comparator 212. The adder 213 adds the first ramp signal Vr1 and the first differential signal Vd1 to generate the first reference signal Vs1.
　第１コンパレータ２１２の出力端は、第１スイッチ出力段２０３の入力端（図示省略）に接続されている。第１コンパレータ２１２は、第１誤差信号Ｖｃ１と第１基準信号Ｖｓ１とを比較して、第１比較信号Ｖａ１を生成する。具体的には、第１比較信号Ｖａ１は、第１基準信号Ｖｓ１が第１誤差信号Ｖｃ１よりも低いときにハイレベルとなり、逆に、第１基準信号Ｖｓ１が第１誤差信号Ｖｃ１よりも高いときにローレベルとなる。 The output terminal of the first comparator 212 is connected to the input terminal (not shown) of the first switch output stage 203. The first comparator 212 compares the first error signal Vc1 with the first reference signal Vs1 to generate a first comparison signal Va1. Specifically, the first comparison signal Va1 is at a high level when the first reference signal Vs1 is lower than the first error signal Vc1, and conversely, is at a low level when the first reference signal Vs1 is higher than the first error signal Vc1.
　第１制御回路２０４は、第１クロック信号ＣＬ１および第１比較信号Ｖａ１に基づいて第１スイッチ出力段２０３を駆動制御する。 The first control circuit 204 drives and controls the first switch output stage 203 based on the first clock signal CL1 and the first comparison signal Va1.
　図１１に示すように、第２半導体装置２０２は、第２スイッチ出力段２１５と、第２制御回路２１６とを１つのパッケージ内に集積化したモノリシック半導体集積回路装置（いわゆるマルチフェイズ型スイッチングレギュレータＩＣ）である。第２半導体装置２０２は、第１半導体装置２０１とは別のパッケージとして形成されている。 As shown in FIG. 11, the second semiconductor device 202 is a monolithic semiconductor integrated circuit device (a so-called multi-phase switching regulator IC) in which the second switch output stage 215 and the second control circuit 216 are integrated into a single package. The second semiconductor device 202 is formed as a package separate from the first semiconductor device 201.
　第２スイッチ出力段２１５は、ハイサイドトランジスタおよびロ―サイドトランジスタ（図示省略）と、第２ドライバと（図示省略）と、を含んで構成される。ハイサイドトランジスタおよびロ―サイドトランジスタは、ハーフブリッジを形成するように互いに接続されたＭＯＳＦＥＴである。第２ドライバは、ハイサイドトランジスタおよびロ―サイドトランジスタを駆動制御する。第２スイッチ出力段２１５は、ハイサイドトランジスタおよびロ―サイドトランジスタをオン／オフすることにより第２インダクタ電流ＩＬ２を駆動する。 The second switch output stage 215 includes a high-side transistor and a low-side transistor (not shown) and a second driver (not shown). The high-side transistor and the low-side transistor are MOSFETs connected to each other to form a half bridge. The second driver drives and controls the high-side transistor and the low-side transistor. The second switch output stage 215 drives the second inductor current IL2 by turning the high-side transistor and the low-side transistor on and off.
　第２制御回路２１６は、第２スイッチ出力段２１５を駆動制御するように構成されている。第２制御回路２１６は、整合回路２１７と、位相同期回路２１８と、第２ランプ信号生成部２１９と、第２コンパレータ２３０と、を含んで構成されている。 The second control circuit 216 is configured to drive and control the second switch output stage 215. The second control circuit 216 includes a matching circuit 217, a phase synchronization circuit 218, a second ramp signal generating unit 219, and a second comparator 230.
　整合回路２１７は、第１誤差信号Ｖｃ１および伝送信号Ｖｔ（＝本図では第１スイッチ電圧Ｖｓｔ１）に基づいて第２誤差信号Ｖｃ２を生成するように構成されている。具体的には、整合回路２１７は、第１ローパスフィルタ２２０と、第２ローパスフィルタ２２１と、補正コンパレータ２２２と、整合部２２３とを含んで構成されている。 The matching circuit 217 is configured to generate a second error signal Vc2 based on the first error signal Vc1 and the transmission signal Vt (= the first switch voltage Vst1 in this figure). Specifically, the matching circuit 217 includes a first low-pass filter 220, a second low-pass filter 221, a correction comparator 222, and a matching unit 223.
　第１ローパスフィルタ２２０の第１端は、インダクタＬ２１の第１端に接続されている。第１ローパスフィルタ２２０の第２端は、補正コンパレータ２２２の非反転入力端子に接続されている。第１ローパスフィルタ２２０は、第１スイッチ電圧Ｖｓｔ１を平滑化（平均化）して第１平均電圧Ｖａｖｅ１を生成し、補正コンパレータ２２２に送信する。 A first end of the first low-pass filter 220 is connected to a first end of the inductor L21. A second end of the first low-pass filter 220 is connected to a non-inverting input terminal of the correction comparator 222. The first low-pass filter 220 smoothes (averages) the first switch voltage Vst1 to generate a first average voltage Vave1 and transmits it to the correction comparator 222.
　第２ローパスフィルタ２２１の第１端は、インダクタＬ２２の第１端に接続されている。第２ローパスフィルタ２２１の第２端は、補正コンパレータ２２２の反転入力端子に接続されている。第２ローパスフィルタ２２１は、第２スイッチ電圧Ｖｓｔ２を平滑化（平均化）して第２平均電圧Ｖａｖｅ２を生成し、補正コンパレータ２２２に送信する。 The first end of the second low-pass filter 221 is connected to the first end of the inductor L22. The second end of the second low-pass filter 221 is connected to the inverting input terminal of the correction comparator 222. The second low-pass filter 221 smoothes (averages) the second switch voltage Vst2 to generate a second average voltage Vave2 and transmits it to the correction comparator 222.
　補正コンパレータ２２２の出力端子は、整合部２２３に接続されている。補正コンパレータ２２２は、第１平均電圧Ｖａｖｅ１と第２平均電圧Ｖａｖｅ２とを比較して補正信号Ｖｃｒを生成し、補正信号Ｖｃｒを整合部２２３に送信する。 The output terminal of the correction comparator 222 is connected to the matching unit 223. The correction comparator 222 compares the first average voltage Vave1 with the second average voltage Vave2 to generate a correction signal Vcr, and transmits the correction signal Vcr to the matching unit 223.
　整合部２２３の出力端は、第２コンパレータ２３０の非反転入力端子に接続されている。整合部２２３の第１入力端は、補正コンパレータ２２２の出力端に接続されている。整合部２２３の第２入力端は、誤差増幅アンプ２０７の出力端に接続されている。整合部２２３は、誤差増幅アンプ２０７の出力する第１誤差信号Ｖｃ１を補正コンパレータ２２２の出力する補正信号Ｖｃｒに基づいて補正して、第２誤差信号Ｖｃ２を生成する。第２誤差信号Ｖｃ２は、第２コンパレータ２３０の非反転入力端子に入力される。なお、第１半導体装置２０１の誤差増幅回路２０５に相当する機能ブロックは、図中の破線で示すように無効化されている。 The output terminal of the matching unit 223 is connected to the non-inverting input terminal of the second comparator 230. The first input terminal of the matching unit 223 is connected to the output terminal of the correction comparator 222. The second input terminal of the matching unit 223 is connected to the output terminal of the error amplifier 207. The matching unit 223 corrects the first error signal Vc1 output from the error amplifier 207 based on the correction signal Vcr output from the correction comparator 222 to generate a second error signal Vc2. The second error signal Vc2 is input to the non-inverting input terminal of the second comparator 230. Note that the functional block corresponding to the error amplifier circuit 205 of the first semiconductor device 201 is disabled as indicated by the dashed line in the figure.
　位相同期回路２１８は、伝送信号Ｖｔに基づいて第２クロック信号ＣＬ２を生成するように構成されている。第２クロック信号ＣＬ２は、第２スイッチ出力段２１５のスイッチング周波数（以下、「第２スイッチング周波数」と称する）を規定する信号である。 The phase-locked loop 218 is configured to generate a second clock signal CL2 based on the transmission signal Vt. The second clock signal CL2 is a signal that defines the switching frequency of the second switch output stage 215 (hereinafter referred to as the "second switching frequency").
　位相同期回路２１８は、第２オシレータ２２４と、第２ＰＬＬ２２５と、第２セレクタ２２６と、を含んで構成されている。 The phase synchronization circuit 218 includes a second oscillator 224, a second PLL 225, and a second selector 226.
　第２オシレータ２２４および第２ＰＬＬ２２５は、第２セレクタ２２６に接続されている。第２セレクタ２２６の出力端は、第２スイッチ出力段２１５と共に、第２ランプ信号生成部２１９に接続されている。なお、本図では、第２半導体装置２０２がスレーブとなる。この場合、第２セレクタ２２６は、内部で第２オシレータ２２４との接続を遮断する。第２ＰＬＬ２２５の出力端は、第２セレクタ２２６を介して第２スイッチ出力段２１５及び第２ランプ信号生成部２１９に電気的に接続されている。 The second oscillator 224 and the second PLL 225 are connected to the second selector 226. The output terminal of the second selector 226 is connected to the second ramp signal generating unit 219 together with the second switch output stage 215. In this figure, the second semiconductor device 202 is the slave. In this case, the second selector 226 internally cuts off the connection to the second oscillator 224. The output terminal of the second PLL 225 is electrically connected to the second switch output stage 215 and the second ramp signal generating unit 219 via the second selector 226.
　第２ＰＬＬ２２５の入力端は、伝送経路２２８を介して、インダクタＬ２１の第１端に接続されている。すなわち、第２ＰＬＬ２２５は、第１クロック信号ＣＬ１のクロック情報を含む第１スイッチ電圧Ｖｓｔ１に基づいて第２クロック信号ＣＬ２を生成し、第２クロック信号ＣＬ２を第２スイッチ出力段２１５及び第２ランプ信号生成部２１９に入力する。第２ＰＬＬ２２５は、機能的に見ると、第１クロック信号ＣＬ１をフェイズシフトさせて、高周波に変換することで第２クロック信号ＣＬ２を生成する。 The input end of the second PLL 225 is connected to the first end of the inductor L21 via the transmission path 228. That is, the second PLL 225 generates the second clock signal CL2 based on the first switch voltage Vst1 including the clock information of the first clock signal CL1, and inputs the second clock signal CL2 to the second switch output stage 215 and the second ramp signal generating unit 219. From a functional perspective, the second PLL 225 generates the second clock signal CL2 by phase-shifting the first clock signal CL1 and converting it to a high frequency.
　第２ランプ信号生成部２１９の出力端は、第２スイッチ出力段２１５の第２差動ライン２２９と共に加算部２２７の入力端に接続されている。第２ランプ信号生成部２１９は、第２クロック信号ＣＬ２に応じて鋸波形の第２ランプ信号Ｖｒ２を生成する。第２差動ライン２２９は、第２スイッチ出力段２１５の生成した第２差動信号Ｖｄ２（＝第２インダクタ電流ＩＬ２に応じた電流帰還信号）を加算部２２７に伝達する。 The output terminal of the second ramp signal generating unit 219 is connected to the input terminal of the adder unit 227 together with the second differential line 229 of the second switch output stage 215. The second ramp signal generating unit 219 generates a second ramp signal Vr2 having a sawtooth waveform in response to the second clock signal CL2. The second differential line 229 transmits the second differential signal Vd2 (= a current feedback signal corresponding to the second inductor current IL2) generated by the second switch output stage 215 to the adder unit 227.
　加算部２２７の出力端は、第２コンパレータ２３０の反転入力端子に接続されている。加算部２２７は、第２ランプ信号Ｖｒ２と第２差動信号Ｖｄ２とを加算して、第２基準信号Ｖｓ２を生成する。 The output terminal of the adder 227 is connected to the inverting input terminal of the second comparator 230. The adder 227 adds the second ramp signal Vr2 and the second differential signal Vd2 to generate the second reference signal Vs2.
　第２コンパレータ２３０の出力端は、第２スイッチ出力段２１５の入力端（図示省略）に接続されている。第２コンパレータ２３０は、第２誤差信号Ｖｃ２と第２基準信号Ｖｓ２とを比較して、第２比較信号Ｖａ２を生成する。第２スイッチ出力段２１５は、第２クロック信号ＣＬ２及び第２比較信号Ｖａ２に基づいて駆動する。 The output terminal of the second comparator 230 is connected to the input terminal (not shown) of the second switch output stage 215. The second comparator 230 compares the second error signal Vc2 with the second reference signal Vs2 to generate a second comparison signal Va2. The second switch output stage 215 is driven based on the second clock signal CL2 and the second comparison signal Va2.
　第２制御回路２１６は、第２クロック信号ＣＬ２および第２比較信号Ｖａ２に基づいて第２スイッチ出力段２１５を駆動制御する。 The second control circuit 216 drives and controls the second switch output stage 215 based on the second clock signal CL2 and the second comparison signal Va2.
　図１２は、第１ランプ信号Ｖｒ１、第２ランプ信号Ｖｒ２、第１誤差信号Ｖｃ１、第２誤差信号Ｖｃ２、第１スイッチ電圧Ｖｓｔ１、第２スイッチ電圧Ｖｓｔ２、第１インダクタ電流ＩＬ１、および第２インダクタ電流ＩＬ２を示すタイミングチャートである。 FIG. 12 is a timing chart showing the first ramp signal Vr1, the second ramp signal Vr2, the first error signal Vc1, the second error signal Vc2, the first switch voltage Vst1, the second switch voltage Vst2, the first inductor current IL1, and the second inductor current IL2.
　図１２に示すように、第１スイッチ電圧Ｖｓｔ１がハイレベルに立ち上げられると、第１インダクタ電流ＩＬ１が徐々に大きくなる。これに伴い、第１ランプ信号Ｖｒ１が上昇し始める。第１ランプ信号Ｖｒ１が第１誤差信号Ｖｃ１を上回ると、第１スイッチ電圧Ｖｓｔ１がローレベルに立ち下げられる。すると第１インダクタ電流ＩＬ１が徐々に小さくなる。 As shown in FIG. 12, when the first switch voltage Vst1 is raised to a high level, the first inductor current IL1 gradually increases. In response to this, the first ramp signal Vr1 begins to rise. When the first ramp signal Vr1 exceeds the first error signal Vc1, the first switch voltage Vst1 is lowered to a low level. Then, the first inductor current IL1 gradually decreases.
　同様に、第２スイッチ電圧Ｖｓｔ２がハイレベルに立ち上げられると、第２インダクタ電流ＩＬ２が徐々に大きくなる。これに伴い、第２ランプ信号Ｖｒ２が上昇し始める。第２ランプ信号Ｖｒ２が第２誤差信号Ｖｃ２を上回ると、第２スイッチ電圧Ｖｓｔ２がローレベルに立ち下げられる。すると第２インダクタ電流ＩＬ２が徐々に小さくなる。 Similarly, when the second switch voltage Vst2 is raised to a high level, the second inductor current IL2 gradually increases. In response to this, the second ramp signal Vr2 begins to rise. When the second ramp signal Vr2 exceeds the second error signal Vc2, the second switch voltage Vst2 is lowered to a low level. Then, the second inductor current IL2 gradually decreases.
　図１２に示すように、第２誤差信号Ｖｃ２は、第１誤差信号Ｖｃ１よりも第２オフセット信号Ｓ２分大きくなっている。これにより、第２スイッチ電圧Ｖｓｔ２のオン時間のDuty比が大きくなり、第２インダクタ電流ＩＬ２の最大値が大きくなる。 As shown in FIG. 12, the second error signal Vc2 is larger than the first error signal Vc1 by the second offset signal S2. This increases the duty ratio of the on-time of the second switch voltage Vst2, and increases the maximum value of the second inductor current IL2.
　比較例の電源装置Ｙ２０では、仮に、第１誤差信号Ｖｃ１と第２誤差信号Ｖｃ２とが同一の場合に、デバイスの製造ばらつき等に起因して、第２スイッチ電圧Ｖｓｔ２のオン時間のDuty比が第１スイッチ電圧Ｖｓｔ１のオン時間のDuty比よりも小さくなる場合があり得る。この場合、第２インダクタ電流ＩＬ２の平均値Ａ２は、第１インダクタ電流ＩＬ１の平均値Ａ１よりも電流値が小さなものとなる。 In the power supply device Y20 of the comparative example, if the first error signal Vc1 and the second error signal Vc2 are the same, the duty ratio of the on-time of the second switch voltage Vst2 may be smaller than the duty ratio of the on-time of the first switch voltage Vst1 due to manufacturing variations in the device, etc. In this case, the average value A2 of the second inductor current IL2 is smaller than the average value A1 of the first inductor current IL1.
　対して、本開示の電源装置Ｘ２０では、上記の場合であっても、第２誤差信号Ｖｃ２が第１誤差信号Ｖｃ１よりも大きくなり、第２インダクタ電流ＩＬ２が大きくなる。このため、図１２に示すように、第２インダクタ電流ＩＬ２の平均値Ａ２は、第１インダクタ電流ＩＬ１の平均値Ａ１と略等しいものとなる。従って、第１インダクタ電流ＩＬ１と第２インダクタ電流ＩＬ２の電流バランスが取れ、電源装置Ｘ２０の効率の低下を抑制できる。 In contrast, in the power supply device X20 of the present disclosure, even in the above case, the second error signal Vc2 becomes larger than the first error signal Vc1, and the second inductor current IL2 becomes larger. Therefore, as shown in FIG. 12, the average value A2 of the second inductor current IL2 becomes approximately equal to the average value A1 of the first inductor current IL1. Therefore, a current balance is achieved between the first inductor current IL1 and the second inductor current IL2, and a decrease in the efficiency of the power supply device X20 can be suppressed.
＜その他＞
　本開示の実施形態は、特許請求の範囲に示された技術的思想の範囲内において、適宜、種々の変更が可能である。これまでに説明してきた各種の実施形態は、矛盾のない範囲で適宜組み合わせて実施してもよい。以上の実施形態は、あくまでも、本開示の実施形態の例であって、本開示ないし各構成要件の用語の意義は、以上の実施形態に記載されたものに制限されるものではない。 ＜Other＞
The embodiments of the present disclosure may be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The various embodiments described above may be combined as appropriate within a range that does not cause inconsistency. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments.
　例えば、上述した実施形態では、電圧監視回路１５は、電源ＩＣである半導体集積回路装置に設けられたが、電源ＩＣ以外の半導体集積回路装置に設けられてもよい。 For example, in the above-described embodiment, the voltage monitoring circuit 15 is provided in a semiconductor integrated circuit device that is a power supply IC, but it may also be provided in a semiconductor integrated circuit device other than a power supply IC.
　例えば、上記実施形態では、第１半導体装置２０１と第２半導体装置２０２とは別々のパッケージ内に形成されている、としたが、同一のパッケージ内に形成されている構成を採用することもできる。 For example, in the above embodiment, the first semiconductor device 201 and the second semiconductor device 202 are formed in separate packages, but a configuration in which they are formed in the same package can also be adopted.
　また、上記実施形態では、降圧型の出力段を用いた構成を例に挙げて説明を行ったが、本発明の構成はこれに限定されるものではなく、昇圧型の出力段又は昇降圧型の出力段を用いても構わない。 In addition, in the above embodiment, a configuration using a step-down output stage has been described as an example, but the configuration of the present invention is not limited to this, and a step-up output stage or a step-up/step-down output stage may also be used.
　また、上記の説明では、本開示の実施形態について、２つの半導体装置（第１半導体装置２０１および第２半導体装置２０２）からなるマルチフェイズ型スイッチングレギュレータＩＣを例に示した。しかし、第１半導体装置２０１および第２半導体装置２０２に加えて、更に別の半導体装置を１つ以上備える構成を採用することもできる。 In the above description, a multi-phase switching regulator IC consisting of two semiconductor devices (first semiconductor device 201 and second semiconductor device 202) has been shown as an example of an embodiment of the present disclosure. However, a configuration including one or more other semiconductor devices in addition to first semiconductor device 201 and second semiconductor device 202 may also be adopted.
　この場合、この別の半導体装置は、第１半導体装置２０１および第２半導体装置２０２と同じ構成のものを採用するのが好ましい。そして、第１半導体装置２０１は、第２半導体装置２０２だけでなく、上記の別の半導体装置にも伝送信号Ｖｔを送信する。この別の半導体装置は、第２半導体装置２０２と同様に、伝送信号Ｖｔに基づいてスイッチ出力段の駆動制御を行う。すなわち、１つのマスタから複数のスレーブに第１誤差信号Ｖｃ１及び伝送信号Ｖｔが供給される形となる。 In this case, it is preferable that this other semiconductor device has the same configuration as the first semiconductor device 201 and the second semiconductor device 202. The first semiconductor device 201 transmits the transmission signal Vt not only to the second semiconductor device 202 but also to the other semiconductor device. This other semiconductor device, like the second semiconductor device 202, controls the drive of the switch output stage based on the transmission signal Vt. In other words, the first error signal Vc1 and the transmission signal Vt are supplied from one master to multiple slaves.
　また、上記実施形態の整合部２２３について、以下の構成を採用することもできる（図１３参照）。図１３は、整合部２２３の詳細を示すブロック図である。整合部２２３は、カレントバランサ―２３１をさらに備えている。 The matching unit 223 of the above embodiment may also have the following configuration (see FIG. 13). FIG. 13 is a block diagram showing the details of the matching unit 223. The matching unit 223 further includes a current balancer 231.
　カレントバランサ―２３１の入力端は、補正コンパレータ２２２の出力端に接続されている。カレントバランサ―２３１の第１出力端は、第１コンパレータ２１２の印加端に接続されている。カレントバランサ―２３１の第２出力端は、第２コンパレータ２３０の印加端に接続されている。 The input terminal of the current balancer 231 is connected to the output terminal of the correction comparator 222. The first output terminal of the current balancer 231 is connected to the application terminal of the first comparator 212. The second output terminal of the current balancer 231 is connected to the application terminal of the second comparator 230.
　カレントバランサ―２３１は、補正信号Ｖｃｒに応じて、第１オフセット信号Ｓ１を第１コンパレータ２１２に、第２オフセット信号Ｓ２を第２コンパレータ２３０に伝送する。 The current balancer 231 transmits the first offset signal S1 to the first comparator 212 and the second offset signal S2 to the second comparator 230 in response to the correction signal Vcr.
　第１コンパレータ２１２は、第１オフセット信号Ｓ１に応じて、第１誤差信号Ｖｃ１、第１ランプ信号Ｖｒ１及び第１差動信号Ｖｄ１のうち少なくとも一つのオフセットを調整する。第２コンパレータ２３０は、第２オフセット信号Ｓ２に応じて、第１誤差信号Ｖｃ１、第２ランプ信号Ｖｒ２及び第２差動信号Ｖｄ２のうち少なくとも一つのオフセットを調整する。 The first comparator 212 adjusts the offset of at least one of the first error signal Vc1, the first ramp signal Vr1, and the first differential signal Vd1 in response to the first offset signal S1. The second comparator 230 adjusts the offset of at least one of the first error signal Vc1, the second ramp signal Vr2, and the second differential signal Vd2 in response to the second offset signal S2.
＜付記＞
　上述の実施形態にて具体的構成例が示された本開示について付記を設ける。 <Additional Notes>
Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.
　本開示の電圧監視回路（１５）は、基準電圧を受け取るように構成された第１トランジスタ（Ｍ１）及び監視対象電圧を受け取るように構成された第２トランジスタ（Ｍ２）を含む第１差動入力対（Ｐ１）と、第１電圧を受け取るように構成された第３トランジスタ及（Ｍ３）び第２電圧を受け取るように構成された第４トランジスタ（Ｍ４）を含む第２差動入力対（Ｐ２）と、を備え、前記第１トランジスタの出力端と前記第３トランジスタの出力端とが共通接続され、前記第２トランジスタの出力端と前記第４トランジスタの出力端とが共通接続される構成（第１の構成）である。 The voltage monitoring circuit (15) disclosed herein comprises a first differential input pair (P1) including a first transistor (M1) configured to receive a reference voltage and a second transistor (M2) configured to receive a voltage to be monitored, and a second differential input pair (P2) including a third transistor (M3) configured to receive a first voltage and a fourth transistor (M4) configured to receive a second voltage, and is configured (first configuration) in which the output terminal of the first transistor and the output terminal of the third transistor are commonly connected, and the output terminal of the second transistor and the output terminal of the fourth transistor are commonly connected.
　上記第１の構成の電圧監視回路において、前記第１電圧及び前記第２電圧の少なくとも一方は、抵抗分圧回路（Ｒ３～Ｒ６）の出力電圧である構成（第２の構成）であってもよい。 In the voltage monitoring circuit of the first configuration described above, at least one of the first voltage and the second voltage may be the output voltage of a resistor voltage divider circuit (R3 to R6) (second configuration).
　上記第１又は第２の構成の電圧監視回路において、前記第１電圧及び前記第２電圧の少なくとも一方は、ＤＡＣ（１５７）の出力電圧である構成（第３の構成）であってもよい。 In the voltage monitoring circuit of the first or second configuration, at least one of the first voltage and the second voltage may be the output voltage of a DAC (157) (third configuration).
　上記第１～第３いずれかの構成の電圧監視回路において、前記第１電圧及び前記第２電圧の少なくとも一方の値が時分割で切り替えられる構成（第４の構成）であってもよい。 In the voltage monitoring circuit of any of the first to third configurations, the value of at least one of the first voltage and the second voltage may be switched in a time-division manner (fourth configuration).
　上記第１～第４いずれかの構成の電圧監視回路において、前記第１トランジスタと前記第２トランジスタとの閾値電圧の差及び前記第３トランジスタと前記第４トランジスタとの閾値電圧の差によるオフセットをキャンセルするように構成されたキャリブレーション回路（ＣＡＬ１）を備える構成（第５の構成）であってもよい。 The voltage monitoring circuit of any of the first to fourth configurations may be configured (fifth configuration) to include a calibration circuit (CAL1) configured to cancel offsets due to the difference in threshold voltage between the first transistor and the second transistor and the difference in threshold voltage between the third transistor and the fourth transistor.
　本開示の半導体集積回路装置（１０）は、上記第１～第５いずれかの構成の電圧監視回路を備える構成（第６の構成）である。 The semiconductor integrated circuit device (10) disclosed herein has a configuration (sixth configuration) that includes a voltage monitoring circuit having any of the first to fifth configurations described above.
　本開示の車両（Ｘ）は、上記第６の構成の半導体集積回路装置を備える構成（第７の構成）である。 The vehicle (X) disclosed herein is configured (seventh configuration) to include a semiconductor integrated circuit device of the sixth configuration described above.
　明細書中に開示されている制御装置（２５０）は、少なくとも第１スイッチ出力段（２０３）及び第２スイッチ出力段（２１５）を所定の位相差で駆動することにより入力電圧（Ｖｉ）から所望の出力電圧（Ｖｏ）を生成するように構成されたスイッチングレギュレータの制御装置（２５０）であって、第１スイッチ出力段（２０３）及び第２スイッチ出力段（２１５）をそれぞれ駆動するように構成された第１制御回路（２０４）および第２制御回路（２１６）を含み、第１制御回路（２０４）から第２制御回路（２１６）へ、第１スイッチ出力段（２０３）のクロック情報とDuty情報を併せ持つ伝送信号（Ｖｔ）が伝送される構成（第８の構成）とされている。 The control device (250) disclosed in the specification is a switching regulator control device (250) configured to generate a desired output voltage (Vo) from an input voltage (Vi) by driving at least the first switch output stage (203) and the second switch output stage (215) with a predetermined phase difference, and includes a first control circuit (204) and a second control circuit (216) configured to drive the first switch output stage (203) and the second switch output stage (215), respectively, and is configured (8th configuration) in which a transmission signal (Vt) having both clock information and duty information of the first switch output stage (203) is transmitted from the first control circuit (204) to the second control circuit (216).
　なお、第８の構成からなる制御装置（２５０）は、第１制御回路（２０４）は、出力電圧（Ｖｏ）とその目標値との誤差に応じた第１誤差信号（Ｖｃ１）を生成するように構成された誤差増幅回路（２０５）と、第１スイッチ出力段（２０３）の第１スイッチング周波数を規定する第１クロック信号（ＣＬ１）を生成するように構成されたスイッチ制御回路（２０６）と、を含み、第１クロック信号（ＣＬ１）および第１誤差信号（Ｖｃ１）に基づいて第１スイッチ出力段（２０３）を駆動制御し、かつ第１誤差信号（Ｖｃ１）を第２制御回路（２１６）に伝送するように構成され、クロック情報は、第１クロック信号（ＣＬ１）の立上がり又は立下りのタイミング情報であり、第２制御回路（２１６）は、第１誤差信号（Ｖｃ１）および伝送信号（Ｖｔ）に基づいて第２スイッチ出力段（２１５）を駆動制御する構成（第９の構成）にするとよい。 In addition, the control device (250) having the eighth configuration may be configured such that the first control circuit (204) includes an error amplifier circuit (205) configured to generate a first error signal (Vc1) corresponding to the error between the output voltage (Vo) and its target value, and a switch control circuit (206) configured to generate a first clock signal (CL1) that defines a first switching frequency of the first switch output stage (203), and is configured to drive and control the first switch output stage (203) based on the first clock signal (CL1) and the first error signal (Vc1) and transmit the first error signal (Vc1) to the second control circuit (216), the clock information is timing information of the rise or fall of the first clock signal (CL1), and the second control circuit (216) drives and controls the second switch output stage (215) based on the first error signal (Vc1) and the transmission signal (Vt) (ninth configuration).
　また、第９の構成からなる制御装置（２５０）は、第２制御回路（２１６）は、伝送信号（Ｖｔ）に基づいて第２スイッチ出力段（２１５）の第２スイッチング周波数を規定する第２クロック信号（ＣＬ２）を生成するように構成された位相同期回路（２１８）と、第１誤差信号（Ｖｃ１）および伝送信号（Ｖｔ）に基づいて第２誤差信号（Ｖｃ２）を生成するように構成された整合回路と、を含み、第２クロック信号（ＣＬ２）および第２誤差信号（Ｖｃ２）に基づいて第２スイッチ出力段（２１５）を駆動制御するように構成（第１０の構成）するとよい。 Furthermore, in the control device (250) having a ninth configuration, the second control circuit (216) includes a phase synchronization circuit (218) configured to generate a second clock signal (CL2) that defines a second switching frequency of the second switch output stage (215) based on the transmission signal (Vt), and a matching circuit configured to generate a second error signal (Vc2) based on the first error signal (Vc1) and the transmission signal (Vt), and is configured to drive and control the second switch output stage (215) based on the second clock signal (CL2) and the second error signal (Vc2) (tenth configuration).
　また、第１０の構成からなる制御装置（２５０）は、伝送信号（Ｖｔ）は、第１スイッチ出力段（２０３）が出力する第１スイッチ電圧（Ｖｓｔ１）又は第１スイッチ出力段（２０３）をＰＷＭ制御するための第１スイッチ制御信号であり、整合回路は、伝送信号（Ｖｔ）を平均化して第１平均電圧（Ｖａｖｅ１）を生成する第１ローパスフィルタ（２２０）と、第２スイッチ出力段（２１５）が出力する第２スイッチ電圧（Ｖｓｔ２）又は第２スイッチ出力段（２１５）をＰＷＭ制御するための第２スイッチ制御信号を平均化して第２平均電圧（Ｖａｖｅ２）を生成する第２ローパスフィルタ（２２１）と、第１平均電圧（Ｖａｖｅ１）と、第２平均電圧（Ｖａｖｅ２）とを比較して補正信号（Ｖｃｒ）を生成するように構成された補正コンパレータ（２２２）と、補正信号（Ｖｃｒ）に基づいて第１誤差信号（Ｖｃ１）を補正して第２誤差信号（Ｖｃ２）を生成するように構成された整合部（２２３）と、を含むように構成（第１１の構成）するとよい。 In addition, in the control device (250) having the tenth configuration, the transmission signal (Vt) is a first switch voltage (Vst1) output by the first switch output stage (203) or a first switch control signal for PWM controlling the first switch output stage (203), and the matching circuit is a first low-pass filter (220) that averages the transmission signal (Vt) to generate a first average voltage (Vave1), and a second switch voltage (Vst2) output by the second switch output stage (215) or a second switch control signal for PWM controlling the second switch output stage (215). It is preferable to configure the 11th configuration to include a second low-pass filter (221) that averages the second switch control signal for M control to generate a second average voltage (Vave2), a correction comparator (222) configured to compare the first average voltage (Vave1) and the second average voltage (Vave2) to generate a correction signal (Vcr), and a matching unit (223) configured to correct the first error signal (Vc1) based on the correction signal (Vcr) to generate a second error signal (Vc2).
　また、第１１の構成からなる制御装置（２５０）は、第１制御回路（２０４）は、第１クロック信号（ＣＬ１）に同期して第１ランプ信号（Ｖｒ１）を生成するように構成された第１ランプ信号生成部（２１１）と、第１誤差信号（Ｖｃ１）と第１ランプ信号（Ｖｒ１）に応じた第１基準信号（Ｖｓ１）とを比較して第１比較信号（Ｖａ１）を生成するように構成された第１コンパレータ（２１２）と、を含み、第１クロック信号（ＣＬ１）および第１比較信号（Ｖａ１）に基づいて第１スイッチ出力段（２０３）の駆動制御を行うように構成され、第２制御回路（２１６）は、第２クロック信号（ＣＬ２）に同期して第２ランプ信号（Ｖｒ２）を生成するように構成された第２ランプ信号生成部（２１９）と、第２誤差信号（Ｖｃ２）と第２ランプ信号（Ｖｒ２）に応じた第２基準信号（Ｖｓ２）とを比較して第２比較信号（Ｖａ２）を生成するように構成された第２コンパレータ（２３０）と、を含み、第２クロック信号（ＣＬ２）および第２比較信号（Ｖａ２）に応じて第２スイッチ出力段（２１５）の駆動制御を行うように構成（第１２の構成）するとよい。 In addition, the control device (250) having the 11th configuration includes a first control circuit (204) including a first ramp signal generating unit (211) configured to generate a first ramp signal (Vr1) in synchronization with a first clock signal (CL1), and a first comparator (212) configured to compare a first error signal (Vc1) with a first reference signal (Vs1) corresponding to the first ramp signal (Vr1) to generate a first comparison signal (Va1), and performs drive control of a first switch output stage (203) based on the first clock signal (CL1) and the first comparison signal (Va1). The second control circuit (216) includes a second ramp signal generating unit (219) configured to generate a second ramp signal (Vr2) in synchronization with the second clock signal (CL2), and a second comparator (230) configured to compare the second error signal (Vc2) with a second reference signal (Vs2) corresponding to the second ramp signal (Vr2) to generate a second comparison signal (Va2), and is configured to control the drive of the second switch output stage (215) in response to the second clock signal (CL2) and the second comparison signal (Va2) (12th configuration).
　また、第８の構成から第１２の構成のいずれかの構成からなる制御装置（２５０）は、第１制御回路（２０４）および第２制御回路（２１６）は、同一のパッケージ内に形成されている構成（第１３の構成）とするとよい。 In addition, in the control device (250) having any of the eighth to twelfth configurations, the first control circuit (204) and the second control circuit (216) may be configured in the same package (thirteenth configuration).
　また、第８の構成から第１２の構成のいずれかの構成からなる制御装置（２５０）は、第１制御回路（２０４）および第２制御回路（２１６）は、それぞれ異なるパッケージ内に形成されている構成とするとよい（第１４の構成） In addition, in the control device (250) having any of the eighth to twelfth configurations, the first control circuit (204) and the second control circuit (216) may be formed in different packages (14th configuration)
　また、第１４の構成からなる制御装置（２５０）は、第１制御回路（２０４）を内部に含み、伝送信号（Ｖｔ）を出力するように構成された第１外部端子を有する第１半導体装置（２０１）と、第２制御回路（２１６）を内部に含み、伝送信号（Ｖｔ）が入力されるように構成された第２外部端子を有する第２半導体装置（２０２）と、第１外部端子と第２外部端子とを電気的に接続し、伝送信号（Ｖｔ）の伝送経路（２２８）となるように構成された伝送線路と、を含む構成（第１５の構成）とするとよい。 Furthermore, the control device (250) having the 14th configuration may be configured (15th configuration) to include a first semiconductor device (201) having a first external terminal configured to output a transmission signal (Vt) and including a first control circuit (204), a second semiconductor device (202) having a second external terminal configured to input the transmission signal (Vt), and a transmission line electrically connecting the first external terminal and the second external terminal and configured to be a transmission path (228) for the transmission signal (Vt).
　また、明細書中に開示されているスイッチングレギュレータは、第８の構成から第１２の構成のいずれかの制御装置（２５０）を備える構成（第１６の構成）とされている。 The switching regulator disclosed in the specification is configured (16th configuration) to include a control device (250) having any of the eighth to twelfth configurations.
　また、明細書中に開示されている電源装置（Ｘ２０）は、第１６の構成からなるスイッチングレギュレータを備える構成（第１７の構成）とされている。 Furthermore, the power supply device (X20) disclosed in the specification is configured to include a switching regulator having a 16th configuration (17th configuration).
　第８の構成に係る制御装置（２５０）によれば、第２制御回路（２１６）は、第１スイッチ出力段（２０３）のクロック情報およびDuty情報を得ることができる。このクロック情報およびDuty情報に基づいて第２スイッチ出力段（２１５）を駆動制御することで、第１スイッチ出力段（２０３）の駆動とのバランスが崩れるのを抑制することができる。 According to the control device (250) of the eighth configuration, the second control circuit (216) can obtain clock information and duty information of the first switch output stage (203). By controlling the drive of the second switch output stage (215) based on this clock information and duty information, it is possible to prevent imbalance with the drive of the first switch output stage (203).
　第９の構成に係る制御装置（２５０）によれば、第２制御回路（２１６）は、第１誤差信号（Ｖｃ１）に基づいて第２スイッチ出力段（２１５）の駆動を制御する。このため、第１スイッチ出力段（２０３）と第２スイッチ出力段（２１５）の駆動のバランスが崩れるのをより好適に抑制することが可能となる。 According to the control device (250) of the ninth configuration, the second control circuit (216) controls the drive of the second switch output stage (215) based on the first error signal (Vc1). This makes it possible to more effectively prevent the drive balance between the first switch output stage (203) and the second switch output stage (215) from being lost.
　第９の構成に係る制御装置（２５０）によれば、第２スイッチ出力段（２１５）は、第１誤差信号（Ｖｃ１）および伝送信号（Ｖｔ）に基づいて駆動する。そして、伝送信号（Ｖｔ）に含まれるクロック情報は、第１クロック信号（ＣＬ１）の立上がりまたは立下りのタイミング情報である。このため、第２スイッチ出力段（２１５）は、このタイミング情報および第１誤差信号（Ｖｃ１）に基づいて駆動するため、第１スイッチ出力段（２０３）と第２スイッチ出力段（２１５）の駆動のバランスが崩れるのを、より好適に抑制できる。 According to the control device (250) of the ninth configuration, the second switch output stage (215) is driven based on the first error signal (Vc1) and the transmission signal (Vt). The clock information contained in the transmission signal (Vt) is timing information of the rising or falling edge of the first clock signal (CL1). Therefore, the second switch output stage (215) is driven based on this timing information and the first error signal (Vc1), and therefore, it is possible to more suitably prevent the drive balance between the first switch output stage (203) and the second switch output stage (215) from being lost.
　第１０の構成に係る制御装置（２５０）によれば、第２クロック信号（ＣＬ２）および第２誤差信号（Ｖｃ２）に基づいて第２スイッチ出力段（２１５）が駆動する。第２クロック信号（ＣＬ２）は第１クロック信号（ＣＬ１）に基づいて生成され、第２誤差信号（Ｖｃ２）は第１誤差信号（Ｖｃ１）に基づいて生成される。このため、第１スイッチ出力段（２０３）の駆動制御に対応するように第２スイッチ出力段（２１５）の駆動制御をすることが可能になり、第１スイッチ出力段（２０３）と第２スイッチ出力段（２１５）とのバランスが崩れるのを、より好適に抑制できる。 According to the control device (250) of the tenth configuration, the second switch output stage (215) is driven based on the second clock signal (CL2) and the second error signal (Vc2). The second clock signal (CL2) is generated based on the first clock signal (CL1), and the second error signal (Vc2) is generated based on the first error signal (Vc1). This makes it possible to control the drive of the second switch output stage (215) in response to the drive control of the first switch output stage (203), and more suitably prevents imbalance between the first switch output stage (203) and the second switch output stage (215).
　第１１の構成に係る制御装置（２５０）によれば、第２誤差信号（Ｖｃ２）は、第１平均電圧（Ｖａｖｅ１）と第２平均電圧（Ｖａｖｅ２）とを比較して生成された補正信号（Ｖｃｒ）に基づいて第１誤差信号（Ｖｃ１）を補正して生成される。このため、第２誤差信号（Ｖｃ２）が第１スイッチ出力段（２０３）と第２スイッチ出力段（２１５）との駆動のバランスが崩れるのをより好適に抑制可能な第２誤差信号（Ｖｃ２）を生成することができる。 According to the control device (250) of the eleventh configuration, the second error signal (Vc2) is generated by correcting the first error signal (Vc1) based on the correction signal (Vcr) generated by comparing the first average voltage (Vave1) and the second average voltage (Vave2). Therefore, it is possible to generate the second error signal (Vc2) that can more suitably suppress the loss of balance in the drive between the first switch output stage (203) and the second switch output stage (215).
　第１２の構成に係る制御装置（２５０）によれば、第２基準信号（Ｖｓ２）は、第２クロック信号（ＣＬ２）と同期している第２ランプ信号（Ｖｒ２）に応じたものとなっている。この第２基準信号（Ｖｓ２）と第２誤差信号（Ｖｃ２）とを比較して第２比較信号（Ｖａ２）が生成されており、第２スイッチ出力段（２１５）は、第２クロック信号（ＣＬ２）および第２比較信号（Ｖａ２）に応じて駆動する。第２クロック信号（ＣＬ２）は、伝送信号（Ｖｔ）に基づいて生成されている。このため、第１スイッチ出力段（２０３）と第２スイッチ出力段（２１５）の駆動のバランスが崩れるのを、より好適に抑制できる。 According to the control device (250) of the twelfth configuration, the second reference signal (Vs2) corresponds to the second ramp signal (Vr2) synchronized with the second clock signal (CL2). The second reference signal (Vs2) is compared with the second error signal (Vc2) to generate the second comparison signal (Va2), and the second switch output stage (215) is driven in response to the second clock signal (CL2) and the second comparison signal (Va2). The second clock signal (CL2) is generated based on the transmission signal (Vt). This makes it possible to more effectively prevent the drive balance between the first switch output stage (203) and the second switch output stage (215) from being lost.
　第１３の構成に係る制御装置（２５０）によれば、１つのパッケージ内に第１制御回路（２０４）および第２制御回路（２１６）が形成されるものとなり、制御装置（２５０）の省スペース化を図ることができる。 According to the control device (250) of the thirteenth configuration, the first control circuit (204) and the second control circuit (216) are formed in a single package, which allows the control device (250) to be space-saving.
　第１４の構成に係る制御装置（２５０）によれば、１つのパッケージ内に形成される制御回路が比較的簡易な構成となり、制御装置（２５０）の製造コストの増大を抑制可能となる。 The control device (250) according to the 14th configuration has a relatively simple control circuit formed in one package, making it possible to suppress increases in the manufacturing costs of the control device (250).
　第１５の構成に係る制御装置（２５０）によれば、伝送線路の接続に用いる外部端子を、第１外部端子と第２外部端子のみとすることができる。この伝送線路を経由してDuty情報およびクロック情報を含む伝送信号（Ｖｔ）が伝送される。このため、第１半導体装置（２０１）および第２半導体装置（２０２）の外部端子の使用数が増加するのを抑制しつつ、Duty情報およびクロック情報を第１半導体装置（２０１）から第２半導体装置（２０２）に伝送することができる。 According to the control device (250) of the fifteenth configuration, the external terminals used to connect the transmission line can be limited to the first external terminal and the second external terminal. A transmission signal (Vt) including duty information and clock information is transmitted via this transmission line. Therefore, it is possible to transmit duty information and clock information from the first semiconductor device (201) to the second semiconductor device (202) while suppressing an increase in the number of external terminals used in the first semiconductor device (201) and the second semiconductor device (202).
　第１６の構成に係る制御装置（２５０）によれば、第１スイッチ出力段（２０３）と第２スイッチ出力段（２１５）の駆動のバランスが崩れるのを抑制可能なスイッチングレギュレータを提供できる。 The control device (250) according to the 16th configuration can provide a switching regulator capable of suppressing imbalance in the drive of the first switch output stage (203) and the second switch output stage (215).
　第１７の構成に係る制御装置（２５０）によれば、第１スイッチ出力段（２０３）と第２スイッチ出力段（２１５）の駆動のバランスが崩れるのを抑制可能な電源装置（Ｘ２０）を提供することができる。 The control device (250) according to the seventeenth configuration can provide a power supply device (X20) capable of suppressing imbalance in the drive of the first switch output stage (203) and the second switch output stage (215).
　１　スイッチング電源装置
　１０　半導体集積回路装置
　１１、１５６　デジタルデータ生成回路
　１２、１５７　ＤＡＣ
　１３　バッファアンプ
　１４　スイッチ電圧生成回路
　１５　電圧監視回路
　１６　定電圧生成回路
　１５１、１５２　電圧生成回路
　１５３、１５４　コンパレータ
　１５５　４入力端子コンパレータ
　Ｃ１、Ｃ２　コンデンサ
　ＣＡＬ１　キャリブレーション回路
　ＣＳ１～ＣＳ６　電流源
　ＣＯＵＴ　出力コンデンサ
　Ｌ１　インダクタ
　Ｍ１～Ｍ１６　トランジスタ
　Ｐ１　第１差動入力対
　Ｐ２　第２差動入力対
　Ｒ１～Ｒ６　抵抗
　ＳＷ１～ＳＷ６　スイッチ
　Ｘ　車両
　Ｘ１１～Ｘ１８　電子機器
　２０１　第１半導体装置
　２０２　第２半導体装置
　２０３　第１スイッチ出力段
　２０４　第１制御回路
　２０５　誤差増幅回路
　２０６　スイッチ制御回路
　２０７　誤差増幅アンプ
　２０８　第１オシレータ
　２０９　第１ＰＬＬ
　２１０　第１セレクタ
　２１１　第１ランプ信号生成部
　２１２　第１コンパレータ
　２１３　加算部
　２１４　第１差動ライン
　２１５　第２スイッチ出力段
　２１６　第２制御回路
　２１７　整合回路
　２１８　位相同期回路
　２１９　第２ランプ信号生成部
　２２０　第１ローパスフィルタ
　２２１　第２ローパスフィルタ
　２２２　補正コンパレータ
　２２３　整合部
　２２４　第２オシレータ
　２２５　第２ＰＬＬ
　２２６　第２セレクタ
　２２７　加算部
　２２８　伝送経路
　２２９　第２差動ライン
　２３０　第２コンパレータ
　２５０　制御装置
　３０１　第１半導体装置
　３０２　第２半導体装置
　Ｃ２１、Ｃ２２　キャパシタ
　ＣＬ１　第１クロック信号
　ＣＬ２　第２クロック信号
　Ｅ３　電圧源
　ＩＬ１　第１インダクタ電流
　ＩＬ２　第２インダクタ電流
　Ｉｏ　出力電流
　Ｌ２１、Ｌ２２　インダクタ
　Ｒ２１、Ｒ２２　抵抗
　Ｓ１　第１オフセット信号
　Ｓ２　第２オフセット信号
　Ｖａｖｅ１　第１平均電圧
　Ｖａｖｅ２　第２平均電圧
　Ｖａ１　第１比較信号
　Ｖａ２　第２比較信号
　Ｖｃ１　第１誤差信号
　Ｖｃ２　第２誤差信号
　Ｖｃｒ　補正信号
　Ｖｄ１　第１差動信号
　Ｖｄ２　第２差動信号
　Ｖｉ　入力電圧
　Ｖｏ　出力電圧
　Ｖｒ１　第１ランプ信号
　Ｖｒ２　第２ランプ信号
　Ｖｓ１　第１基準信号
　Ｖｓ２　第２基準信号
Ｖｓｔ１　第１スイッチ電圧
Ｖｓｔ２　第２スイッチ電圧
　Ｖｔ　伝送信号
　Ｘ２０　電源装置
　Ｙ２０　電源装置
　Ｚ２０　負荷 1 Switching power supply device 10 Semiconductor integrated circuit device 11, 156 Digital data generation circuit 12, 157 DAC
13 Buffer amplifier 14 Switch voltage generation circuit 15 Voltage monitoring circuit 16 Constant voltage generation circuit 151, 152 Voltage generation circuit 153, 154 Comparator 155 Four-input terminal comparator C1, C2 Capacitor CAL1 Calibration circuit CS1 to CS6 Current source COUT Output capacitor L1 Inductor M1 to M16 Transistor P1 First differential input pair P2 Second differential input pair R1 to R6 Resistor SW1 to SW6 Switch X Vehicle X11 to X18 Electronic device 201 First semiconductor device 202 Second semiconductor device 203 First switch output stage 204 First control circuit 205 Error amplifier circuit 206 Switch control circuit 207 Error amplifier 208 First oscillator 209 First PLL
210 First selector 211 First ramp signal generating section 212 First comparator 213 Adding section 214 First differential line 215 Second switch output stage 216 Second control circuit 217 Matching circuit 218 Phase locked loop circuit 219 Second ramp signal generating section 220 First low pass filter 221 Second low pass filter 222 Correction comparator 223 Matching section 224 Second oscillator 225 Second PLL
226 Second selector 227 Adder 228 Transmission path 229 Second differential line 230 Second comparator 250 Control device 301 First semiconductor device 302 Second semiconductor device C21, C22 Capacitor CL1 First clock signal CL2 Second clock signal E3 Voltage source IL1 First inductor current IL2 Second inductor current Io Output current L21, L22 Inductor R21, R22 Resistor S1 First offset signal S2 Second offset signal Vave1 First average voltage Vave2 Second average voltage Va1 First comparison signal Va2 Second comparison signal Vc1 First error signal Vc2 Second error signal Vcr Correction signal Vd1 First differential signal Vd2 Second differential signal Vi Input voltage Vo Output voltage Vr1 First ramp signal Vr2 Second ramp signal Vs1 First reference signal Vs2 Second reference signal Vst1 First switch voltage Vst2 Second switch voltage Vt Transmission signal X20 Power supply unit Y20 Power supply unit Z20 Load

Claims (17)

  1. 　基準電圧を受け取るように構成された第１トランジスタ及び監視対象電圧を受け取るように構成された第２トランジスタを含む第１差動入力対と、
    　第１電圧を受け取るように構成された第３トランジスタ及び第２電圧を受け取るように構成された第４トランジスタを含む第２差動入力対と、
    　を備え、
    　前記第１トランジスタの出力端と前記第３トランジスタの出力端とが共通接続され、
    　前記第２トランジスタの出力端と前記第４トランジスタの出力端とが共通接続される、電圧監視回路。     a first differential input pair including a first transistor configured to receive a reference voltage and a second transistor configured to receive a monitored voltage;
    a second differential input pair including a third transistor configured to receive the first voltage and a fourth transistor configured to receive the second voltage;
    Equipped with
    an output terminal of the first transistor and an output terminal of the third transistor are commonly connected;
    an output terminal of the second transistor and an output terminal of the fourth transistor are commonly connected to each other;
  2. 　前記第１電圧及び前記第２電圧の少なくとも一方は、抵抗分圧回路の出力電圧である、請求項１に記載の電圧監視回路。 The voltage monitoring circuit according to claim 1, wherein at least one of the first voltage and the second voltage is an output voltage of a resistor voltage divider circuit.
  3. 　前記第１電圧及び前記第２電圧の少なくとも一方は、ＤＡＣの出力電圧である、請求項１又は請求項２に記載の電圧監視回路。 The voltage monitoring circuit according to claim 1 or 2, wherein at least one of the first voltage and the second voltage is an output voltage of a DAC.
  4. 　前記第１電圧及び前記第２電圧の少なくとも一方の値が時分割で切り替えられる、請求項１～３のいずれか一項に記載の電圧監視回路。 The voltage monitoring circuit according to any one of claims 1 to 3, wherein the value of at least one of the first voltage and the second voltage is switched in a time-division manner.
  5. 　前記第１トランジスタと前記第２トランジスタとの閾値電圧の差及び前記第３トランジスタと前記第４トランジスタとの閾値電圧の差によるオフセットをキャンセルするように構成されたキャリブレーション回路を備える、請求項１～４のいずれか一項に記載の電圧監視回路。 The voltage monitoring circuit according to any one of claims 1 to 4, comprising a calibration circuit configured to cancel an offset due to a difference in threshold voltage between the first transistor and the second transistor and a difference in threshold voltage between the third transistor and the fourth transistor.
  6. 　請求項１～５のいずれか一項に記載の電圧監視回路を備える、半導体集積回路装置。 A semiconductor integrated circuit device comprising a voltage monitoring circuit according to any one of claims 1 to 5.
  7. 　請求項６に記載の半導体集積回路装置を備える、車両。 A vehicle equipped with the semiconductor integrated circuit device according to claim 6.
  8. 　少なくとも第１スイッチ出力段及び第２スイッチ出力段を所定の位相差で駆動することにより入力電圧から所望の出力電圧を生成するように構成されたスイッチングレギュレータの制御装置であって、
    　前記第１スイッチ出力段及び前記第２スイッチ出力段をそれぞれ駆動するように構成された第１制御回路および第２制御回路を含み、
    　前記第１制御回路から前記第２制御回路へ、前記第１スイッチ出力段のクロック情報とDuty情報を併せ持つ伝送信号が伝送される制御装置。     A control device for a switching regulator configured to generate a desired output voltage from an input voltage by driving at least a first switch output stage and a second switch output stage with a predetermined phase difference,
    a first control circuit and a second control circuit configured to drive the first switch output stage and the second switch output stage, respectively;
    A control device in which a transmission signal having both clock information and duty information of the first switch output stage is transmitted from the first control circuit to the second control circuit.
  9. 　前記第１制御回路は、
    　　前記出力電圧とその目標値との誤差に応じた第１誤差信号を生成するように構成された誤差増幅回路と、
    　　前記第１スイッチ出力段の第１スイッチング周波数を規定する第１クロック信号を生成するように構成されたスイッチ制御回路と、
    　を含み、前記第１クロック信号および前記第１誤差信号に基づいて前記第１スイッチ出力段を駆動制御し、かつ前記第１誤差信号を前記第２制御回路に伝送するように構成され、
    　前記クロック情報は、前記第１クロック信号の立上がり又は立下りのタイミング情報であり、
    　前記第２制御回路は、前記第１誤差信号および前記伝送信号に基づいて前記第２スイッチ出力段を駆動制御するように構成されている請求項８に記載の制御装置。     The first control circuit is
    an error amplifier circuit configured to generate a first error signal corresponding to an error between the output voltage and a target value thereof;
    a switch control circuit configured to generate a first clock signal defining a first switching frequency of the first switch output stage;
    configured to drive and control the first switch output stage based on the first clock signal and the first error signal, and to transmit the first error signal to the second control circuit;
    the clock information is timing information of a rising edge or a falling edge of the first clock signal,
    9. The control device according to claim 8, wherein the second control circuit is configured to drive and control the second switch output stage based on the first error signal and the transmission signal.
  10. 　前記第２制御回路は、
    　前記伝送信号に基づいて前記第２スイッチ出力段の第２スイッチング周波数を規定する第２クロック信号を生成するように構成された位相同期回路と、
    　前記第１誤差信号および前記伝送信号に基づいて第２誤差信号を生成するように構成された整合回路と、
    　を含み、前記第２クロック信号および前記第２誤差信号に基づいて前記第２スイッチ出力段を駆動制御するように構成されている請求項９に記載の制御装置。     The second control circuit is
    a phase locked loop configured to generate a second clock signal based on the transmit signal, the second clock signal defining a second switching frequency of the second switch output stage;
    a matching circuit configured to generate a second error signal based on the first error signal and the transmission signal;
    10. The control device according to claim 9, further comprising: a second switch output stage configured to drive and control the second switch output stage based on the second clock signal and the second error signal.
  11. 　前記伝送信号は、前記第１スイッチ出力段が出力する第１スイッチ電圧又は前記第１スイッチ出力段をＰＷＭ制御するための第１スイッチ制御信号であり、
    　前記整合回路は、
    　　前記伝送信号を平均化して第１平均電圧を生成する第１ローパスフィルタと、
    　　前記第２スイッチ出力段が出力する第２スイッチ電圧又は前記第２スイッチ出力段をＰＷＭ制御するための第２スイッチ制御信号を平均化して第２平均電圧を生成する第２ローパスフィルタと、
    　　前記第１平均電圧と、前記第２平均電圧とを比較して補正信号を生成するように構成された補正コンパレータと、
    　　前記補正信号に基づいて前記第１誤差信号を補正して前記第２誤差信号を生成するように構成された整合部と、
    　を含むように構成された請求項１０に記載の制御装置。     the transmission signal is a first switch voltage output by the first switch output stage or a first switch control signal for PWM-controlling the first switch output stage,
    The matching circuit includes:
    a first low pass filter that averages the transmission signal to generate a first average voltage;
    a second low-pass filter that averages a second switch voltage output by the second switch output stage or a second switch control signal for PWM controlling the second switch output stage to generate a second average voltage;
    a correction comparator configured to compare the first average voltage and the second average voltage to generate a correction signal;
    a matching unit configured to correct the first error signal based on the correction signal to generate the second error signal;
    The control device of claim 10 configured to include:
  12. 　前記第１制御回路は、
    　　前記第１クロック信号に同期して第１ランプ信号を生成するように構成された第１ランプ信号生成部と、
    　　前記第１誤差信号と前記第１ランプ信号に応じた第１基準信号とを比較して第１比較信号を生成するように構成された第１コンパレータと、
    　を含み、前記第１クロック信号および前記第１比較信号に基づいて前記第１スイッチ出力段の駆動制御を行うように構成され、
    　前記第２制御回路は、
    　　前記第２クロック信号に同期して第２ランプ信号を生成するように構成された第２ランプ信号生成部と、
    　　前記第２誤差信号と前記第２ランプ信号に応じた第２基準信号とを比較して第２比較信号を生成するように構成された第２コンパレータと、
    　を含み、前記第２クロック信号および前記第２比較信号に応じて前記第２スイッチ出力段の駆動制御を行うように構成されている請求項１１に記載の制御装置。     The first control circuit is
    a first ramp signal generating unit configured to generate a first ramp signal in synchronization with the first clock signal;
    a first comparator configured to compare the first error signal with a first reference signal responsive to the first ramp signal to generate a first comparison signal;
    and configured to perform drive control of the first switch output stage based on the first clock signal and the first comparison signal;
    The second control circuit is
    a second ramp signal generating unit configured to generate a second ramp signal in synchronization with the second clock signal;
    a second comparator configured to compare the second error signal with a second reference signal responsive to the second ramp signal to generate a second comparison signal;
    12. The control device according to claim 11, further comprising: a second switch output stage configured to perform drive control of the second switch output stage in response to the second clock signal and the second comparison signal.
  13. 　前記第１制御回路および前記第２制御回路は、同一のパッケージ内に形成されている請求項８～１２のいずれか一項に記載の制御装置。 The control device according to any one of claims 8 to 12, wherein the first control circuit and the second control circuit are formed in the same package.
  14. 　前記第１制御回路および前記第２制御回路は、それぞれ異なるパッケージ内に形成されている請求項８～１２のいずれか一項に記載の制御装置。 The control device according to any one of claims 8 to 12, wherein the first control circuit and the second control circuit are formed in different packages.
  15. 　前記第１制御回路を内部に含み、前記伝送信号を出力するように構成された第１外部端子を有する第１半導体装置と、
    　前記第２制御回路を内部に含み、前記伝送信号が入力されるように構成された第２外部端子を有する第２半導体装置と、
    　前記第１外部端子と前記第２外部端子とを電気的に接続し、前記伝送信号の伝送経路となるように構成された伝送線路と、
    　を含む請求項１４に記載の制御装置。     a first semiconductor device including the first control circuit therein and having a first external terminal configured to output the transmission signal;
    a second semiconductor device including the second control circuit therein and having a second external terminal configured to receive the transmission signal;
    a transmission line electrically connecting the first external terminal and the second external terminal and configured to be a transmission path for the transmission signal;
    The control device of claim 14 including:
  16. 　請求項８～１２のいずれか一項に記載の制御装置を備えるスイッチングレギュレータ。 A switching regulator equipped with a control device according to any one of claims 8 to 12.
  17. 　請求項１６に記載のスイッチングレギュレータを備える電源装置。 A power supply device comprising the switching regulator according to claim 16.
PCT/JP2023/035185 2022-10-17 2023-09-27 Voltage monitoring circuit, semiconductor integrated circuit device, vehicle, control device, switching regulator, and power supply device WO2024084911A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7804286B2 (en) * 2007-09-05 2010-09-28 Linear Technology Corporation Multiple output amplifiers and comparators
JP2015180121A (en) * 2014-03-18 2015-10-08 株式会社リコー Multiphase power supply device
JP2018161008A (en) * 2017-03-23 2018-10-11 ローム株式会社 Switching regulator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7804286B2 (en) * 2007-09-05 2010-09-28 Linear Technology Corporation Multiple output amplifiers and comparators
JP2015180121A (en) * 2014-03-18 2015-10-08 株式会社リコー Multiphase power supply device
JP2018161008A (en) * 2017-03-23 2018-10-11 ローム株式会社 Switching regulator

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