WO2024082586A1 - Signal generation apparatus and method for generating low-phase noise signal - Google Patents

Signal generation apparatus and method for generating low-phase noise signal Download PDF

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Publication number
WO2024082586A1
WO2024082586A1 PCT/CN2023/089468 CN2023089468W WO2024082586A1 WO 2024082586 A1 WO2024082586 A1 WO 2024082586A1 CN 2023089468 W CN2023089468 W CN 2023089468W WO 2024082586 A1 WO2024082586 A1 WO 2024082586A1
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Prior art keywords
signal
connection end
circuit
phase
frequency
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PCT/CN2023/089468
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French (fr)
Chinese (zh)
Inventor
黄智辉
吴永康
刘源
熊林江
马兴望
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深圳市鼎阳科技股份有限公司
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Publication of WO2024082586A1 publication Critical patent/WO2024082586A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0483—Transmitters with multiple parallel paths
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0491—Circuits with frequency synthesizers, frequency converters or modulators

Definitions

  • the present invention relates to the field of microwave and millimeter wave technology, and in particular to a signal generating device and a signal generating method for generating a low phase noise signal.
  • phase noise is an important parameter indicator for transmitters and receivers.
  • the size of phase noise can reflect the quality of the RF system.
  • the smaller the phase noise the better the performance of the RF system.
  • the phase noise of the entire RF system is limited by the phase noise of the phase-locked loop output signal; in the mixer phase-locked loop circuit, the size of the phase noise of the phase-locked loop output signal is limited by the phase noise of the reference signal. Therefore, to improve the phase noise of the entire RF system, it is first necessary to generate a signal with good phase noise indicators.
  • the main technical problem solved by the present invention is how to generate a signal with a lower phase noise index.
  • the present invention provides a signal generating device for generating a low phase noise signal, comprising a signal preprocessing circuit, a mixer phase-locked loop circuit and a signal post-processing circuit;
  • the signal preprocessing circuit comprises a first signal connection terminal and a second signal connection terminal; the first signal connection terminal of the signal preprocessing circuit is used as a signal input terminal of the signal generating device, and is used for inputting a preset signal to be optimized; the second signal connection terminal of the signal preprocessing circuit is connected to the mixer phase-locked loop circuit; the signal preprocessing circuit is used to perform frequency division or frequency multiplication processing on the signal to be optimized, and send the preprocessed signal obtained after the frequency division or frequency multiplication processing to the mixer phase-locked loop circuit;
  • the mixing phase-locked loop circuit includes a first connection end, a second connection end, a phase detector, a loop filter circuit, a voltage-controlled oscillator, a power divider, a mixer and a first amplifier; the first connection end of the mixing phase-locked loop circuit is connected to the second signal connection end of the signal preprocessing circuit, the second connection end of the mixing phase-locked loop circuit is connected to the signal post-processing circuit, and the mixing phase-locked loop circuit is used to perform loop locking on the pre-processing signal, and send the loop phase-locked signal obtained by loop locking to the signal post-processing circuit;
  • the phase detector comprises a first signal input terminal, a second signal input terminal and a first phase detection signal output terminal, the first signal input terminal of the phase detector is connected to the first connection terminal of the mixer phase-locked loop circuit, the second signal input terminal of the phase detector is connected to the first amplifier, and the first phase detection signal output terminal of the phase detector is connected to the loop filter circuit;
  • the loop filter circuit comprises a first connection end and a second connection end, the first connection end of the loop filter circuit is connected to the first phase detection signal output end of the phase detector, and the second connection end of the loop filter circuit is connected to the voltage controlled oscillator;
  • the voltage controlled oscillator comprises a first connection end and a second connection end, the first connection end of the voltage controlled oscillator is connected to the second connection end of the loop filter circuit, and the second connection end of the voltage controlled oscillator is connected to the power distributor;
  • the power divider comprises a first power signal input terminal, a first power signal output terminal and a second power signal output terminal, the first power signal input terminal of the power divider is connected to the second connection terminal of the voltage-controlled oscillator, the first power signal output terminal of the power divider is connected to the second connection terminal of the mixer phase-locked loop circuit, and the second power signal output terminal of the power divider is connected to the mixer;
  • the mixer comprises a local oscillator signal input terminal, a signal input terminal for mixing and a mixing signal output terminal, wherein the local oscillator signal input terminal of the mixer is used for inputting a preset local oscillator signal, the signal input terminal for mixing of the mixer is connected to the second power signal output terminal of the power divider, and the mixing signal output terminal of the mixer is connected to the first amplifier;
  • the first amplifier comprises a first connection end and a second connection end, the first connection end of the first amplifier is connected to the mixing signal output end of the mixer, and the second connection end of the first amplifier is connected to the second signal input end of the phase detector;
  • the signal post-processing circuit includes a first signal connection end and a second signal connection end; the first signal connection end of the signal post-processing circuit is connected to the second connection end of the mixing phase-locked loop circuit, and the second signal connection end of the signal post-processing circuit is used as a signal output end of the signal generating device; the signal post-processing circuit is used to amplify, divide or multiply the loop phase-locked signal, and output the noise reduction processed signal obtained by the amplification, division or multiplication processing as an optimized signal.
  • the present invention provides a signal generation method for generating a low phase noise signal, characterized in that it is applied to the signal generation device as described in the first aspect, and the signal generation method comprises:
  • the loop phase-locked signal is amplified, divided or multiplied, and the noise reduction signal obtained by the amplification, division or multiplication is output as an optimized signal.
  • the mixing phase-locked loop circuit uses a mixer to build a mixing loop to compensate for the limitation of the fractional frequency division method by the fractional loop, and optimizes the spurious signal.
  • the signal generating device is not limited by the input and output signal frequency, can achieve an ultra-wideband input and output from low frequency to millimeter wave frequency band, and can be applied to a variety of radio frequency systems.
  • FIG1 is a structural block diagram of a signal generating device in an embodiment
  • FIG. 2 is a schematic flow chart of a signal generating method in an embodiment.
  • connection and “coupling” mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).
  • a signal generating circuit for generating a low phase noise signal generally uses a method of building a fractional loop by fractional frequency division to reduce the phase noise of the signal (see Chinese patent document with patent number CN201410245306.3, and the invention name is a device and method for generating an extremely low phase noise phase-trial reference signal).
  • the low phase noise performance reference generated by this signal generating circuit is limited by the fractional loop, and the usage scenarios are restricted.
  • the signal generated by the fractional frequency division will introduce spurious signals. Therefore, this method is not very applicable in some systems with high spurious requirements.
  • the signal generating circuit disclosed in the embodiment of the present application uses a mixer to build a mixing loop to compensate for the limitation of the fractional frequency division method by the fractional loop, thereby optimizing the spurious signal.
  • the signal generating circuit is not limited by the frequency of the input and output signals, and realizes an ultra-wideband input and output from low frequency to millimeter wave frequency band, thereby being applicable to a variety of radio frequency systems.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG1 is a structural block diagram of a signal generating device in an embodiment, wherein the signal generating device includes a signal preprocessing circuit 10, a mixing phase-locked loop circuit 20 and a signal post-processing circuit 30.
  • the signal preprocessing circuit 10 includes a first signal connection terminal and a second signal connection terminal, wherein the first signal connection terminal of the signal preprocessing circuit 10 is used as a signal input terminal of the signal generating device, and is used for inputting a preset signal to be optimized.
  • the second signal connection terminal of the signal preprocessing circuit 10 is connected to the mixing phase-locked loop circuit 20, and the signal preprocessing circuit 10 is used for frequency division or frequency multiplication of the signal to be optimized, and sending the preprocessed signal obtained after the frequency division or frequency multiplication to the mixing phase-locked loop circuit 20.
  • the mixing phase-locked loop circuit 20 includes a first connection terminal, a second connection terminal, a phase detector 21, a loop filter circuit 22, a voltage-controlled oscillator 23, a power divider 24, a mixer 25 and a first amplifier 26.
  • the first connection end of the mixer phase-locked loop circuit 20 is connected to the second signal connection end of the signal preprocessing circuit 10, and the second connection end of the mixer phase-locked loop circuit is connected to the signal post-processing circuit 30.
  • the mixer phase-locked loop circuit 20 is used to perform loop locking on the preprocessing signal, and send the loop phase-locked signal obtained by loop locking to the signal post-processing circuit 30.
  • the phase detector 21 includes a first signal input end, a second signal input end and a first phase-detection signal output end. The first signal input end of the phase detector 21 is connected to the first connection end of the mixer phase-locked loop circuit 20, the second signal input end of the phase detector 21 is connected to the first amplifier 26, and the first phase-detection signal output end of the phase detector 21 is connected to the loop filter circuit 22.
  • the loop filter circuit 22 includes a first connection end and a second connection end.
  • the first connection end of the loop filter circuit 22 is connected to the first phase-detection signal output end of the phase detector 21, and the second connection end of the loop filter circuit 22 is connected to the voltage-controlled oscillator 23.
  • the voltage controlled oscillator 23 includes a first connection end and a second connection end.
  • the first connection end of the voltage controlled oscillator 23 is connected to the second connection end of the loop filter circuit 22, and the second connection end of the voltage controlled oscillator 23 is connected to the power distributor 24.
  • the power distributor 24 includes a first power signal input end, a first power signal output end, and a second power signal output end.
  • the first power signal input end of the power distributor 24 is connected to the second connection end of the voltage controlled oscillator 23, the first power signal output end of the power distributor 24 is connected to the second connection end of the mixer phase locked loop circuit 20, and the second power signal output end of the power distributor 24 is connected to the mixer 25.
  • the mixer 25 includes a local oscillator signal input end, a signal input end to be mixed, and a mixing signal output end.
  • the local oscillator signal input end of the mixer 25 is used for inputting a preset local oscillator signal, the signal input end to be mixed of the mixer 25 is connected to the second power signal output end of the power distributor 24, and the mixing signal output end of the mixer 25 is connected to the first amplifier 26.
  • the first amplifier 26 includes a first connection end and a second connection end, the first connection end of the first amplifier 26 is connected to the mixing signal output end of the mixer 25, and the second connection end of the first amplifier 26 is connected to the second signal input end of the phase detector 21.
  • the signal post-processing circuit 30 includes a first signal connection end and a second signal connection end, the first signal connection end of the signal post-processing circuit 30 is connected to the second connection end of the mixer phase-locked loop circuit 20, and the second signal connection end of the signal post-processing circuit 30 is used as a signal output end of the signal generating device.
  • the signal post-processing circuit 30 is used to amplify, divide or multiply the loop phase-locked signal, and output the noise reduction signal obtained by the amplification, division or multiplication process as an optimized signal.
  • the signal preprocessing circuit 10 includes a first switching switch circuit 11, a second switching switch circuit 14, a first programmable frequency divider 12 and a first frequency multiplier 13.
  • the first switching switch circuit 11 includes a first connection end, a second connection end, a third connection end and a fourth connection end.
  • the first connection end of the first switching switch circuit 11 is connected to the first signal connection end of the signal preprocessing circuit 10, the second connection end of the first switching switch circuit 11 is connected to the first programmable frequency divider 12, the third connection end of the first switching switch circuit 10 is connected to the second switching switch circuit 14, and the fourth connection end of the first switching switch circuit 11 is connected to the first frequency multiplier 13.
  • the first switching switch circuit 11 is used to output the signal to be optimized to the second switching switch circuit, the first programmable frequency divider 12 or the first frequency multiplier 13.
  • the first programmable frequency divider 12 includes a first connection end and a second connection end. The first connection end of the first programmable frequency divider 12 is connected to the first connection end of the first switching switch circuit 11, and the second connection end of the first programmable frequency divider 12 is connected to the second switching switch circuit 14.
  • the first programmable frequency divider 12 is used to perform frequency division processing on the signal to be optimized.
  • the first frequency multiplier 13 includes a first connection end and a second connection end, the first connection end of the first frequency multiplier 13 is connected to the fourth connection end of the first switching circuit 11, and the second connection end of the first frequency multiplier 13 is connected to the second switching circuit 14.
  • the first frequency multiplier 13 is used to perform frequency multiplication processing on the signal to be optimized.
  • the second switching circuit 14 includes a first connection end, a second connection end, a third connection end and a fourth connection end, the first connection end of the second switching circuit 14 is connected to the second signal connection end of the signal preprocessing circuit 10, the second connection end of the second switching circuit 14 is connected to the first programmable frequency divider 12, the third connection end of the second switching circuit 14 is connected to the first switching circuit 11, and the fourth connection end of the second switching circuit 14 is connected to the first frequency multiplier 13.
  • the second switching circuit 14 is used to send the signal to be optimized output by the first switching circuit 11, the signal to be optimized after the frequency division processing by the first programmable frequency divider 12, or the signal to be optimized after the frequency multiplication processing by the first frequency multiplier 13 as a preprocessing signal to the mixing phase-locked loop circuit 20.
  • the signal post-processing circuit 30 includes a third switching switch circuit 31, a fourth switching switch circuit 35, a second programmable frequency divider 32, a second amplifier 33 and a second frequency multiplier 34.
  • the third switching switch circuit 31 includes a first connection end, a second connection end, a third connection end and a fourth connection end.
  • the first connection end of the third switching switch circuit 31 is connected to the first signal connection end of the signal post-processing circuit 30, the second connection end of the third switching switch circuit 31 is connected to the second programmable frequency divider 32, the third connection end of the third switching switch circuit 31 is connected to the second amplifier 33, and the fourth connection end of the third switching switch circuit 31 is connected to the second frequency multiplier 34.
  • the third switching switch circuit 31 is used to send the loop phase-locked signal 20 to the second programmable frequency divider 32, the second amplifier 33 or the second frequency multiplier 34.
  • the second programmable frequency divider 32 includes a first connection end and a second connection end. The first connection end of the second programmable frequency divider 32 is connected to the second connection end of the third switching switch circuit 31, and the second connection end of the second programmable frequency divider 32 is connected to the fourth switching switch circuit 35.
  • the second amplifier 33 includes a first connection terminal and a second connection terminal, the first connection terminal of the second amplifier 33 is connected to the third connection terminal of the third switch circuit 31, and the second connection terminal of the second amplifier 33 is connected to the fourth switch circuit 35.
  • the second frequency multiplier 34 includes a first connection terminal and a second connection terminal, the first connection terminal of the second frequency multiplier 34 is connected to the fourth connection terminal of the third switch circuit 31, and the second connection terminal of the second frequency multiplier 34 is connected to the fourth switch circuit 35.
  • the fourth switch circuit 35 includes a first connection terminal, a second connection terminal, a third connection terminal and a fourth connection terminal, the first connection terminal of the fourth switch circuit 35 is connected to the second signal connection terminal of the signal post-processing circuit 30, the second connection terminal of the fourth switch circuit 35 is connected to the second programmable frequency divider 32, the third connection terminal of the fourth switch circuit 35 is connected to the second amplifier 33, and the fourth connection terminal of the fourth switch circuit is connected to the second frequency multiplier 34.
  • the fourth switching circuit 35 is used to output the loop phase-locked signal divided by the second programmable frequency divider 32, the loop phase-locked signal amplified by the second amplifier 33, or the loop phase-locked signal multiplied by the second frequency multiplier 34 as an optimized signal.
  • the first switching switch circuit 11, the second switching switch circuit 14, the third switching switch circuit 31 and the fourth switching switch circuit 35 are three-select-one signal switching circuits.
  • the local oscillation signal is generated by a comb wave generating circuit or a comb wave generator.
  • the first programmable frequency divider 12 and the second programmable frequency divider 32 adopt a fractional frequency division mode and/or an integer frequency division mode.
  • the first phase detection signal output terminal of the phase detector 21 outputs a square wave signal.
  • the phase detection frequency of the phase detector is 50MHz.
  • the signal to be optimized is divided into three paths through the first switching switch circuit.
  • the signal higher than the phase detection frequency range of the phase detector is divided by the first programmable frequency divider and then sent to the phase detector through the second switching switch circuit.
  • the signal lower than the phase detection range of the phase detector is multiplied by the first frequency multiplier and then sent to the phase detector through the second switching switch circuit.
  • the signal within the phase detection frequency range of the phase detector is directly sent to the phase detector through the second switching switch circuit.
  • the phase detector (PFD) is connected to a loop filter (LF), and then to a voltage-controlled oscillator (VCO).
  • the voltage-controlled oscillator is connected to a power divider.
  • the power divider has two outputs, one of which is used as an RF signal input to the mixer.
  • the intermediate frequency signal after mixing is phase-detected by the first amplifier and the pre-processed signal; the other is given to the third switching switch circuit, which is used as the output signal of the signal generating device after being processed by the post-processing circuit.
  • the output is divided into three situations after the third switching switch circuit.
  • the first is directly output by the fourth switching switch circuit after being amplified by the second amplifier
  • the second is directly output by the fourth switching switch circuit after being divided by the second programmable divider
  • the third is directly output by the fourth switching switch circuit after being multiplied by the second multiplier.
  • the local oscillator signal LO of the mixer is generated by a comb wave generating circuit or a comb wave generator, and is obtained through frequency selection filtering to obtain a local oscillator signal with a lower phase noise level.
  • the local oscillator signal that can be obtained is (50*N)MHz (N is the order of the comb wave generating circuit or the comb wave generator, which is a positive integer); it can be constructed using a step recovery diode or an integrated chip.
  • the radio frequency signal RF end of the mixer is generated by a voltage-controlled oscillator (VCO) and obtained through a power divider.
  • the generated intermediate frequency signal IF is phase-detected with the pre-processed signal through amplifier 1. That is:
  • the preprocessed signal can be expressed as:
  • comb wave generating circuits or comb wave generators are selected to generate local oscillator signals, which can optimize different reference signal phase noise and spurious.
  • the local oscillator signal of the mixer is generated by the comb wave generating circuit and/or comb wave generator.
  • This comb wave generating circuit is not the protection point of the present invention, so it will not be described here.
  • phase noise theory :
  • Ideal frequency multipliers and dividers Using an ideal frequency multiplier to multiply the frequency of a signal by a factor of N increases the phase noise of the multiplied signal by 20lg(N)dB. Similarly, dividing the signal frequency by N reduces the phase noise of the output signal by 20lg(N)dB.
  • the sideband amplitude of the signal after N-frequency multiplication increases by N times, that is, by 20lg(N)dB.
  • the sideband offset from the carrier is the same as the original signal.
  • the sideband amplitude of the signal after N-frequency division is reduced by N times, that is, by 20lg(N)dB.
  • the sideband offset from the carrier is the same as the original signal.
  • phase noise after optimization is 20lg(N)dBc/Hz lower than the phase noise to be optimized.
  • the sideband amplitude of the spurious signal is reduced by 20lg (N) dB, and the frequency deviation is the same as the original signal.
  • a phase-locked loop circuit can be obtained, which can output various required frequency ranges without changing the phase noise and spurious of the signal.
  • FIG2 is a flow chart of a signal generation method in an embodiment, wherein the signal generation method is applied to the signal generation device as described above to generate a low phase noise signal.
  • the signal generation method includes:
  • Step 100 Obtain a preprocessed signal.
  • the signal to be optimized is processed by frequency division or frequency multiplication to obtain a preprocessed signal.
  • Step 200 obtaining a loop phase-locked signal.
  • the pre-processed signal is loop locked to obtain a loop phase-locked signal.
  • the loop phase-locked signal is a square wave signal converted from a sine wave.
  • Step 300 outputting the optimized signal.
  • the loop phase-locked signal is amplified, divided or multiplied, and the noise reduction signal obtained by the amplification, division or multiplication is output as an optimized signal.
  • the output range of the voltage-controlled oscillator VCO is set to 1-2G; the phase detector frequency range is 10M-1300M.
  • the phase detector In order to obtain the best phase noise, the phase detector generally uses square waves and low frequencies for phase detection; the local oscillator signal is generated by a comb wave generator according to different usage scenarios, and then obtained through frequency selection filtering.
  • the phase noise is optimized by 20lg40dB, that is, 32dB.
  • the signal reaching the phase detector is 50M, and the phase noise at the offset of 100KHz is -162dBc/Hz.
  • the output signal of the voltage-controlled oscillator VCO is 2000MHz, and the phase noise at the offset of 100KHz is -162dBc/Hz.
  • the phase noise of the signal is optimized by 32dB, and the spurious signal is also optimized by 32dB.
  • the phase noise deteriorates by 20lg50dB, that is, deteriorates by 34dB.
  • the signal reaching the phase detector is 50M, and the phase noise at the offset of 100KHz is -101dBc/Hz.
  • the output signal of the voltage-controlled oscillator VCO is 1000MHz, and the phase noise at the offset of 100KHz is -101dBc/Hz.
  • the noise is -101dBc/Hz.
  • the phase noise of the signal is optimized by 20lg1000dB, that is, 60dB.
  • the output signal is 1MHz, and the phase noise at an offset of 100KHz is -161dBc/Hz.
  • the phase noise at an offset of 100KHz is -135dBc/Hz, which is optimized by 26dB.
  • the spurious signal is also optimized by 26dB.
  • the output signal is 50M
  • the phase noise at the offset of 100KHz is -167dBc/Hz, which is 32 dB optimized compared to the input signal of 50MHz and the phase noise at the offset of 100KHz is -135dBc/Hz.
  • the spurious signal is also optimized by 32 dB.
  • the first programmable frequency divider and the second programmable frequency divider both work in integer mode, and the input and output frequencies are the same.
  • the programmable frequency divider has no fractional frequency division spurs, but the obtainable frequency is relatively fixed. If you want to get any output frequency, there are two methods. One is to use the fractional frequency division mode of the programmable frequency divider. In this mode, fractional frequency division spurs will be introduced. If the fractional frequency division spurs can be accepted, this method can also be used. The other is to use different input and output frequencies. Using the programmable frequency divider integer division method, a series of input and output frequencies can be designed to cover the required frequencies. The signal spurious obtained by this method is better.
  • the signal generating device disclosed in the embodiment of the present application includes a signal preprocessing circuit, a mixing phase-locked loop circuit and a signal post-processing circuit.
  • the signal preprocessing circuit is used to perform frequency division or frequency multiplication processing on the signal to be optimized to obtain a preprocessed signal.
  • the mixing phase-locked loop circuit is used to perform loop locking on the preprocessed signal to obtain a loop phase-locked signal.
  • the signal post-processing circuit is used to amplify, divide or multiply the loop phase-locked signal, and output the obtained noise reduction processed signal as an optimized signal.
  • the mixing phase-locked loop circuit uses a mixer to build a mixing loop to compensate for the limitation of the fractional frequency division method by the fractional loop, and optimizes the spurious of the signal.
  • the signal generating device is not limited by the frequency of the input and output signals, and can achieve an ultra-wideband input and output from low frequency to millimeter wave frequency band, and can be applied to a variety of radio frequency systems.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Disclosed in the present application are a signal generation apparatus and method for generating a low-phase noise signal. The signal generation apparatus comprises a signal preprocessing circuit, a frequency mixing phase-locked loop circuit and a signal post-processing circuit, wherein the signal preprocessing circuit is used for performing frequency division or frequency multiplication processing on a signal to be optimized, so as to acquire a preprocessed signal, the frequency mixing phase-locked loop circuit is used for performing loop locking on the preprocessed signal, so as to acquire a loop phase-locked signal, and the signal post-processing circuit is used for performing amplification, frequency division or frequency multiplication processing on the loop phase-locked signal, and outputting an acquired denoised signal as an optimized signal. In the frequency mixing phase-locked loop circuit, a frequency mixing loop is built using a frequency mixer, so as to compensate for the limitation of a decimal loop on a fractional frequency division method, and optimize the stray of a signal. The signal generation apparatus is not limited by the frequency of an input/output signal, can achieve an ultra-wideband input/output from a low frequency to a millimeter-wave frequency band, and can be suitable for multiple radio frequency systems.

Description

用于产生低相位噪声信号的信号发生装置和信号发生方法Signal generating device and signal generating method for generating low phase noise signal 技术领域Technical Field
本发明涉及微波及毫米波技术领域，具体涉及一种用于产生低相位噪声信号的信号发生装置和信号发生方法。The present invention relates to the field of microwave and millimeter wave technology, and in particular to a signal generating device and a signal generating method for generating a low phase noise signal.
背景技术Background technique
在现代微波毫米波***中，相位噪声是发射机和接收机的一个重要参数指标。相位噪声的大小可以反映出射频***的优劣，在设计和使用射频***时，要注意相位噪声对射频***的影响，相位噪声越小，射频***性能越好。而整个射频***的相位噪声受到锁相环输出信号相位噪声的限制；在混频锁相环电路中，锁相环输出信号的相位噪声的大小受到参考信号相位噪声的限制。因此，要提高整个射频***的相位噪声，首先需要产生一个相噪指标好的信号。In modern microwave and millimeter wave systems, phase noise is an important parameter indicator for transmitters and receivers. The size of phase noise can reflect the quality of the RF system. When designing and using the RF system, attention should be paid to the impact of phase noise on the RF system. The smaller the phase noise, the better the performance of the RF system. The phase noise of the entire RF system is limited by the phase noise of the phase-locked loop output signal; in the mixer phase-locked loop circuit, the size of the phase noise of the phase-locked loop output signal is limited by the phase noise of the reference signal. Therefore, to improve the phase noise of the entire RF system, it is first necessary to generate a signal with good phase noise indicators.
技术问题technical problem
本发明主要解决的技术问题是如何产生相位噪声指标较低的信号。The main technical problem solved by the present invention is how to generate a signal with a lower phase noise index.
技术解决方案Technical Solutions
根据第一方面，本发明提供了一种用于产生低相位噪声信号的信号发生装置，包括信号预处理电路、混频锁相环电路和信号后处理电路；According to a first aspect, the present invention provides a signal generating device for generating a low phase noise signal, comprising a signal preprocessing circuit, a mixer phase-locked loop circuit and a signal post-processing circuit;
所述信号预处理电路包括第一信号连接端和第二信号连接端；所述信号预处理电路的第一信号连接端用于作为所述信号发生装置的信号输入端，用于一预设的待优化信号的输入；所述信号预处理电路的第二信号连接端与所述混频锁相环电路连接；所述信号预处理电路用于对所述待优化信号进行分频或倍频处理，并将分频或倍频处理后获取的预处理信号发送给所述混频锁相环电路；The signal preprocessing circuit comprises a first signal connection terminal and a second signal connection terminal; the first signal connection terminal of the signal preprocessing circuit is used as a signal input terminal of the signal generating device, and is used for inputting a preset signal to be optimized; the second signal connection terminal of the signal preprocessing circuit is connected to the mixer phase-locked loop circuit; the signal preprocessing circuit is used to perform frequency division or frequency multiplication processing on the signal to be optimized, and send the preprocessed signal obtained after the frequency division or frequency multiplication processing to the mixer phase-locked loop circuit;
所述混频锁相环电路包括第一连接端、第二连接端、鉴相器、环路滤波电路、压控振荡器、功率分配器、混频器和第一放大器；所述混频锁相环电路的第一连接端与所述信号预处理电路的第二信号连接端连接，所述混频锁相环电路的第二连接端与所述信号后处理电路连接，所述混频锁相环电路用于对所述预处理信号进行环路锁定，并将环路锁定获取的环路锁相信号发送给所述信号后处理电路；The mixing phase-locked loop circuit includes a first connection end, a second connection end, a phase detector, a loop filter circuit, a voltage-controlled oscillator, a power divider, a mixer and a first amplifier; the first connection end of the mixing phase-locked loop circuit is connected to the second signal connection end of the signal preprocessing circuit, the second connection end of the mixing phase-locked loop circuit is connected to the signal post-processing circuit, and the mixing phase-locked loop circuit is used to perform loop locking on the pre-processing signal, and send the loop phase-locked signal obtained by loop locking to the signal post-processing circuit;
所述鉴相器包括第一信号输入端、第二信号输入端和第一鉴相信号输出端，所述鉴相器的第一信号输入端与所述混频锁相环电路的第一连接端连接，所述鉴相器的第二信号输入端与所述第一放大器连接，所述鉴相器的第一鉴相信号输出端与所述环路滤波电路连接；The phase detector comprises a first signal input terminal, a second signal input terminal and a first phase detection signal output terminal, the first signal input terminal of the phase detector is connected to the first connection terminal of the mixer phase-locked loop circuit, the second signal input terminal of the phase detector is connected to the first amplifier, and the first phase detection signal output terminal of the phase detector is connected to the loop filter circuit;
所述环路滤波电路包括第一连接端和第二连接端，所述环路滤波电路的第一连接端与所述鉴相器的第一鉴相信号输出端连接，所述环路滤波电路的第二连接端与所述压控振荡器连接；The loop filter circuit comprises a first connection end and a second connection end, the first connection end of the loop filter circuit is connected to the first phase detection signal output end of the phase detector, and the second connection end of the loop filter circuit is connected to the voltage controlled oscillator;
所述压控振荡器包括第一连接端和第二连接端，所述压控振荡器的第一连接端与所述环路滤波电路的第二连接端连接，所述压控振荡器的第二连接端与所述功率分配器连接；The voltage controlled oscillator comprises a first connection end and a second connection end, the first connection end of the voltage controlled oscillator is connected to the second connection end of the loop filter circuit, and the second connection end of the voltage controlled oscillator is connected to the power distributor;
所述功率分配器包括第一功率信号输入端、第一功率信号输出端和第二功率信号输出端，所述功率分配器的第一功率信号输入端与所述压控振荡器的第二连接端连接，所述功率分配器的第一功率信号输出端与所述混频锁相环电路的第二连接端连接，所述功率分配器的第二功率信号输出端与所述混频器连接；The power divider comprises a first power signal input terminal, a first power signal output terminal and a second power signal output terminal, the first power signal input terminal of the power divider is connected to the second connection terminal of the voltage-controlled oscillator, the first power signal output terminal of the power divider is connected to the second connection terminal of the mixer phase-locked loop circuit, and the second power signal output terminal of the power divider is connected to the mixer;
所述混频器包括本振信号输入端、待混频信号输入端和混频信号输出端，所述混频器的本振信号输入端用于一预设的本振信号的输入，所述混频器的待混频信号输入端与所述功率分配器的第二功率信号输出端连接，所述混频器的混频信号输出端与所述第一放大器连接；The mixer comprises a local oscillator signal input terminal, a signal input terminal for mixing and a mixing signal output terminal, wherein the local oscillator signal input terminal of the mixer is used for inputting a preset local oscillator signal, the signal input terminal for mixing of the mixer is connected to the second power signal output terminal of the power divider, and the mixing signal output terminal of the mixer is connected to the first amplifier;
所述第一放大器包括第一连接端和第二连接端，所述第一放大器的第一连接端与所述混频器的混频信号输出端连接，所述第一放大器的第二连接端与所述鉴相器的第二信号输入端连接；The first amplifier comprises a first connection end and a second connection end, the first connection end of the first amplifier is connected to the mixing signal output end of the mixer, and the second connection end of the first amplifier is connected to the second signal input end of the phase detector;
所述信号后处理电路包括第一信号连接端和第二信号连接端；所述信号后处理电路的第一信号连接端与所述混频锁相环电路的第二连接端连接，所述信号后处理电路的第二信号连接端用于作为所述信号发生装置的信号输出端；所述信号后处理电路用于对所述环路锁相信号进行放大、分频或倍频处理，并将放大、分频或倍频处理获取的降噪处理信号作为优化后信号输出。The signal post-processing circuit includes a first signal connection end and a second signal connection end; the first signal connection end of the signal post-processing circuit is connected to the second connection end of the mixing phase-locked loop circuit, and the second signal connection end of the signal post-processing circuit is used as a signal output end of the signal generating device; the signal post-processing circuit is used to amplify, divide or multiply the loop phase-locked signal, and output the noise reduction processed signal obtained by the amplification, division or multiplication processing as an optimized signal.
根据第二方面，本发明提供了一种用于产生低相位噪声信号的信号发生方法，其特征在于，应用于如第一方面所述的信号发生装置，所述信号发生方法包括：According to a second aspect, the present invention provides a signal generation method for generating a low phase noise signal, characterized in that it is applied to the signal generation device as described in the first aspect, and the signal generation method comprises:
对待优化信号进行分频或倍频处理，以获取预处理信号；Perform frequency division or frequency multiplication processing on the signal to be optimized to obtain a preprocessed signal;
对所述预处理信号进行环路锁定，以获取环路锁相信号；Loop locking the preprocessed signal to obtain a loop phase-locked signal;
对所述环路锁相信号进行放大、分频或倍频处理，并将放大、分频或倍频处理获取的降噪处理信号作为优化后信号输出。The loop phase-locked signal is amplified, divided or multiplied, and the noise reduction signal obtained by the amplification, division or multiplication is output as an optimized signal.
有益效果Beneficial Effects
上述实施例中提供的信号发生装置，其中混频锁相环电路是利用混频器搭建混频环来弥补小数分频的方法受到小数环的限制，优化信号的杂散。该信号发生装置不受输入输出的信号频率限制，可以实现低频到毫米波频段的一个超宽带输入输出，可以适用于多种射频***中。In the signal generating device provided in the above embodiment, the mixing phase-locked loop circuit uses a mixer to build a mixing loop to compensate for the limitation of the fractional frequency division method by the fractional loop, and optimizes the spurious signal. The signal generating device is not limited by the input and output signal frequency, can achieve an ultra-wideband input and output from low frequency to millimeter wave frequency band, and can be applied to a variety of radio frequency systems.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为一种实施例中信号发生装置的结构框图；FIG1 is a structural block diagram of a signal generating device in an embodiment;
图2为一种实施例中信号发生方法的流程示意图。FIG. 2 is a schematic flow chart of a signal generating method in an embodiment.
本发明的实施方式Embodiments of the present invention
下面通过具体实施方式结合附图对本发明作进一步详细说明。其中不同实施方式中类似元件采用了相关联的类似的元件标号。在以下的实施方式中，很多细节描述是为了使得本申请能被更好的理解。然而，本领域技术人员可以毫不费力的认识到，其中部分特征在不同情况下是可以省略的，或者可以由其他元件、材料、方法所替代。在某些情况下，本申请相关的一些操作并没有在说明书中显示或者描述，这是为了避免本申请的核心部分被过多的描述所淹没，而对于本领域技术人员而言，详细描述这些相关操作并不是必要的，他们根据说明书中的描述以及本领域的一般技术知识即可完整了解相关操作。The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.
另外，说明书中所描述的特点、操作或者特征可以以任意适当的方式结合形成各种实施方式。同时，方法描述中的各步骤或者动作也可以按照本领域技术人员所能显而易见的方式进行顺序调换或调整。因此，说明书和附图中的各种顺序只是为了清楚描述某一个实施例，并不意味着是必须的顺序，除非另有说明其中某个顺序是必须遵循的。In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.
本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本申请所说“连接”、“联接”，如无特别说明，均包括直接和间接连接（联接）。The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).
现有技术中，用于产生低相位噪声信号的信号发生电路一般是利用小数分频搭建小数环的方法来降低信号的相位噪声的（参见专利号为CN201410245306.3，发明名称为一种极低相位噪声鉴相参考信号的生成装置和方法的中文专利文献），该种信号发生电路产生的低相位噪声性能参考受到小数环的限制，使用场景受限，同时小数分频产生的信号会引入杂散，因此，这种方法在某些对杂散要求很高的***中也不太适用。In the prior art, a signal generating circuit for generating a low phase noise signal generally uses a method of building a fractional loop by fractional frequency division to reduce the phase noise of the signal (see Chinese patent document with patent number CN201410245306.3, and the invention name is a device and method for generating an extremely low phase noise phase-trial reference signal). The low phase noise performance reference generated by this signal generating circuit is limited by the fractional loop, and the usage scenarios are restricted. At the same time, the signal generated by the fractional frequency division will introduce spurious signals. Therefore, this method is not very applicable in some systems with high spurious requirements.
在本申请实施例中公开的信号发生电路，利用混频器来搭建混频环来弥补小数分频的方法受到小数环的限制，进而可以优化信号的杂散。同时，该信号发生电路可以不受输入输出信号的频率限制，实现低频到毫米波频段的一个超宽带输入输出，进而能适用于多种射频***中。The signal generating circuit disclosed in the embodiment of the present application uses a mixer to build a mixing loop to compensate for the limitation of the fractional frequency division method by the fractional loop, thereby optimizing the spurious signal. At the same time, the signal generating circuit is not limited by the frequency of the input and output signals, and realizes an ultra-wideband input and output from low frequency to millimeter wave frequency band, thereby being applicable to a variety of radio frequency systems.
实施例一：Embodiment 1:
请参考图1，为一种实施例中信号发生装置的结构框图，信号发生装置包括信号预处理电路10、混频锁相环电路20和信号后处理电路30。信号预处理电路10包括第一信号连接端和第二信号连接端，信号预处理电路10的第一信号连接端用于作为信号发生装置的信号输入端，用于一预设的待优化信号的输入。信号预处理电路10的第二信号连接端与混频锁相环电路20连接，信号预处理电路10用于对待优化信号进行分频或倍频处理，并将分频或倍频处理后获取的预处理信号发送给混频锁相环电路20。混频锁相环电路20包括第一连接端、第二连接端、鉴相器21、环路滤波电路22、压控振荡器23、功率分配器24、混频器25和第一放大器26。混频锁相环电路20的第一连接端与信号预处理电路10的第二信号连接端连接，混频锁相环电路的第二连接端与信号后处理电路30连接，混频锁相环电路20用于对预处理信号进行环路锁定，并将环路锁定获取的环路锁相信号发送给信号后处理电路30。鉴相器21包括第一信号输入端、第二信号输入端和第一鉴相信号输出端，鉴相器21的第一信号输入端与混频锁相环电路20的第一连接端连接，鉴相器21的第二信号输入端与第一放大器26连接，鉴相器21的第一鉴相信号输出端与环路滤波电路22连接。环路滤波电路22包括第一连接端和第二连接端，环路滤波电路22的第一连接端与鉴相器21的第一鉴相信号输出端连接，环路滤波电路22的第二连接端与压控振荡器23连接。压控振荡器23包括第一连接端和第二连接端，压控振荡器23的第一连接端与环路滤波电路22的第二连接端连接，压控振荡器23的第二连接端与功率分配器24连接。功率分配器24包括第一功率信号输入端、第一功率信号输出端和第二功率信号输出端，功率分配器24的第一功率信号输入端与压控振荡器23的第二连接端连接，功率分配器24的第一功率信号输出端与混频锁相环电路20的第二连接端连接，功率分配器24的第二功率信号输出端与混频器25连接。混频器25包括本振信号输入端、待混频信号输入端和混频信号输出端，混频器25的本振信号输入端用于一预设的本振信号的输入，混频器25的待混频信号输入端与功率分配器24的第二功率信号输出端连接，混频器25的混频信号输出端与第一放大器26连接。第一放大器26包括第一连接端和第二连接端，第一放大器26的第一连接端与混频器25的混频信号输出端连接，第一放大器26的第二连接端与鉴相21器的第二信号输入端连接。信号后处理电路30包括第一信号连接端和第二信号连接端，信号后处理电路30的第一信号连接端与混频锁相环电路20的第二连接端连接，信号后处理电路30的第二信号连接端用于作为信号发生装置的信号输出端。信号后处理电路30用于对环路锁相信号进行放大、分频或倍频处理，并将放大、分频或倍频处理获取的降噪处理信号作为优化后信号输出。Please refer to FIG1, which is a structural block diagram of a signal generating device in an embodiment, wherein the signal generating device includes a signal preprocessing circuit 10, a mixing phase-locked loop circuit 20 and a signal post-processing circuit 30. The signal preprocessing circuit 10 includes a first signal connection terminal and a second signal connection terminal, wherein the first signal connection terminal of the signal preprocessing circuit 10 is used as a signal input terminal of the signal generating device, and is used for inputting a preset signal to be optimized. The second signal connection terminal of the signal preprocessing circuit 10 is connected to the mixing phase-locked loop circuit 20, and the signal preprocessing circuit 10 is used for frequency division or frequency multiplication of the signal to be optimized, and sending the preprocessed signal obtained after the frequency division or frequency multiplication to the mixing phase-locked loop circuit 20. The mixing phase-locked loop circuit 20 includes a first connection terminal, a second connection terminal, a phase detector 21, a loop filter circuit 22, a voltage-controlled oscillator 23, a power divider 24, a mixer 25 and a first amplifier 26. The first connection end of the mixer phase-locked loop circuit 20 is connected to the second signal connection end of the signal preprocessing circuit 10, and the second connection end of the mixer phase-locked loop circuit is connected to the signal post-processing circuit 30. The mixer phase-locked loop circuit 20 is used to perform loop locking on the preprocessing signal, and send the loop phase-locked signal obtained by loop locking to the signal post-processing circuit 30. The phase detector 21 includes a first signal input end, a second signal input end and a first phase-detection signal output end. The first signal input end of the phase detector 21 is connected to the first connection end of the mixer phase-locked loop circuit 20, the second signal input end of the phase detector 21 is connected to the first amplifier 26, and the first phase-detection signal output end of the phase detector 21 is connected to the loop filter circuit 22. The loop filter circuit 22 includes a first connection end and a second connection end. The first connection end of the loop filter circuit 22 is connected to the first phase-detection signal output end of the phase detector 21, and the second connection end of the loop filter circuit 22 is connected to the voltage-controlled oscillator 23. The voltage controlled oscillator 23 includes a first connection end and a second connection end. The first connection end of the voltage controlled oscillator 23 is connected to the second connection end of the loop filter circuit 22, and the second connection end of the voltage controlled oscillator 23 is connected to the power distributor 24. The power distributor 24 includes a first power signal input end, a first power signal output end, and a second power signal output end. The first power signal input end of the power distributor 24 is connected to the second connection end of the voltage controlled oscillator 23, the first power signal output end of the power distributor 24 is connected to the second connection end of the mixer phase locked loop circuit 20, and the second power signal output end of the power distributor 24 is connected to the mixer 25. The mixer 25 includes a local oscillator signal input end, a signal input end to be mixed, and a mixing signal output end. The local oscillator signal input end of the mixer 25 is used for inputting a preset local oscillator signal, the signal input end to be mixed of the mixer 25 is connected to the second power signal output end of the power distributor 24, and the mixing signal output end of the mixer 25 is connected to the first amplifier 26. The first amplifier 26 includes a first connection end and a second connection end, the first connection end of the first amplifier 26 is connected to the mixing signal output end of the mixer 25, and the second connection end of the first amplifier 26 is connected to the second signal input end of the phase detector 21. The signal post-processing circuit 30 includes a first signal connection end and a second signal connection end, the first signal connection end of the signal post-processing circuit 30 is connected to the second connection end of the mixer phase-locked loop circuit 20, and the second signal connection end of the signal post-processing circuit 30 is used as a signal output end of the signal generating device. The signal post-processing circuit 30 is used to amplify, divide or multiply the loop phase-locked signal, and output the noise reduction signal obtained by the amplification, division or multiplication process as an optimized signal.
一实施例中，信号预处理电路10包括第一切换开关电路11、第二切换开关电路14、第一可编程分频器12和第一倍频器13。第一切换开关电路11包括第一连接端、第二连接端、第三连接端和第四连接端，第一切换开关电路11的第一连接端与信号预处理电路10的第一信号连接端连接，第一切换开关电路11的第二连接端与第一可编程分频器12连接，第一切换开关电路10的第三连接端与第二切换开关电路14连接，第一切换开关电路11的第四连接端与第一倍频器13连接。第一切换开关电路11用于将待优化信号输出给第二切换开关电路、第一可编程分频器12或第一倍频器13。第一可编程分频器12包括第一连接端和第二连接端，第一可编程分频器12的第一连接端与第一切换开关电路11的第一连接端连接，第一可编程分频器12的第二连接端与第二切换开关电路14连接。第一可编程分频器12用于对待优化信号进行分频处理。第一倍频器13包括第一连接端和第二连接端，第一倍频器13的第一连接端与第一切换开关电路11的第四连接端连接，第一倍频器13的第二连接端与第二切换开关电路14连接。第一倍频器13用于对待优化信号进行倍频处理。第二切换开关电路14包括第一连接端、第二连接端、第三连接端和第四连接端，第二切换开关电路14的第一连接端与信号预处理电路10的第二信号连接端连接，第二切换开关电路14的第二连接端与第一可编程分频器12，第二切换开关电路14的第三连接端与第一切换开关电路11连接，第二切换开关电路14的第四连接端与第一倍频器13连接。第二切换开关电路14用于将第一切换开关电路11输出的待优化信号、经第一可编程分频器12分频处理后的待优化信号或经第一倍频器13倍频处理的待优化信号作为预处理信号发送给混频锁相环电路20。In one embodiment, the signal preprocessing circuit 10 includes a first switching switch circuit 11, a second switching switch circuit 14, a first programmable frequency divider 12 and a first frequency multiplier 13. The first switching switch circuit 11 includes a first connection end, a second connection end, a third connection end and a fourth connection end. The first connection end of the first switching switch circuit 11 is connected to the first signal connection end of the signal preprocessing circuit 10, the second connection end of the first switching switch circuit 11 is connected to the first programmable frequency divider 12, the third connection end of the first switching switch circuit 10 is connected to the second switching switch circuit 14, and the fourth connection end of the first switching switch circuit 11 is connected to the first frequency multiplier 13. The first switching switch circuit 11 is used to output the signal to be optimized to the second switching switch circuit, the first programmable frequency divider 12 or the first frequency multiplier 13. The first programmable frequency divider 12 includes a first connection end and a second connection end. The first connection end of the first programmable frequency divider 12 is connected to the first connection end of the first switching switch circuit 11, and the second connection end of the first programmable frequency divider 12 is connected to the second switching switch circuit 14. The first programmable frequency divider 12 is used to perform frequency division processing on the signal to be optimized. The first frequency multiplier 13 includes a first connection end and a second connection end, the first connection end of the first frequency multiplier 13 is connected to the fourth connection end of the first switching circuit 11, and the second connection end of the first frequency multiplier 13 is connected to the second switching circuit 14. The first frequency multiplier 13 is used to perform frequency multiplication processing on the signal to be optimized. The second switching circuit 14 includes a first connection end, a second connection end, a third connection end and a fourth connection end, the first connection end of the second switching circuit 14 is connected to the second signal connection end of the signal preprocessing circuit 10, the second connection end of the second switching circuit 14 is connected to the first programmable frequency divider 12, the third connection end of the second switching circuit 14 is connected to the first switching circuit 11, and the fourth connection end of the second switching circuit 14 is connected to the first frequency multiplier 13. The second switching circuit 14 is used to send the signal to be optimized output by the first switching circuit 11, the signal to be optimized after the frequency division processing by the first programmable frequency divider 12, or the signal to be optimized after the frequency multiplication processing by the first frequency multiplier 13 as a preprocessing signal to the mixing phase-locked loop circuit 20.
一实施例中，信号后处理电路30包括第三切换开关电路31、第四切换开关电路35、第二可编程分频器32、第二放大器33和第二倍频器34。第三切换开关电路31包括第一连接端、第二连接端、第三连接端和第四连接端，第三切换开关电路31的第一连接端与信号后处理电路30的第一信号连接端连接，第三切换开关电路31的第二连接端与第二可编程分频器32连接，第三切换开关电路31的第三连接端与第二放大器33连接，第三切换开关电路31的第四接端与第二倍频器34连接。第三切换开关电路31用于将环路锁相信号20发送给第二可编程分频器32、第二放大器33或第二倍频器34。第二可编程分频器32包括第一连接端和第二连接端，第二可编程分频器32的第一连接端与第三切换开关电路31的第二连接端连接，第二可编程分频器32的第二连接端与第四切换开关电路35连接。第二放大器33包括第一连接端和第二连接端，第二放大器33的第一连接端与第三切换开关电路31的第三连接端连接，第二放大器33的第二连接端与第四切换开关电路35连接。第二倍频器34包括第一连接端和第二连接端，第二倍频器34的第一连接端与第三切换开关电路31的第四连接端连接，第二倍频器34的第二连接端与第四切换开关电路35连接。第四切换开关电路35包括第一连接端、第二连接端、第三连接端和第四连接端，第四切换开关电路35的第一连接端与信号后处理电路30的第二信号连接端连接，第四切换开关电路35的第二连接端与第二可编程分频器32，第四切换开关电路35的第三连接端与第二放大器33连接，第四切换开关电路的第四接端与第二倍频器34连接。第四切换开关电路35用于将经第二可编程分频器32分频处理的环路锁相信号、经第二放大器33放大处理的环路锁相信号或经第二倍频器34倍频处理后的环路锁相信号作为优化后信号输出。In one embodiment, the signal post-processing circuit 30 includes a third switching switch circuit 31, a fourth switching switch circuit 35, a second programmable frequency divider 32, a second amplifier 33 and a second frequency multiplier 34. The third switching switch circuit 31 includes a first connection end, a second connection end, a third connection end and a fourth connection end. The first connection end of the third switching switch circuit 31 is connected to the first signal connection end of the signal post-processing circuit 30, the second connection end of the third switching switch circuit 31 is connected to the second programmable frequency divider 32, the third connection end of the third switching switch circuit 31 is connected to the second amplifier 33, and the fourth connection end of the third switching switch circuit 31 is connected to the second frequency multiplier 34. The third switching switch circuit 31 is used to send the loop phase-locked signal 20 to the second programmable frequency divider 32, the second amplifier 33 or the second frequency multiplier 34. The second programmable frequency divider 32 includes a first connection end and a second connection end. The first connection end of the second programmable frequency divider 32 is connected to the second connection end of the third switching switch circuit 31, and the second connection end of the second programmable frequency divider 32 is connected to the fourth switching switch circuit 35. The second amplifier 33 includes a first connection terminal and a second connection terminal, the first connection terminal of the second amplifier 33 is connected to the third connection terminal of the third switch circuit 31, and the second connection terminal of the second amplifier 33 is connected to the fourth switch circuit 35. The second frequency multiplier 34 includes a first connection terminal and a second connection terminal, the first connection terminal of the second frequency multiplier 34 is connected to the fourth connection terminal of the third switch circuit 31, and the second connection terminal of the second frequency multiplier 34 is connected to the fourth switch circuit 35. The fourth switch circuit 35 includes a first connection terminal, a second connection terminal, a third connection terminal and a fourth connection terminal, the first connection terminal of the fourth switch circuit 35 is connected to the second signal connection terminal of the signal post-processing circuit 30, the second connection terminal of the fourth switch circuit 35 is connected to the second programmable frequency divider 32, the third connection terminal of the fourth switch circuit 35 is connected to the second amplifier 33, and the fourth connection terminal of the fourth switch circuit is connected to the second frequency multiplier 34. The fourth switching circuit 35 is used to output the loop phase-locked signal divided by the second programmable frequency divider 32, the loop phase-locked signal amplified by the second amplifier 33, or the loop phase-locked signal multiplied by the second frequency multiplier 34 as an optimized signal.
一实施例中，第一切换开关电路11、第二切换开关电路14、第三切换开关电路31和第四切换开关电路35为三选一信号开关电路。一实施例中，本振信号由梳状波发生电路或梳状波发生器产生。一实施例中，第一可编程分频器12和第二可编程分频器32采用小数分频模式和/或采用整数分频模式。一实施例中，鉴相器21的第一鉴相信号输出端输出的是方波信号。一实施例中，鉴相器的鉴相频率是50MHz。In one embodiment, the first switching switch circuit 11, the second switching switch circuit 14, the third switching switch circuit 31 and the fourth switching switch circuit 35 are three-select-one signal switching circuits. In one embodiment, the local oscillation signal is generated by a comb wave generating circuit or a comb wave generator. In one embodiment, the first programmable frequency divider 12 and the second programmable frequency divider 32 adopt a fractional frequency division mode and/or an integer frequency division mode. In one embodiment, the first phase detection signal output terminal of the phase detector 21 outputs a square wave signal. In one embodiment, the phase detection frequency of the phase detector is 50MHz.
在本申请实施例中，待优化信号经过第一切换开关电路分成三路，高于鉴相器鉴相频率范围的信号通过第一可编程分频器分频后经过第二切换开关电路发送给到鉴相器，低于鉴相器鉴相范围的信号通过第一倍频器倍频处理后经过第二切换开关电路发送给鉴相器，在鉴相器鉴相频率范围内的信号直通经过第二切换开关电路发送给鉴相器。鉴相器(PFD)后接一个环路滤波器(LF)，之后接一个压控振荡器(VCO)，压控振荡器之后接功率分配器，功率分配器有两路输出，一路给混频器当RF信号输入，混频后的中频信号经过第一放大器与预处理信号进行鉴相；一路给到第三切换开关电路，用于后处理电路处理后当信号发生装置的输出信号。经过第三切换开关电路分三种情况输出，第一种经过第二放大器放大后由第四切换开关电路直接输出，第二种经过第二可编程分频器分频处理后由第四切换开关电路直接输出，第三种经过第二倍频器倍频处理后由第四切换开关电路直接输出。In the embodiment of the present application, the signal to be optimized is divided into three paths through the first switching switch circuit. The signal higher than the phase detection frequency range of the phase detector is divided by the first programmable frequency divider and then sent to the phase detector through the second switching switch circuit. The signal lower than the phase detection range of the phase detector is multiplied by the first frequency multiplier and then sent to the phase detector through the second switching switch circuit. The signal within the phase detection frequency range of the phase detector is directly sent to the phase detector through the second switching switch circuit. The phase detector (PFD) is connected to a loop filter (LF), and then to a voltage-controlled oscillator (VCO). The voltage-controlled oscillator is connected to a power divider. The power divider has two outputs, one of which is used as an RF signal input to the mixer. The intermediate frequency signal after mixing is phase-detected by the first amplifier and the pre-processed signal; the other is given to the third switching switch circuit, which is used as the output signal of the signal generating device after being processed by the post-processing circuit. The output is divided into three situations after the third switching switch circuit. The first is directly output by the fourth switching switch circuit after being amplified by the second amplifier, the second is directly output by the fourth switching switch circuit after being divided by the second programmable divider, and the third is directly output by the fourth switching switch circuit after being multiplied by the second multiplier.
一实施例中，混频器的本振信号LO由梳状波发生电路或梳状波发生器产生，经过选频滤波得到，可以获得较低相噪水平的本振信号，如果梳状波发生电路或梳状波发生器输入为50MHz，可以得到的本振信号即为(50*N)MHz（N为梳状波发生电路或梳状波发生器的阶数，是一个正整数）；可以采用阶跃恢复二极管来搭建，也可以采用集成的芯片来实现。混频器的射频信号RF端由压控振荡器(VCO)产生，经过功率分配器得到，产生的中频信号IF经过放大器1与预处理信号进行鉴相。即有：In one embodiment, the local oscillator signal LO of the mixer is generated by a comb wave generating circuit or a comb wave generator, and is obtained through frequency selection filtering to obtain a local oscillator signal with a lower phase noise level. If the input of the comb wave generating circuit or the comb wave generator is 50MHz, the local oscillator signal that can be obtained is (50*N)MHz (N is the order of the comb wave generating circuit or the comb wave generator, which is a positive integer); it can be constructed using a step recovery diode or an integrated chip. The radio frequency signal RF end of the mixer is generated by a voltage-controlled oscillator (VCO) and obtained through a power divider. The generated intermediate frequency signal IF is phase-detected with the pre-processed signal through amplifier 1. That is:
预处理信号可表示为：The preprocessed signal can be expressed as:
REF=IF=LO±VCO。REF=IF=LO±VCO.
根据实际使用的情况选择不同的梳状波发生电路或梳状波发生器来生成本振信号，可以优化不同的参考信号相位噪声及杂散。混频器的本振信号由梳状波发生电路和或梳状波发生器产生，此梳状波发生电路不是本发明的保护点，故在此不做赘述。依据相位噪声理论：According to the actual use situation, different comb wave generating circuits or comb wave generators are selected to generate local oscillator signals, which can optimize different reference signal phase noise and spurious. The local oscillator signal of the mixer is generated by the comb wave generating circuit and/or comb wave generator. This comb wave generating circuit is not the protection point of the present invention, so it will not be described here. According to the phase noise theory:
理想的倍频器和分频器。使用理想的倍频器将信号的频率乘以N的系数，会将被乘以的信号的相位噪声增加20lg(N)dB。类似地，将信号频率除以N可将输出信号的相位噪声降低20lg(N)dB。Ideal frequency multipliers and dividers. Using an ideal frequency multiplier to multiply the frequency of a signal by a factor of N increases the phase noise of the multiplied signal by 20lg(N)dB. Similarly, dividing the signal frequency by N reduces the phase noise of the output signal by 20lg(N)dB.
由此理论可以推导：From this theory we can deduce:
对于一个调频信号：For an FM signal:
f(t) = cos(ωct + βsin(ωmt))；f(t) = cos(ωct + βsin(ωmt));
经过N倍频后为：After N times the frequency:
f(t) = cos(Nωct + Nβsin(ωmt))；f(t) = cos(Nωct + Nβsin(ωmt));
经过N倍频后的信号边带振幅增加了N倍，即增加了20lg(N)dB。在倍频信号中，与载波的边带偏移与原始信号相同。The sideband amplitude of the signal after N-frequency multiplication increases by N times, that is, by 20lg(N)dB. In the frequency-multiplied signal, the sideband offset from the carrier is the same as the original signal.
经过N分频后为：After N division, it is:
f(t) = cos((ωc/N)t +(β/N)sin(ωmt))；f(t) = cos((ωc/N)t +(β/N)sin(ωmt));
经过N分频后的信号边带振幅降低了N倍，即降低了20lg(N)dB。在分频信号中，与载波的边带偏移与原始信号相同。The sideband amplitude of the signal after N-frequency division is reduced by N times, that is, by 20lg(N)dB. In the divided signal, the sideband offset from the carrier is the same as the original signal.
由上述理论可知，开关切换电路、鉴相器、环路滤波器、压控振荡器、功率分配器、混频器、放大器等器件不会恶化相位噪声；一个信号经过N分频，其相位噪声降低20lg(N)dB。所以经过优化后的相噪比待优化的相噪低20lg(N)dBc/Hz。From the above theory, we know that the switching circuit, phase detector, loop filter, voltage-controlled oscillator, power divider, mixer, amplifier and other devices will not deteriorate the phase noise; after a signal is divided by N, its phase noise is reduced by 20lg(N)dB. Therefore, the phase noise after optimization is 20lg(N)dBc/Hz lower than the phase noise to be optimized.
而对于杂散信号边带幅度降低了20lg (N) dB，且频偏与原信号相同。The sideband amplitude of the spurious signal is reduced by 20lg (N) dB, and the frequency deviation is the same as the original signal.
因此，在混频锁相环电路中利用混频器，将VCO的输出频率通过混频方式降低至PFD所需要的频率，就可以得到一个锁相环电路，该电路在不改变信号的相位噪声和杂散的情况下可以输出需要的各种频率范围。Therefore, by using a mixer in a mixing phase-locked loop circuit to reduce the output frequency of the VCO to the frequency required by the PFD through mixing, a phase-locked loop circuit can be obtained, which can output various required frequency ranges without changing the phase noise and spurious of the signal.
请参考图2，为一种实施例中信号发生方法的流程示意图，该信号发生方法应用于如上所述的信号发生装置，用于产生低相位噪声信号。该信号发生方法包括：Please refer to FIG2 , which is a flow chart of a signal generation method in an embodiment, wherein the signal generation method is applied to the signal generation device as described above to generate a low phase noise signal. The signal generation method includes:
步骤100，获取预处理信号。Step 100: Obtain a preprocessed signal.
对待优化信号进行分频或倍频处理，以获取预处理信号。The signal to be optimized is processed by frequency division or frequency multiplication to obtain a preprocessed signal.
步骤200，获取环路锁相信号。Step 200, obtaining a loop phase-locked signal.
对所述预处理信号进行环路锁定，以获取环路锁相信号。一实施例中，环路锁相信号为正弦波转化后的方波信号。The pre-processed signal is loop locked to obtain a loop phase-locked signal. In one embodiment, the loop phase-locked signal is a square wave signal converted from a sine wave.
步骤300，输出优化后信号。Step 300: outputting the optimized signal.
对环路锁相信号进行放大、分频或倍频处理，并将放大、分频或倍频处理获取的降噪处理信号作为优化后信号输出。The loop phase-locked signal is amplified, divided or multiplied, and the noise reduction signal obtained by the amplification, division or multiplication is output as an optimized signal.
下面通过具体应用实例描述本申请公开的信号发生装置的技术效果，具体包括：The following describes the technical effects of the signal generating device disclosed in the present application through specific application examples, including:
设定压控振荡器VCO可输出范围为1-2G；鉴相器鉴相频率范围为10M-1300M，为获得最好的相噪，鉴相器一般采用方波，低频率来进行鉴相；本振信号根据不同使用场景通过梳状波发生器产生，再经过选频滤波得到。The output range of the voltage-controlled oscillator VCO is set to 1-2G; the phase detector frequency range is 10M-1300M. In order to obtain the best phase noise, the phase detector generally uses square waves and low frequencies for phase detection; the local oscillator signal is generated by a comb wave generator according to different usage scenarios, and then obtained through frequency selection filtering.
举例一：设定鉴相频率为50M，待优化信号为2000MHz，偏移100KHz处的相噪为-130dBc/Hz，需要经过第一可编程分频器来进行分频，分频比为2000M/50M=40，在此处相噪优化20lg40dB，即优化32dB，到达鉴相器的信号为50M，偏移100KHz处的相噪为-162dBc/Hz，经过压控振荡器VCO输出信号为2000MHz,偏移100KHz处的相噪为-162dBc/Hz，此时经过第二放大器输出，相比于输入信号为2000MHz,偏移100KHz处的相噪为-130dBc/Hz，该信号的相噪被优化了32dB，同样杂散也被优化32dB。Example 1: Set the phase detector frequency to 50M, the signal to be optimized is 2000MHz, and the phase noise at the offset of 100KHz is -130dBc/Hz. It needs to be divided by the first programmable divider, and the division ratio is 2000M/50M=40. Here the phase noise is optimized by 20lg40dB, that is, 32dB. The signal reaching the phase detector is 50M, and the phase noise at the offset of 100KHz is -162dBc/Hz. The output signal of the voltage-controlled oscillator VCO is 2000MHz, and the phase noise at the offset of 100KHz is -162dBc/Hz. At this time, after the output of the second amplifier, compared with the input signal of 2000MHz and the phase noise at the offset of 100KHz is -130dBc/Hz, the phase noise of the signal is optimized by 32dB, and the spurious signal is also optimized by 32dB.
举例二：设定鉴相频率为50M；输入信号为1MHz,偏移100KHz处的相噪为-135dBc/Hz，需要经过第一倍频器来进行倍频，倍频比为50M/1M=50，在此处相噪恶化20lg50dB，即恶化34dB，到达鉴相器的信号为50M，偏移100KHz处的相噪为-101dBc/Hz，经过压控振荡器VCO输出信号为1000MHz,偏移100KHz处的相噪为-101dBc/Hz，此时经过第二可编程分频器输出，分频比为1000M/1M=1000，该信号的相噪被优化了20lg1000dB，即优化60dB，此时的输出信号为1MHz，偏移100KHz处的相噪为-161dBc/Hz，相对于输入的待优化信号1MHz,偏移100KHz处的相噪为-135dBc/Hz，优化了26dB；同样杂散也被优化26dB。Example 2: Set the phase detector frequency to 50M; the input signal is 1MHz, and the phase noise at the offset of 100KHz is -135dBc/Hz. It needs to pass through the first frequency multiplier for frequency multiplication, and the frequency multiplication ratio is 50M/1M=50. Here, the phase noise deteriorates by 20lg50dB, that is, deteriorates by 34dB. The signal reaching the phase detector is 50M, and the phase noise at the offset of 100KHz is -101dBc/Hz. The output signal of the voltage-controlled oscillator VCO is 1000MHz, and the phase noise at the offset of 100KHz is -101dBc/Hz. The noise is -101dBc/Hz. At this time, it is output through the second programmable divider with a division ratio of 1000M/1M=1000. The phase noise of the signal is optimized by 20lg1000dB, that is, 60dB. At this time, the output signal is 1MHz, and the phase noise at an offset of 100KHz is -161dBc/Hz. Compared with the input signal to be optimized of 1MHz, the phase noise at an offset of 100KHz is -135dBc/Hz, which is optimized by 26dB. Similarly, the spurious signal is also optimized by 26dB.
举例三：设定鉴相频率为50M；输入信号为50MHz,偏移100KHz处的相噪为-135dBc/Hz，直接进入鉴相器鉴相，到达鉴相器的信号为50M，偏移100KHz处的相噪为-135dBc/Hz，经过压控振荡器VCO输出信号为2000MHz,偏移100KHz处的相噪为-135dBc/Hz，此时经过可编程分频器2输出，分频比为2000M/50M=40，该信号的相噪被优化了20lg40 dB，即优化32 dB，此时的输出信号为50M，偏移100KHz处的相噪为-167dBc/Hz，相对于输入信号50MHz,偏移100KHz处的相噪为-135dBc/Hz，优化了32 dB；同样杂散也被优化32 dB。Example 3: Set the phase detector frequency to 50M; the input signal is 50MHz, and the phase noise at the offset of 100KHz is -135dBc/Hz. It directly enters the phase detector for phase detection. The signal reaching the phase detector is 50M, and the phase noise at the offset of 100KHz is -135dBc/Hz. The output signal after the voltage-controlled oscillator VCO is 2000MHz, and the phase noise at the offset of 100KHz is -135dBc/Hz. At this time, it is output through the programmable divider 2, and the division ratio is 2000M/50M=40. The phase noise of the signal is optimized by 20lg40 dB, that is, optimized by 32 dB. At this time, the output signal is 50M, and the phase noise at the offset of 100KHz is -167dBc/Hz, which is 32 dB optimized compared to the input signal of 50MHz and the phase noise at the offset of 100KHz is -135dBc/Hz. Similarly, the spurious signal is also optimized by 32 dB.
在上述举例中，第一可编程分频器和第二可编程分频器都是工作在整数模式下，输入输出频点相同，这种模式下可编程分频器没有小数分频杂散，但是能得到的频点较为固定；若想得到任意输出频点，有两种方法，一种是采用可编程分频器的小数分频模式，这种模式下会引入小数分频杂散，若能接受小数分频杂散，也可用此方法；另一种是采用输入输出频点不同，采用可编程分频器整数分频的方法，可以设计一系列输入输出频点来覆盖所需要的频点，此方法得到的信号杂散较好。In the above example, the first programmable frequency divider and the second programmable frequency divider both work in integer mode, and the input and output frequencies are the same. In this mode, the programmable frequency divider has no fractional frequency division spurs, but the obtainable frequency is relatively fixed. If you want to get any output frequency, there are two methods. One is to use the fractional frequency division mode of the programmable frequency divider. In this mode, fractional frequency division spurs will be introduced. If the fractional frequency division spurs can be accepted, this method can also be used. The other is to use different input and output frequencies. Using the programmable frequency divider integer division method, a series of input and output frequencies can be designed to cover the required frequencies. The signal spurious obtained by this method is better.
在本申请实施例中公开的信号发生装置，包括信号预处理电路、混频锁相环电路和信号后处理电路，信号预处理电路用于对待优化信号进行分频或倍频处理以获取预处理信号，混频锁相环电路用于对预处理信号进行环路锁定以获取环路锁相信号，信号后处理电路用于对环路锁相信号进行放大、分频或倍频处理，并将获取的降噪处理信号作为优化后信号输出。混频锁相环电路是利用混频器搭建混频环来弥补小数分频的方法受到小数环的限制，优化信号的杂散。该信号发生装置不受输入输出的信号频率限制，可以实现低频到毫米波频段的一个超宽带输入输出，可以适用于多种射频***中。The signal generating device disclosed in the embodiment of the present application includes a signal preprocessing circuit, a mixing phase-locked loop circuit and a signal post-processing circuit. The signal preprocessing circuit is used to perform frequency division or frequency multiplication processing on the signal to be optimized to obtain a preprocessed signal. The mixing phase-locked loop circuit is used to perform loop locking on the preprocessed signal to obtain a loop phase-locked signal. The signal post-processing circuit is used to amplify, divide or multiply the loop phase-locked signal, and output the obtained noise reduction processed signal as an optimized signal. The mixing phase-locked loop circuit uses a mixer to build a mixing loop to compensate for the limitation of the fractional frequency division method by the fractional loop, and optimizes the spurious of the signal. The signal generating device is not limited by the frequency of the input and output signals, and can achieve an ultra-wideband input and output from low frequency to millimeter wave frequency band, and can be applied to a variety of radio frequency systems.
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本发明所属技术领域的技术人员，依据本发明的思想，还可以做出若干简单推演、变形或替换。The above specific examples are used to illustrate the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art, according to the idea of the present invention, some simple deductions, modifications or substitutions can be made.

Claims (10)

  1. 一种用于产生低相位噪声信号的信号发生装置，其特征在于，包括信号预处理电路、混频锁相环电路和信号后处理电路；A signal generating device for generating a low phase noise signal, characterized in that it comprises a signal preprocessing circuit, a mixing phase-locked loop circuit and a signal post-processing circuit;
    所述信号预处理电路包括第一信号连接端和第二信号连接端；所述信号预处理电路的第一信号连接端用于作为所述信号发生装置的信号输入端，用于一预设的待优化信号的输入；所述信号预处理电路的第二信号连接端与所述混频锁相环电路连接；所述信号预处理电路用于对所述待优化信号进行分频或倍频处理，并将分频或倍频处理后获取的预处理信号发送给所述混频锁相环电路；The signal preprocessing circuit comprises a first signal connection terminal and a second signal connection terminal; the first signal connection terminal of the signal preprocessing circuit is used as a signal input terminal of the signal generating device, and is used for inputting a preset signal to be optimized; the second signal connection terminal of the signal preprocessing circuit is connected to the mixer phase-locked loop circuit; the signal preprocessing circuit is used to perform frequency division or frequency multiplication processing on the signal to be optimized, and send the preprocessed signal obtained after the frequency division or frequency multiplication processing to the mixer phase-locked loop circuit;
    所述混频锁相环电路包括第一连接端、第二连接端、鉴相器、环路滤波电路、压控振荡器、功率分配器、混频器和第一放大器；所述混频锁相环电路的第一连接端与所述信号预处理电路的第二信号连接端连接，所述混频锁相环电路的第二连接端与所述信号后处理电路连接，所述混频锁相环电路用于对所述预处理信号进行环路锁定，并将环路锁定获取的环路锁相信号发送给所述信号后处理电路；The mixing phase-locked loop circuit includes a first connection end, a second connection end, a phase detector, a loop filter circuit, a voltage-controlled oscillator, a power divider, a mixer and a first amplifier; the first connection end of the mixing phase-locked loop circuit is connected to the second signal connection end of the signal preprocessing circuit, the second connection end of the mixing phase-locked loop circuit is connected to the signal post-processing circuit, and the mixing phase-locked loop circuit is used to perform loop locking on the pre-processing signal, and send the loop phase-locked signal obtained by loop locking to the signal post-processing circuit;
    所述鉴相器包括第一信号输入端、第二信号输入端和第一鉴相信号输出端，所述鉴相器的第一信号输入端与所述混频锁相环电路的第一连接端连接，所述鉴相器的第二信号输入端与所述第一放大器连接，所述鉴相器的第一鉴相信号输出端与所述环路滤波电路连接；The phase detector comprises a first signal input terminal, a second signal input terminal and a first phase detection signal output terminal, the first signal input terminal of the phase detector is connected to the first connection terminal of the mixer phase-locked loop circuit, the second signal input terminal of the phase detector is connected to the first amplifier, and the first phase detection signal output terminal of the phase detector is connected to the loop filter circuit;
    所述环路滤波电路包括第一连接端和第二连接端，所述环路滤波电路的第一连接端与所述鉴相器的第一鉴相信号输出端连接，所述环路滤波电路的第二连接端与所述压控振荡器连接；The loop filter circuit comprises a first connection end and a second connection end, the first connection end of the loop filter circuit is connected to the first phase detection signal output end of the phase detector, and the second connection end of the loop filter circuit is connected to the voltage controlled oscillator;
    所述压控振荡器包括第一连接端和第二连接端，所述压控振荡器的第一连接端与所述环路滤波电路的第二连接端连接，所述压控振荡器的第二连接端与所述功率分配器连接；The voltage controlled oscillator comprises a first connection end and a second connection end, the first connection end of the voltage controlled oscillator is connected to the second connection end of the loop filter circuit, and the second connection end of the voltage controlled oscillator is connected to the power distributor;
    所述功率分配器包括第一功率信号输入端、第一功率信号输出端和第二功率信号输出端，所述功率分配器的第一功率信号输入端与所述压控振荡器的第二连接端连接，所述功率分配器的第一功率信号输出端与所述混频锁相环电路的第二连接端连接，所述功率分配器的第二功率信号输出端与所述混频器连接；The power divider comprises a first power signal input terminal, a first power signal output terminal and a second power signal output terminal, the first power signal input terminal of the power divider is connected to the second connection terminal of the voltage-controlled oscillator, the first power signal output terminal of the power divider is connected to the second connection terminal of the mixer phase-locked loop circuit, and the second power signal output terminal of the power divider is connected to the mixer;
    所述混频器包括本振信号输入端、待混频信号输入端和混频信号输出端，所述混频器的本振信号输入端用于一预设的本振信号的输入，所述混频器的待混频信号输入端与所述功率分配器的第二功率信号输出端连接，所述混频器的混频信号输出端与所述第一放大器连接；The mixer comprises a local oscillator signal input terminal, a signal input terminal for mixing and a mixing signal output terminal, wherein the local oscillator signal input terminal of the mixer is used for inputting a preset local oscillator signal, the signal input terminal for mixing of the mixer is connected to the second power signal output terminal of the power divider, and the mixing signal output terminal of the mixer is connected to the first amplifier;
    所述第一放大器包括第一连接端和第二连接端，所述第一放大器的第一连接端与所述混频器的混频信号输出端连接，所述第一放大器的第二连接端与所述鉴相器的第二信号输入端连接；The first amplifier comprises a first connection end and a second connection end, the first connection end of the first amplifier is connected to the mixing signal output end of the mixer, and the second connection end of the first amplifier is connected to the second signal input end of the phase detector;
    所述信号后处理电路包括第一信号连接端和第二信号连接端；所述信号后处理电路的第一信号连接端与所述混频锁相环电路的第二连接端连接，所述信号后处理电路的第二信号连接端用于作为所述信号发生装置的信号输出端；所述信号后处理电路用于对所述环路锁相信号进行放大、分频或倍频处理，并将放大、分频或倍频处理获取的降噪处理信号作为优化后信号输出。The signal post-processing circuit includes a first signal connection end and a second signal connection end; the first signal connection end of the signal post-processing circuit is connected to the second connection end of the mixing phase-locked loop circuit, and the second signal connection end of the signal post-processing circuit is used as a signal output end of the signal generating device; the signal post-processing circuit is used to amplify, divide or multiply the loop phase-locked signal, and output the noise reduction processed signal obtained by the amplification, division or multiplication processing as an optimized signal.
  2.  如权利要求1所述的信号发生装置，其特征在于，所述信号预处理电路包括第一切换开关电路、第二切换开关电路、第一可编程分频器和第一倍频器；The signal generating device as claimed in claim 1 is characterized in that the signal preprocessing circuit includes a first switching circuit, a second switching circuit, a first programmable frequency divider and a first frequency multiplier;
    所述第一切换开关电路包括第一连接端、第二连接端、第三连接端和第四连接端，所述第一切换开关电路的第一连接端与所述信号预处理电路的第一信号连接端连接，所述第一切换开关电路的第二连接端与所述第一可编程分频器连接，所述第一切换开关电路的第三连接端与所述第二切换开关电路连接；所述第一切换开关电路的第四连接端与所述第一倍频器连接；所述第一切换开关电路用于将所述待优化信号输出给所述第二切换开关电路、第一可编程分频器或第一倍频器；The first switching switch circuit includes a first connection end, a second connection end, a third connection end and a fourth connection end, the first connection end of the first switching switch circuit is connected to the first signal connection end of the signal preprocessing circuit, the second connection end of the first switching switch circuit is connected to the first programmable frequency divider, and the third connection end of the first switching switch circuit is connected to the second switching switch circuit; the fourth connection end of the first switching switch circuit is connected to the first frequency multiplier; the first switching switch circuit is used to output the signal to be optimized to the second switching switch circuit, the first programmable frequency divider or the first frequency multiplier;
    所述第一可编程分频器包括第一连接端和第二连接端，所述第一可编程分频器的第一连接端与所述第一切换开关电路的第一连接端连接，所述第一可编程分频器的第二连接端与所述第二切换开关电路连接；所述第一可编程分频器用于对所述待优化信号进行分频处理；The first programmable frequency divider includes a first connection end and a second connection end, the first connection end of the first programmable frequency divider is connected to the first connection end of the first switching circuit, and the second connection end of the first programmable frequency divider is connected to the second switching circuit; the first programmable frequency divider is used to perform frequency division processing on the signal to be optimized;
    所述第一倍频器包括第一连接端和第二连接端，所述第一倍频器的第一连接端与所述第一切换开关电路的第四连接端连接，所述第一倍频器的第二连接端与所述第二切换开关电路连接；所述第一倍频器用于对所述待优化信号进行倍频处理；The first frequency multiplier includes a first connection end and a second connection end, the first connection end of the first frequency multiplier is connected to the fourth connection end of the first switching circuit, and the second connection end of the first frequency multiplier is connected to the second switching circuit; the first frequency multiplier is used to perform frequency multiplication processing on the signal to be optimized;
    第二切换开关电路包括第一连接端、第二连接端、第三连接端和第四连接端，所述第二切换开关电路的第一连接端与所述信号预处理电路的第二信号连接端连接，所述第二切换开关电路的第二连接端与所述第一可编程分频器，所述第二切换开关电路的第三连接端与所述第一切换开关电路连接；所述第二切换开关电路的第四连接端与所述第一倍频器连接；所述第二切换开关电路用于将所述第一切换开关电路输出的所述待优化信号、经所述第一可编程分频器分频处理后的所述待优化信号或经所述第一倍频器倍频处理的所述待优化信号作为所述预处理信号发送给所述混频锁相环电路。The second switching switch circuit includes a first connection end, a second connection end, a third connection end and a fourth connection end. The first connection end of the second switching switch circuit is connected to the second signal connection end of the signal preprocessing circuit, the second connection end of the second switching switch circuit is connected to the first programmable frequency divider, and the third connection end of the second switching switch circuit is connected to the first switching switch circuit; the fourth connection end of the second switching switch circuit is connected to the first frequency multiplier; the second switching switch circuit is used to send the signal to be optimized output by the first switching switch circuit, the signal to be optimized after frequency division processing by the first programmable frequency divider, or the signal to be optimized after frequency multiplication processing by the first frequency multiplier as the preprocessing signal to the mixing phase-locked loop circuit.
  3.  如权利要求2所述的信号发生装置，其特征在于，所述信号后处理电路包括第三切换开关电路、第四切换开关电路、第二可编程分频器、第二放大器和第二倍频器；The signal generating device as described in claim 2 is characterized in that the signal post-processing circuit includes a third switching circuit, a fourth switching circuit, a second programmable frequency divider, a second amplifier and a second frequency multiplier;
    所述第三切换开关电路包括第一连接端、第二连接端、第三连接端和第四连接端，所述第三切换开关电路的第一连接端与所述信号后处理电路的第一信号连接端连接，所述第三切换开关电路的第二连接端与所述第二可编程分频器连接，所述第三切换开关电路的第三连接端与所述第二放大器连接，所述第三切换开关电路的第四接端与所述第二倍频器连接；所述第三切换开关电路用于将所述环路锁相信号发送给所述第二可编程分频器、所述第二放大器或所述第二倍频器；The third switching switch circuit includes a first connection end, a second connection end, a third connection end and a fourth connection end, the first connection end of the third switching switch circuit is connected to the first signal connection end of the signal post-processing circuit, the second connection end of the third switching switch circuit is connected to the second programmable frequency divider, the third connection end of the third switching switch circuit is connected to the second amplifier, and the fourth connection end of the third switching switch circuit is connected to the second frequency multiplier; the third switching switch circuit is used to send the loop phase-locked signal to the second programmable frequency divider, the second amplifier or the second frequency multiplier;
    所述第二可编程分频器包括第一连接端和第二连接端，所述第二可编程分频器的第一连接端与所述第三切换开关电路的第二连接端连接，所述第二可编程分频器的第二连接端与所述第四切换开关电路连接；The second programmable frequency divider includes a first connection end and a second connection end, the first connection end of the second programmable frequency divider is connected to the second connection end of the third switching circuit, and the second connection end of the second programmable frequency divider is connected to the fourth switching circuit;
    所述第二放大器包括第一连接端和第二连接端，所述第二放大器的第一连接端与所述第三切换开关电路的第三连接端连接，所述第二放大器的第二连接端与所述第四切换开关电路连接；The second amplifier includes a first connection end and a second connection end, the first connection end of the second amplifier is connected to the third connection end of the third switching circuit, and the second connection end of the second amplifier is connected to the fourth switching circuit;
    所述第二倍频器包括第一连接端和第二连接端，所述第二倍频器的第一连接端与所述第三切换开关电路的第四连接端连接，所述第二倍频器的第二连接端与所述第四切换开关电路连接；The second frequency multiplier includes a first connection end and a second connection end, the first connection end of the second frequency multiplier is connected to the fourth connection end of the third switching circuit, and the second connection end of the second frequency multiplier is connected to the fourth switching circuit;
    所述第四切换开关电路包括第一连接端、第二连接端、第三连接端和第四连接端，所述第四切换开关电路的第一连接端与所述信号后处理电路的第二信号连接端连接，所述第四切换开关电路的第二连接端与所述第二可编程分频器，所述第四切换开关电路的第三连接端与所述第二放大器连接，所述第四切换开关电路的第四接端与所述第二倍频器连接；所述第四切换开关电路用于将经所述第二可编程分频器分频处理的所述环路锁相信号、经所述第二放大器放大处理的所述环路锁相信号或经所述第二倍频器倍频处理后的所述环路锁相信号作为所述优化后信号输出。The fourth switching switch circuit includes a first connection end, a second connection end, a third connection end and a fourth connection end. The first connection end of the fourth switching switch circuit is connected to the second signal connection end of the signal post-processing circuit, the second connection end of the fourth switching switch circuit is connected to the second programmable frequency divider, the third connection end of the fourth switching switch circuit is connected to the second amplifier, and the fourth connection end of the fourth switching switch circuit is connected to the second frequency multiplier. The fourth switching switch circuit is used to output the loop phase-locked signal divided by the second programmable frequency divider, the loop phase-locked signal amplified by the second amplifier, or the loop phase-locked signal multiplied by the second frequency multiplier as the optimized signal.
  4.  如权利要求3所述的信号发生装置，其特征在于，所述第一切换开关电路、所述第二切换开关电路、所述第三切换开关电路和所述第四切换开关电路为三选一信号开关电路。The signal generating device as described in claim 3 is characterized in that the first switching switch circuit, the second switching switch circuit, the third switching switch circuit and the fourth switching switch circuit are three-select-one signal switching circuits.
  5.  如权利要求3所述的信号发生装置，其特征在于，所述本振信号由梳状波发生电路或梳状波发生器产生。The signal generating device as described in claim 3 is characterized in that the local oscillator signal is generated by a comb wave generating circuit or a comb wave generator.
  6.  如权利要求3所述的信号发生装置，其特征在于，所述第一可编程分频器和所述第二可编程分频器采用小数分频模式和/或采用整数分频模式。The signal generating device as described in claim 3 is characterized in that the first programmable frequency divider and the second programmable frequency divider adopt a fractional frequency division mode and/or an integer frequency division mode.
  7.  如权利要求3所述的信号发生装置，其特征在于，所述鉴相器的第一鉴相信号输出端输出的是方波信号。The signal generating device as described in claim 3 is characterized in that the first phase-detection signal output terminal of the phase detector outputs a square wave signal.
  8.  如权利要求7所述的信号发生装置，其特征在于，所述鉴相器的鉴相频率是50MHz。The signal generating device as described in claim 7 is characterized in that the phase detection frequency of the phase detector is 50MHz.
  9.  一种用于产生低相位噪声信号的信号发生方法，其特征在于，应用于如权利要求1至8任一项所述的信号发生装置，所述信号发生方法包括：A signal generating method for generating a low phase noise signal, characterized in that it is applied to the signal generating device according to any one of claims 1 to 8, and the signal generating method comprises:
    对待优化信号进行分频或倍频处理，以获取预处理信号；Perform frequency division or frequency multiplication processing on the signal to be optimized to obtain a preprocessed signal;
    对所述预处理信号进行环路锁定，以获取环路锁相信号；Loop locking the preprocessed signal to obtain a loop phase-locked signal;
    对所述环路锁相信号进行放大、分频或倍频处理，并将放大、分频或倍频处理获取的降噪处理信号作为优化后信号输出。The loop phase-locked signal is amplified, divided or multiplied, and the noise reduction signal obtained by the amplification, division or multiplication is output as an optimized signal.
  10. 如权利要求9所述的信号发生方法，其特征在于，所述环路锁相信号为方波信号。The signal generating method according to claim 9, wherein the loop phase-locked signal is a square wave signal.
PCT/CN2023/089468 2022-10-20 2023-04-20 Signal generation apparatus and method for generating low-phase noise signal WO2024082586A1 (en)

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