WO2024065853A1 - Chip and preparation method therefor, and electronic device - Google Patents

Chip and preparation method therefor, and electronic device Download PDF

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Publication number
WO2024065853A1
WO2024065853A1 PCT/CN2022/123658 CN2022123658W WO2024065853A1 WO 2024065853 A1 WO2024065853 A1 WO 2024065853A1 CN 2022123658 W CN2022123658 W CN 2022123658W WO 2024065853 A1 WO2024065853 A1 WO 2024065853A1
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WO
WIPO (PCT)
Prior art keywords
layer
film
conductive column
dielectric
resistor
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PCT/CN2022/123658
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French (fr)
Chinese (zh)
Inventor
范荣伟
马野
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华为技术有限公司
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Priority to PCT/CN2022/123658 priority Critical patent/WO2024065853A1/en
Publication of WO2024065853A1 publication Critical patent/WO2024065853A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a chip and a method for preparing the same, and an electronic device.
  • chips include not only active devices such as transistors, but also passive devices such as resistors.
  • active devices such as transistors
  • passive devices such as resistors.
  • the yield rate of resistors has always been a technical barrier that is difficult for technicians in this field to overcome.
  • the embodiments of the present application provide a chip and a method for manufacturing the same, and an electronic device, which are used to improve the yield of resistors in the chip.
  • a chip which can be a bare chip or a packaged chip.
  • the chip includes a first dielectric layer, which includes a first region and a second region; a resistor layer and a resistor protection layer, which are sequentially stacked in the first region on the first dielectric layer;
  • the resistor protection layer includes an etch stop layer and an etch barrier layer, and the etch stop layer is arranged between the etch barrier layer and the resistor layer;
  • the etch barrier layer has a first via hole, and the etch stop layer has a second via hole;
  • a second dielectric layer which is arranged on the first dielectric layer and covers the resistor protection layer; a first conductive column, which penetrates the second dielectric layer and is electrically connected to the resistor layer through the first via hole and the second via hole; wherein the etch barrier layer is used as an etch protection layer in the first etching process of forming the resistor layer, and the etch stop layer is used as an etch protection layer in the
  • the resistor protection layer above the resistor layer includes an etch stop layer and an etch barrier layer.
  • the etch barrier layer is used as a barrier layer when etching the resistor film to form the resistor layer to protect the pattern shape of the resistor layer.
  • the etch stop layer is used as a stop layer when etching the etch barrier layer to form the first via hole for placing the first conductive column. In this way, due to the existence of the etch stop layer, no matter what etching process is used to form an opening on the etch barrier layer, it will hardly affect the resistor layer below the etch stop layer, so as to ensure the yield of the resistor layer.
  • a separate etching step is used to form a second via hole on the etch stop layer.
  • the damage to the resistor layer can be minimized and the yield of the resistor layer can be improved.
  • the resistor layer is not exposed, which can reduce the exposure time of the resistor layer, reduce the probability of oxidation of the resistor layer, and further improve the yield of the resistor layer.
  • the resistor layer includes a first part in contact with the first conductive column and a second part in contact with the resistor protection layer, and the ratio of the thickness of the first part to the thickness of the second part is in the range of 0.2-1.
  • the resistor layer is protected by the resistor protection layer during the preparation process, and the resistor layer is not exposed before the first conductive column is prepared. The exposure time of the first part is short and the damage is small.
  • a separate etching process is used to open the resistor protection layer, and there is almost no over-etching damage to the first part.
  • the damage to the first part of the resistor layer located below the first conductive column during the chip preparation process can be reduced, and the ratio of the thickness of the first part of the resistor layer to the thickness of the second part can reach 0.2-1.
  • the actual resistance value of the resistor layer in the chip of the present application is closer to the set resistance value, which can effectively improve the resistance deviation caused by the damage of the resistor layer and improve the chip performance.
  • the resistor protection layer further includes an oxidation barrier layer, which is disposed between the etching stop layer and the resistor layer, and has a third via hole, which is connected to the second via hole.
  • the first conductive column includes a first conductive column body and a first filling layer, and the first filling layer covers the side and bottom surfaces of the first conductive column body.
  • the first filling layer can improve the adhesion between the first conductive column and the second dielectric layer.
  • the material of the oxidation barrier layer includes silicon nitride
  • the material of the etch stop layer includes silicon oxide
  • the material of the etch barrier layer includes silicon nitride. This is a low-cost implementation.
  • the material of the resistance layer includes titanium nitride, tantalum nitride or titanium oxide. This is a low-cost implementation.
  • the chip further includes a second conductive column and a transistor; the transistor is disposed on a side of the first dielectric layer away from the second dielectric layer, and a projection of the transistor on the first dielectric layer does not overlap with a projection of the resistor layer on the first dielectric layer; the second conductive column penetrates the second dielectric layer and the first dielectric layer and is electrically connected to the transistor.
  • the preparation provided in the embodiment of the present application can achieve the preparation of the first conductive column in the area where the resistor layer is located and the second conductive column in the area where the transistor is located while ensuring the product yield of the resistor layer.
  • the sidewalls where the first dielectric layer contacts the second conductive pillar and the sidewalls where the second dielectric layer contacts the second conductive pillar are doped with heavy atoms.
  • the sidewalls where the first dielectric layer contacts the second conductive pillar and the sidewalls where the second dielectric layer contacts the second conductive pillar are doped with heavy atoms.
  • the concentration of heavy atoms in the second dielectric layer is greater than that in the first dielectric layer.
  • the expansion degree of the second dielectric layer is greater than that of the first dielectric layer, and even if the first dielectric layer and the second conductive pillar are not attached, the second dielectric layer can be attached to the second conductive pillar, so as to improve the problem of damaging the transistor due to the acidic polishing liquid flowing into the gap between the second conductive pillar and the second dielectric layer in the subsequent preparation process.
  • the second conductive column includes a second conductive column body, and the second conductive column body is electrically connected to the transistor. This is a possible structure.
  • the second conductive column further includes a third conductive column body and a second filling layer; the third conductive column body is arranged on a side of the second conductive column body away from the transistor, and the second filling layer covers the side and bottom surfaces of the third conductive column body.
  • the side of the second dielectric layer in contact with the first conductive pillar is doped with heavy atoms.
  • the side of the second dielectric layer doped with heavy atoms can change the surface properties of the second dielectric layer and improve the adhesion between the second dielectric layer and the first conductive pillar.
  • the second conductive column body extends into the transistor, and the portion of the second conductive column body extending into the transistor contacts the surface of the first dielectric layer away from the second dielectric layer. In this way, even if a solution such as an acidic polishing liquid or an etching liquid flows into the gap between the second conductive column and the second dielectric layer during the subsequent preparation process, it will first contact the portion of the end of the second conductive column located in the groove, thereby reducing the damage of the solution such as the acidic polishing liquid or the etching liquid to the transistor.
  • a solution such as an acidic polishing liquid or an etching liquid
  • the chip further includes a first conductive pattern and a second conductive pattern; the first conductive pattern and the second conductive pattern are arranged on a side of the second dielectric layer away from the first dielectric layer; the first conductive column is electrically connected to the first conductive pattern, and the second conductive column is electrically connected to the second conductive pattern.
  • the signal of the resistor layer is transferred to the first conductive pattern through the first conductive column, and the signal of the transistor is transferred to the second conductive pattern through the second conductive column.
  • a second aspect of an embodiment of the present application provides an electronic device, comprising the chip and circuit board of any one of the first aspects, wherein the chip is arranged on the circuit board.
  • a chip manufacturing method comprising: forming a first dielectric film; sequentially forming a stacked resistor film and a resistor protection film on the first dielectric film, the resistor film covers the first dielectric film, and the resistor protection film is located in a first region of the first dielectric film; the resistor protection film comprises an etch stop film and an etch barrier film, and the etch stop film is located between the etch barrier film and the resistor film; performing a first etching on the resistor film to form a resistor layer; the etch barrier film is used as an etching protection layer in the first etching process of forming the resistor layer, and the resistor layer is located in the first region; forming a second dielectric film; the second dielectric film is formed on the first dielectric film and covers the resistor protection film; forming a fourth via hole penetrating the second dielectric film and a first via hole penetrating the etch barrier film by a second
  • the resistance protection layer above the resistance layer includes an etching stop layer and an etching barrier layer
  • the etching barrier layer is used as a barrier layer when etching the resistance film to form the resistance layer to protect the pattern shape of the resistance layer.
  • the etching stop layer is used as a stop layer when etching the etching barrier layer to form an opening for placing the first conductive column. In this way, due to the existence of the etching stop layer, no matter what etching process is used to form the first via hole on the etching barrier film during the second etching process, it will hardly affect the resistance layer below the etching stop layer.
  • the resistance layer can improve the yield of the resistance layer and improve the compatibility of the process in the chip preparation process.
  • a separate etching step is used to form the second via hole on the etching stop layer. By adjusting the etching conditions, the damage to the resistance layer can be minimized and the yield of the resistance layer can be improved.
  • the resistance layer is not exposed, which can reduce the exposure time of the resistance layer, reduce the probability of oxidation of the resistance layer, and further improve the yield of the resistance layer.
  • the preparation method before forming the first dielectric film, further includes: forming a transistor; the projection of the transistor on the first dielectric film does not overlap with the projection of the resistance layer on the first dielectric film; before removing the portion of the resistance protection film located below the third opening, the preparation method further includes: forming a second opening that penetrates the second dielectric film and the first dielectric film to form a first dielectric layer; the second opening exposes the transistor; and forming a second conductive column body in the second opening, the second conductive column body being electrically connected to the transistor.
  • the manufacturing processes of the first conductive pillar in the region where the resistor layer is located and the second conductive pillar in the region where the transistor is located can be compatible.
  • the third opening and the second opening are formed simultaneously.
  • the manufacturing method of the chip provided in the embodiment of the present application can achieve compatibility with the manufacturing processes of the first conductive pillar and the second conductive pillar on the basis of ensuring the product yield of the resistor layer.
  • the preparation method before forming the second conductive pillar body in the second opening, the preparation method further includes: performing a first heavy atom implantation on the second dielectric film.
  • performing the heavy atom doping process the problem of poor adhesion between the second conductive pillar and the sidewall of the second opening can be improved.
  • the preparation method further includes: performing a second heavy atom implantation on the second dielectric film.
  • the second heavy atom implantation causes the surface of the second dielectric film to expand, fills the gap between the second conductive column body and the side wall of the second opening, makes the second conductive column body contact more closely with the side wall of the second opening, and further improves the adhesion between the second conductive column body and the side wall of the second opening.
  • the energy of the second heavy atom injection is less than the energy of the first heavy atom injection.
  • the dosage of the second heavy atom implantation is smaller than the dosage of the first heavy atom implantation.
  • the angle of the second heavy atom implantation is smaller than the angle of the first heavy atom implantation.
  • the heavy atoms injected for the second time can be mainly concentrated on the side of the second dielectric film close to the end of the second conductive column body, thereby reducing the number of heavy atoms splashed into the second dielectric film during the heavy atom injection process, thereby improving the problem of chip performance being affected by the inclusion of heavy atoms in the second dielectric film.
  • a first conductive column is formed in a first opening, and a second dielectric layer is formed, including: forming a first filling film covering a second dielectric film; forming a conductive film on the first filling film; grinding the first filling film, the conductive film, and the second dielectric film to form a first filling layer, a first conductive column body, and a second dielectric layer; the first conductive column body is located in the first opening, and the first filling layer covers the bottom surface and side surfaces of the first conductive column body; the first conductive column includes a first filling layer and a first conductive column body.
  • the first conductive column is formed by the above-mentioned preparation method. When preparing the first conductive column, the chemical mechanical grinding of the second conductive column can be completed simultaneously, and the preparation of the second conductive column can be completed simultaneously. Therefore, the process steps can be reduced, the cost can be reduced, and the efficiency can be improved.
  • the third conductive column body and the second filling layer are also formed; the second filling layer covers the bottom and side surfaces of the third conductive column body, and the third conductive column body is disposed on the side of the second conductive column body away from the transistor. This is a possible structure.
  • the resistor protection film further includes an oxidation barrier film; the oxidation barrier film is disposed between the etching stop film and the resistor layer; the preparation method further includes forming a third via hole penetrating the oxidation barrier film, the third via hole being connected to the second via hole.
  • FIG1 is a schematic diagram of a framework of an electronic device provided in an embodiment of the present application.
  • 2A-2D are schematic diagrams of a chip preparation process according to an embodiment of the present application.
  • FIG. 3-5 are schematic diagrams of another chip preparation process according to an embodiment of the present application.
  • FIG6 is a flow chart of a method for preparing a chip provided in an embodiment of the present application.
  • FIGS. 7 to 16 are schematic diagrams of a chip preparation process provided in an embodiment of the present application.
  • FIG17 is a schematic diagram of steps for preparing a chip provided in an embodiment of the present application.
  • FIG. 18 is a schematic diagram of the preparation steps of another chip provided in an embodiment of the present application.
  • the term “including” is interpreted as an open, inclusive meaning, that is, “including, but not limited to”.
  • the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “exemplarily” or “some examples” and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure.
  • the schematic representation of the above terms does not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.
  • the term “electrically connected” and its derivative expressions may be used.
  • the term “electrically connected” may be used to indicate that two or more components are in direct physical or electrical contact.
  • the term “electrically connected” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the contents of this document.
  • exemplary embodiments are described with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams as idealized exemplary drawings.
  • the thickness of the layers and regions is magnified for clarity. Therefore, it is conceivable that the shape changes relative to the drawings are caused by, for example, manufacturing technology and/or tolerances. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as a rectangle will generally have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the electronic device may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc.
  • consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVD), etc.
  • Financial terminal products include automated teller machines (ATMs), self-service terminals, etc.
  • Communication electronic products such as servers, storage devices, base stations and other communication equipment.
  • the electronic device 1 mainly includes a display module 2 , a middle frame 3 , a housing (or battery cover, rear housing) 4 and a cover plate 5 .
  • the display module 2 has a light emitting side through which a display image can be seen and a back side arranged opposite to the light emitting side.
  • the back side of the display module 2 is close to the middle frame 3 , and the cover plate 5 is arranged on the light emitting side of the display module 2 .
  • the above-mentioned display module 2 includes a display panel (DP).
  • the display module 2 is a liquid crystal display module.
  • the display screen is a liquid crystal display (LCD).
  • the display module 2 also includes a backlight unit (BLU) located on the back of the liquid crystal display (away from the side of the LCD for displaying images).
  • BLU backlight unit
  • the backlight module can provide light source to the LCD screen so that each sub-pixel in the LCD screen can emit light to realize image display.
  • the display module 2 is an organic light emitting diode display module.
  • the display screen is an organic light emitting diode (OLED) display screen. Since an electroluminescent layer is provided in each sub-pixel in the OLED display screen, the OLED display screen can realize self-luminescence after receiving the operating voltage. In this case, the display module 2 having the OLED display screen does not need to be provided with the backlight module.
  • the cover plate 5 is located on the side of the display module 2 away from the middle frame 3.
  • the cover plate 5 may be, for example, a cover glass (CG), and the cover glass may have a certain toughness.
  • the middle frame 3 is located between the display module 2 and the housing 4.
  • the surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc. After the housing 4 and the middle frame 3 are covered, the above internal components are located between the housing 4 and the middle frame 3.
  • the electronic device 1 also includes a processor (center processing unit, CPU) chip, a radio frequency chip, a radio frequency power amplifier ((power amplifier, PA) chip, a system-on-a-chip (system on a chip, SOC), a power management chip (power management integrated circuits, PMIC), a storage chip (such as high bandwidth memory (high bandwidth memory, HBM)), an audio processor chip, a touch screen control chip, a NAND flash (flash memory), an image sensor chip, a charging protection chip and other chips arranged on the PCB.
  • the PCB is used to carry the above chips and complete signal interaction with the above chips.
  • the reliability and other performance of the chip (which can be called a logic integrated device, or an integrated circuit device) itself has a direct impact on the service life and performance of electronic equipment.
  • the chip preparation process usually includes the front end of line (FEOL), the mid end of line (MEOL) and the back end of line (BEOL).
  • the front-end process is used to form a transistor.
  • the transistor includes a source S, a drain D and a gate G.
  • the middle process is used to form a transfer layer that leads the conductive patterns in multiple transistors to the same plane.
  • the conductive pillars in the transfer layer are electrically connected to the source S, drain D, and gate G of the transistor.
  • the formation of the transfer layer usually first forms a dielectric layer with holes, and the holes in the dielectric layer are located above the conductive patterns, and then the conductive pillars are formed using the hole filling technology.
  • the transfer layer formed by the middle process includes two parts, the first part is: the transfer metal arranged on the surface of the transistor and the first middle dielectric layer wrapped around the transfer metal, and the transfer metal is electrically connected to the source S, drain D, and gate G of the transistor.
  • the second part is: the conductive column arranged on the surface of the transfer metal and the second middle dielectric layer wrapped around the conductive column, and the conductive column is electrically connected to the transfer metal.
  • the transfer metal is, for example, in the shape of a strip
  • the conductive column is, for example, in the shape of a column.
  • the dielectric layer wrapped around the transfer metal formed in the middle process is referred to as the first middle dielectric layer
  • the dielectric layer wrapped around the conductive column is referred to as the second middle dielectric layer.
  • the structure of FIG. 2C can optimize the arrangement of the redistribution layer in the back-end process.
  • the structure formed in the middle process is taken as shown in FIG. 2C as an example.
  • the back-end process is used to form a redistribution layer located on the transfer layer.
  • the signal in the transistor is transmitted to the redistribution layer through the transfer layer, and then led out to the signal terminal on the surface of the redistribution layer.
  • the signal terminal is exposed to the surface of the chip.
  • the signal terminal serves as a pad of the chip.
  • the chip includes not only active devices such as transistors, but also passive devices such as resistors. In some technologies, passive devices such as resistors are formed simultaneously in the middle process.
  • a method for preparing a chip integrating a transistor and a resistor comprising:
  • a first middle-stage dielectric layer and a transfer metal are formed by a middle-stage process, and then a first dielectric film is formed on the first middle-stage dielectric layer. Subsequently, a stacked resistance layer and an etching barrier film are sequentially formed on a first region of the first dielectric film. Next, a second dielectric film is formed on the first dielectric film, and the second dielectric film covers the etching barrier film located on the first region.
  • the resistor layer and the transition metal prepared in the first middle dielectric layer are staggered, or it can be understood that the projection of the resistor layer on the first dielectric film and the projection of the transition metal on the first dielectric film do not overlap.
  • the position of the resistor layer corresponds to the first area of the first dielectric film
  • the position of the transition metal corresponds to the second area of the first dielectric film
  • the first area and the second area do not overlap.
  • a first opening is formed through the second dielectric film and the etch stop film, and a second opening is formed through the first dielectric film and the second dielectric film.
  • the portion of the first dielectric film retained is used as the first dielectric layer
  • the portion of the second dielectric film retained is used as the second dielectric layer
  • the portion of the etch stop film retained is used as the etch stop layer.
  • the resistor layer is exposed by setting the first opening
  • the transfer metal is exposed by setting the second opening.
  • the thickness of the first dielectric film above the transition metal is greater than the thickness of the resistor protection film.
  • the thickness of the portion of the second dielectric film located above the transition metal is greater than the thickness of the portion of the second dielectric film located above the resistor layer.
  • the sum of the thickness of the portion of the second dielectric film located above the resistor layer and the thickness of the resistor protection film is less than the sum of the thickness of the second dielectric film and the thickness of the first dielectric film.
  • an embodiment of the present application provides a chip and a method for manufacturing the same, which are used to improve the yield of resistors in the chip while being compatible with the preparation process of components.
  • the chip provided in the embodiment of the present application can be applied to the above-mentioned electronic device.
  • the chip provided in the embodiment of the present application can be an unpackaged bare chip.
  • the unpackaged bare chip can include one integrated circuit block (which can be called a two-dimensional (2D) bare chip).
  • the unpackaged bare chip can also include multiple integrated circuit blocks (which can be called a three-dimensional (3D) bare chip).
  • the chip provided in the embodiment of the present application can also be a packaged chip.
  • the packaged chip can include one bare chip or multiple bare chips.
  • the present application embodiment provides a method for preparing a chip, as shown in FIG6 , comprising:
  • step S000 includes:
  • the material of the substrate 200 is an insulating material.
  • the material of the substrate 200 is a conductive material.
  • the transistor 10 includes a complementary metal oxide semiconductor device (CMOS), and the CMOS includes a source S, a drain D, and a gate G.
  • CMOS complementary metal oxide semiconductor device
  • FIG7 also illustrates a gate insulating layer below the gate G and a sidewall on the side of the gate G.
  • the structure of the transistor 10 illustrated in FIG7 is only an illustration and is not limited in any way.
  • transistor 10 is a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), etc.
  • HEMT high electron mobility transistor
  • HBT heterojunction bipolar transistor
  • BJT bipolar junction transistor
  • the chip may include at least one transistor 10.
  • the chip preparation method provided in the embodiment of the present application only takes one transistor 10 in the chip as an example to schematically illustrate the structure of each part in the chip.
  • the multiple transistors 10 may be transistors of the same type or transistors of different types.
  • the embodiment of the present application does not limit the number, type, and arrangement of the transistors 10 in the chip, and can be reasonably set as needed.
  • An inter-level dielectric (ILD) layer is formed on the surface of the transistor 10.
  • a transition metal 20 is provided in the inter-level dielectric layer, which penetrates the inter-level dielectric layer and connects the source S, drain D or gate G of the transistor 10.
  • the embodiment of the present application does not limit the shape of the top view of the transfer metal, for example, it can be any shape such as a strip, a column, etc.
  • the chip includes at least one transfer metal 20 .
  • the material of the transfer metal 20 may be, for example, molybdenum (Mo).
  • the material of the interlayer dielectric layer ILD may be, for example, silicon nitride.
  • a first dielectric film 30 ′ is formed on the transfer metal 20 .
  • the first dielectric film 30' covers the interlayer dielectric layer ILD and the transfer metal 20.
  • the embodiment of the present application is not limited to forming the first dielectric film 30' on the transfer metal 20 shown in FIG7.
  • the first dielectric film 30' can also be formed on the transistor 10.
  • FIG7 is only a schematic diagram.
  • a resistor film 40 ′ and a resistor protection film 50 ′ are formed on the first dielectric film 30 ′.
  • the resistor film 40' is located on the side of the first dielectric film 30' away from the interlayer dielectric layer ILD, and the resistor protection film 50' is located on the surface of the resistor layer 40 away from the first dielectric film 30'.
  • the resistor film 40' covers the first dielectric film 30', and the resistor protection film 50' is located in the first region of the first dielectric film 30'.
  • the resistance protection film 50' comprises a multi-layer dielectric covering film, wherein the multi-layer dielectric covering film comprises at least two layers of dielectric covering films made of different materials.
  • step S200 includes:
  • the resistance protection base film 50 ′′ includes an oxidation blocking base film 51 ′′, an etch stop base film 52 ′′, and an etch blocking base film 53 ′′.
  • the material of the etch stop base film 52 ′′ and the material of the etch barrier base film 53 ′′ include different dielectric materials.
  • the material of the oxidation barrier base film 51 ′′ is a dielectric material that does not contain oxygen.
  • FIG. 8B is only a schematic diagram and does not make any limitation.
  • a photolithography process combined with a dry etching process can be used to remove the oxidation barrier base film 51′′, the etch stop base film 52′′ and the etch barrier base film 53′′ in the area where the transfer metal 20 is located (non-high resistance device area), and retain the oxidation barrier base film 51′′, the etch stop base film 52′′ and the etch barrier base film 53′′ in the area where the resistance layer 40 to be formed is located (high resistance device area).
  • the retained portions of the oxidation barrier base film 51′′, the etch stop base film 52′′ and the etch barrier base film 53′′ serve as the oxidation barrier film 51′, the etch stop film 52′ and the etch barrier film 53′ in the resistance protection film 50′.
  • the area where the resistance layer 40 to be formed is located is the high resistance device area, that is, the first area where the resistance protection film 50' is located is the high resistance device area, and the remaining areas are non-high resistance device areas.
  • the projection of the transfer metal 20 on the first dielectric film 30' does not overlap with the projection of the resistor layer 40 on the first dielectric film 30'.
  • the transfer metal 20 and the resistor layer 40 are staggered along the thickness direction of the chip.
  • the first region where the resistor layer 40 is located is called a high resistance region
  • the second region where the transfer metal 20 is located is called a low resistance region.
  • all regions except the first region in the first dielectric film 30' are divided into the second region.
  • a wet etching process may be used to pattern the resistor film 40'.
  • the etching barrier film 53' is used as an etching protection layer in the first etching process of forming the resistor layer 40.
  • the etching barrier film 53' is used to protect the portion of the resistor film 40' located below it from being etched in the first etching.
  • the formed resistor layer 40 is located in the first region of the first dielectric film 30'.
  • the resistor protection film 50 ′ is disposed on the surface of the resistor layer 40 , for example, it may be a projection of the resistor protection film 50 ′ on the first dielectric film 30 ′, which overlaps with a projection of the resistor layer 40 on the first dielectric film 30 ′.
  • the etching barrier film 53′ in the resistor protection film 50′ is used as an etching barrier layer in the high resistance device area.
  • it serves as an etching barrier layer in the dry etching process to prevent the high resistance device area from being opened, resulting in the removal of the resistor film 40′ in the high resistance device area.
  • the material of the etch stop film 53 ′ includes silicon nitride (SiN), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), silicon carbide (SiC), etc. Then, the material of the subsequently formed etch stop layer 53 includes SiN, SiCN, SiCON, SiC, etc.
  • the etching stop film 52 ′ in the resistor protection film 50 ′ is used as the first dielectric film 30 ′ for etching the non-high resistance device region to form an etching stop layer for the non-high resistance device connection hole, and is used to protect the resistor layer 40 .
  • the material of the etch stop film 52' includes silicon oxide (SiO), SiCN, SiCON, SiC, etc. Then, the material of the subsequently formed etch stop layer 52 includes SiO, SiCN, SiCON, SiC, etc. The material of the etch stop film 52' is different from the material of the etch barrier film 53' and the oxidation barrier film 51'.
  • the oxidation barrier film 51 ′ in the resistor protection film 50 ′ is used to prevent the etching stop film 52 ′ from oxidizing the resistor layer 40 below.
  • the material of the oxidation barrier film 51 ′ includes SiN, SiCN, SiCON, SiC, etc. Then, the material of the subsequently formed oxidation barrier layer 51 includes SiN, SiCN, SiCON, SiC, etc.
  • the first dielectric film 30 ′, the oxidation barrier film 51 ′, and the etching barrier film 53 ′ are made of the same material, which simplifies the process and avoids frequent material replacement.
  • the material of the resistor layer 40 is a conductive material, and the resistor layer 40 includes metal and non-metal oxides or metal nitrides.
  • the material of the resistor layer 40 includes titanium oxide, titanium nitride, tantalum nitride, and the like.
  • the second dielectric film 60' covers the resistor protection film 50' and the first dielectric film 30'.
  • the material of the second dielectric film 60' is different from that of the first dielectric film 30', so the materials of the first dielectric layer and the second dielectric layer formed finally are also different.
  • the material of the first dielectric film 30' includes silicon nitride
  • the material of the second dielectric film 60' includes silicon oxide (eg, silicon oxide), silicon doped oxide, silicon fluoride oxide, silicon carbon doped oxide, and the like.
  • the second dielectric film 60′ can be formed by chemical vapor deposition (CVD), physical vapor deposition or other deposition methods.
  • CVD chemical vapor deposition
  • physical vapor deposition or other deposition methods.
  • a fourth via hole 62 penetrating the second dielectric film 60' and a first via hole 531 penetrating the etching stop film 53' are formed by a second etching.
  • a second opening 72' penetrating the second dielectric film 60' and the first dielectric film 30' is formed, and the second opening 72' exposes the transfer metal 20.
  • the fourth via hole 62 is connected to the first via hole 531 to form a third opening 71', and the third opening 71' and the second opening 72' can be formed by photolithography and etching.
  • the etching stop film 52' is used as an etching protection layer in the second etching process of forming the first via hole 531, and is used to protect the resistance layer 40 below the etching stop film 52' from being etched in the second etching process.
  • step S400 the third opening 71′ and the second opening 72′ are formed simultaneously, the third opening 71′ penetrates the second dielectric film 60′ and the etching stop film 53′, and the second opening 72′ penetrates the second dielectric film 60′ and the first dielectric film 30′.
  • the third opening 71′ and the second opening 72′ are formed, the first dielectric layer 30 and the etching stop layer 53 are formed simultaneously.
  • a fourth via hole 62 is formed on the second dielectric film 60 ′, and a first via hole 531 is formed on the etching stop film 53 ′.
  • the first via hole 531 and the fourth via hole 62 are connected to form a third opening 71 ′.
  • the embodiment of the present application does not limit the shape and size of the third opening 71′ and the second opening 72′.
  • the second opening 72′ may expose part or all of the top surface of the transfer metal 20 away from the substrate 200.
  • the projection of the second opening 72′ on the substrate 200 may be located within the projection of the transfer metal 20 on the substrate 200, and the projection of the second opening 72′ on the substrate 200 may also overlap with the projection of the transfer metal 20 on the substrate 200.
  • the projection of the second opening 72′ on the substrate 200 may also cover the projection of the transfer metal 20 on the substrate 200, as long as it is ensured that the second conductive column subsequently formed in the second opening 72′ does not cause a short circuit between adjacent transfer metals 20.
  • the second opening 72′ is located directly above the transfer metal 20, the area of the second opening 72′ may be smaller than the area of the transfer metal 20, the area of the second opening 72′ may also be equal to the area of the transfer metal 20, and the area of the second opening 72′ may also be larger than the area of the transfer metal 20.
  • the embodiment of the present application is illustrated by taking the example that the area of the second opening 72 ′ is smaller than the area of the transfer metal 20 .
  • the embodiment of the present application does not limit the number of the third openings 71′ and the second openings 72′.
  • the number of the third openings 71′ corresponds to the number of the resistance layers 40
  • the number of the second openings 72′ corresponds to the number of the transition metals 20.
  • one transition metal 20 can be arranged corresponding to one second opening 72′, that is, only one second opening 72′ can be arranged above one transition metal 20.
  • One transition metal 20 can also be arranged corresponding to multiple second openings 72′, that is, multiple second openings 72′ can be arranged above one transition metal 20.
  • multiple transition metals 20 are arranged corresponding to the same second opening 72′, that is, the same second opening 72′ is arranged above multiple transition metals 20 (for example, the multiple transition metals 20 transmit the same signal).
  • a third opening 71 ′ and a plurality of second openings 72 ′ are formed in step S400 , each third opening 71 ′ is arranged corresponding to an electrode layer 40 , and each second opening 72 ′ exposes a transfer metal 20 .
  • the etching byproducts can be removed first, and then the subsequent step S500 is performed.
  • the method of removing the etching byproducts can be, for example, dry cleaning first to remove most of the etching byproducts; and then wet cleaning to deeply remove the etching byproducts.
  • Heavy atoms may refer to atoms having an atomic number greater than that of silicon, and heavy atoms may be, for example, heavy metals such as Ge (germanium), Ar (argon), Si (silicon), and Xe (xenon).
  • the structure obtained in step S400 is implanted with heavy atoms, and the heavy atom implantation can change the film layer properties on the surface of the second dielectric film 60'.
  • the surface here includes the top surface of the second dielectric film 60' away from the first dielectric film 30', and the side surfaces of the second dielectric film 60' that surround the third opening 71' and the second opening 72'.
  • the improved adhesion between the second conductive pillar and the side of the second opening 72' can improve the problem that the random and irregular gap defects between the second conductive pillar and the side of the second opening 72' lead to the infiltration of acidic polishing liquid or etching liquid or other solutions from the gap between the second conductive pillar and the side of the second opening 72' during the subsequent chemical mechanical polishing (CMP) after hole filling or the subsequent film patterning by etching process, thereby damaging the transfer metal 20 at the bottom of the second conductive pillar and eventually causing chip failure.
  • CMP chemical mechanical polishing
  • the problem that the second conductive pillar is easily carried away during the subsequent chemical mechanical polishing process due to the poor adhesion between the second conductive pillar and the side of the second opening 72' can be improved, resulting in the loss of the second conductive pillar, thereby causing chip failure and causing chip reliability.
  • Performing the first heavy atom injection process before forming the second conductive column can avoid the sputtering of metal atoms (such as W) in the conductive column body during the heavy atom injection process, compared with the heavy atom injection and exit process after forming the second conductive column, causing the metal atoms to sputter into the second dielectric film 60'. Since the metal atoms are not easily removed after being sputtered into the second dielectric film 60', it is easy to cause chip failure. Therefore, the preparation method provided in the embodiment of the present application can improve the product yield.
  • metal atoms such as W
  • the gap between the second conductive column and the second dielectric film 60' is filled near the top of the second conductive column, but the gap near the bottom of the second conductive column has not been eliminated, resulting in an unsatisfactory filling effect of the gap near the transfer metal 20.
  • the etching extent may be to remove the portion of the transfer metal 20 doped with heavy atoms.
  • the extent of etching may be to etch back the transfer metal 20, remove the portion doped with heavy atoms in the transfer metal 20, and form a groove on the surface of the transfer metal 20, the groove being connected to the second opening 72′.
  • the opening area of the groove is greater than the opening area of the second opening 72′.
  • the shape of the groove is not limited.
  • FIG. 12 shows an arc-shaped groove as an example.
  • the groove may also be a rectangular groove, a V-shaped groove, or a trapezoidal groove.
  • the cross-sectional area of the end of the second conductive column formed subsequently close to the transfer metal 20 can be larger than the cross-sectional area at other positions, thereby generating a rivet effect.
  • a solution such as an acidic grinding liquid or an etching liquid flows into the gap between the second conductive column and the second dielectric film 60' during the subsequent preparation process, it will first contact the portion of the end of the second conductive column located in the groove, thereby reducing the damage of the solution such as the acidic grinding liquid or the etching liquid to the transfer metal 20.
  • step S600 may not be executed, and after step S500 is executed, the subsequent step S700 is executed.
  • a copper (Cu) column is formed as the second conductive column body 721 using an electroplating process.
  • CVD chemical vapor deposition
  • a thinner titanium nitride (TiN) is used as a barrier layer, and a hole-filling cobalt (Co) column is used as the second conductive column body 721.
  • TiN titanium nitride
  • Co hole-filling cobalt
  • a selective deposition process is used to form a second conductive column body 721 in the second opening 72′.
  • the second conductive pillar body 721 formed by the selective growth process is in contact with the sidewall of the second opening 72 ′.
  • the selective growth process refers to epitaxial growth in a limited area on the substrate.
  • the epitaxial growth starts from the surface of the transition metal 20, and does not start from the surface of the second dielectric film 60' and the etch stop film 52'.
  • the second conductive column body 721 is finally formed by the selective growth process in the present application, the bottom surface of the second conductive column body 721 is directly in contact with the transfer metal 20, the side surface of the second conductive column body 721 is directly in contact with the side wall of the second opening 72′, the second conductive column body 721 is a solid structure, and there are no pores inside the second conductive column body 721.
  • the second conductive column body 721 is epitaxially grown directly on the surface of the metal structure of the transfer metal 20 by a selective epitaxial growth process. Therefore, the second conductive column body 721 is formed by a selective growth process without the need for film layers such as a barrier layer and a nucleation layer, which can reduce the contact resistance between the second conductive column body 721 and the transfer metal 20 and can be applied to chip structures with a high aspect ratio. Moreover, since the metal tungsten grows from bottom to top, the second conductive column body 721 formed will not have pores inside, which can reduce the resistance of the second conductive column body 721.
  • the height of the second conductive pillar body 721 can be adjusted according to the depth of the second opening 72' and the polishing thickness of the subsequent chemical mechanical polishing process.
  • the heights of the multiple second conductive pillar bodies 721 can be the same or different.
  • the surface of the second conductive pillar body 721 is lower than the surface of the second dielectric film 60'. In other words, the depth of the second conductive pillar body 721 is less than the depth of the second opening 72'.
  • the height of the second conductive column body 721 that is polished away can be reduced, thereby reducing material waste and reducing costs.
  • the material of the second conductive column body 721 is not limited.
  • the material of the second conductive column body 721 may include copper (Cu), aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), ruthenium (Ru), cobalt (Co), nickel (Ni), palladium (Pd), platinum (Pt), tungsten (W), silver (Ag), gold (Au), cobalt (CN) and other materials.
  • the second opening 72 ′ is first surface treated to remove chemical residues and dangling bonds on the sidewall of the second opening 72 ′ and the surface of the transfer metal 20 to improve selectivity.
  • the chemical residues may be, for example, chemical substances remaining in the process of forming the second opening 72 ′, and the dangling bonds may be, for example, chemical bonds with no electrons to pair with.
  • the surface of the second opening 72' may be treated by, for example, heat treatment, plasma treatment, treatment with a reducing gas (such as hydrogen), treatment with an oxidizing gas (such as oxygen and nitrous oxide), treatment with an inert gas, etc.
  • a reducing gas such as hydrogen
  • an oxidizing gas such as oxygen and nitrous oxide
  • the concentration of heavy atoms in the second dielectric film 60′ increases, causing the surface of the second dielectric film 60′ to expand, filling the gap between the second conductive column body 721 and the side wall of the second opening 72′, making the contact between the second conductive column body 721 and the side wall of the second opening 72′ more dense, further improving the adhesion between the second conductive column body 721 and the side wall of the second opening 72′.
  • At least one of the implantation energy, the implantation dose, or the implantation angle during the second heavy atom implantation is smaller than that during the first heavy atom implantation.
  • the energy of the second heavy atom implantation is 30 KeV
  • the dose is 3E15
  • the angle is 30°
  • the energy of the first heavy atom implantation is 50 KeV
  • the dose is 3E18
  • the angle is 60°.
  • the heavy atoms injected for the second time can be mainly concentrated on the side of the second dielectric film 60′ close to the end of the second conductive column body 721, thereby reducing the number of heavy atoms splashed onto the surface of the second dielectric film 60′ during the heavy atom injection process, thereby improving the problem of chip performance being affected by the presence of heavy atoms in the second dielectric film 60′.
  • the second heavy atom implantation mainly implants heavy atoms into the second dielectric film 60', and almost none or no heavy atoms are implanted into the first dielectric film 30'.
  • the concentration of heavy atoms in the final second dielectric layer is greater than that in the first dielectric layer.
  • step S900 what is removed in step S900 is actually the portion of the etch stop film 52′ and the oxidation barrier film 51′ located below the third opening 71′.
  • a second via hole is formed on the etch stop film 52′, and a third via hole is formed on the oxidation barrier film 51′ to form a first opening 73′.
  • the first opening 73' penetrates the second dielectric film 60' and the resistor protection film 50', and the first opening 73' exposes the resistor layer 40.
  • an etching stop layer 52 and an oxidation barrier layer 51 are formed, thereby forming a resistor protection layer 50.
  • the resistor protection layer 50 includes an oxidation barrier layer 51, an etching stop layer 52 and an etching barrier layer 53 which are sequentially stacked in a direction away from the resistor layer 40, the oxidation barrier layer 51 has a third via hole 511, the etching stop layer 52 has a second via hole 521, and the etching barrier layer 53 has a first via hole 531.
  • the film layers etched in the first etching, the second etching and the current etching steps are different, so the etching parameters of the first etching, the second etching and the current etching are different.
  • the damage to the resistor layer 40 can be reduced.
  • the resistor layer 40 is divided into two parts, the first part 41 is located below the first opening 73′, and the second part 42 is located below the resistor protection layer 50. After the first conductive column is subsequently formed in the first opening 73′, the first conductive column contacts the first part 41.
  • the film layer above the first part 41 is not removed until the first conductive column is ready to be formed, and a separate removal process is used to remove only this part of the film layer, and there is almost no over-etching damage.
  • step S900 may be performed first, and then step S800 may be performed.
  • a first conductive column 71 is formed in the first opening 73', and a second dielectric layer 60 is formed.
  • the first conductive column 71 is electrically connected to the resistance layer 40 .
  • step S1000 includes:
  • the material of the first filling film 711 ′ is, for example, a conductive material.
  • the conductive film 712′ may be formed by a metal oxide chemical vapor deposition (MOCVD) process.
  • MOCVD metal oxide chemical vapor deposition
  • the first filling film 711 ′ is a barrier layer, and then the conductive film 712 ′ may be formed by an electroplating process.
  • the first filling film 711′, the conductive film 712′ and the second dielectric film 60′ are ground to form a first filling layer (grue layer) 711, a first conductive column body 712 and a second dielectric layer 60.
  • the first filling film 711 ′, the conductive film 712 ′ and the second dielectric film 60 ′ are polished by a chemical mechanical polishing process.
  • the formed first conductive column 71 is located in the first opening 73 ′.
  • the first conductive column 71 includes a first conductive column body 712 and a first filling layer 711 .
  • the first filling layer 711 covers the bottom surface and side surfaces of the first conductive column body 712 .
  • the formed second conductive pillar 72 is located in the second opening 72 ′, and the second conductive pillar 72 includes a second conductive pillar body 721 .
  • the third conductive column body 723 and the second filling layer 722 are also formed.
  • the formed second conductive column 72 is located in the second opening 72′, and the second conductive column 72 includes a second conductive column body 721, a third conductive column body 723 and a second filling layer 722.
  • the third conductive column body 723 is arranged on the side of the second conductive column body 721 away from the transfer metal 20, and the second filling layer 722 covers the bottom and side surfaces of the third conductive column body 723.
  • the portion of the first filling film 711′ located in the third opening 71′ serves as the first filling layer 711
  • the portion of the first filling film 711′ located in the second opening 72′ serves as the second filling layer 722.
  • the portion of the conductive film 712′ located in the third opening 71′ serves as the first conductive column body 712
  • the portion of the conductive film 712′ located in the second opening 72′ serves as the third conductive column body 723.
  • the remaining portion is used as the second dielectric layer 60, the surface of the second dielectric layer 60 away from the first dielectric layer 30 is flat, and the first filling film 711' and the conductive film 712' on the surface of the second dielectric film 60' are completely removed.
  • the above-mentioned preparation method is used to form the first conductive pillar 71.
  • the chemical mechanical polishing of the second conductive pillar 72 can be completed simultaneously, and the preparation of the second conductive pillar 72 can be completed simultaneously. Therefore, the process steps can be reduced, the cost can be reduced, and the efficiency can be improved.
  • step S1000 includes: forming the first conductive pillar 71 by a selective growth process.
  • the first conductive pillar 71 does not include the first filling layer 711 .
  • a first conductive pattern 81 and a second conductive pattern 82 are formed on a side of the second dielectric layer 60 away from the transfer metal 20 .
  • the first conductive pattern 81 is electrically connected to the first conductive pillar 71
  • the second conductive pattern 82 is electrically connected to the second conductive pillar 72 .
  • the embodiment of the present application does not limit the shape, function, and material of the first conductive pattern 81 , and it can be reasonably set according to the application scenario.
  • the first conductive pattern 81 and the second conductive pattern 82 are conductive patterns included in the redistribution layer.
  • the first conductive pattern 81 and the second conductive pattern 82 are conductive patterns in the redistribution layer prepared by the back-end process.
  • the first conductive pattern 81 and the second conductive pattern 82 are conductive patterns in a wiring layer in the redistribution layer that is closest to the second dielectric layer 60.
  • the first conductive pattern 81 and the second conductive pattern 82 may be columnar, linear, or other shapes, which are not limited in the present embodiment.
  • a first conductive pattern 81 can be electrically connected to one or more first conductive pillars 71.
  • the first conductive pattern 81 and the first conductive pillar 71 can be electrically connected by contact or indirectly.
  • the two ends of the first conductive pillar 71 are electrically connected to the resistance layer 40 and the first conductive pattern 81 respectively.
  • a second conductive pattern 82 can be electrically connected to one or more second conductive pillars 72.
  • the second conductive pattern 82 and the second conductive pillar 72 can be electrically connected by contact or indirectly.
  • the two ends of the second conductive pillar 72 are electrically connected to the transfer metal 20 and the second conductive pattern 82 respectively.
  • the resistor protection layer 50 above the resistor layer 40 includes an etch stop layer 52 and an etch barrier layer 53.
  • the etch barrier layer 53 is used as a barrier layer when etching the resistor film 40' to form the resistor layer 40 to protect the pattern shape of the resistor layer 40.
  • the etch stop layer 52 is used as a stop layer when etching the etch barrier layer 53 to form an opening for placing the first conductive column 71. In this way, due to the existence of the etch stop layer 52, no matter what etching process is used to form the first via 531 on the etch barrier layer 53 during the second etching process, it will hardly affect the resistor layer 40 below the etch stop layer 52.
  • the resistor layer 40 can improve the yield of the resistor layer 40 and improve the compatibility of the process in the chip preparation process.
  • a separate etching step is used to form the second via 521 on the etch stop layer 52.
  • the damage to the resistor layer 40 can be minimized and the yield of the resistor layer 40 can be improved.
  • the resistance layer 40 is not exposed, which can reduce the exposure time of the resistance layer 40, reduce the probability of the resistance layer 40 being oxidized, and further improve the yield of the resistance layer 40.
  • the yield of the resistance layer 40 in the chip prepared by the present application can be significantly improved.
  • the actual resistance value of the resistance layer 40 is closer to the set resistance value, which can effectively improve the resistance deviation caused by the damage of the resistance layer 40 and improve the chip performance.
  • the preparation method provided in the embodiment of the present application can be compatible with the preparation process of the first conductive pillar 71 in the high resistance device region and the second conductive pillar 72 in the low resistance device region.
  • the third opening 71′ and the second opening 72′ are formed simultaneously, and the grinding of the second conductive pillar 72 is completed while the first conductive pillar 71 is formed.
  • the preparation method of the chip provided in the embodiment of the present application can achieve compatibility with the preparation process of the first conductive pillar 71 and the second conductive pillar 72 on the basis of ensuring the product yield of the resistance layer 40.
  • the chip provided in the embodiment of the present application includes a transistor 10, a first dielectric layer 30, a resistor layer 40 and a resistor protection layer 50 stacked in sequence in the first region on the first dielectric layer 30, a second dielectric layer 60 and a first conductive column 71.
  • the transistor 10 is covered with an interlayer dielectric layer ILD, which exposes the transistor's source S, drain D and gate G.
  • the first dielectric layer 30 is disposed on the transistor 10 , for example, on the interlayer dielectric layer ILD.
  • the chip further includes a transfer metal 20, which is electrically connected to the source S, drain D and gate G of the transistor 10, and is used to lead the source S, drain D and gate G of the transistor 10 to the same plane.
  • the transfer metal 20 is located in the interlayer dielectric layer ILD.
  • the resistance layer 40 is disposed in a first region of the first dielectric layer 30 .
  • the first region may correspond to a high resistance device region of the chip, for example.
  • the resistance protection layer 50 covers the surface of the resistance layer 40 .
  • the resistor protection layer 50 includes multiple dielectric covering layers.
  • the resistor protection layer 50 includes three dielectric covering layers, which include an oxidation barrier layer 51 , an etch stop layer 52 , and an etch barrier layer 53 stacked in sequence in a direction away from the resistor layer 40 .
  • the etch stop layer 52 is disposed between the etch barrier layer 53 and the resistor layer 40
  • the oxidation barrier layer 51 is disposed between the etch stop layer 52 and the resistor layer 40 .
  • the oxidation blocking layer 51 has a third via hole 511
  • the etch stop layer 52 has a second via hole 521
  • the etch blocking layer 53 has a first via hole 531.
  • the third via hole 511, the second via hole 521, and the first via hole 531 are connected.
  • the etch barrier layer 53 is used as an etch protection layer in the first etching process of forming the resistor layer 40
  • the etch stop layer 52 is used as an etch protection layer in the second etching process of forming the first via hole 531
  • the oxidation barrier layer 51 is used as a protection layer to prevent the etch stop layer 52 from oxidizing the resistor layer 40 .
  • the materials of the etch barrier layer 53 and the etch stop layer 52 include different dielectric materials.
  • the material of the oxidation barrier layer 51 is a dielectric material that does not contain oxygen.
  • the material of the etch stop layer 52 is different from that of the oxidation barrier layer 51 and the etch barrier layer 53 .
  • the etch stop layer 52 is made of the same material as the second dielectric layer 60, and the oxidation barrier layer 51, the etch barrier layer 53 and the first dielectric layer 30 are made of the same material. In this way, the types of materials can be reduced, the preparation process can be simplified, and the cost can be reduced.
  • the second dielectric layer 60 is disposed on the first dielectric layer 30 and covers the resistance protection layer 50 .
  • the second dielectric layer 60 has a fourth via hole, which is connected to the first via hole 531 on the etching stop layer 53 .
  • the materials of the first dielectric layer 30 and the second dielectric layer 60 are different.
  • the material of the first dielectric layer 30 includes silicon nitride
  • the material of the second dielectric layer 60 includes silicon oxide.
  • the resistance layer 40 and the resistance protection layer 50 are sandwiched between the first dielectric layer 30 and the second dielectric layer 60 .
  • the first dielectric layer 30 is in direct contact with the second dielectric layer 60 .
  • the first conductive pillar 71 penetrates the second dielectric layer 60 and the resistor protection layer 50, and the first conductive pillar 71 is electrically connected to the resistor layer 40.
  • the first conductive pillar 71 passes through the fourth via hole, the first via hole, the second via hole, and the third via hole to be electrically connected to the resistor layer 40.
  • the fourth via hole, the first via hole, the second via hole, and the third via hole constitute a first opening 73'.
  • FIG16 illustrates an example in which a chip includes one first conductive pillar 71.
  • the embodiment of the present application does not limit the shape of the first conductive pillar 71 , and the shape of the first conductive pillar 71 may be a cylindrical shape, a rectangular column shape, or a cuboid column shape.
  • the resistance layer 40 may be divided into a first portion 41 contacting the first conductive pillar 71 and a second portion contacting the resistance protection layer 50 .
  • the resistor protection layer 50 above the first portion 41 is not pierced until the first conductive pillar 71 is prepared. Therefore, the exposure time of the first portion 41 is short and the damage is small. In addition, a separate etching process is used to open the resistor protection layer 50, so the first portion 41 is almost free of over-etching damage.
  • the ratio of the thickness of the first portion 41 to the thickness of the second portion 42 in the resistance layer 40 can range from 0.2 to 1.
  • the ratio of the thickness of the first portion 41 to the thickness of the second portion 42 is 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.9.
  • the thickness of the first portion 41 and the thickness of the second portion 42 of the resistance layer 40 are equal.
  • the first conductive pillar 71 includes a first conductive pillar body 712 and a first filling layer 711 , and the first filling layer 711 covers the side surface and the bottom surface of the first conductive pillar body 712 .
  • the first conductive pillar 71 includes a first conductive pillar body 712 and a first filling layer 711. During the preparation of the first conductive pillar 71, chemical mechanical polishing can be performed on the second conductive pillar 72 simultaneously, which can reduce process steps, reduce costs, and improve efficiency.
  • the chip further includes a via metal 20 and a second conductive pillar 72 .
  • the transfer metal 20 may be, for example, a transfer metal on the surface of an integrated circuit.
  • the transfer metal 20 and the resistor layer 40 are arranged in a staggered manner.
  • the projection of the transfer metal 20 on the dielectric layer 30 does not overlap with the projection of the resistor layer 40 on the first dielectric layer 30 .
  • the second conductive pillar 72 penetrates the second dielectric layer 60 and the first dielectric layer 30, and is electrically connected to the transistor 10.
  • the second conductive pillar 72 and the transistor 10 may be electrically connected by contact, or may be electrically connected by a transfer metal 20, or may be coupled to the transistor 10 by other means.
  • FIG16 illustrates a chip including a plurality of second conductive pillars 72 as an example.
  • the embodiment of the present application does not limit the shape of the second conductive pillar 72 , and the shape of the second conductive pillar 72 may be a cylindrical shape, a rectangular column shape, or a cuboid column shape.
  • the second conductive pillar 72 is composed of a second conductive pillar body 721 formed by selective deposition.
  • the second conductive column 72 includes a second conductive column body 721 , a third conductive column body 723 and a second filling layer 722 .
  • the third conductive column body 723 is disposed above the second conductive column body 721 .
  • the third conductive column body 723 may be formed simultaneously with the first conductive column body 712
  • the second filling layer 722 may be formed simultaneously with the first filling layer 711 .
  • the sidewalls of the first dielectric layer 30 in contact with the second conductive pillar 72 and the sidewalls of the second dielectric layer 60 in contact with the second conductive pillar 72 are doped with heavy atoms.
  • the heavy atoms in the second dielectric layer 60 may be formed by doping through a single heavy atom doping process, or may be formed by doping through a double heavy atom doping process.
  • the adhesion between the second conductive pillar 72 and the sidewall of the second opening 72 ′ can be improved, and the problem of damage to the transfer metal 20 caused by poor adhesion between the second conductive pillar 72 and the sidewall can be effectively improved.
  • the chip further includes a first conductive pattern 81 and a second conductive pattern 82, the first conductive pattern 81 and the second conductive pattern 82 are arranged on the side of the second dielectric layer 60 away from the first dielectric layer 30, the first conductive pillar 71 is electrically connected to the first conductive pattern 81, and the second conductive pillar 72 is electrically connected to the second conductive pattern 82.
  • the first conductive pattern 81 and the second conductive pattern 82 may be electrically connected or not electrically connected.
  • the resistor protection layer 50 above the resistor layer 40 includes an etch stop layer 52 and an etch barrier layer 53.
  • the etch barrier layer 53 is used as a barrier layer when etching the resistor film 40' to form the resistor layer 40 to protect the pattern shape of the resistor layer 40.
  • the etch stop layer 52 is used as a stop layer when etching the etch barrier layer 53 to form an opening for placing the first conductive column 71. In this way, due to the existence of the etch stop layer 52, no matter what etching process is used to form the first via 531 on the etch barrier layer 53 during the second etching process, it will hardly affect the resistor layer 40 below the etch stop layer 52.
  • the resistor layer 40 can improve the yield of the resistor layer 40 and improve the compatibility of the process in the chip preparation process.
  • a separate etching step is used to form the second via 521 on the etch stop layer 52.
  • the damage to the resistor layer 40 can be minimized and the yield of the resistor layer 40 can be improved.
  • the resistance layer 40 is not exposed, which can reduce the exposure time of the resistance layer 40 , reduce the probability of the resistance layer 40 being oxidized, and further improve the yield of the resistance layer 40 .
  • Example 2 The main difference between Example 2 and Example 1 is that the preparation processes of the third opening 71 ′ and the second opening 72 ′ are different.
  • the present application provides a chip and a method for preparing the same, including:
  • the first etching in the second etching process forms a fourth via hole 62 and a fifth via hole 61 penetrating the second dielectric film 60 ′.
  • the fourth via hole 62 is located above the resistor layer 40, and the fourth via hole 62 corresponds to the position of the resistor layer 40.
  • the projection of the fourth via hole 62 on the first dielectric film 30' is located within the projection of the resistor layer 40 on the first dielectric film 30'.
  • the fifth via hole 61 is located above the transfer metal 20, and the fifth via hole 61 corresponds to the position of the transfer metal 20. Alternatively, it can be understood that the projection of the fifth via hole 61 on the first dielectric film 30' is located within the projection of the transfer metal 20 on the first dielectric film 30'.
  • the second etching in the second etching process forms a first via hole 531 on the etching stopper film 53 ′.
  • the material of the first dielectric film 30' is the same as that of the etching stop film 53'. Then, during the third etching process, a sixth via hole 31 penetrating the first dielectric film 30' can be formed synchronously, and the sixth via hole 31 is connected to the fifth via hole 61 as a second opening 72'. At the same time, the first dielectric layer 30 is formed.
  • the etching stop film 52 ′ is used as an etching protection layer in the second etching process for forming the first via hole 531 .

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a chip and a preparation method therefor, and an electronic device, which are used for improving the yield of a conductive component in a chip. The chip comprises: a first dielectric layer, wherein the first dielectric layer comprises a first region and a second region; a resistor layer and a resistor protection layer, which are sequentially stacked in the first region on the first dielectric layer, wherein the resistor protection layer comprises an etching stop layer and an etching barrier layer, the etching stop layer is arranged between the etching barrier layer and the resistor layer, the etching barrier layer has a first via hole, and the etching stop layer has a second via hole; a second dielectric layer, which is arranged on the first dielectric layer and covers the resistor protection layer; and a first conductive pillar, which penetrates the second dielectric layer and passes through the first via hole and the second via hole to electrically connect to the resistor layer, wherein the etching barrier layer is used as an etching protection layer in a first etching process for forming the resistor layer, and the etching stop layer is used as an etching protection layer in a second etching process for forming the first via hole.

Description

芯片及其制备方法、电子设备Chip and preparation method thereof, and electronic device 技术领域Technical Field
本申请涉及半导体技术领域，尤其涉及一种芯片及其制备方法、电子设备。The present application relates to the field of semiconductor technology, and in particular to a chip and a method for preparing the same, and an electronic device.
背景技术Background technique
随着电子技术的发展，用户对电子设备的性能要求越来越高，使得电子设备中芯片尺寸越来越大、数量越来越多。但随着电子设备不断向集成化、超薄化趋势发展，电子设备中的芯片也不得不向小型化发展。With the development of electronic technology, users have higher and higher requirements for the performance of electronic devices, which makes the size of chips in electronic devices larger and the number of chips larger. However, as electronic devices continue to develop towards integration and ultra-thinness, the chips in electronic devices have to develop towards miniaturization.
而当前的一些产品中，芯片不仅包括晶体管等有源器件，还会包括电阻等无源器件。在这种有源器件和无源器件集成的芯片中，电阻的良率问题一直是本领域技术人员难以突破的技术关卡。In some current products, chips include not only active devices such as transistors, but also passive devices such as resistors. In such chips integrating active and passive devices, the yield rate of resistors has always been a technical barrier that is difficult for technicians in this field to overcome.
发明内容Summary of the invention
本申请实施例提供一种芯片及其制备方法、电子设备，用于提高芯片中电阻的良率。The embodiments of the present application provide a chip and a method for manufacturing the same, and an electronic device, which are used to improve the yield of resistors in the chip.
为达到上述目的，本申请采用如下技术方案：In order to achieve the above objectives, this application adopts the following technical solutions:
本申请实施例的第一方面，提供一种芯片，芯片可以是裸芯片，也可以是封装后的芯片。芯片包括第一介质层，第一介质层包括第一区域和第二区域；电阻层和电阻保护层，依次层叠设置在第一介质层上的第一区域内；电阻保护层包括刻蚀停止层和刻蚀阻挡层，刻蚀停止层设置在刻蚀阻挡层与电阻层之间；刻蚀阻挡层具有第一过孔，刻蚀停止层具有第二过孔；第二介质层，设置在第一介质层上且覆盖电阻保护层；第一导电柱，贯穿第二介质层，并穿过第一过孔和第二过孔与电阻层电连接；其中，刻蚀阻挡层用于作为形成电阻层的第一刻蚀过程中的刻蚀保护层，刻蚀停止层用于作为形成第一过孔的第二刻蚀过程中的刻蚀保护层。In the first aspect of the embodiment of the present application, a chip is provided, which can be a bare chip or a packaged chip. The chip includes a first dielectric layer, which includes a first region and a second region; a resistor layer and a resistor protection layer, which are sequentially stacked in the first region on the first dielectric layer; the resistor protection layer includes an etch stop layer and an etch barrier layer, and the etch stop layer is arranged between the etch barrier layer and the resistor layer; the etch barrier layer has a first via hole, and the etch stop layer has a second via hole; a second dielectric layer, which is arranged on the first dielectric layer and covers the resistor protection layer; a first conductive column, which penetrates the second dielectric layer and is electrically connected to the resistor layer through the first via hole and the second via hole; wherein the etch barrier layer is used as an etch protection layer in the first etching process of forming the resistor layer, and the etch stop layer is used as an etch protection layer in the second etching process of forming the first via hole.
本申请实施例提供的芯片，电阻层上方的电阻保护层包括刻蚀停止层和刻蚀阻挡层，刻蚀阻挡层作为对电阻膜进行刻蚀以形成电阻层时的阻挡层，来保护电阻层的图案形状。刻蚀停止层作为对刻蚀阻挡层进行刻蚀以形成放置第一导电柱的第一过孔时的停止层。这样一来，由于刻蚀停止层的存在，使得无论采用什么刻蚀工艺在刻蚀阻挡层上形成开口，都几乎不会对刻蚀停止层下方的电阻层产生影响，以保证电阻层的良率。而后续需要制备第一导电柱时，再采用单独的刻蚀步骤在刻蚀停止层上形成第二过孔，通过调整刻蚀条件，可以最大程度的降低对电阻层的损伤，提高电阻层的良率。而且，在制备第一导电柱之前，不露出电阻层，可减少电阻层的暴露时间，降低电阻层被氧化的概率，可进一步提高电阻层的良率。In the chip provided by the embodiment of the present application, the resistor protection layer above the resistor layer includes an etch stop layer and an etch barrier layer. The etch barrier layer is used as a barrier layer when etching the resistor film to form the resistor layer to protect the pattern shape of the resistor layer. The etch stop layer is used as a stop layer when etching the etch barrier layer to form the first via hole for placing the first conductive column. In this way, due to the existence of the etch stop layer, no matter what etching process is used to form an opening on the etch barrier layer, it will hardly affect the resistor layer below the etch stop layer, so as to ensure the yield of the resistor layer. When the first conductive column needs to be prepared later, a separate etching step is used to form a second via hole on the etch stop layer. By adjusting the etching conditions, the damage to the resistor layer can be minimized and the yield of the resistor layer can be improved. Moreover, before preparing the first conductive column, the resistor layer is not exposed, which can reduce the exposure time of the resistor layer, reduce the probability of oxidation of the resistor layer, and further improve the yield of the resistor layer.
在一种可能的实现方式中，电阻层包括与第一导电柱接触的第一部分和与电阻保护层接触的第二部分，第一部分的厚度与第二部分的厚度之比的取值范围为0.2-1。本申请实施例提供的芯片，在制备过程中，通过电阻保护层对电阻层进行保护，在制 备第一导电柱之前，不露出电阻层。使得第一部分的暴露时间短，损伤较小。而且在需要露出电阻层时，是采用单独的刻蚀工艺对电阻保护层进行开孔处理，第一部分几乎不会存在过刻损伤的情况。因此，本申请实施例提供的芯片中，可降低芯片制备过程中对电阻层位于第一导电柱下方的第一部分的损伤，电阻层中第一部分的厚度与第二部分的厚度之比可达到0.2-1。与相关技术中电阻层的第一部分几乎全部损伤相比，本申请芯片中电阻层的实际阻值与设定阻值更为接近，可以有效改善电阻层损伤引起的阻值偏差，提升芯片性能。In a possible implementation, the resistor layer includes a first part in contact with the first conductive column and a second part in contact with the resistor protection layer, and the ratio of the thickness of the first part to the thickness of the second part is in the range of 0.2-1. In the chip provided in the embodiment of the present application, the resistor layer is protected by the resistor protection layer during the preparation process, and the resistor layer is not exposed before the first conductive column is prepared. The exposure time of the first part is short and the damage is small. Moreover, when the resistor layer needs to be exposed, a separate etching process is used to open the resistor protection layer, and there is almost no over-etching damage to the first part. Therefore, in the chip provided in the embodiment of the present application, the damage to the first part of the resistor layer located below the first conductive column during the chip preparation process can be reduced, and the ratio of the thickness of the first part of the resistor layer to the thickness of the second part can reach 0.2-1. Compared with the first part of the resistor layer in the related art that is almost completely damaged, the actual resistance value of the resistor layer in the chip of the present application is closer to the set resistance value, which can effectively improve the resistance deviation caused by the damage of the resistor layer and improve the chip performance.
在一种可能的实现方式中，电阻保护层还包括氧化阻挡层，氧化阻挡层设置在刻蚀停止层与电阻层之间，氧化阻挡层具有第三过孔，第三过孔与第二过孔连通。通过设置氧化阻挡层，可以阻止电阻保护层对电阻层的氧化。In a possible implementation, the resistor protection layer further includes an oxidation barrier layer, which is disposed between the etching stop layer and the resistor layer, and has a third via hole, which is connected to the second via hole. By providing the oxidation barrier layer, the resistor protection layer can be prevented from oxidizing the resistor layer.
在一种可能的实现方式中，第一导电柱包括第一导电柱本体和第一填充层，第一填充层覆盖第一导电柱本体的侧面和底面。通过设置第一填充层，可提高第一导电柱与第二介质层的粘附性。In a possible implementation, the first conductive column includes a first conductive column body and a first filling layer, and the first filling layer covers the side and bottom surfaces of the first conductive column body. The first filling layer can improve the adhesion between the first conductive column and the second dielectric layer.
在一种可能的实现方式中，氧化阻挡层的材料包括氮化硅，刻蚀停止层的材料包括氧化硅，刻蚀阻挡层的材料包括氮化硅。这是一种低成本的实现方式。In a possible implementation, the material of the oxidation barrier layer includes silicon nitride, the material of the etch stop layer includes silicon oxide, and the material of the etch barrier layer includes silicon nitride. This is a low-cost implementation.
在一种可能的实现方式中，电阻层的材料包括氮化钛、氮化钽或者氧化钛。这是一种低成本的实现方式。In a possible implementation, the material of the resistance layer includes titanium nitride, tantalum nitride or titanium oxide. This is a low-cost implementation.
在一种可能的实现方式中，芯片还包括第二导电柱和晶体管；晶体管设置在第一介质层远离第二介质层一侧，晶体管在第一介质层上的投影与电阻层在第一介质层上的投影不交叠；第二导电柱贯穿第二介质层和第一介质层、与晶体管电连接。本申请实施例提供的制备，可以实现在保证电阻层产品良率的基础上，兼容电阻层所在区域的第一导电柱与晶体管所在区域的第二导电柱的制备。In a possible implementation, the chip further includes a second conductive column and a transistor; the transistor is disposed on a side of the first dielectric layer away from the second dielectric layer, and a projection of the transistor on the first dielectric layer does not overlap with a projection of the resistor layer on the first dielectric layer; the second conductive column penetrates the second dielectric layer and the first dielectric layer and is electrically connected to the transistor. The preparation provided in the embodiment of the present application can achieve the preparation of the first conductive column in the area where the resistor layer is located and the second conductive column in the area where the transistor is located while ensuring the product yield of the resistor layer.
在一种可能的实现方式中，第一介质层与第二导电柱接触的侧壁和第二介质层与第二导电柱接触的侧壁处掺杂有重原子。通过在侧壁处掺杂有重原子，可以改善第二导电柱与第二开口侧壁粘附性差的问题。In a possible implementation, the sidewalls where the first dielectric layer contacts the second conductive pillar and the sidewalls where the second dielectric layer contacts the second conductive pillar are doped with heavy atoms. By doping the sidewalls with heavy atoms, the problem of poor adhesion between the second conductive pillar and the sidewalls of the second opening can be improved.
在一种可能的实现方式中，第二介质层中重原子的浓度大于第一介质层中重原子的浓度。这样一来，第二介质层的膨胀程度大于第一介质层的膨胀程度，即使第一介质层与第二导电柱未贴合，第二介质层也可以与第二导电柱贴合，以改善因后续制备过程中的酸性研磨液从第二导电柱与第二介质层之间的缝隙处流入，而损害晶体管的问题。In a possible implementation, the concentration of heavy atoms in the second dielectric layer is greater than that in the first dielectric layer. In this way, the expansion degree of the second dielectric layer is greater than that of the first dielectric layer, and even if the first dielectric layer and the second conductive pillar are not attached, the second dielectric layer can be attached to the second conductive pillar, so as to improve the problem of damaging the transistor due to the acidic polishing liquid flowing into the gap between the second conductive pillar and the second dielectric layer in the subsequent preparation process.
在一种可能的实现方式中，第二导电柱包括第二导电柱本体，第二导电柱本体与晶体管电连接。这是一种可能的结构。In a possible implementation, the second conductive column includes a second conductive column body, and the second conductive column body is electrically connected to the transistor. This is a possible structure.
在一种可能的实现方式中，第二导电柱还包括第三导电柱本体和第二填充层；第三导电柱本体设置在第二导电柱本体远离晶体管一侧，第二填充层覆盖第三导电柱本体的侧面和底面。这是一种可能的结构。In a possible implementation, the second conductive column further includes a third conductive column body and a second filling layer; the third conductive column body is arranged on a side of the second conductive column body away from the transistor, and the second filling layer covers the side and bottom surfaces of the third conductive column body. This is a possible structure.
在一种可能的实现方式中，第二介质层与第一导电柱接触的侧面掺杂有重原子。第二介质层的侧面掺杂有重原子，可以改变第二介质层的表面特性，提高第二介质层与第一导电柱的粘合度。In a possible implementation, the side of the second dielectric layer in contact with the first conductive pillar is doped with heavy atoms. The side of the second dielectric layer doped with heavy atoms can change the surface properties of the second dielectric layer and improve the adhesion between the second dielectric layer and the first conductive pillar.
在一种可能的实现方式中，第二导电柱本体伸入晶体管，第二导电柱本体伸入晶 体管的部分与第一介质层远离第二介质层的表面接触。这样一来，即使在后续制备过程中有酸性研磨液或者刻蚀液等溶液从第二导电柱与第二介质层之间的缝隙处流入，也会先与第二导电柱端部位于凹槽内的部分接触，可降低酸性研磨液或者刻蚀液等溶液对晶体管的损害。In a possible implementation, the second conductive column body extends into the transistor, and the portion of the second conductive column body extending into the transistor contacts the surface of the first dielectric layer away from the second dielectric layer. In this way, even if a solution such as an acidic polishing liquid or an etching liquid flows into the gap between the second conductive column and the second dielectric layer during the subsequent preparation process, it will first contact the portion of the end of the second conductive column located in the groove, thereby reducing the damage of the solution such as the acidic polishing liquid or the etching liquid to the transistor.
在一种可能的实现方式中，芯片还包括第一导电图案和第二导电图案；第一导电图案和第二导电图案设置在第二介质层远离第一介质层一侧；第一导电柱与第一导电图案电连接，第二导电柱与第二导电图案电连接。电阻层的信号通过第一导电柱转接至第一导电图案，晶体管的信号通过第二导电柱转接至第二导电图案。In a possible implementation, the chip further includes a first conductive pattern and a second conductive pattern; the first conductive pattern and the second conductive pattern are arranged on a side of the second dielectric layer away from the first dielectric layer; the first conductive column is electrically connected to the first conductive pattern, and the second conductive column is electrically connected to the second conductive pattern. The signal of the resistor layer is transferred to the first conductive pattern through the first conductive column, and the signal of the transistor is transferred to the second conductive pattern through the second conductive column.
本申请实施例的第二方面，提供一种电子设备，包括第一方面任一项的芯片和电路板，芯片设置在电路板上。A second aspect of an embodiment of the present application provides an electronic device, comprising the chip and circuit board of any one of the first aspects, wherein the chip is arranged on the circuit board.
本申请实施例的第三方面，提供一种芯片的制备方法，包括：形成第一介质膜；在第一介质膜上依次形成层叠设置的电阻膜和电阻保护膜，电阻膜覆盖第一介质膜，电阻保护膜位于第一介质膜的第一区域内；电阻保护膜包括刻蚀停止膜和刻蚀阻挡膜，刻蚀停止膜位于刻蚀阻挡膜与电阻膜之间；对电阻膜进行第一刻蚀，形成电阻层；刻蚀阻挡膜用于作为形成电阻层的第一刻蚀过程中的刻蚀保护层，电阻层位于第一区域内；形成第二介质膜；第二介质膜形成在第一介质膜上、且覆盖电阻保护膜；通过第二刻蚀，形成贯穿第二介质膜的第四过孔和贯穿刻蚀阻挡膜的第一过孔；刻蚀停止膜用于作为形成第一过孔的第二刻蚀过程中的刻蚀保护层；在刻蚀停止膜上形成第二过孔，形成贯穿第二介质膜和电阻保护膜的第一开口及电阻保护层；在第一开口内形成第一导电柱，并形成第二介质层；第一导电柱与电阻层电连接。According to a third aspect of the embodiments of the present application, a chip manufacturing method is provided, comprising: forming a first dielectric film; sequentially forming a stacked resistor film and a resistor protection film on the first dielectric film, the resistor film covers the first dielectric film, and the resistor protection film is located in a first region of the first dielectric film; the resistor protection film comprises an etch stop film and an etch barrier film, and the etch stop film is located between the etch barrier film and the resistor film; performing a first etching on the resistor film to form a resistor layer; the etch barrier film is used as an etching protection layer in the first etching process of forming the resistor layer, and the resistor layer is located in the first region; forming a second dielectric film; the second dielectric film is formed on the first dielectric film and covers the resistor protection film; forming a fourth via hole penetrating the second dielectric film and a first via hole penetrating the etch barrier film by a second etching; the etch stop film is used as an etching protection layer in the second etching process of forming the first via hole; forming a second via hole on the etch stop film to form a first opening penetrating the second dielectric film and the resistor protection film and the resistor protection layer; forming a first conductive column in the first opening, and forming a second dielectric layer; the first conductive column is electrically connected to the resistor layer.
本申请实施例提供的芯片的制备方法，电阻层上方的电阻保护层包括刻蚀停止层和刻蚀阻挡层，刻蚀阻挡层作为对电阻膜进行刻蚀以形成电阻层时的阻挡层，来保护电阻层的图案形状。刻蚀停止层作为对刻蚀阻挡层进行刻蚀以形成放置第一导电柱的开口时的停止层。这样一来，由于刻蚀停止层的存在，使得第二刻蚀过程中无论采用什么刻蚀工艺在刻蚀阻挡膜上形成第一过孔，都几乎不会对刻蚀停止层下方的电阻层产生影响。既可以提高电阻层的良率，又可以提高芯片制备过程中对工艺的兼容性。而后续需要制备第一导电柱时，再采用单独的刻蚀步骤在刻蚀停止层上形成第二过孔，通过调整刻蚀条件，可以最大程度的降低对电阻层的损伤，提高电阻层的良率。而且，在制备第一导电柱之前，不露出电阻层，可减少电阻层的暴露时间，降低电阻层被氧化的概率，可进一步提高电阻层的良率。In the chip preparation method provided by the embodiment of the present application, the resistance protection layer above the resistance layer includes an etching stop layer and an etching barrier layer, and the etching barrier layer is used as a barrier layer when etching the resistance film to form the resistance layer to protect the pattern shape of the resistance layer. The etching stop layer is used as a stop layer when etching the etching barrier layer to form an opening for placing the first conductive column. In this way, due to the existence of the etching stop layer, no matter what etching process is used to form the first via hole on the etching barrier film during the second etching process, it will hardly affect the resistance layer below the etching stop layer. It can improve the yield of the resistance layer and improve the compatibility of the process in the chip preparation process. When the first conductive column needs to be prepared later, a separate etching step is used to form the second via hole on the etching stop layer. By adjusting the etching conditions, the damage to the resistance layer can be minimized and the yield of the resistance layer can be improved. Moreover, before preparing the first conductive column, the resistance layer is not exposed, which can reduce the exposure time of the resistance layer, reduce the probability of oxidation of the resistance layer, and further improve the yield of the resistance layer.
在一种可能的实现方式中，形成第一介质膜之前，制备方法还包括：形成晶体管；晶体管在第一介质膜上的投影与电阻层在第一介质膜上的投影不交叠；去除电阻保护膜中位于第三开口下方的部分之前，制备方法还包括：形成贯穿第二介质膜和第一介质膜的第二开口，以形成第一介质层；第二开口露出晶体管；在第二开口内形成第二导电柱本体，第二导电柱本体与晶体管电连接。In a possible implementation, before forming the first dielectric film, the preparation method further includes: forming a transistor; the projection of the transistor on the first dielectric film does not overlap with the projection of the resistance layer on the first dielectric film; before removing the portion of the resistance protection film located below the third opening, the preparation method further includes: forming a second opening that penetrates the second dielectric film and the first dielectric film to form a first dielectric layer; the second opening exposes the transistor; and forming a second conductive column body in the second opening, the second conductive column body being electrically connected to the transistor.
本申请实施例提供的制备方法，电阻层所在区域的第一导电柱与晶体管所在区域的第二导电柱的制备工艺可以兼容。例如，同步形成第三开口和第二开口。也就是说，本申请实施例提供的芯片的制备方法，可以实现在保证电阻层产品良率的基础上，兼容第一导电柱和第二导电柱的制备工艺。In the manufacturing method provided in the embodiment of the present application, the manufacturing processes of the first conductive pillar in the region where the resistor layer is located and the second conductive pillar in the region where the transistor is located can be compatible. For example, the third opening and the second opening are formed simultaneously. In other words, the manufacturing method of the chip provided in the embodiment of the present application can achieve compatibility with the manufacturing processes of the first conductive pillar and the second conductive pillar on the basis of ensuring the product yield of the resistor layer.
在一种可能的实现方式中，在第二开口内形成第二导电柱本体之前，制备方法还包括：对第二介质膜进行第一次重原子注入。通过执行重原子掺杂工艺，可以改善第二导电柱与第二开口侧壁粘附性差的问题。In a possible implementation, before forming the second conductive pillar body in the second opening, the preparation method further includes: performing a first heavy atom implantation on the second dielectric film. By performing the heavy atom doping process, the problem of poor adhesion between the second conductive pillar and the sidewall of the second opening can be improved.
在一种可能的实现方式中，在第二开口内形成第二导电柱本体之后，制备方法还包括：对第二介质膜进行第二次重原子注入。通过再一次的重原子注入，使第二介质膜的表面发生膨胀，填充第二导电柱本体与第二开口侧壁之间的缝隙，使第二导电柱本体与第二开口侧壁接触更致密，进一步提高第二导电柱本体与第二开口侧壁的粘附性。In a possible implementation, after forming the second conductive column body in the second opening, the preparation method further includes: performing a second heavy atom implantation on the second dielectric film. The second heavy atom implantation causes the surface of the second dielectric film to expand, fills the gap between the second conductive column body and the side wall of the second opening, makes the second conductive column body contact more closely with the side wall of the second opening, and further improves the adhesion between the second conductive column body and the side wall of the second opening.
在一种可能的实现方式中，第二次重原子注入时的能量小于第一次重原子注入时的能量。In a possible implementation, the energy of the second heavy atom injection is less than the energy of the first heavy atom injection.
在一种可能的实现方式中，第二次重原子注入时的剂量小于第一次重原子注入时的剂量。In a possible implementation, the dosage of the second heavy atom implantation is smaller than the dosage of the first heavy atom implantation.
在一种可能的实现方式中，第二次重原子注入时的角度小于第一次重原子注入时的角度。In a possible implementation, the angle of the second heavy atom implantation is smaller than the angle of the first heavy atom implantation.
通过调整第二次重原子注入时的能量、剂量、角度，可使第二次注入的重原子主要集中在第二介质膜侧面的靠近第二导电柱本体端部的位置处，减少重原子注入过程中飞溅至第二介质膜中的重原子的数量，以改善因第二介质膜中包含重原子而影响芯片性能的问题。By adjusting the energy, dosage and angle of the second heavy atom injection, the heavy atoms injected for the second time can be mainly concentrated on the side of the second dielectric film close to the end of the second conductive column body, thereby reducing the number of heavy atoms splashed into the second dielectric film during the heavy atom injection process, thereby improving the problem of chip performance being affected by the inclusion of heavy atoms in the second dielectric film.
在一种可能的实现方式中，在第一开口内形成第一导电柱，并形成第二介质层，包括：形成覆盖第二介质膜的第一填充膜；在第一填充膜上形成导电膜；对第一填充膜、导电膜以及第二介质膜进行研磨，形成第一填充层、第一导电柱本体以及第二介质层；第一导电柱本***于第一开口内，第一填充层覆盖第一导电柱本体的底面和侧面；第一导电柱包括第一填充层和第一导电柱本体。采用上述制备方法形成第一导电柱，在制备第一导电柱时，可以同步完成对第二导电柱的化学机械研磨，同步完成第二导电柱的制备。因此，可以减少工艺步骤、降低成本、提升效率。In a possible implementation, a first conductive column is formed in a first opening, and a second dielectric layer is formed, including: forming a first filling film covering a second dielectric film; forming a conductive film on the first filling film; grinding the first filling film, the conductive film, and the second dielectric film to form a first filling layer, a first conductive column body, and a second dielectric layer; the first conductive column body is located in the first opening, and the first filling layer covers the bottom surface and side surfaces of the first conductive column body; the first conductive column includes a first filling layer and a first conductive column body. The first conductive column is formed by the above-mentioned preparation method. When preparing the first conductive column, the chemical mechanical grinding of the second conductive column can be completed simultaneously, and the preparation of the second conductive column can be completed simultaneously. Therefore, the process steps can be reduced, the cost can be reduced, and the efficiency can be improved.
在一种可能的实现方式中，形成第一填充层、第一导电柱本体以及第二介质层的同时，还形成第三导电柱本体和第二填充层；第二填充层覆盖第三导电柱本体的底面和侧面，第三导电柱本体设置在第二导电柱本体远离晶体管一侧。这是一种可能的结构。In a possible implementation, while forming the first filling layer, the first conductive column body and the second dielectric layer, the third conductive column body and the second filling layer are also formed; the second filling layer covers the bottom and side surfaces of the third conductive column body, and the third conductive column body is disposed on the side of the second conductive column body away from the transistor. This is a possible structure.
在一种可能的实现方式中，电阻保护膜还包括氧化阻挡膜；氧化阻挡膜设置在刻蚀停止膜与电阻层之间；制备方法还包括在形成贯穿氧化阻挡膜的第三过孔，第三过孔与所述第二过孔连通。通过设置氧化阻挡膜，可以阻止电阻保护膜对电阻层的氧化。In a possible implementation, the resistor protection film further includes an oxidation barrier film; the oxidation barrier film is disposed between the etching stop film and the resistor layer; the preparation method further includes forming a third via hole penetrating the oxidation barrier film, the third via hole being connected to the second via hole. By providing the oxidation barrier film, oxidation of the resistor layer by the resistor protection film can be prevented.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为本申请实施例提供的一种电子设备的框架示意图；FIG1 is a schematic diagram of a framework of an electronic device provided in an embodiment of the present application;
图2A-图2D为本申请实施例示意的一种芯片的制备过程示意图；2A-2D are schematic diagrams of a chip preparation process according to an embodiment of the present application;
图3-图5为本申请实施例示意的又一种芯片的制备过程示意图；3-5 are schematic diagrams of another chip preparation process according to an embodiment of the present application;
图6为本申请实施例提供的一种芯片的制备方法的流程图；FIG6 is a flow chart of a method for preparing a chip provided in an embodiment of the present application;
图7-图16为本申请实施例提供的一种芯片的制备过程示意图；7 to 16 are schematic diagrams of a chip preparation process provided in an embodiment of the present application;
图17为本申请实施例提供的一种芯片的制备步骤示意图；FIG17 is a schematic diagram of steps for preparing a chip provided in an embodiment of the present application;
图18为本申请实施例提供的另一种芯片的制备步骤示意图。FIG. 18 is a schematic diagram of the preparation steps of another chip provided in an embodiment of the present application.
附图标记：Reference numerals:
1-电子设备；2-显示模组；3-中框；4-壳体；5-盖板；200-衬底；10-晶体管；20-转接金属；30′-第一介质膜；30-第一介质层；31-第六过孔；40′-电阻膜；40-电阻层；41-第一部分；42-第二部分；50-电阻保护层；51-氧化阻挡层；52-刻蚀停止层；53-刻蚀阻挡层；50′-电阻保护膜；51′-氧化阻挡膜；52′-刻蚀停止膜；53′-刻蚀阻挡膜；50″-电阻保护基膜；51″-氧化阻挡基膜；52″-刻蚀停止基膜；53″-刻蚀阻挡基膜；531-第一过孔；521-第二过孔；511-第三过孔；60′-第二介质膜；60-第二介质层；61-第五过孔；62-第四过孔；71′-第三开口；71-第一导电柱；711′-第一填充膜；711-第一填充层；712′-导电膜；712-第一导电柱本体；72′-第二开口；72-第二导电柱；721-第二导电柱本体；722-第二填充层；723-第三导电柱；73′-第一开口；81-第一导电图案；82-第二导电图案。1-electronic device; 2-display module; 3-middle frame; 4-housing; 5-cover plate; 200-substrate; 10-transistor; 20-transistor metal; 30′-first dielectric film; 30-first dielectric layer; 31-sixth via; 40′-resistance film; 40-resistance layer; 41-first part; 42-second part; 50-resistance protection layer; 51-oxidation barrier layer; 52-etching stop layer; 53-etching barrier layer; 50′-resistance protection film; 51′-oxidation barrier film; 52′-etching stop film; 53′-etching barrier film; 50″-resistance protection base film; 51″-oxidation barrier base film; 52″-etching stop Base film; 53″-etching stop base film; 531-first via hole; 521-second via hole; 511-third via hole; 60′-second dielectric film; 60-second dielectric layer; 61-fifth via hole; 62-fourth via hole; 71′-third opening; 71-first conductive column; 711′-first filling film; 711-first filling layer; 712′-conductive film; 712-first conductive column body; 72′-second opening; 72-second conductive column; 721-second conductive column body; 722-second filling layer; 723-third conductive column; 73′-first opening; 81-first conductive pattern; 82-second conductive pattern.
具体实施方式Detailed ways
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。In the following, in the embodiments of the present application, the terms "first", "second", etc. are only used for convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "plurality" means two or more.
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。In the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to being defined relative to the positions of the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts. They are used for relative description and clarification, and may change accordingly according to the change of the positions of the components in the drawings.
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。In the embodiments of the present application, unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.
在描述一些实施例时，可能使用了“电连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“电连接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“电连接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。When describing some embodiments, the term "electrically connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "electrically connected" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或” 的关系。In the embodiments of the present application, "and/or" is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character "/" in this article generally indicates that the associated objects before and after are in an "or" relationship.
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。In the embodiments of the present application, exemplary embodiments are described with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams as idealized exemplary drawings. In the drawings, the thickness of the layers and regions is magnified for clarity. Therefore, it is conceivable that the shape changes relative to the drawings are caused by, for example, manufacturing technology and/or tolerances. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as a rectangle will generally have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
本申请实施例提供一种的电子设备。示例性地，该电子设备可以为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品等。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘(digital video disc，DVD)等。金融终端产品如为自动取款机(automated teller machine，ATM)机、自助办理业务的终端等。通信电子产品如为服务器、存储器、基站等通信设备。An electronic device is provided in an embodiment of the present application. Exemplarily, the electronic device may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVD), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. Communication electronic products such as servers, storage devices, base stations and other communication equipment.
本申请实施例对上述电子设备的具体形式不做特殊限制。为了方便说明，以下实施例以电子设备为手机为例进行举例说明。The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device. For the convenience of description, the following embodiments are described by taking the electronic device as a mobile phone as an example.
在此情况下，如图1所示，电子设备1主要包括显示模组2、中框3、壳体(或者称为电池盖、后壳)4以及盖板5。In this case, as shown in FIG. 1 , the electronic device 1 mainly includes a display module 2 , a middle frame 3 , a housing (or battery cover, rear housing) 4 and a cover plate 5 .
显示模组2具有能够看到显示画面的出光侧和与上述出光侧相对设置的背面，显示模组2的背面靠近中框3，盖板5设置在显示模组2的出光侧。The display module 2 has a light emitting side through which a display image can be seen and a back side arranged opposite to the light emitting side. The back side of the display module 2 is close to the middle frame 3 , and the cover plate 5 is arranged on the light emitting side of the display module 2 .
上述显示模组2，包括显示屏(display panel，DP)。The above-mentioned display module 2 includes a display panel (DP).
在本申请的一种可能的实施例中，显示模组2为液晶显示模组。在此情况下，上述显示屏为液晶显示屏(liquid crystal display，LCD)。基于此，显示模组2还包括位于液晶显示屏背面(远离LCD用于显示画面的一侧面)的背光模组(back light unit，BLU)。In a possible embodiment of the present application, the display module 2 is a liquid crystal display module. In this case, the display screen is a liquid crystal display (LCD). Based on this, the display module 2 also includes a backlight unit (BLU) located on the back of the liquid crystal display (away from the side of the LCD for displaying images).
背光模组可以向液晶显示屏提供光源，以使得液晶显示屏中的各个亚像素(sub pixel)能够发光以实现图像显示。The backlight module can provide light source to the LCD screen so that each sub-pixel in the LCD screen can emit light to realize image display.
或者，在本申请的另一种可能的实施例中，显示模组2为有机发光二极管显示模组。在此情况下，上述显示屏为有机发光二极管(organic lightemitting diode，OLED)显示屏。由于OLED显示屏中每个亚像素内设置有电致发光层，所以可以使得OLED显示屏在接收到工作电压后，实现自发光。在此情况下，具有OLED显示屏的显示模组2中无需再设置上述背光模组。Alternatively, in another possible embodiment of the present application, the display module 2 is an organic light emitting diode display module. In this case, the display screen is an organic light emitting diode (OLED) display screen. Since an electroluminescent layer is provided in each sub-pixel in the OLED display screen, the OLED display screen can realize self-luminescence after receiving the operating voltage. In this case, the display module 2 having the OLED display screen does not need to be provided with the backlight module.
盖板5位于显示模组2远离中框3一侧，盖板5例如可以是盖板玻璃(cover glass，CG)，该盖板玻璃可以具有一定的韧性。The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 may be, for example, a cover glass (CG), and the cover glass may have a certain toughness.
中框3位于显示模组2和壳体4之间，中框3远离显示模组2的表面用于安装电池、印刷电路板(printed circuit board，PCB)、摄像头(camera)、天线等内部元件。壳体4与中框3盖合后，上述内部元件位于壳体4与中框3之间。The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc. After the housing 4 and the middle frame 3 are covered, the above internal components are located between the housing 4 and the middle frame 3.
上述电子设备1还包括设置于PCB上的处理器(center processing unit，CPU)芯片、射频芯片、射频功率放大器((power amplifier，PA)芯片、***级芯片(system on a chip，SOC)、电源管理芯片(power management integrated circuits，PMIC)、存储芯片(例如高带宽存储器(high bandwidth memory，HBM))、音频处理器芯片、触摸屏控制芯片、NAND flash(闪存)、图像传感器芯片、充电保护芯片等芯片，PCB用于承载上述芯片，并与上述芯片完成信号交互。The electronic device 1 also includes a processor (center processing unit, CPU) chip, a radio frequency chip, a radio frequency power amplifier ((power amplifier, PA) chip, a system-on-a-chip (system on a chip, SOC), a power management chip (power management integrated circuits, PMIC), a storage chip (such as high bandwidth memory (high bandwidth memory, HBM)), an audio processor chip, a touch screen control chip, a NAND flash (flash memory), an image sensor chip, a charging protection chip and other chips arranged on the PCB. The PCB is used to carry the above chips and complete signal interaction with the above chips.
芯片(可以称之为逻辑集成器件，或者称之为集成电路器件)自身的可靠性等性能，对电子设备的使用寿命和性能有着直接的影响。The reliability and other performance of the chip (which can be called a logic integrated device, or an integrated circuit device) itself has a direct impact on the service life and performance of electronic equipment.
芯片制备过程通常包括前段制程(front end of line，FEOL)、中段制程(midend of line，MEOL)以及后段制程(back end of line，BEOL)。The chip preparation process usually includes the front end of line (FEOL), the mid end of line (MEOL) and the back end of line (BEOL).
如图2A所示，前段制程用于形成晶体管。示例的，晶体管包括源极S，漏极D以及栅极G。As shown in FIG2A , the front-end process is used to form a transistor. For example, the transistor includes a source S, a drain D and a gate G.
如图2B所示，中段制程用于形成将多个晶体管中的导电图案引出至同一平面的转接层。转接层中的导电柱与晶体管的源极S、漏极D、栅极G电连接。转接层的形成，通常先形成具有孔的介质层，介质层中的孔位于导电图案上方，然后再用填孔技术形成导电柱。As shown in Figure 2B, the middle process is used to form a transfer layer that leads the conductive patterns in multiple transistors to the same plane. The conductive pillars in the transfer layer are electrically connected to the source S, drain D, and gate G of the transistor. The formation of the transfer layer usually first forms a dielectric layer with holes, and the holes in the dielectric layer are located above the conductive patterns, and then the conductive pillars are formed using the hole filling technology.
其中，如图2C所示，在一些工艺节点中，中段制程形成的转接层包括两部分，第一部分为：设置在晶体管表面的转接金属和包裹在转接金属***的第一中段介质层，转接金属与晶体管的源极S、漏极D、栅极G电连接。第二部分为：设置在转接金属表面的导电柱和包裹在导电柱***的第二中段介质层，导电柱与转接金属电连接。转接金属例如为条状，导电柱例如为柱状。本申请中将在中段工艺中形成的包裹在转接金属***的介质层称为第一中段介质层，将包裹在导电柱***的介质层称为第二中段介质层。Among them, as shown in Figure 2C, in some process nodes, the transfer layer formed by the middle process includes two parts, the first part is: the transfer metal arranged on the surface of the transistor and the first middle dielectric layer wrapped around the transfer metal, and the transfer metal is electrically connected to the source S, drain D, and gate G of the transistor. The second part is: the conductive column arranged on the surface of the transfer metal and the second middle dielectric layer wrapped around the conductive column, and the conductive column is electrically connected to the transfer metal. The transfer metal is, for example, in the shape of a strip, and the conductive column is, for example, in the shape of a column. In this application, the dielectric layer wrapped around the transfer metal formed in the middle process is referred to as the first middle dielectric layer, and the dielectric layer wrapped around the conductive column is referred to as the second middle dielectric layer.
图2C的这种结构，可以优化后段制程中重布线层的排布。The structure of FIG. 2C can optimize the arrangement of the redistribution layer in the back-end process.
以下为了便于说明，以中段制程形成的结构为图2C所示的结构为例进行示意。For the sake of convenience in explanation, the structure formed in the middle process is taken as shown in FIG. 2C as an example.
如图2D所示，后段制程用于形成位于转接层上的重布线层。晶体管中的信号通过转接层传输至重布线层，从而引出至重布线层表面的信号端。芯片形成后，信号端暴露于芯片的表面。例如，信号端作为芯片的焊盘。As shown in FIG2D , the back-end process is used to form a redistribution layer located on the transfer layer. The signal in the transistor is transmitted to the redistribution layer through the transfer layer, and then led out to the signal terminal on the surface of the redistribution layer. After the chip is formed, the signal terminal is exposed to the surface of the chip. For example, the signal terminal serves as a pad of the chip.
当前的一些芯片中，芯片不仅包括晶体管等有源器件，还会包括电阻等无源器件。在一些技术中，电阻等无源器件会在中段制程中同步形成。In some current chips, the chip includes not only active devices such as transistors, but also passive devices such as resistors. In some technologies, passive devices such as resistors are formed simultaneously in the middle process.
在一些技术中，示意一种用于制备集成有晶体管和电阻的芯片的制备方法，包括：In some techniques, a method for preparing a chip integrating a transistor and a resistor is illustrated, comprising:
S10、如图3所示，在前段制程制备的晶体管上，通过中段制程形成第一中段介质层和转接金属，然后在第一中段介质层上形成第一介质膜，接着在第一介质膜的第一区域上依次形成层叠的电阻层和刻蚀阻挡膜；下来在第一介质膜上形成第二介质膜，第二介质膜覆盖位于第一区域上的刻蚀阻挡膜。S10. As shown in FIG3 , on the transistor prepared by the front-end process, a first middle-stage dielectric layer and a transfer metal are formed by a middle-stage process, and then a first dielectric film is formed on the first middle-stage dielectric layer. Subsequently, a stacked resistance layer and an etching barrier film are sequentially formed on a first region of the first dielectric film. Next, a second dielectric film is formed on the first dielectric film, and the second dielectric film covers the etching barrier film located on the first region.
电阻层与第一中段介质层中制备的转接金属错位设置，或者理解为，电阻层在第一介质膜上的投影与转接金属在第一介质膜上的投影不交叠。也就是说，电阻层的位置对应第一介质膜的第一区域，转接金属的位置对应第一介质膜的第二区域，第一区域和第二区域不交叠。The resistor layer and the transition metal prepared in the first middle dielectric layer are staggered, or it can be understood that the projection of the resistor layer on the first dielectric film and the projection of the transition metal on the first dielectric film do not overlap. In other words, the position of the resistor layer corresponds to the first area of the first dielectric film, the position of the transition metal corresponds to the second area of the first dielectric film, and the first area and the second area do not overlap.
S20、如图4所示，形成贯穿第二介质膜和刻蚀阻挡膜的第一开孔，以及，形成贯穿第一介质膜和第二介质膜的第二开孔，第一介质膜中保留下来的部分作为第一介质层、第二介质膜中保留下来的部分作为第二介质层、刻蚀阻挡膜中保留下来的部分作为刻蚀阻挡层。S20. As shown in FIG. 4 , a first opening is formed through the second dielectric film and the etch stop film, and a second opening is formed through the first dielectric film and the second dielectric film. The portion of the first dielectric film retained is used as the first dielectric layer, the portion of the second dielectric film retained is used as the second dielectric layer, and the portion of the etch stop film retained is used as the etch stop layer.
此处，通过设置第一开孔露出电阻层，并通过设置第二开孔露出转接金属。Here, the resistor layer is exposed by setting the first opening, and the transfer metal is exposed by setting the second opening.
S30、在第一开孔内形成第一导电柱，在第二开孔内形成第二导电柱。S30, forming a first conductive column in the first opening, and forming a second conductive column in the second opening.
由于通常情况下，转接金属上方的第一介质膜的厚度(沿芯片厚度反向的尺寸)，大于，电阻保护膜的厚度。而且，第二介质膜位于转接金属上方的部分的厚度，大于，第二介质膜位于电阻层上方的部分的厚度。也就是说，第二介质膜位于电阻层上方的部分的厚度与电阻保护膜的厚度之和，小于，第二介质膜的厚度与第一介质膜的厚度之和。在同步形成第一开孔和第二开孔时，由于刻蚀时间、刻蚀液浓度、工艺环境等条件都相同，因此，第一开孔会比第二开孔先准备完成。但是，工艺还没有停止，这就导致刻蚀液会继续对电阻层进行损伤，影响电阻层的良率。而且，如图5所示，若第一导电柱下方的电阻层损害程度比较高，而第一导电柱与第一开孔的侧壁处又存在缝隙，也会影响第一导电柱与电阻层中位于电阻保护层下方的部分的电连接效果。Because usually, the thickness of the first dielectric film above the transition metal (the dimension in the opposite direction of the chip thickness) is greater than the thickness of the resistor protection film. Moreover, the thickness of the portion of the second dielectric film located above the transition metal is greater than the thickness of the portion of the second dielectric film located above the resistor layer. In other words, the sum of the thickness of the portion of the second dielectric film located above the resistor layer and the thickness of the resistor protection film is less than the sum of the thickness of the second dielectric film and the thickness of the first dielectric film. When the first opening and the second opening are formed simultaneously, since the etching time, etching solution concentration, process environment and other conditions are the same, the first opening will be prepared before the second opening. However, the process has not stopped, which causes the etching solution to continue to damage the resistor layer, affecting the yield of the resistor layer. Moreover, as shown in Figure 5, if the resistance layer below the first conductive column is more damaged, and there is a gap between the first conductive column and the side wall of the first opening, it will also affect the electrical connection effect between the first conductive column and the portion of the resistor layer located below the resistor protection layer.
基于此，本申请实施例提供一种芯片及其制备方法，用于提高芯片中电阻的良率，同时兼容部件的制备工艺。Based on this, an embodiment of the present application provides a chip and a method for manufacturing the same, which are used to improve the yield of resistors in the chip while being compatible with the preparation process of components.
本申请实施例提供的芯片可以应用于上述电子设备中，本申请实施例提供的芯片可以是未封装的裸芯片，未封装的裸芯片可以包括一个集成电路块(可以称为二维(2D)裸芯片)，未封装的裸芯片也可以包括多个集成电路块(可以称为三维(3D)裸芯片)。本申请实施例提供的芯片也可以是封装后的芯片，封装后的芯片中可以包括一个裸芯片，也可以包括多个裸芯片。The chip provided in the embodiment of the present application can be applied to the above-mentioned electronic device. The chip provided in the embodiment of the present application can be an unpackaged bare chip. The unpackaged bare chip can include one integrated circuit block (which can be called a two-dimensional (2D) bare chip). The unpackaged bare chip can also include multiple integrated circuit blocks (which can be called a three-dimensional (3D) bare chip). The chip provided in the embodiment of the present application can also be a packaged chip. The packaged chip can include one bare chip or multiple bare chips.
以下，以几个示例，对本申请实施例提供的芯片及制备方法进行示意说明。The following uses several examples to schematically illustrate the chip and preparation method provided in the embodiments of the present application.
示例一Example 1
本申请实施例提供一种芯片的制备方法，如图6所示，包括：The present application embodiment provides a method for preparing a chip, as shown in FIG6 , comprising:
S000、如图7所示，提供晶体管10。S000 , as shown in FIG7 , a transistor 10 is provided.
在一些实施例中，步骤S000包括：In some embodiments, step S000 includes:
S010、在衬底200上形成晶体管10。S010 : forming a transistor 10 on a substrate 200 .
其中，在芯片作为射频器件应用于基站等电子设备中时，衬底200的材料为绝缘材料。在芯片作为功率器件应用于手机等电子设备中时，衬底200的材料为导电材料。When the chip is used as a radio frequency device in electronic devices such as base stations, the material of the substrate 200 is an insulating material. When the chip is used as a power device in electronic devices such as mobile phones, the material of the substrate 200 is a conductive material.
示例的，如图7所示，晶体管10包括互补金属氧化物半导体器件(complementary metal oxide semiconductor，CMOS)，CMOS包括源极S、漏极D以及栅极G。其中，图7中还示意出了位于栅极G下方的栅绝缘层和位于栅极G侧面的侧墙。图7中示意 的晶体管10的结构仅为一种示意，不做任何限定。For example, as shown in FIG7 , the transistor 10 includes a complementary metal oxide semiconductor device (CMOS), and the CMOS includes a source S, a drain D, and a gate G. FIG7 also illustrates a gate insulating layer below the gate G and a sidewall on the side of the gate G. The structure of the transistor 10 illustrated in FIG7 is only an illustration and is not limited in any way.
或者，示例的，晶体管10为高电子迁移率晶体管(high electron mobility transistor，HEMT)、异质结双极晶体管(heterojunction bipolar transistor，HBT)、双极结型晶体管(bipolar junction transistor，BJT)等。Alternatively, for example, transistor 10 is a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), etc.
芯片可以包括至少一个晶体管10，本申请实施例提供的芯片的制备方法仅是以芯片中的一个晶体管10为例，对芯片中各部分的结构进行示意说明。芯片包括多个晶体管10的情况下，多个晶体管10可以是同一种类型的晶体管，也可以是不同种类型的晶体管。本申请实施例对芯片中的晶体管10的数量、种类、排布方式不做限定，根据需要合理设置即可。The chip may include at least one transistor 10. The chip preparation method provided in the embodiment of the present application only takes one transistor 10 in the chip as an example to schematically illustrate the structure of each part in the chip. When the chip includes multiple transistors 10, the multiple transistors 10 may be transistors of the same type or transistors of different types. The embodiment of the present application does not limit the number, type, and arrangement of the transistors 10 in the chip, and can be reasonably set as needed.
S020、在晶体管10的表面形成层间介质层(inter level dielectric，ILD)，该层间介质层中设置有贯穿层间介质层且连接晶体管10的源极S、漏极D或者栅极G的转接金属20。S020. An inter-level dielectric (ILD) layer is formed on the surface of the transistor 10. A transition metal 20 is provided in the inter-level dielectric layer, which penetrates the inter-level dielectric layer and connects the source S, drain D or gate G of the transistor 10.
本申请实施例不对转接金属俯视图的形状进行限定，例如可以为条状、柱状等任意形状。芯片包括至少一个转接金属20。The embodiment of the present application does not limit the shape of the top view of the transfer metal, for example, it can be any shape such as a strip, a column, etc. The chip includes at least one transfer metal 20 .
转接金属20的材料，例如可以为钼(Mo)。层间介质层ILD的材料，例如可以是氮化硅。The material of the transfer metal 20 may be, for example, molybdenum (Mo). The material of the interlayer dielectric layer ILD may be, for example, silicon nitride.
S100、如图8A所示，在转接金属20上形成第一介质膜30′。S100 , as shown in FIG. 8A , a first dielectric film 30 ′ is formed on the transfer metal 20 .
示例的，第一介质膜30′覆盖层间介质层ILD和转接金属20。当然，本申请实施例并不限定为在图7所示转接金属20上形成第一介质膜30′，第一介质膜30′也可以在晶体管10上形成第一介质膜30′，图7中仅为一种示意。For example, the first dielectric film 30' covers the interlayer dielectric layer ILD and the transfer metal 20. Of course, the embodiment of the present application is not limited to forming the first dielectric film 30' on the transfer metal 20 shown in FIG7. The first dielectric film 30' can also be formed on the transistor 10. FIG7 is only a schematic diagram.
S200、如图8B所示，在第一介质膜30′上形成电阻膜40′和电阻保护膜50′。S200 , as shown in FIG. 8B , a resistor film 40 ′ and a resistor protection film 50 ′ are formed on the first dielectric film 30 ′.
电阻膜40′位于第一介质膜30′远离层间介质层ILD一侧，电阻保护膜50′位于电阻层40远离第一介质膜30′的表面上。电阻膜40′覆盖第一介质膜30′，电阻保护膜50′位于第一介质膜30′的第一区域内。The resistor film 40' is located on the side of the first dielectric film 30' away from the interlayer dielectric layer ILD, and the resistor protection film 50' is located on the surface of the resistor layer 40 away from the first dielectric film 30'. The resistor film 40' covers the first dielectric film 30', and the resistor protection film 50' is located in the first region of the first dielectric film 30'.
电阻保护膜50′包括多层介质覆盖膜，多层介质覆盖膜中至少包括两层材料不同的介质覆盖膜。The resistance protection film 50' comprises a multi-layer dielectric covering film, wherein the multi-layer dielectric covering film comprises at least two layers of dielectric covering films made of different materials.
在一些实施例中，如图8B所示，步骤S200包括：In some embodiments, as shown in FIG8B , step S200 includes:
S210、在第一介质膜30′上依次形成电阻膜40′以及电阻保护基膜50″。S210 , forming a resistor film 40 ′ and a resistor protection base film 50 ″ in sequence on the first dielectric film 30 ′.
示例的，如图8B所示，电阻保护基膜50″包括氧化阻挡基膜51″、刻蚀停止基膜52″以及刻蚀阻挡基膜53″。Illustratively, as shown in FIG. 8B , the resistance protection base film 50 ″ includes an oxidation blocking base film 51 ″, an etch stop base film 52 ″, and an etch blocking base film 53 ″.
本申请实施例中，刻蚀停止基膜52″的材料与刻蚀阻挡基膜53″的材料中包括不同介质材料。氧化阻挡基膜51″的材料为不含氧的介质材料。In the embodiment of the present application, the material of the etch stop base film 52 ″ and the material of the etch barrier base film 53 ″ include different dielectric materials. The material of the oxidation barrier base film 51 ″ is a dielectric material that does not contain oxygen.
当然，氧化阻挡基膜51″用于保护电阻膜40′被氧化，那么，电阻保护基膜50″中也可以不包括氧化阻挡基膜51″。图8B中仅为一种示意，不做任何限定。Of course, the oxidation blocking base film 51 ″ is used to protect the resistor film 40 ′ from being oxidized, so the resistor protection base film 50 ″ may not include the oxidation blocking base film 51 ″. FIG. 8B is only a schematic diagram and does not make any limitation.
S220、对电阻保护基膜50″进行图案化，形成电阻保护膜50′。S220 , patterning the resistor protection base film 50 ″ to form a resistor protection film 50 ′.
例如，可以采用光刻工艺结合干法刻蚀工艺，去除转接金属20所在区域(非高阻器件区域)的氧化阻挡基膜51″、刻蚀停止基膜52″以及刻蚀阻挡基膜53″，保留待形成的电阻层40所在区域(高阻器件区域)的氧化阻挡基膜51″、刻蚀停止基膜52″以及刻蚀阻挡基膜53″。氧化阻挡基膜51″、刻蚀停止基膜52″以及刻蚀阻挡基膜 53″中被保留下来的部分(位于高阻器件区域的部分)，作为电阻保护膜50′中的氧化阻挡膜51′、刻蚀停止膜52′以及刻蚀阻挡膜53′。For example, a photolithography process combined with a dry etching process can be used to remove the oxidation barrier base film 51″, the etch stop base film 52″ and the etch barrier base film 53″ in the area where the transfer metal 20 is located (non-high resistance device area), and retain the oxidation barrier base film 51″, the etch stop base film 52″ and the etch barrier base film 53″ in the area where the resistance layer 40 to be formed is located (high resistance device area). The retained portions of the oxidation barrier base film 51″, the etch stop base film 52″ and the etch barrier base film 53″ (the portions located in the high resistance device area) serve as the oxidation barrier film 51′, the etch stop film 52′ and the etch barrier film 53′ in the resistance protection film 50′.
关于高阻器件区域和非高阻器件区域的划分，例如可以是待形成的电阻层40所在区域为高阻器件区域，也就是电阻保护膜50′所在的第一区域为高阻器件区域，其余区域为非高阻器件区域。Regarding the division of high resistance device area and non-high resistance device area, for example, the area where the resistance layer 40 to be formed is located is the high resistance device area, that is, the first area where the resistance protection film 50' is located is the high resistance device area, and the remaining areas are non-high resistance device areas.
S250、如图8C所示，对电阻膜40′进行第一刻蚀，形成电阻层40。S250 , as shown in FIG. 8C , performing a first etching process on the resistor film 40 ′ to form a resistor layer 40 .
转接金属20在第一介质膜30′(或者衬底200)上的投影与电阻层40在第一介质膜30′上的投影不交叠。或者理解为，沿芯片的厚度方向，转接金属20与电阻层40错位排布。The projection of the transfer metal 20 on the first dielectric film 30' (or substrate 200) does not overlap with the projection of the resistor layer 40 on the first dielectric film 30'. Alternatively, it can be understood that the transfer metal 20 and the resistor layer 40 are staggered along the thickness direction of the chip.
示例的，电阻层40所在的第一区域称为高阻区域，转接金属20所在第二区域称为低阻区域。例如，本申请实施例中，第一介质膜30′中除第一区域以外的区域均划分至第二区域。For example, the first region where the resistor layer 40 is located is called a high resistance region, and the second region where the transfer metal 20 is located is called a low resistance region. For example, in the embodiment of the present application, all regions except the first region in the first dielectric film 30' are divided into the second region.
例如，可以采用湿法刻蚀工艺，对电阻膜40′进行图案化。刻蚀阻挡膜53′用于作为形成电阻层40的第一刻蚀过程中的刻蚀保护层，刻蚀阻挡膜53′用于保护电阻膜40′中位于其下方的部分在第一次刻蚀中不被刻蚀。形成的电阻层40位于第一介质膜30′的第一区域内。For example, a wet etching process may be used to pattern the resistor film 40'. The etching barrier film 53' is used as an etching protection layer in the first etching process of forming the resistor layer 40. The etching barrier film 53' is used to protect the portion of the resistor film 40' located below it from being etched in the first etching. The formed resistor layer 40 is located in the first region of the first dielectric film 30'.
电阻保护膜50′设置在电阻层40的表面上，例如，可以是电阻保护膜50′在第一介质膜30′上的投影，与电阻层40在第一介质膜30′上的投影重合。The resistor protection film 50 ′ is disposed on the surface of the resistor layer 40 , for example, it may be a projection of the resistor protection film 50 ′ on the first dielectric film 30 ′, which overlaps with a projection of the resistor layer 40 on the first dielectric film 30 ′.
电阻保护膜中50′中的刻蚀阻挡膜53′，用于作为高阻器件区域的刻蚀阻挡层，在去除非高阻器件区域的电阻膜40′时，作为干法刻蚀工艺的刻蚀阻挡层，避免高阻器件区域被打开，导致高阻器件区域的电阻膜40′被去除。The etching barrier film 53′ in the resistor protection film 50′ is used as an etching barrier layer in the high resistance device area. When removing the resistor film 40′ in the non-high resistance device area, it serves as an etching barrier layer in the dry etching process to prevent the high resistance device area from being opened, resulting in the removal of the resistor film 40′ in the high resistance device area.
示例的，刻蚀阻挡膜53′的材料包括氮化硅(SiN)、硅碳氮(SiCN)、硅碳氧氮(SiCON)、碳化硅(SiC)等。那么，后续形成的刻蚀阻挡层53的材料包括SiN、SiCN、SiCON、SiC等。For example, the material of the etch stop film 53 ′ includes silicon nitride (SiN), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), silicon carbide (SiC), etc. Then, the material of the subsequently formed etch stop layer 53 includes SiN, SiCN, SiCON, SiC, etc.
电阻保护膜中50′中的刻蚀停止膜52′，作为刻蚀非高阻器件区域的第一介质膜30′，形成非高阻器件连接孔的刻蚀停止层，用于保护电阻层40。The etching stop film 52 ′ in the resistor protection film 50 ′ is used as the first dielectric film 30 ′ for etching the non-high resistance device region to form an etching stop layer for the non-high resistance device connection hole, and is used to protect the resistor layer 40 .
示例的，刻蚀停止膜52′的材料包括氧化硅(SiO)、SiCN、SiCON、SiC等。那么，后续形成的刻蚀停止层52的材料包括SiO、SiCN、SiCON、SiC等。刻蚀停止膜52′的材料与刻蚀阻挡膜53′和氧化阻挡膜51′的材料不同。For example, the material of the etch stop film 52' includes silicon oxide (SiO), SiCN, SiCON, SiC, etc. Then, the material of the subsequently formed etch stop layer 52 includes SiO, SiCN, SiCON, SiC, etc. The material of the etch stop film 52' is different from the material of the etch barrier film 53' and the oxidation barrier film 51'.
电阻保护膜中50′中的氧化阻挡膜51′，用于防止刻蚀停止膜52′氧化下层的电阻层40。The oxidation barrier film 51 ′ in the resistor protection film 50 ′ is used to prevent the etching stop film 52 ′ from oxidizing the resistor layer 40 below.
示例的，氧化阻挡膜51′的材料包括SiN、SiCN、SiCON、SiC等。那么，后续形成的氧化阻挡层51的材料包括SiN、SiCN、SiCON、SiC等。For example, the material of the oxidation barrier film 51 ′ includes SiN, SiCN, SiCON, SiC, etc. Then, the material of the subsequently formed oxidation barrier layer 51 includes SiN, SiCN, SiCON, SiC, etc.
在一些实施例中，第一介质膜30′、氧化阻挡膜51′、刻蚀阻挡膜53′的材料相同。这样一来，可简化工艺难度，避免频繁更换材料。In some embodiments, the first dielectric film 30 ′, the oxidation barrier film 51 ′, and the etching barrier film 53 ′ are made of the same material, which simplifies the process and avoids frequent material replacement.
电阻层40的材料为导电材料，电阻层40包括金属和非金属的氧化物或者金属氮化物。例如，电阻层40的材料包括氧化钛、氮化钛、氮化钽等。The material of the resistor layer 40 is a conductive material, and the resistor layer 40 includes metal and non-metal oxides or metal nitrides. For example, the material of the resistor layer 40 includes titanium oxide, titanium nitride, tantalum nitride, and the like.
S300、如图9所示，形成第二介质膜60′。S300 , as shown in FIG. 9 , forming a second dielectric film 60 ′.
第二介质膜60′覆盖电阻保护膜50′和第一介质膜30′。第二介质膜60′的材料与第 一介质膜30′的材料不同，那么，最终形成的第一介质层和第二介质层的材料也不相同。The second dielectric film 60' covers the resistor protection film 50' and the first dielectric film 30'. The material of the second dielectric film 60' is different from that of the first dielectric film 30', so the materials of the first dielectric layer and the second dielectric layer formed finally are also different.
例如，第一介质膜30′的材料包括硅的氮化物，第二介质膜60′的材料包括硅的氧化物(例如氧化硅)、硅的掺杂氧化物、硅的氟化氧化物、硅的掺碳氧化物等。For example, the material of the first dielectric film 30' includes silicon nitride, and the material of the second dielectric film 60' includes silicon oxide (eg, silicon oxide), silicon doped oxide, silicon fluoride oxide, silicon carbon doped oxide, and the like.
示例的，可以采用化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积或其它沉积方法形成第二介质膜60′。For example, the second dielectric film 60′ can be formed by chemical vapor deposition (CVD), physical vapor deposition or other deposition methods.
S400、如图10所示，通过第二刻蚀，形成贯穿第二介质膜60′的第四过孔62和贯穿刻蚀阻挡膜53′的第一过孔531。同时，形成贯穿第二介质膜60′和第一介质膜30′的第二开口72′，第二开口72′露出转接金属20。S400, as shown in FIG10, a fourth via hole 62 penetrating the second dielectric film 60' and a first via hole 531 penetrating the etching stop film 53' are formed by a second etching. At the same time, a second opening 72' penetrating the second dielectric film 60' and the first dielectric film 30' is formed, and the second opening 72' exposes the transfer metal 20.
例如，第四过孔62和第一过孔531连通，构成第三开口71′，可以采用光刻和刻蚀的方法，形成第三开口71′和第二开口72′。刻蚀停止膜52′用于作为形成第一过孔531的第二刻蚀过程中的刻蚀保护层，用于保护刻蚀停止膜52′下方的电阻层40在第二次刻蚀过程中不被刻蚀。For example, the fourth via hole 62 is connected to the first via hole 531 to form a third opening 71', and the third opening 71' and the second opening 72' can be formed by photolithography and etching. The etching stop film 52' is used as an etching protection layer in the second etching process of forming the first via hole 531, and is used to protect the resistance layer 40 below the etching stop film 52' from being etched in the second etching process.
示例的，如图10所示，在步骤S400中，同步形成第三开口71′和第二开口72′，第三开口71′贯穿第二介质膜60′及刻蚀阻挡膜53′，第二开口72′贯穿第二介质膜60′及第一介质膜30′。形成第三开口71′和第二开口72′时，第一介质层30和刻蚀阻挡层53同步形成。For example, as shown in FIG10 , in step S400, the third opening 71′ and the second opening 72′ are formed simultaneously, the third opening 71′ penetrates the second dielectric film 60′ and the etching stop film 53′, and the second opening 72′ penetrates the second dielectric film 60′ and the first dielectric film 30′. When the third opening 71′ and the second opening 72′ are formed, the first dielectric layer 30 and the etching stop layer 53 are formed simultaneously.
那么，第二刻蚀时在第二介质膜60′上形成第四过孔62，在刻蚀阻挡膜53′上形成第一过孔531，第一过孔531和第四过孔62连通构成第三开口71′。Then, during the second etching, a fourth via hole 62 is formed on the second dielectric film 60 ′, and a first via hole 531 is formed on the etching stop film 53 ′. The first via hole 531 and the fourth via hole 62 are connected to form a third opening 71 ′.
本申请实施例不对第三开口71′和第二开口72′的形状和大小进行限定。第二开口72′可以露出转接金属20远离衬底200的顶面的部分或者全部区域。或者说，第二开口72′在衬底200上的投影可以位于转接金属20在衬底200上的投影内，第二开口72′在衬底200上的投影也可以与转接金属20在衬底200上的投影重合。当然，第二开口72′在衬底200上的投影也可以覆盖转接金属20在衬底200上的投影，只要确保后续形成在第二开口72′内的第二导电柱不会导致相邻转接金属20短路即可。或者理解为，第二开口72′位于转接金属20的正上方，第二开口72′的面积可以小于转接金属20的面积，第二开口72′的面积也可以等于转接金属20的面积，第二开口72′的面积也可以大于转接金属20的面积。本申请实施例以第二开口72′的面积小于转接金属20的面积为例进行示意。The embodiment of the present application does not limit the shape and size of the third opening 71′ and the second opening 72′. The second opening 72′ may expose part or all of the top surface of the transfer metal 20 away from the substrate 200. In other words, the projection of the second opening 72′ on the substrate 200 may be located within the projection of the transfer metal 20 on the substrate 200, and the projection of the second opening 72′ on the substrate 200 may also overlap with the projection of the transfer metal 20 on the substrate 200. Of course, the projection of the second opening 72′ on the substrate 200 may also cover the projection of the transfer metal 20 on the substrate 200, as long as it is ensured that the second conductive column subsequently formed in the second opening 72′ does not cause a short circuit between adjacent transfer metals 20. Alternatively, it is understood that the second opening 72′ is located directly above the transfer metal 20, the area of the second opening 72′ may be smaller than the area of the transfer metal 20, the area of the second opening 72′ may also be equal to the area of the transfer metal 20, and the area of the second opening 72′ may also be larger than the area of the transfer metal 20. The embodiment of the present application is illustrated by taking the example that the area of the second opening 72 ′ is smaller than the area of the transfer metal 20 .
本申请实施例不对第三开口71′和第二开口72′的数量进行限定，第三开口71′的数量与电阻层40的数量对应，第二开口72′的数量与转接金属20的数量对应即可。需要强调的是，一个转接金属20可以与一个第二开口72′对应设置，也就是说，一个转接金属20上方可以仅设置一个第二开口72′。一个转接金属20也可以与多个第二开口72′对应设置，也就是说，一个转接金属20上方可以设置多个第二开口72′。也可以是多个转接金属20与同一个第二开口72′对应设置，也就是说，多个转接金属20(例如该多个转接金属20例如传输同一信号)上方对应设置同一个第二开口72′。The embodiment of the present application does not limit the number of the third openings 71′ and the second openings 72′. The number of the third openings 71′ corresponds to the number of the resistance layers 40, and the number of the second openings 72′ corresponds to the number of the transition metals 20. It should be emphasized that one transition metal 20 can be arranged corresponding to one second opening 72′, that is, only one second opening 72′ can be arranged above one transition metal 20. One transition metal 20 can also be arranged corresponding to multiple second openings 72′, that is, multiple second openings 72′ can be arranged above one transition metal 20. It is also possible that multiple transition metals 20 are arranged corresponding to the same second opening 72′, that is, the same second opening 72′ is arranged above multiple transition metals 20 (for example, the multiple transition metals 20 transmit the same signal).
为了便于说明，如图10所示，本申请实施例中以步骤S400中形成一个第三开口71′和多个第二开口72′，每个第三开口71′与一个电极层40对应设置，每个第二开口72′露出一个转接金属20为例进行示意。For ease of explanation, as shown in FIG. 10 , in the embodiment of the present application, a third opening 71 ′ and a plurality of second openings 72 ′ are formed in step S400 , each third opening 71 ′ is arranged corresponding to an electrode layer 40 , and each second opening 72 ′ exposes a transfer metal 20 .
此处需要强调的是，在形成第三开口71′和第二开口72′后，可以先去除刻蚀副产 物，然后再执行后续步骤S500。去除刻蚀副产物的方式，例如可以是先干法清洗，去除大部分刻蚀副产物；然后再湿法清洗，深度去除刻蚀副产物。It should be emphasized here that after forming the third opening 71' and the second opening 72', the etching byproducts can be removed first, and then the subsequent step S500 is performed. The method of removing the etching byproducts can be, for example, dry cleaning first to remove most of the etching byproducts; and then wet cleaning to deeply remove the etching byproducts.
S500、如图11所示，对第二介质膜60′进行第一次重原子注入。S500 , as shown in FIG. 11 , performing a first heavy atom implantation into the second dielectric film 60 ′.
重原子可以是指原子序数大于硅的原子，重原子例如可以是Ge(锗)、Ar(氩)、Si(硅)、Xe(氙)等重金属。Heavy atoms may refer to atoms having an atomic number greater than that of silicon, and heavy atoms may be, for example, heavy metals such as Ge (germanium), Ar (argon), Si (silicon), and Xe (xenon).
也就是说，对步骤S400得到的结构进行重原子注入，重原子注入可以改变第二介质膜60′表面的膜层性质。此处的表面包括第二介质膜60′远离第一介质膜30′的顶面、第二介质膜60′围成第三开口71′和第二开口72′的侧面。改变第二介质膜60′围成第二开口72′的侧面的膜层性质后，可以使后续在第二开口72′中选择性生长第二导电柱时，第二导电柱与第二开口72′的侧面之间接触更致密、粘附性更好。That is, the structure obtained in step S400 is implanted with heavy atoms, and the heavy atom implantation can change the film layer properties on the surface of the second dielectric film 60'. The surface here includes the top surface of the second dielectric film 60' away from the first dielectric film 30', and the side surfaces of the second dielectric film 60' that surround the third opening 71' and the second opening 72'. After changing the film layer properties of the side surfaces of the second dielectric film 60' that surround the second opening 72', when the second conductive pillar is selectively grown in the second opening 72', the contact between the second conductive pillar and the side surfaces of the second opening 72' is denser and the adhesion is better.
第二导电柱与第二开口72′的侧面的粘附性提高，可以改善因第二导电柱与第二开口72′的侧面之间存在随机的、无规则的缝隙缺陷，导致在后续填孔后的化学机械研磨(chemical mechanical polishing，CMP)，或者后续通过刻蚀工艺对膜层图案化等工艺中，从第二导电柱与第二开口72′的侧面之间的缝隙处渗入酸性研磨液或者刻蚀液等溶液，从而导致第二导电柱底部的转接金属20损伤，最终导致芯片失效的问题。另一方面，可以改善由于第二导电柱与第二开口72′的侧面之间的粘附效果差，导致在后续化学机械研磨过程中容易出现将第二导电柱带走，导致第二导电柱缺失，从而导致芯片失效，引起芯片可靠性(reliability)的问题。The improved adhesion between the second conductive pillar and the side of the second opening 72' can improve the problem that the random and irregular gap defects between the second conductive pillar and the side of the second opening 72' lead to the infiltration of acidic polishing liquid or etching liquid or other solutions from the gap between the second conductive pillar and the side of the second opening 72' during the subsequent chemical mechanical polishing (CMP) after hole filling or the subsequent film patterning by etching process, thereby damaging the transfer metal 20 at the bottom of the second conductive pillar and eventually causing chip failure. On the other hand, the problem that the second conductive pillar is easily carried away during the subsequent chemical mechanical polishing process due to the poor adhesion between the second conductive pillar and the side of the second opening 72' can be improved, resulting in the loss of the second conductive pillar, thereby causing chip failure and causing chip reliability.
在形成第二导电柱之前执行第一次重原子注入工艺，与形成第二导电柱之后形成重原子出入工艺相比，可以避免重原子注入过程中导电柱本体中的金属原子(例如W)溅射，导致金属原子溅射到第二介质膜60′中。由于金属原子溅射到第二介质膜60′中后不易被去除，容易导致芯片失效。因此，本申请实施例提供的制备方法可以提升产品良率。而且，形成第二导电柱之后在进行重原子注入，容易出现第二导电柱与第二介质膜60′之间的缝隙中，靠近第二导电柱顶部的缝隙已经被填充，但是靠近第二导电柱底部的缝隙还没有消除导致靠近转接金属20处的缝隙的填充效果不理想。Performing the first heavy atom injection process before forming the second conductive column can avoid the sputtering of metal atoms (such as W) in the conductive column body during the heavy atom injection process, compared with the heavy atom injection and exit process after forming the second conductive column, causing the metal atoms to sputter into the second dielectric film 60'. Since the metal atoms are not easily removed after being sputtered into the second dielectric film 60', it is easy to cause chip failure. Therefore, the preparation method provided in the embodiment of the present application can improve the product yield. Moreover, after the second conductive column is formed, when the heavy atom injection is performed, it is easy for the gap between the second conductive column and the second dielectric film 60' to be filled near the top of the second conductive column, but the gap near the bottom of the second conductive column has not been eliminated, resulting in an unsatisfactory filling effect of the gap near the transfer metal 20.
S600、如图12所示，对转接金属20进行刻蚀。S600 , as shown in FIG. 12 , etching the transfer metal 20 .
示例的，对转接金属20进行刻蚀时，刻蚀的程度，可以是去除转接金属20中掺杂有重原子的部分即可。For example, when etching the transfer metal 20 , the etching extent may be to remove the portion of the transfer metal 20 doped with heavy atoms.
或者，示例的，如图12所示，对转接金属20进行刻蚀时，刻蚀的程度，可以是对转接金属20进行回刻，去除转接金属20中掺杂有重原子的部分，并在转接金属20的表面形成凹槽，凹槽与第二开口72′联通。例如，凹槽的开口面积大于第二开口72′的开口面积。Alternatively, for example, as shown in FIG12 , when etching the transfer metal 20, the extent of etching may be to etch back the transfer metal 20, remove the portion doped with heavy atoms in the transfer metal 20, and form a groove on the surface of the transfer metal 20, the groove being connected to the second opening 72′. For example, the opening area of the groove is greater than the opening area of the second opening 72′.
不对凹槽的形状进行限定，图12中以凹槽为弧面凹槽为例进行示意，凹槽也可以是矩形凹槽、V型凹槽、或者梯形凹槽等。The shape of the groove is not limited. FIG. 12 shows an arc-shaped groove as an example. The groove may also be a rectangular groove, a V-shaped groove, or a trapezoidal groove.
通过在转接金属20的表面回刻形成凹槽，且凹槽的开口大于第二开口72′的开口。可使后续形成的第二导电柱靠近转接金属20一侧的端部的横截面积大于其他位置处的横截面积，从而产生铆钉效应。这样一来，即使在后续制备过程中有酸性研磨液或者刻蚀液等溶液从第二导电柱与第二介质膜60′之间的缝隙处流入，也会先与第二导电柱端部位于凹槽内的部分接触，可降低酸性研磨液或者刻蚀液等溶液对转接金 属20的损害。By back-etching a groove on the surface of the transfer metal 20, and the opening of the groove is larger than the opening of the second opening 72', the cross-sectional area of the end of the second conductive column formed subsequently close to the transfer metal 20 can be larger than the cross-sectional area at other positions, thereby generating a rivet effect. In this way, even if a solution such as an acidic grinding liquid or an etching liquid flows into the gap between the second conductive column and the second dielectric film 60' during the subsequent preparation process, it will first contact the portion of the end of the second conductive column located in the groove, thereby reducing the damage of the solution such as the acidic grinding liquid or the etching liquid to the transfer metal 20.
当然，也可以不执行步骤S600，执行完步骤S500后，执行后续步骤S700。Of course, step S600 may not be executed, and after step S500 is executed, the subsequent step S700 is executed.
S700、如图13所示，在第二开口72′内形成第二导电柱本体721。S700 , as shown in FIG. 13 , forming a second conductive pillar body 721 in the second opening 72 ′.
在一些技术中，采用电镀工艺形成铜(Cu)柱作为第二导电柱本体721。In some technologies, a copper (Cu) column is formed as the second conductive column body 721 using an electroplating process.
在另一些技术中，采用化学气相沉积(chemical vapor deposition，CVD)形成钨(W)柱作为第二导电柱本体721。In other techniques, chemical vapor deposition (CVD) is used to form a tungsten (W) column as the second conductive column body 721.
在又一些技术中，采用较薄的氮化钛(TiN)作为阻挡层，填孔钴(Co)柱作为第二导电柱本体721。这样一来，可以增大第二导电柱本体721的工艺窗口，降低导电柱的电阻。In some other technologies, a thinner titanium nitride (TiN) is used as a barrier layer, and a hole-filling cobalt (Co) column is used as the second conductive column body 721. In this way, the process window of the second conductive column body 721 can be increased and the resistance of the conductive column can be reduced.
在又一些技术中，采用选择性生长(selective deposition)工艺，在第二开口72′内形成第二导电柱本体721。In some other techniques, a selective deposition process is used to form a second conductive column body 721 in the second opening 72′.
其中，选择性生长工艺形成的第二导电柱本体721与第二开口72′的侧壁接触。The second conductive pillar body 721 formed by the selective growth process is in contact with the sidewall of the second opening 72 ′.
选择性生长工艺是指在衬底上限定的区域内进行的外延生长，应用在本申请中，就是在转接金属20的表面开始外延生长，不从第二介质膜60′和刻蚀停止膜52′的表面开始外延生长。The selective growth process refers to epitaxial growth in a limited area on the substrate. In the present application, the epitaxial growth starts from the surface of the transition metal 20, and does not start from the surface of the second dielectric film 60' and the etch stop film 52'.
那么，本申请采用选择性生长工艺最终形成的第二导电柱本体721，第二导电柱本体721的底面直接与转接金属20接触，第二导电柱本体721的侧面直接与第二开口72′的侧壁接触，第二导电柱本体721为实心结构，第二导电柱本体721的内部没有孔隙。Then, the second conductive column body 721 is finally formed by the selective growth process in the present application, the bottom surface of the second conductive column body 721 is directly in contact with the transfer metal 20, the side surface of the second conductive column body 721 is directly in contact with the side wall of the second opening 72′, the second conductive column body 721 is a solid structure, and there are no pores inside the second conductive column body 721.
通过选择性外延生长工艺直接在转接金属20这个金属结构的表面外延生长第二导电柱本体721的，因此，采用选择性生长工艺形成第二导电柱本体721，无需阻挡层、成核层等膜层，可降低第二导电柱本体721与转接金属20之间的接触电阻，可适用于高深宽比的芯片结构中。而且，由于金属钨是自下而上生长，因此，形成的第二导电柱本体721内部不会成孔隙，可降低第二导电柱本体721的电阻。The second conductive column body 721 is epitaxially grown directly on the surface of the metal structure of the transfer metal 20 by a selective epitaxial growth process. Therefore, the second conductive column body 721 is formed by a selective growth process without the need for film layers such as a barrier layer and a nucleation layer, which can reduce the contact resistance between the second conductive column body 721 and the transfer metal 20 and can be applied to chip structures with a high aspect ratio. Moreover, since the metal tungsten grows from bottom to top, the second conductive column body 721 formed will not have pores inside, which can reduce the resistance of the second conductive column body 721.
其中，第二导电柱本体721的高度，可以根据第二开口72′的深度以及后续化学机械研磨工艺的研磨厚度调节。在同时形成多个第二导电柱本体721的情况下，多个第二导电柱本体721的高度可以相同，也可以不同。The height of the second conductive pillar body 721 can be adjusted according to the depth of the second opening 72' and the polishing thickness of the subsequent chemical mechanical polishing process. When multiple second conductive pillar bodies 721 are formed simultaneously, the heights of the multiple second conductive pillar bodies 721 can be the same or different.
在一些实施例中，如图13所示，第二导电柱本体721的表面低于第二介质膜60′的表面。也就是说，第二导电柱本体721的深度，小于第二开口72′的深度。In some embodiments, as shown in Fig. 13, the surface of the second conductive pillar body 721 is lower than the surface of the second dielectric film 60'. In other words, the depth of the second conductive pillar body 721 is less than the depth of the second opening 72'.
这样一来，在后续化学机械研磨过程中，可减小被研磨掉的第二导电柱本体721的高度，减小材料浪费，降低成本。In this way, in the subsequent chemical mechanical polishing process, the height of the second conductive column body 721 that is polished away can be reduced, thereby reducing material waste and reducing costs.
不对第二导电柱本体721的材料进行限定，第二导电柱本体721的材料可以包括铜(Cu)、铝(Al)、钛(Ti)、锆(Zr)、铪(Hf)、钒(V)、钌(Ru)、钴(Co)、镍(Ni)、钯(Pd)、铂(Pt)、钨(W)、银(Ag)、金(Au)、鎶(CN)等材料。The material of the second conductive column body 721 is not limited. The material of the second conductive column body 721 may include copper (Cu), aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), ruthenium (Ru), cobalt (Co), nickel (Ni), palladium (Pd), platinum (Pt), tungsten (W), silver (Ag), gold (Au), cobalt (CN) and other materials.
在一些实施例中，执行步骤S700之前，先对第二开口72′进行表面处理，去除第二开口72′的侧壁和转接金属20表面的化学残余物和悬挂键，提高选择性。In some embodiments, before executing step S700 , the second opening 72 ′ is first surface treated to remove chemical residues and dangling bonds on the sidewall of the second opening 72 ′ and the surface of the transfer metal 20 to improve selectivity.
化学残余物例如可以是形成第二开口72′的过程中残留下的化学物质，悬挂键例如可以是没有电子能配对的化学键。The chemical residues may be, for example, chemical substances remaining in the process of forming the second opening 72 ′, and the dangling bonds may be, for example, chemical bonds with no electrons to pair with.
对第二开口72′的表面进行处理的方式，例如可以是加热处理、等离子体处理、通 入还原性气体(例如氢气)处理、通入氧化性气体(例如氧气和一氧化二氮)处理、通入惰性气体处理等方式进行表面处理。The surface of the second opening 72' may be treated by, for example, heat treatment, plasma treatment, treatment with a reducing gas (such as hydrogen), treatment with an oxidizing gas (such as oxygen and nitrous oxide), treatment with an inert gas, etc.
S800、对第二介质膜60′进行第二次重原子注入。S800 , performing a second heavy atom implantation on the second dielectric film 60 ′.
通过再一次的重原子注入，第二介质膜60′中重原子的浓度增大，使第二介质膜60′的表面发生膨胀，填充第二导电柱本体721与第二开口72′侧壁之间的缝隙，使第二导电柱本体721与第二开口72′侧壁接触更致密，进一步提高第二导电柱本体721与第二开口72′侧壁的粘附性。By injecting heavy atoms again, the concentration of heavy atoms in the second dielectric film 60′ increases, causing the surface of the second dielectric film 60′ to expand, filling the gap between the second conductive column body 721 and the side wall of the second opening 72′, making the contact between the second conductive column body 721 and the side wall of the second opening 72′ more dense, further improving the adhesion between the second conductive column body 721 and the side wall of the second opening 72′.
在一些实施例中，第二次重原子注入时注入能量、注入剂量或者注入角度中的至少一个比第一次重原子注入时小。In some embodiments, at least one of the implantation energy, the implantation dose, or the implantation angle during the second heavy atom implantation is smaller than that during the first heavy atom implantation.
示例的，第二次重原子注入时的能量为30KeV，剂量为3E15，角度为30°。第一次重原子注入时的能量为50KeV，剂量为3E18，角度为60°。For example, the energy of the second heavy atom implantation is 30 KeV, the dose is 3E15, and the angle is 30°. The energy of the first heavy atom implantation is 50 KeV, the dose is 3E18, and the angle is 60°.
通过调整第二次重原子注入时的注入能量、注入剂量或者注入角度，可使第二次注入的重原子主要集中在第二介质膜60′侧面的靠近第二导电柱本体721端部的位置处，减少重原子注入过程中飞溅至第二介质膜60′表面的重原子的数量，以改善因第二介质膜60′中包含重原子而影响芯片性能的问题。By adjusting the injection energy, injection dose or injection angle during the second heavy atom injection, the heavy atoms injected for the second time can be mainly concentrated on the side of the second dielectric film 60′ close to the end of the second conductive column body 721, thereby reducing the number of heavy atoms splashed onto the surface of the second dielectric film 60′ during the heavy atom injection process, thereby improving the problem of chip performance being affected by the presence of heavy atoms in the second dielectric film 60′.
相当于说，第二次重原子注入，主要将重原子注入在第二介质膜60′中，第一介质膜30′中没有或者几乎没有注入。在一些实施例中，最终形成的第二介质层中重原子的浓度大于第一介质层中重原子的浓度。In other words, the second heavy atom implantation mainly implants heavy atoms into the second dielectric film 60', and almost none or no heavy atoms are implanted into the first dielectric film 30'. In some embodiments, the concentration of heavy atoms in the final second dielectric layer is greater than that in the first dielectric layer.
S900、如图14所示，去除电阻保护膜50′中位于第三开口71′下方的部分，形成第一开口73′，并形成电阻保护层50。S900 , as shown in FIG. 14 , removing the portion of the resistor protection film 50 ′ located below the third opening 71 ′, forming a first opening 73 ′, and forming a resistor protection layer 50 .
电阻保护膜50′中的刻蚀阻挡膜53′已经被第三开口71′打开，因此，步骤S900中去除的实为刻蚀停止膜52′和氧化阻挡膜51′中位于第三开口71′下方的部分，在刻蚀停止膜52′上形成第二过孔，在氧化阻挡膜51′上形成第三过孔，以形成第一开口73′。The etch barrier film 53′ in the resistor protection film 50′ has been opened by the third opening 71′. Therefore, what is removed in step S900 is actually the portion of the etch stop film 52′ and the oxidation barrier film 51′ located below the third opening 71′. A second via hole is formed on the etch stop film 52′, and a third via hole is formed on the oxidation barrier film 51′ to form a first opening 73′.
第一开口73′贯穿第二介质膜60′和电阻保护膜50′，第一开口73′露出电阻层40。刻蚀停止膜52′和氧化阻挡膜51′中位于第三开口71′下方的部分被去除后，形成刻蚀停止层52和氧化阻挡层51，从而形成电阻保护层50。电阻保护层50包括沿远离电阻层40的方向，依次层叠设置的氧化阻挡层51、刻蚀停止层52以及刻蚀阻挡层53，氧化阻挡层51具有第三过孔511，刻蚀停止层52具有第二过孔521，刻蚀阻挡层53具有第一过孔531。The first opening 73' penetrates the second dielectric film 60' and the resistor protection film 50', and the first opening 73' exposes the resistor layer 40. After the etching stop film 52' and the part of the oxidation barrier film 51' located below the third opening 71' are removed, an etching stop layer 52 and an oxidation barrier layer 51 are formed, thereby forming a resistor protection layer 50. The resistor protection layer 50 includes an oxidation barrier layer 51, an etching stop layer 52 and an etching barrier layer 53 which are sequentially stacked in a direction away from the resistor layer 40, the oxidation barrier layer 51 has a third via hole 511, the etching stop layer 52 has a second via hole 521, and the etching barrier layer 53 has a first via hole 531.
上述第一刻蚀、第二刻蚀以及本次刻蚀步骤中刻蚀的膜层不同，因此，上述第一刻蚀、第二刻蚀以及本次刻蚀的刻蚀参数不同。通过调整本次刻蚀的刻蚀参数，可以降低对电阻层40的损伤。The film layers etched in the first etching, the second etching and the current etching steps are different, so the etching parameters of the first etching, the second etching and the current etching are different. By adjusting the etching parameters of the current etching, the damage to the resistor layer 40 can be reduced.
如图14所示，电阻层40划分为两部分，第一部分41位于第一开口73′下方，第二部分42位于电阻保护层50下方。后续在第一开口73′中形成第一导电柱后，第一导电柱与第一部分41接触。本申请中，直到准备形成第一导电柱时，才将第一部分41上方的膜层去除，且是采用单独的去除工艺，只去除该部分膜层，几乎不会存在过刻损伤的情况。As shown in FIG. 14 , the resistor layer 40 is divided into two parts, the first part 41 is located below the first opening 73′, and the second part 42 is located below the resistor protection layer 50. After the first conductive column is subsequently formed in the first opening 73′, the first conductive column contacts the first part 41. In the present application, the film layer above the first part 41 is not removed until the first conductive column is ready to be formed, and a separate removal process is used to remove only this part of the film layer, and there is almost no over-etching damage.
在一些实施例中，也可以先执行步骤S900，然后执行步骤S800。In some embodiments, step S900 may be performed first, and then step S800 may be performed.
S1000、如图15A所示，在第一开口73′中形成第一导电柱71，并形成第二介质 层60。S1000. As shown in FIG. 15A , a first conductive column 71 is formed in the first opening 73', and a second dielectric layer 60 is formed.
其中，第一导电柱71与电阻层40电连接。The first conductive column 71 is electrically connected to the resistance layer 40 .
在一些实施例中，如图15A所示，步骤S1000包括：In some embodiments, as shown in FIG. 15A , step S1000 includes:
S1100、形成覆盖第二介质膜60′的第一填充膜711′。S1100 , forming a first filling film 711 ′ covering the second dielectric film 60 ′.
第一填充膜711′的材料例如为导电材料。The material of the first filling film 711 ′ is, for example, a conductive material.
S1200、在第一填充膜711′上形成导电膜712′。S1200 , forming a conductive film 712 ′ on the first filling film 711 ′.
例如，第一填充膜711′为成核层，那么，可以采用金属氧化物化学气相沉积(metal oxide chemical vapor deposition，MOCVD)工艺形成导电膜712′。For example, if the first filling film 711′ is a nucleation layer, then the conductive film 712′ may be formed by a metal oxide chemical vapor deposition (MOCVD) process.
或者，例如，第一填充膜711′为阻挡层，那么，可以采用电镀工艺形成导电膜712′。Alternatively, for example, the first filling film 711 ′ is a barrier layer, and then the conductive film 712 ′ may be formed by an electroplating process.
S1300、对第一填充膜711′、导电膜712′以及第二介质膜60′进行研磨，形成第一填充层(grue layer)711、第一导电柱本体712以及第二介质层60。S1300, the first filling film 711′, the conductive film 712′ and the second dielectric film 60′ are ground to form a first filling layer (grue layer) 711, a first conductive column body 712 and a second dielectric layer 60.
例如，采用化学机械研磨工艺，对第一填充膜711′、导电膜712′以及第二介质膜60′进行研磨。For example, the first filling film 711 ′, the conductive film 712 ′ and the second dielectric film 60 ′ are polished by a chemical mechanical polishing process.
如图15A所示，形成的第一导电柱71位于第一开口73′内，第一导电柱71包括第一导电柱本体712和第一填充层711，第一填充层711覆盖第一导电柱本体712的底面和侧面。As shown in FIG. 15A , the formed first conductive column 71 is located in the first opening 73 ′. The first conductive column 71 includes a first conductive column body 712 and a first filling layer 711 . The first filling layer 711 covers the bottom surface and side surfaces of the first conductive column body 712 .
形成的第二导电柱72位于第二开口72′内，第二导电柱72包括第二导电柱本体721。The formed second conductive pillar 72 is located in the second opening 72 ′, and the second conductive pillar 72 includes a second conductive pillar body 721 .
根据研磨程度的不同，在一些实施例中，如图15B所示，形成第一填充层711、第一导电柱本体712以及第二介质层60的同时，还形成第三导电柱本体723和第二填充层722。Depending on the degree of grinding, in some embodiments, as shown in FIG. 15B , while forming the first filling layer 711 , the first conductive column body 712 , and the second dielectric layer 60 , the third conductive column body 723 and the second filling layer 722 are also formed.
那么，形成的第二导电柱72位于第二开口72′内，第二导电柱72包括第二导电柱本体721、第三导电柱本体723以及第二填充层722，第三导电柱本体723设置在第二导电柱本体721远离转接金属20一侧，第二填充层722覆盖第三导电柱本体723的底面和侧面。Then, the formed second conductive column 72 is located in the second opening 72′, and the second conductive column 72 includes a second conductive column body 721, a third conductive column body 723 and a second filling layer 722. The third conductive column body 723 is arranged on the side of the second conductive column body 721 away from the transfer metal 20, and the second filling layer 722 covers the bottom and side surfaces of the third conductive column body 723.
也就是说，第一填充膜711′位于第三开口71′内的部分作为第一填充层711，第一填充膜711′位于第二开口72′内的部分作为第二填充层722。导电膜712′位于第三开口71′内的部分作为第一导电柱本体712，导电膜712′位于第二开口72′内的部分作为第三导电柱本体723。That is, the portion of the first filling film 711′ located in the third opening 71′ serves as the first filling layer 711, and the portion of the first filling film 711′ located in the second opening 72′ serves as the second filling layer 722. The portion of the conductive film 712′ located in the third opening 71′ serves as the first conductive column body 712, and the portion of the conductive film 712′ located in the second opening 72′ serves as the third conductive column body 723.
对第二介质膜60′研磨后，保留下来的部分作为第二介质层60，第二介质层60远离第一介质层30的表面为平面，位于第二介质膜60′表面的第一填充膜711′和导电膜712′被完全去除。After grinding the second dielectric film 60', the remaining portion is used as the second dielectric layer 60, the surface of the second dielectric layer 60 away from the first dielectric layer 30 is flat, and the first filling film 711' and the conductive film 712' on the surface of the second dielectric film 60' are completely removed.
采用上述制备方法形成第一导电柱71，在制备第一导电柱71时，可以同步完成对第二导电柱72的化学机械研磨，同步完成第二导电柱72的制备。因此，可以减少工艺步骤、降低成本、提升效率。The above-mentioned preparation method is used to form the first conductive pillar 71. When preparing the first conductive pillar 71, the chemical mechanical polishing of the second conductive pillar 72 can be completed simultaneously, and the preparation of the second conductive pillar 72 can be completed simultaneously. Therefore, the process steps can be reduced, the cost can be reduced, and the efficiency can be improved.
在另一些实施例中，步骤S1000包括：采用选择性生长工艺形成第一导电柱71。在这种情况下，第一导电柱71不包括第一填充层711。In some other embodiments, step S1000 includes: forming the first conductive pillar 71 by a selective growth process. In this case, the first conductive pillar 71 does not include the first filling layer 711 .
S2000、如图16所示，在第二介质层60远离转接金属20一侧形成第一导电图案81和第二导电图案82，第一导电图案81与第一导电柱71电连接，第二导电图案82 与第二导电柱72电连接。S2000 , as shown in FIG. 16 , a first conductive pattern 81 and a second conductive pattern 82 are formed on a side of the second dielectric layer 60 away from the transfer metal 20 . The first conductive pattern 81 is electrically connected to the first conductive pillar 71 , and the second conductive pattern 82 is electrically connected to the second conductive pillar 72 .
本申请实施例对第一导电图案81的形状、作用、材料不做限定，根据应用场景合理设置即可。The embodiment of the present application does not limit the shape, function, and material of the first conductive pattern 81 , and it can be reasonably set according to the application scenario.
在一些实施例中，如图16所示，第一导电图案81和第二导电图案82为重布线层中包括的导电图案。也就是说，第一导电图案81和第二导电图案82为后段工艺制备的重布线层中的导电图案。In some embodiments, as shown in Fig. 16, the first conductive pattern 81 and the second conductive pattern 82 are conductive patterns included in the redistribution layer. In other words, the first conductive pattern 81 and the second conductive pattern 82 are conductive patterns in the redistribution layer prepared by the back-end process.
例如，第一导电图案81和第二导电图案82为重布线层中最靠近第二介质层60的一层布线层中的导电图案。其中，第一导电图案81和第二导电图案82可以为柱状，第一导电图案81和第二导电图案82也可以为线条状，第一导电图案81和第二导电图案82还可以是其他形状，本申请实施例对此不做限定。For example, the first conductive pattern 81 and the second conductive pattern 82 are conductive patterns in a wiring layer in the redistribution layer that is closest to the second dielectric layer 60. The first conductive pattern 81 and the second conductive pattern 82 may be columnar, linear, or other shapes, which are not limited in the present embodiment.
一个第一导电图案81可以与一个或多个第一导电柱71电连接，第一导电图案81与第一导电柱71可以接触电连接，也可以间接电连接。第一导电柱71两端分别电连接电阻层40和第一导电图案81。一个第二导电图案82可以与一个或多个第二导电柱72电连接，第二导电图案82与第二导电柱72可以接触电连接，也可以间接电连接。第二导电柱72的两端分别电连接有转接金属20和第二导电图案82。A first conductive pattern 81 can be electrically connected to one or more first conductive pillars 71. The first conductive pattern 81 and the first conductive pillar 71 can be electrically connected by contact or indirectly. The two ends of the first conductive pillar 71 are electrically connected to the resistance layer 40 and the first conductive pattern 81 respectively. A second conductive pattern 82 can be electrically connected to one or more second conductive pillars 72. The second conductive pattern 82 and the second conductive pillar 72 can be electrically connected by contact or indirectly. The two ends of the second conductive pillar 72 are electrically connected to the transfer metal 20 and the second conductive pattern 82 respectively.
本申请实施例提供的芯片，电阻层40上方的电阻保护层50包括刻蚀停止层52和刻蚀阻挡层53，刻蚀阻挡层53作为对电阻膜40′进行刻蚀以形成电阻层40时的阻挡层，来保护电阻层40的图案形状。刻蚀停止层52作为对刻蚀阻挡层53进行刻蚀以形成放置第一导电柱71的开口时的停止层。这样一来，由于刻蚀停止层52的存在，使得第二刻蚀过程中无论采用什么刻蚀工艺在刻蚀阻挡层53上形成第一过孔531，都几乎不会对刻蚀停止层52下方的电阻层40产生影响。既可以提高电阻层40的良率，又可以提高芯片制备过程中对工艺的兼容性。而后续需要制备第一导电柱71时，再采用单独的刻蚀步骤在刻蚀停止层52上形成第二过孔521，通过调整刻蚀条件，可以最大程度的降低对电阻层40的损伤，提高电阻层40的良率。而且，在制备第一导电柱71之前，不露出电阻层40，可减少电阻层40的暴露时间，降低电阻层40被氧化的概率，可进一步提高电阻层40的良率。与相关技术中电阻层40的第一部分41几乎全部损伤相比，本申请制备得到的芯片中电阻层40的良率可明显得到提升。使得电阻层40的实际阻值与设定阻值更为接近，可以有效改善电阻层40损伤引起的阻值偏差，提升芯片性能。In the chip provided in the embodiment of the present application, the resistor protection layer 50 above the resistor layer 40 includes an etch stop layer 52 and an etch barrier layer 53. The etch barrier layer 53 is used as a barrier layer when etching the resistor film 40' to form the resistor layer 40 to protect the pattern shape of the resistor layer 40. The etch stop layer 52 is used as a stop layer when etching the etch barrier layer 53 to form an opening for placing the first conductive column 71. In this way, due to the existence of the etch stop layer 52, no matter what etching process is used to form the first via 531 on the etch barrier layer 53 during the second etching process, it will hardly affect the resistor layer 40 below the etch stop layer 52. It can improve the yield of the resistor layer 40 and improve the compatibility of the process in the chip preparation process. When the first conductive column 71 needs to be prepared later, a separate etching step is used to form the second via 521 on the etch stop layer 52. By adjusting the etching conditions, the damage to the resistor layer 40 can be minimized and the yield of the resistor layer 40 can be improved. Moreover, before preparing the first conductive pillar 71, the resistance layer 40 is not exposed, which can reduce the exposure time of the resistance layer 40, reduce the probability of the resistance layer 40 being oxidized, and further improve the yield of the resistance layer 40. Compared with the first part 41 of the resistance layer 40 in the related art that is almost completely damaged, the yield of the resistance layer 40 in the chip prepared by the present application can be significantly improved. The actual resistance value of the resistance layer 40 is closer to the set resistance value, which can effectively improve the resistance deviation caused by the damage of the resistance layer 40 and improve the chip performance.
而且，在芯片包括第一导电柱71和第二导电柱72的情况下，本申请实施例提供的制备方法，高阻器件区域的第一导电柱71与低阻器件区域的第二导电柱72的制备工艺可以兼容。例如，同步形成第三开口71′和第二开口72′，形成第一导电柱71的同时，完成对第二导电柱72的研磨。也就是说，本申请实施例提供的芯片的制备方法，可以实现在保证电阻层40产品良率的基础上，兼容第一导电柱71和第二导电柱72的制备工艺。Moreover, in the case where the chip includes the first conductive pillar 71 and the second conductive pillar 72, the preparation method provided in the embodiment of the present application can be compatible with the preparation process of the first conductive pillar 71 in the high resistance device region and the second conductive pillar 72 in the low resistance device region. For example, the third opening 71′ and the second opening 72′ are formed simultaneously, and the grinding of the second conductive pillar 72 is completed while the first conductive pillar 71 is formed. In other words, the preparation method of the chip provided in the embodiment of the present application can achieve compatibility with the preparation process of the first conductive pillar 71 and the second conductive pillar 72 on the basis of ensuring the product yield of the resistance layer 40.
另外，通过执行两次重原子掺杂工艺，可以改善第二导电柱72与第二开口72′侧壁粘附性差的问题。In addition, by performing the heavy atom doping process twice, the problem of poor adhesion between the second conductive pillar 72 and the sidewall of the second opening 72 ′ can be improved.
基于此，本申请实施例提供的芯片，如图16所示，芯片包括晶体管10、第一介质层30、依次层叠设置在第一介质层30上的第一区域内的电阻层40和电阻保护层50、 第二介质层60以及第一导电柱71。Based on this, the chip provided in the embodiment of the present application, as shown in Figure 16, includes a transistor 10, a first dielectric layer 30, a resistor layer 40 and a resistor protection layer 50 stacked in sequence in the first region on the first dielectric layer 30, a second dielectric layer 60 and a first conductive column 71.
在一些实施例中，晶体管10上覆盖有层间介质层ILD，层间介质层ILD露出晶体管的源极S、漏极D以及栅极G。第一介质层30设置在晶体管10上，第一介质层30例如设置在层间介质层ILD上。In some embodiments, the transistor 10 is covered with an interlayer dielectric layer ILD, which exposes the transistor's source S, drain D and gate G. The first dielectric layer 30 is disposed on the transistor 10 , for example, on the interlayer dielectric layer ILD.
在一些实施例中，芯片还包括转接金属20，转接金属20与晶体管10的源极S、漏极D以及栅极G电连接，用于将晶体管10的源极S、漏极D以及栅极G引出至同一平面。示例的，转接金属20位于层间介质层ILD内。In some embodiments, the chip further includes a transfer metal 20, which is electrically connected to the source S, drain D and gate G of the transistor 10, and is used to lead the source S, drain D and gate G of the transistor 10 to the same plane. For example, the transfer metal 20 is located in the interlayer dielectric layer ILD.
电阻层40设置在第一介质层30的第一区域内，第一区域例如可以对应芯片的高阻器件区域，电阻保护层50覆盖在电阻层40的表面上。The resistance layer 40 is disposed in a first region of the first dielectric layer 30 . The first region may correspond to a high resistance device region of the chip, for example. The resistance protection layer 50 covers the surface of the resistance layer 40 .
电阻保护层50包括多层介质覆盖层，示例的，如图16所示，电阻保护层50包括三层介质覆盖层，三层介质覆盖层包括沿远离电阻层40的方向依次层叠设置的氧化阻挡层51、刻蚀停止层52以及刻蚀阻挡层53。The resistor protection layer 50 includes multiple dielectric covering layers. For example, as shown in FIG. 16 , the resistor protection layer 50 includes three dielectric covering layers, which include an oxidation barrier layer 51 , an etch stop layer 52 , and an etch barrier layer 53 stacked in sequence in a direction away from the resistor layer 40 .
刻蚀停止层52设置在刻蚀阻挡层53与电阻层40之间，氧化阻挡层51设置在刻蚀停止层52与电阻层40之间。The etch stop layer 52 is disposed between the etch barrier layer 53 and the resistor layer 40 , and the oxidation barrier layer 51 is disposed between the etch stop layer 52 and the resistor layer 40 .
氧化阻挡层51具有第三过孔511，刻蚀停止层52具有第二过孔521，刻蚀阻挡层53具有第一过孔531。第三过孔511、第二过孔521以及第一过孔531连通。The oxidation blocking layer 51 has a third via hole 511, the etch stop layer 52 has a second via hole 521, and the etch blocking layer 53 has a first via hole 531. The third via hole 511, the second via hole 521, and the first via hole 531 are connected.
刻蚀阻挡层53用于作为形成电阻层40的第一刻蚀过程中的刻蚀保护层，刻蚀停止层52用于作为形成第一过孔531的第二刻蚀过程中的刻蚀保护层，氧化阻挡层51用于作为阻止刻蚀停止层52氧化电阻层40的保护层。The etch barrier layer 53 is used as an etch protection layer in the first etching process of forming the resistor layer 40 , the etch stop layer 52 is used as an etch protection layer in the second etching process of forming the first via hole 531 , and the oxidation barrier layer 51 is used as a protection layer to prevent the etch stop layer 52 from oxidizing the resistor layer 40 .
刻蚀阻挡层53和刻蚀停止层52的材料中包括不同介质材料，氧化阻挡层51的材料为不含氧的介质材料，刻蚀停止层52与氧化阻挡层51和刻蚀阻挡层53的材料不同。The materials of the etch barrier layer 53 and the etch stop layer 52 include different dielectric materials. The material of the oxidation barrier layer 51 is a dielectric material that does not contain oxygen. The material of the etch stop layer 52 is different from that of the oxidation barrier layer 51 and the etch barrier layer 53 .
示例的，本申请实施例提供的芯片，刻蚀停止层52与第二介质层60的材料相同，氧化阻挡层51、刻蚀阻挡层53及第一介质层30的材料相同。这样一来，可以减少材料种类，简化制备工艺，降低成本。For example, in the chip provided in the embodiment of the present application, the etch stop layer 52 is made of the same material as the second dielectric layer 60, and the oxidation barrier layer 51, the etch barrier layer 53 and the first dielectric layer 30 are made of the same material. In this way, the types of materials can be reduced, the preparation process can be simplified, and the cost can be reduced.
第二介质层60设置在第一介质层30上，覆盖电阻保护层50。第二介质层60具有第四过孔，第四过孔与刻蚀阻挡层53上的第一过孔531连通。The second dielectric layer 60 is disposed on the first dielectric layer 30 and covers the resistance protection layer 50 . The second dielectric layer 60 has a fourth via hole, which is connected to the first via hole 531 on the etching stop layer 53 .
在一些实施例中，第一介质层30与第二介质层60的材料不同。例如，第一介质层30的材料包括氮化硅，第二介质层60的材料包括氧化硅。In some embodiments, the materials of the first dielectric layer 30 and the second dielectric layer 60 are different. For example, the material of the first dielectric layer 30 includes silicon nitride, and the material of the second dielectric layer 60 includes silicon oxide.
在高阻器件区域，第一介质层30与第二介质层60之间夹叠有电阻层40和电阻保护层50，在非高阻器件区域，第一介质层30与第二介质层60直接接触。In the high resistance device region, the resistance layer 40 and the resistance protection layer 50 are sandwiched between the first dielectric layer 30 and the second dielectric layer 60 . In the non-high resistance device region, the first dielectric layer 30 is in direct contact with the second dielectric layer 60 .
第一导电柱71贯穿第二介质层60和电阻保护层50，第一导电柱71与电阻层40电连接。示例的，第一导电柱71穿过第四过孔、第一过孔、第二过孔以及第三过孔与电阻层40电连接。第四过孔、第一过孔、第二过孔以及第三过孔构成第一开口73′。The first conductive pillar 71 penetrates the second dielectric layer 60 and the resistor protection layer 50, and the first conductive pillar 71 is electrically connected to the resistor layer 40. For example, the first conductive pillar 71 passes through the fourth via hole, the first via hole, the second via hole, and the third via hole to be electrically connected to the resistor layer 40. The fourth via hole, the first via hole, the second via hole, and the third via hole constitute a first opening 73'.
其中，第一导电柱71可以为一个，也可以为多个。图16中以芯片包括一个第一导电柱71为例进行示意。There may be one or more first conductive pillars 71. FIG16 illustrates an example in which a chip includes one first conductive pillar 71.
另外，本申请实施例对第一导电柱71的形状不做限定，第一导电柱71的形状可以是圆柱状、矩形柱状、或者长方体形柱状等。In addition, the embodiment of the present application does not limit the shape of the first conductive pillar 71 , and the shape of the first conductive pillar 71 may be a cylindrical shape, a rectangular column shape, or a cuboid column shape.
在这种情况下，可将电阻层40划分为与第一导电柱71接触的第一部分41和与 电阻保护层50接触的第二部分。In this case, the resistance layer 40 may be divided into a first portion 41 contacting the first conductive pillar 71 and a second portion contacting the resistance protection layer 50 .
由于本申请实施例在制备芯片时，是直到准备形成第一导电柱71时，才将第一部分41上方的电阻保护层50打穿。因此，第一部分41的暴露时间短，损伤较小。而且是采用单独的刻蚀工艺对电阻保护层50进行开孔处理，因此第一部分41几乎不会存在过刻损伤的情况。In the embodiment of the present application, when preparing the chip, the resistor protection layer 50 above the first portion 41 is not pierced until the first conductive pillar 71 is prepared. Therefore, the exposure time of the first portion 41 is short and the damage is small. In addition, a separate etching process is used to open the resistor protection layer 50, so the first portion 41 is almost free of over-etching damage.
所以本申请实施例提供的芯片中，电阻层40中第一部分41的厚度与第二部分42的厚度之比的取值范围可以达到0.2-1。Therefore, in the chip provided in the embodiment of the present application, the ratio of the thickness of the first portion 41 to the thickness of the second portion 42 in the resistance layer 40 can range from 0.2 to 1.
示例的，第一部分41的厚度与第二部分42的厚度之比为0.3、0.4、0.5、0.6、0.7、0.8或者0.9。Illustratively, the ratio of the thickness of the first portion 41 to the thickness of the second portion 42 is 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.9.
在一些实施例中，电阻层40中第一部分41的厚度与第二部分42的厚度相等。In some embodiments, the thickness of the first portion 41 and the thickness of the second portion 42 of the resistance layer 40 are equal.
在一些实施例中，第一导电柱71包括第一导电柱本体712和第一填充层711，第一填充层711覆盖第一导电柱本体712的侧面和底面。In some embodiments, the first conductive pillar 71 includes a first conductive pillar body 712 and a first filling layer 711 , and the first filling layer 711 covers the side surface and the bottom surface of the first conductive pillar body 712 .
结合上述芯片的制备方法可知，采用第一导电柱71包括第一导电柱本体712和第一填充层711的结构，在制备第一导电柱71的过程中，可以同步对第二导电柱72进行化学机械研磨。可以减少工艺步骤、降低成本、提升效率。According to the chip manufacturing method described above, the first conductive pillar 71 includes a first conductive pillar body 712 and a first filling layer 711. During the preparation of the first conductive pillar 71, chemical mechanical polishing can be performed on the second conductive pillar 72 simultaneously, which can reduce process steps, reduce costs, and improve efficiency.
在一些实施例中，如图16所示，芯片还包括转接金属20和第二导电柱72。In some embodiments, as shown in FIG. 16 , the chip further includes a via metal 20 and a second conductive pillar 72 .
转接金属20例如可以是集成电路表面的转接金属，转接金属20与电阻层40错位排布，转接金属20一介质层30上的投影与电阻层40在第一介质层30上的投影不交叠。The transfer metal 20 may be, for example, a transfer metal on the surface of an integrated circuit. The transfer metal 20 and the resistor layer 40 are arranged in a staggered manner. The projection of the transfer metal 20 on the dielectric layer 30 does not overlap with the projection of the resistor layer 40 on the first dielectric layer 30 .
第二导电柱72贯穿第二介质层60和第一介质层30，第二导电柱72与晶体管10电连接。当然，第二导电柱72与晶体管10可以接触电连接，第二导电柱72与晶体管10也可以通过转接金属20电连接，或者，第二导电柱72与晶体管10通过其他方式耦接。The second conductive pillar 72 penetrates the second dielectric layer 60 and the first dielectric layer 30, and is electrically connected to the transistor 10. Of course, the second conductive pillar 72 and the transistor 10 may be electrically connected by contact, or may be electrically connected by a transfer metal 20, or may be coupled to the transistor 10 by other means.
其中，第二导电柱72可以为一个，也可以为多个。图16中以芯片包括多个第二导电柱72为例进行示意。There may be one or more second conductive pillars 72. FIG16 illustrates a chip including a plurality of second conductive pillars 72 as an example.
另外，本申请实施例对第二导电柱72的形状不做限定，第二导电柱72的形状可以是圆柱状、矩形柱状、或者长方体形柱状等。In addition, the embodiment of the present application does not limit the shape of the second conductive pillar 72 , and the shape of the second conductive pillar 72 may be a cylindrical shape, a rectangular column shape, or a cuboid column shape.
在一些实施例中，第二导电柱72由选择性沉积形成的第二导电柱本体721构成。In some embodiments, the second conductive pillar 72 is composed of a second conductive pillar body 721 formed by selective deposition.
在另一些实施例中，第二导电柱72包括第二导电柱本体721、第三导电柱本体723以及第二填充层722。In some other embodiments, the second conductive column 72 includes a second conductive column body 721 , a third conductive column body 723 and a second filling layer 722 .
第三导电柱本体723设置在第二导电柱本体721上方，第三导电柱本体723可以是与第一导电柱本体712同步形成，第二填充层722可以是与第一填充层711同步形成。The third conductive column body 723 is disposed above the second conductive column body 721 . The third conductive column body 723 may be formed simultaneously with the first conductive column body 712 , and the second filling layer 722 may be formed simultaneously with the first filling layer 711 .
在一些实施例中，第一介质层30与第二导电柱72接触的侧壁和第二介质层60与第二导电柱72接触的侧壁处掺杂有重原子。In some embodiments, the sidewalls of the first dielectric layer 30 in contact with the second conductive pillar 72 and the sidewalls of the second dielectric layer 60 in contact with the second conductive pillar 72 are doped with heavy atoms.
第二介质层60中的重原子可以是通过一次重原子掺杂工艺掺杂形成的，重原子也可以是通过两次重原子掺杂工艺掺杂形成的。The heavy atoms in the second dielectric layer 60 may be formed by doping through a single heavy atom doping process, or may be formed by doping through a double heavy atom doping process.
通过两次重原子掺杂工艺，可以提升第二导电柱72与第二开口72′的侧壁的粘附性，有效改善因第二导电柱72与侧壁粘附性差导致转接金属20损伤的问题。Through two heavy atom doping processes, the adhesion between the second conductive pillar 72 and the sidewall of the second opening 72 ′ can be improved, and the problem of damage to the transfer metal 20 caused by poor adhesion between the second conductive pillar 72 and the sidewall can be effectively improved.
在一些实施例中，请继续参考图16，芯片还包括第一导电图案81和第二导电图案82，第一导电图案81和第二导电图案82设置在第二介质层60远离第一介质层30一侧，第一导电柱71与第一导电图案81电连接，第二导电柱72与第二导电图案82电连接。第一导电图案81和第二导电图案82可以电连接，也可以不电连接。In some embodiments, please continue to refer to FIG. 16 , the chip further includes a first conductive pattern 81 and a second conductive pattern 82, the first conductive pattern 81 and the second conductive pattern 82 are arranged on the side of the second dielectric layer 60 away from the first dielectric layer 30, the first conductive pillar 71 is electrically connected to the first conductive pattern 81, and the second conductive pillar 72 is electrically connected to the second conductive pattern 82. The first conductive pattern 81 and the second conductive pattern 82 may be electrically connected or not electrically connected.
本申请实施例提供的芯片，电阻层40上方的电阻保护层50包括刻蚀停止层52和刻蚀阻挡层53，刻蚀阻挡层53作为对电阻膜40′进行刻蚀以形成电阻层40时的阻挡层，来保护电阻层40的图案形状。刻蚀停止层52作为对刻蚀阻挡层53进行刻蚀以形成放置第一导电柱71的开口时的停止层。这样一来，由于刻蚀停止层52的存在，使得第二刻蚀过程中无论采用什么刻蚀工艺在刻蚀阻挡层53上形成第一过孔531，都几乎不会对刻蚀停止层52下方的电阻层40产生影响。既可以提高电阻层40的良率，又可以提高芯片制备过程中对工艺的兼容性。而后续需要制备第一导电柱71时，再采用单独的刻蚀步骤在刻蚀停止层52上形成第二过孔521，通过调整刻蚀条件，可以最大程度的降低对电阻层40的损伤，提高电阻层40的良率。而且，在制备第一导电柱71之前，不露出电阻层40，可减少电阻层40的暴露时间，降低电阻层40被氧化的概率，可进一步提高电阻层40的良率。In the chip provided in the embodiment of the present application, the resistor protection layer 50 above the resistor layer 40 includes an etch stop layer 52 and an etch barrier layer 53. The etch barrier layer 53 is used as a barrier layer when etching the resistor film 40' to form the resistor layer 40 to protect the pattern shape of the resistor layer 40. The etch stop layer 52 is used as a stop layer when etching the etch barrier layer 53 to form an opening for placing the first conductive column 71. In this way, due to the existence of the etch stop layer 52, no matter what etching process is used to form the first via 531 on the etch barrier layer 53 during the second etching process, it will hardly affect the resistor layer 40 below the etch stop layer 52. It can improve the yield of the resistor layer 40 and improve the compatibility of the process in the chip preparation process. When the first conductive column 71 needs to be prepared later, a separate etching step is used to form the second via 521 on the etch stop layer 52. By adjusting the etching conditions, the damage to the resistor layer 40 can be minimized and the yield of the resistor layer 40 can be improved. Furthermore, before preparing the first conductive pillar 71 , the resistance layer 40 is not exposed, which can reduce the exposure time of the resistance layer 40 , reduce the probability of the resistance layer 40 being oxidized, and further improve the yield of the resistance layer 40 .
示例二Example 2
示例二与示例一的主要不同之处在于：第三开口71′和第二开口72′的制备过程不同。The main difference between Example 2 and Example 1 is that the preparation processes of the third opening 71 ′ and the second opening 72 ′ are different.
本申请实施例提供一种芯片及其制备方法，包括：The present application provides a chip and a method for preparing the same, including:
执行示例一中的步骤S100-S300。Execute steps S100-S300 in Example 1.
S400′、如图17所示，第二刻蚀中的第一次刻蚀，形成贯穿第二介质膜60′的第四过孔62和第五过孔61。S400 ′, as shown in FIG. 17 , the first etching in the second etching process forms a fourth via hole 62 and a fifth via hole 61 penetrating the second dielectric film 60 ′.
第四过孔62位于电阻层40上方，第四过孔62与电阻层40的位置对应。或者理解为，第四过孔62在第一介质膜30′上的投影位于电阻层40在第一介质膜30′上的投影内。The fourth via hole 62 is located above the resistor layer 40, and the fourth via hole 62 corresponds to the position of the resistor layer 40. Alternatively, the projection of the fourth via hole 62 on the first dielectric film 30' is located within the projection of the resistor layer 40 on the first dielectric film 30'.
第五过孔61位于转接金属20上方，第五过孔61与转接金属20的位置对应。或者理解为，第五过孔61在第一介质膜30′上的投影位于转接金属20在第一介质膜30′上的投影内。The fifth via hole 61 is located above the transfer metal 20, and the fifth via hole 61 corresponds to the position of the transfer metal 20. Alternatively, it can be understood that the projection of the fifth via hole 61 on the first dielectric film 30' is located within the projection of the transfer metal 20 on the first dielectric film 30'.
执行示例一中的步骤S500，对第二介质膜60′进行第一次重原子注入。Execute step S500 in Example 1 to perform a first heavy atom implantation on the second dielectric film 60 ′.
S550、如图18所示，第二刻蚀中的第二次刻蚀，在刻蚀阻挡膜53′上形成第一过孔531。S550 , as shown in FIG. 18 , the second etching in the second etching process forms a first via hole 531 on the etching stopper film 53 ′.
在一些实施例中，第一介质膜30′的材料与刻蚀阻挡膜53′的材料相同。那么，第三刻蚀过程中，同步的可以形成贯穿第一介质膜30′的第六过孔31，第六过孔31与第五过孔61连通作为第二开口72′。与此同时，形成第一介质层30。In some embodiments, the material of the first dielectric film 30' is the same as that of the etching stop film 53'. Then, during the third etching process, a sixth via hole 31 penetrating the first dielectric film 30' can be formed synchronously, and the sixth via hole 31 is connected to the fifth via hole 61 as a second opening 72'. At the same time, the first dielectric layer 30 is formed.
该步骤中，刻蚀停止膜52′用于作为形成第一过孔531的第二刻蚀过程中的刻蚀保护层。In this step, the etching stop film 52 ′ is used as an etching protection layer in the second etching process for forming the first via hole 531 .
执行示例一中的步骤S600-S2000，完成芯片的制备。Execute steps S600-S2000 in Example 1 to complete the preparation of the chip.
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换， 都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (21)

  1. 一种芯片，其特征在于，包括：A chip, characterized by comprising:
    第一介质层；a first dielectric layer;
    电阻层和电阻保护层，依次层叠设置在所述第一介质层上的第一区域内；所述电阻保护层包括刻蚀停止层和刻蚀阻挡层，所述刻蚀停止层设置在所述刻蚀阻挡层与所述电阻层之间；所述刻蚀阻挡层具有第一过孔，所述刻蚀停止层具有第二过孔；A resistor layer and a resistor protection layer are sequentially stacked in a first region on the first dielectric layer; the resistor protection layer comprises an etch stop layer and an etch barrier layer, the etch stop layer is arranged between the etch barrier layer and the resistor layer; the etch barrier layer has a first via hole, and the etch stop layer has a second via hole;
    第二介质层，设置在所述第一介质层上且覆盖所述电阻保护层；A second dielectric layer, disposed on the first dielectric layer and covering the resistance protection layer;
    第一导电柱，贯穿所述第二介质层，并穿过所述第一过孔和所述第二过孔与所述电阻层电连接；A first conductive column, penetrating the second dielectric layer and passing through the first via hole and the second via hole to be electrically connected to the resistance layer;
    其中，所述刻蚀阻挡层用于作为形成所述电阻层的第一刻蚀过程中的刻蚀保护层，所述刻蚀停止层用于作为形成所述第一过孔的第二刻蚀过程中的刻蚀保护层。The etching barrier layer is used as an etching protection layer in a first etching process for forming the resistance layer, and the etching stop layer is used as an etching protection layer in a second etching process for forming the first via hole.
  2. 根据权利要求1所述的芯片，其特征在于，所述电阻层包括与所述第一导电柱接触的第一部分和与所述电阻保护层接触的第二部分，所述第一部分的厚度与所述第二部分的厚度之比的取值范围为0.2-1。The chip according to claim 1 is characterized in that the resistance layer includes a first portion in contact with the first conductive column and a second portion in contact with the resistance protection layer, and the ratio of the thickness of the first portion to the thickness of the second portion is in the range of 0.2-1.
  3. 根据权利要求2所述的芯片，其特征在于，所述电阻保护层还包括氧化阻挡层；The chip according to claim 2, characterized in that the resistance protection layer further comprises an oxidation barrier layer;
    所述氧化阻挡层设置在所述刻蚀停止层与所述电阻层之间，所述氧化阻挡层具有第三过孔，所述第三过孔与所述第二过孔连通。The oxidation blocking layer is disposed between the etch stop layer and the resistance layer. The oxidation blocking layer has a third via hole, and the third via hole is connected to the second via hole.
  4. 根据权利要求1-3任一项所述的芯片，其特征在于，所述第一导电柱包括第一导电柱本体和第一填充层，所述第一填充层覆盖所述第一导电柱本体的侧面和底面。The chip according to any one of claims 1 to 3 is characterized in that the first conductive column comprises a first conductive column body and a first filling layer, and the first filling layer covers the side surface and bottom surface of the first conductive column body.
  5. 根据权利要求4所述的芯片，其特征在于，所述氧化阻挡层的材料包括氮化硅，所述刻蚀停止层的材料包括氧化硅，所述刻蚀阻挡层的材料包括氮化硅。The chip according to claim 4 is characterized in that the material of the oxidation blocking layer includes silicon nitride, the material of the etch stop layer includes silicon oxide, and the material of the etch blocking layer includes silicon nitride.
  6. 根据权利要求1-5任一项所述的芯片，其特征在于，所述电阻层的材料包括氮化钛、氮化钽或者氧化钛。The chip according to any one of claims 1 to 5, characterized in that the material of the resistance layer includes titanium nitride, tantalum nitride or titanium oxide.
  7. 根据权利要求1-6任一项所述的芯片，其特征在于，所述芯片还包括晶体管和第二导电柱；The chip according to any one of claims 1 to 6, characterized in that the chip further comprises a transistor and a second conductive column;
    所述晶体管设置在所述第一介质层远离所述第二介质层一侧，所述晶体管在所述第一介质层上的投影与所述电阻层在所述第一介质层上的投影不交叠；The transistor is arranged on a side of the first dielectric layer away from the second dielectric layer, and a projection of the transistor on the first dielectric layer does not overlap with a projection of the resistance layer on the first dielectric layer;
    所述第二导电柱贯穿所述第二介质层和所述第一介质层，与所述晶体管电连接。The second conductive column penetrates the second dielectric layer and the first dielectric layer and is electrically connected to the transistor.
  8. 根据权利要求7所述的芯片，其特征在于，所述第一介质层与所述第二导电柱接触的侧壁和所述第二介质层与所述第二导电柱接触的侧壁处掺杂有重原子。The chip according to claim 7, characterized in that the sidewalls of the first dielectric layer in contact with the second conductive pillar and the sidewalls of the second dielectric layer in contact with the second conductive pillar are doped with heavy atoms.
  9. 根据权利要求7或8所述的芯片，其特征在于，所述第二导电柱包括第二导电柱本体，所述第二导电柱本体与所述晶体管电连接。The chip according to claim 7 or 8 is characterized in that the second conductive column includes a second conductive column body, and the second conductive column body is electrically connected to the transistor.
  10. 根据权利要求9所述的芯片，其特征在于，所述第二导电柱还包括第三导电柱本体和第二填充层；The chip according to claim 9, characterized in that the second conductive column further comprises a third conductive column body and a second filling layer;
    所述第三导电柱本体设置在所述第二导电柱本体远离所述晶体管一侧，所述第二填充层覆盖所述第三导电柱本体的侧面和底面。The third conductive column body is disposed on a side of the second conductive column body away from the transistor, and the second filling layer covers a side surface and a bottom surface of the third conductive column body.
  11. 根据权利要求1-10任一项所述的芯片，其特征在于，所述第二介质层与所述第一导电柱接触的侧面掺杂有重原子。The chip according to any one of claims 1 to 10, characterized in that the side of the second dielectric layer in contact with the first conductive pillar is doped with heavy atoms.
  12. 根据权利要求7-11任一项所述的芯片，其特征在于，所述芯片还包括第一导电图案和第二导电图案；The chip according to any one of claims 7 to 11, characterized in that the chip further comprises a first conductive pattern and a second conductive pattern;
    所述第一导电图案和所述第二导电图案设置在所述第二介质层远离所述第一介质层一侧；所述第一导电柱与所述第一导电图案电连接，所述第二导电柱与所述第二导电图案电连接。The first conductive pattern and the second conductive pattern are arranged on a side of the second dielectric layer away from the first dielectric layer; the first conductive column is electrically connected to the first conductive pattern, and the second conductive column is electrically connected to the second conductive pattern.
  13. 一种电子设备，其特征在于，包括权利要求1-12任一项所述的芯片和电路板，所述芯片设置在所述电路板上。An electronic device, characterized in that it comprises the chip and circuit board according to any one of claims 1 to 12, wherein the chip is arranged on the circuit board.
  14. 一种芯片的制备方法，其特征在于，包括：A method for preparing a chip, characterized by comprising:
    形成第一介质膜；forming a first dielectric film;
    在所述第一介质膜上依次形成层叠设置的电阻膜和电阻保护膜，所述电阻膜覆盖所述第一介质膜，所述电阻保护膜位于所述第一介质膜的第一区域内；所述电阻保护膜包括刻蚀停止膜和刻蚀阻挡膜，所述刻蚀停止膜位于所述刻蚀阻挡膜与所述电阻膜之间；A resistor film and a resistor protection film are sequentially formed on the first dielectric film, wherein the resistor film covers the first dielectric film and the resistor protection film is located in the first region of the first dielectric film; the resistor protection film includes an etch stop film and an etch barrier film, and the etch stop film is located between the etch barrier film and the resistor film;
    对所述电阻膜进行第一刻蚀，形成电阻层；所述刻蚀阻挡膜用于作为形成所述电阻层的第一刻蚀过程中的刻蚀保护层，所述电阻层位于所述第一区域内；Performing a first etching on the resistor film to form a resistor layer; the etching barrier film is used as an etching protection layer in the first etching process of forming the resistor layer, and the resistor layer is located in the first region;
    形成第二介质膜；所述第二介质膜形成在所述第一介质膜上、且覆盖所述电阻保护膜；forming a second dielectric film; the second dielectric film is formed on the first dielectric film and covers the resistor protection film;
    通过第二刻蚀，形成贯穿所述第二介质膜的第四过孔和贯穿所述刻蚀阻挡膜的第一过孔；所述刻蚀停止膜用于作为形成所述第一过孔的第二刻蚀过程中的刻蚀保护层；By second etching, a fourth via hole penetrating the second dielectric film and a first via hole penetrating the etching stop film are formed; the etching stop film is used as an etching protection layer in the second etching process of forming the first via hole;
    在刻蚀停止膜上形成第二过孔，形成贯穿所述第二介质膜和所述电阻保护膜的第一开口及电阻保护层；forming a second via hole on the etching stop film, forming a first opening penetrating the second dielectric film and the resistance protection film and the resistance protection layer;
    在所述第一开口内形成第一导电柱，并形成第二介质层；所述第一导电柱与所述电阻层电连接。A first conductive column is formed in the first opening, and a second dielectric layer is formed; the first conductive column is electrically connected to the resistance layer.
  15. 根据权利要求14所述的芯片的制备方法，其特征在于，形成所述第一介质膜之前，所述制备方法还包括：形成晶体管；所述晶体管在所述第一介质膜上的投影与所述电阻层在所述第一介质膜上的投影不交叠；The chip manufacturing method according to claim 14 is characterized in that before forming the first dielectric film, the manufacturing method further comprises: forming a transistor; the projection of the transistor on the first dielectric film does not overlap with the projection of the resistance layer on the first dielectric film;
    在刻蚀停止膜上形成第二过孔之前，所述制备方法还包括：形成贯穿所述第二介质膜和所述第一介质膜的第二开口，以形成第一介质层；所述第二开口露出所述晶体管；Before forming the second via hole on the etching stop film, the preparation method further includes: forming a second opening penetrating the second dielectric film and the first dielectric film to form a first dielectric layer; the second opening exposes the transistor;
    在所述第二开口内形成第二导电柱本体，所述第二导电柱本体与所述晶体管电连接。A second conductive column body is formed in the second opening, and the second conductive column body is electrically connected to the transistor.
  16. 根据权利要求15所述的芯片的制备方法，其特征在于，在所述第二开口内形成第二导电柱本体之前，所述制备方法还包括：The chip manufacturing method according to claim 15, characterized in that before forming the second conductive column body in the second opening, the manufacturing method further comprises:
    对所述第二介质膜进行第一次重原子注入。A first heavy atom implantation is performed on the second dielectric film.
  17. 根据权利要求15或16所述的芯片的制备方法，其特征在于，在所述第二开口内形成第二导电柱本体之后，所述制备方法还包括：The method for preparing a chip according to claim 15 or 16, characterized in that after forming the second conductive pillar body in the second opening, the method further comprises:
    对所述第二介质膜进行第二次重原子注入。A second heavy atom implantation is performed on the second dielectric film.
  18. 根据权利要求17所述的芯片的制备方法，其特征在于，所述第二次重原子注 入时的能量小于所述第一次重原子注入时的能量；The chip manufacturing method according to claim 17, characterized in that the energy of the second heavy atom injection is less than the energy of the first heavy atom injection;
    和/或，and / or,
    所述第二次重原子注入时的剂量小于所述第一次重原子注入时的剂量；The dosage of the second heavy atom implantation is less than the dosage of the first heavy atom implantation;
    和/或，and / or,
    所述第二次重原子注入时的角度小于所述第一次重原子注入时的角度。The angle of the second heavy atom injection is smaller than the angle of the first heavy atom injection.
  19. 根据权利要求14-18任一项所述的芯片的制备方法，其特征在于，在所述第一开口内形成第一导电柱，并形成第二介质层，包括：The method for preparing a chip according to any one of claims 14 to 18, characterized in that forming a first conductive column in the first opening and forming a second dielectric layer comprises:
    形成覆盖所述第二介质膜的第一填充膜；forming a first filling film covering the second dielectric film;
    在所述第一填充膜上形成导电膜；forming a conductive film on the first filling film;
    对所述第一填充膜、所述导电膜以及所述第二介质膜进行研磨，形成第一填充层、第一导电柱本体以及第二介质层；所述第一导电柱本***于所述第一开口内，所述第一填充层覆盖所述第一导电柱本体的底面和侧面；所述第一导电柱包括所述第一填充层和所述第一导电柱本体。The first filling film, the conductive film and the second dielectric film are ground to form a first filling layer, a first conductive column body and a second dielectric layer; the first conductive column body is located in the first opening, and the first filling layer covers the bottom and side surfaces of the first conductive column body; the first conductive column includes the first filling layer and the first conductive column body.
  20. 根据权利要求19所述的芯片的制备方法，其特征在于，The method for preparing a chip according to claim 19, characterized in that:
    形成第一填充层、第一导电柱本体以及第二介质层的同时，还形成第三导电柱本体和第二填充层；所述第二填充层覆盖所述第三导电柱本体的底面和侧面，所述第三导电柱本体设置在第二导电柱本体远离晶体管一侧。While forming the first filling layer, the first conductive column body and the second dielectric layer, a third conductive column body and a second filling layer are also formed; the second filling layer covers the bottom and side surfaces of the third conductive column body, and the third conductive column body is arranged on the side of the second conductive column body away from the transistor.
  21. 根据权利要求14-20任一项所述的芯片的制备方法，其特征在于，所述电阻保护膜还包括氧化阻挡膜；所述氧化阻挡膜设置在所述刻蚀停止膜与所述电阻层之间；所述制备方法还包括在形成贯穿所述氧化阻挡膜的第三过孔，所述第三过孔与所述第二过孔连通。The chip preparation method according to any one of claims 14-20 is characterized in that the resistor protection film also includes an oxidation barrier film; the oxidation barrier film is arranged between the etch stop film and the resistor layer; the preparation method also includes forming a third via hole penetrating the oxidation barrier film, and the third via hole is connected to the second via hole.
PCT/CN2022/123658 2022-09-30 2022-09-30 Chip and preparation method therefor, and electronic device WO2024065853A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190027406A1 (en) * 2017-07-18 2019-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of interconnection structure of semiconductor device
CN112216738A (en) * 2019-07-09 2021-01-12 台湾积体电路制造股份有限公司 Integrated chip and forming method thereof
US20220102343A1 (en) * 2020-09-25 2022-03-31 Intel Corporation Multi-layer etch stop layers for advanced integrated circuit structure fabrication
WO2022198674A1 (en) * 2021-03-26 2022-09-29 华为技术有限公司 Chip, electronic device, and forming method for film perforation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190027406A1 (en) * 2017-07-18 2019-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of interconnection structure of semiconductor device
CN112216738A (en) * 2019-07-09 2021-01-12 台湾积体电路制造股份有限公司 Integrated chip and forming method thereof
US20220102343A1 (en) * 2020-09-25 2022-03-31 Intel Corporation Multi-layer etch stop layers for advanced integrated circuit structure fabrication
WO2022198674A1 (en) * 2021-03-26 2022-09-29 华为技术有限公司 Chip, electronic device, and forming method for film perforation

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