WO2024065465A1 - 显示面板、显示装置 - Google Patents

显示面板、显示装置 Download PDF

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Publication number
WO2024065465A1
WO2024065465A1 PCT/CN2022/122820 CN2022122820W WO2024065465A1 WO 2024065465 A1 WO2024065465 A1 WO 2024065465A1 CN 2022122820 W CN2022122820 W CN 2022122820W WO 2024065465 A1 WO2024065465 A1 WO 2024065465A1
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WIPO (PCT)
Prior art keywords
data line
substrate
conductive pattern
display panel
display area
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PCT/CN2022/122820
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English (en)
French (fr)
Inventor
张春旭
周茂秀
姜晓婷
程敏
杨海鹏
戴珂
李会
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/122820 priority Critical patent/WO2024065465A1/zh
Publication of WO2024065465A1 publication Critical patent/WO2024065465A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel and a display device.
  • At least one embodiment of the present application provides a display panel, comprising: a first display area and at least one second display area, wherein the second display area is located on one side of the first display area; the display panel further comprises:
  • a plurality of gate lines and a plurality of data lines are located on the substrate, the gate lines and the data lines intersect and are insulated, the sub-pixels are located at positions defined by the gate lines and the data lines; at least one of the data lines is located at a junction of the first display area and the second display area;
  • first conductive patterns are at least located in the second display area, and the first conductive patterns are electrically connected to one of the gate lines or the common electrodes;
  • a plurality of second conductive patterns are located in the second display area and electrically connected to the data line at the junction; wherein the orthographic projections of some of the first conductive patterns on the substrate overlap with the orthographic projections of the second conductive patterns on the substrate.
  • the plurality of first conductive patterns include a first portion
  • the first conductive pattern in the first part is located in the second display area and is electrically connected to the gate line; the orthographic projection of the second conductive pattern on the substrate is located within the orthographic projection of the first conductive pattern in the first part on the substrate.
  • the plurality of first conductive patterns include a second portion
  • the first conductive pattern in the second part extends from the first display area to the second display area and is electrically connected to the common electrode; the orthographic projection of the first conductive pattern in the second part on the substrate overlaps with the orthographic projection of the data line at the junction on the substrate.
  • an outer contour of an orthographic projection of the second conductive pattern on the substrate is located within an outer contour of an orthographic projection of the first conductive pattern on the substrate in the first part.
  • the second display area includes multiple first virtual capacitors, a first portion of the first conductive patterns serve as first electrodes of the first virtual capacitors, and the second conductive patterns serve as second electrodes of the first virtual capacitors.
  • the second display area includes multiple dummy transistors, the gates of the dummy transistors are electrically connected to the gate lines, the first ends of the dummy transistors are electrically connected to the data lines at the junctions, and the second ends of the dummy transistors are isolated.
  • a partial area of the first conductive pattern in the first part serves as a gate of the dummy transistor
  • At least part of the second conductive pattern includes a first conductive portion and a second conductive portion, the first conductive portion and the second conductive portion are disconnected, the first conductive portion serves as a first end of the dummy transistor, and the second conductive portion serves as a second end of the dummy transistor.
  • the number of the dummy transistors is less than or equal to half the number of the sub-pixel rows.
  • each of the gate lines divides the data line at the junction into multiple data line segments;
  • the first display area includes multiple transistors, some of the data line segments are electrically connected to the transistors, and at least a portion of the data line segments not connected to the transistors are electrically connected to the virtual transistors.
  • the number of the virtual transistors is equal to half the number of sub-pixel rows
  • the data line segments not connected to the transistors are all electrically connected to the virtual transistors
  • the data line segments electrically connected to the transistors and the data line segments electrically connected to the virtual transistors are arranged at intervals.
  • the first conductive pattern in the second part and the common electrode are an integrated structure.
  • the display panel includes a plurality of second virtual capacitors, a second portion of the first conductive pattern serves as a first electrode of the second virtual capacitor, and a portion of the data line at the junction serves as a second electrode of the second virtual capacitor;
  • the orthographic projection area of the second portion of the first conductive pattern located in the second display area on the substrate is larger than the orthographic projection area of the second portion of the first conductive pattern located in the first display area on the substrate.
  • the orthographic projection shape of the second part of the first conductive pattern on the substrate includes a polygon, an arc, or a combination of a polygon and an arc.
  • the orthographic projection figure of the first conductive pattern in the second part on the substrate includes a first edge and a second edge that are relatively arranged, the first edge and the second edge have the same extension direction, the first edge is located in the second display area, the second edge is located in the first display area, and the length of the first edge along its extension direction is greater than or equal to the length of the second edge along its extension direction.
  • a distance between the first conductive pattern in the second part and the data line at the junction is a first distance
  • the orthographic projection figure of the first conductive pattern in the second part on the substrate includes a right-angled trapezoid, and the difference between the size of the upper base and the lower base of the right-angled trapezoid is proportional to the first distance.
  • a distance between the first conductive pattern in the second part and the data line at the junction is a first distance
  • the orthographic projection figure of the first conductive pattern in the second part on the substrate includes a combination of a rectangle and a first figure, the first figure includes a plurality of right-angled trapezoids, and the right-angled sides of each of the right-angled trapezoids are in contact with the rectangle; the sum of the sizes of the upper base and the lower base of each of the right-angled trapezoids is proportional to the first distance.
  • the orthographic projection pattern of the first conductive pattern in the second part on the substrate includes a combination of a second pattern and a third pattern connected to each other, the second pattern includes a corner-cut rectangle, and the third pattern includes a polygon, an arc, or a combination of a polygon and an arc;
  • the second figure extends from the first display area to the second display area
  • the third figure is located in the second display area
  • the part of the second part of the first conductive pattern that is projected as the third figure is in direct contact with the common electrode line of the display panel
  • the cut corner of the cut corner rectangle is located in the second display area.
  • the vertex corners of the orthographic projection figure of the second part of the first conductive pattern on the substrate include rounded corners.
  • the number of the second virtual capacitors is greater than or equal to half the number of the sub-pixel rows.
  • each gate line divides the data line at the intersection into multiple data line segments; the orthographic projection of at least part of the data line segments on the substrate overlaps with the orthographic projection of a second part of the first conductive pattern on the substrate.
  • the number of the second virtual capacitors is equal to the number of sub-pixel rows, and the orthographic projection of each of the data line segments on the substrate overlaps with the orthographic projection of the second portion of the first conductive pattern on the substrate.
  • the number of the second virtual capacitors is equal to half of the number of sub-pixel rows, and the orthographic projection of half of the data line segments on the substrate overlaps with the orthographic projection of the second part of the first conductive pattern on the substrate.
  • each of the data line segments includes a first group and a second group, and the orthographic projection of the data line segments of the first group on the substrate overlaps with the orthographic projection of the first conductive pattern of the second part on the substrate, and the orthographic projection of the data line segments of the second group on the substrate does not overlap with the orthographic projection of the first conductive pattern of the second part on the substrate; wherein the data line segments of the first group and the data line segments of the second group are arranged at intervals.
  • a capacitance load difference between the data line at the junction and the data line in the first display area there is a capacitance load difference between the data line at the junction and the data line in the first display area, and a second virtual capacitor is configured to compensate for the capacitance load difference between the two data line segments.
  • the display panel further includes a third conductive pattern, the third conductive pattern is electrically connected to the common electrode, the third conductive pattern is at least located in the second display area, and at least a portion of the third conductive pattern is located between the first conductive pattern in the first part and the data line at the junction;
  • the orthographic projection of at least a partial area of the third conductive pattern on the substrate does not overlap with the orthographic projection of the data line at the boundary on the substrate.
  • the display panel also includes a third virtual capacitor, the third conductive pattern serves as the first electrode of the third virtual capacitor and is electrically connected to the common electrode, and a partial line segment of the data line at the junction serves as the second electrode of the third virtual capacitor.
  • the orthographic projection of the third conductive pattern on the substrate and the orthographic projection of the data line at the junction on the substrate do not overlap with each other.
  • the sub-pixels in the same row are connected to the same gate line;
  • a column of sub-pixels is arranged between every two adjacent data lines, and the sub-pixels in the same column include a first category and a second category, and any sub-pixel of the first category is located between two sub-pixels of the second category, wherein the first category of sub-pixels in the same column are electrically connected to one data line, and the second category of sub-pixels in the same column are electrically connected to another data line.
  • the plurality of gate lines also divide the data line located in the first display area into a plurality of data line segments, and in each of the data line segments, some of the data line segments include a supporting portion, a first connecting portion, and a second connecting portion, and the supporting portion is located between the first connecting portion and the second connecting portion;
  • the size of the supporting portion along the direction perpendicular to the extension direction of the data line segment is larger than the size of the first connecting portion along the direction perpendicular to the extension direction of the data line segment
  • the size of the supporting portion along the direction perpendicular to the extension direction of the data line segment is larger than the size of the second connecting portion along the direction perpendicular to the extension direction of the data line segment.
  • the display panel further includes a spacer and a protective portion, the spacer is located on a side of a portion of the supporting portion away from the substrate, and the protective portion is located on at least one side of each of the supporting portions; the height of the protective portion along a plane perpendicular to the substrate is greater than the height of the supporting portion along a plane perpendicular to the substrate.
  • an embodiment of the present application provides a display device, comprising the display panel described in the first aspect.
  • FIG. 1 and FIG. 3 are schematic structural diagrams of display panels in two related technologies provided in embodiments of the present application;
  • FIG. 2 is a schematic diagram of capacitance load distribution on a data line of the display panel shown in FIG. 3 ;
  • 4 to 12 are schematic diagrams of partial planar structures of nine display panels provided in embodiments of the present application.
  • FIGS. 13 to 20 are schematic planar structural diagrams of eight second virtual capacitors provided in embodiments of the present application.
  • FIG. 21 is an analysis curve of the effect of alignment deviation of a data line on a capacitive load provided by an embodiment of the present application.
  • 22-23 are schematic diagrams of planar structures of two second virtual capacitors provided in embodiments of the present application.
  • 24 to 27 are schematic diagrams of partial planar structures of four display panels provided in embodiments of the present application.
  • FIG28 is a schematic structural diagram of a display panel using a Z-inversion technology provided by an embodiment of the present application.
  • FIG29 is a planar design layout of a display panel provided in an embodiment of the present application.
  • FIG30 is a schematic diagram of a structure in a first display area of a display panel provided in an embodiment of the present application.
  • FIG. 31 and FIG. 32 are schematic diagrams of partial planar structures of two display panels provided in embodiments of the present application.
  • plural means two or more; the orientation or positional relationship indicated by the term “on” and the like is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the structure or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.
  • the term “including” is to be interpreted as an open, inclusive meaning, that is, “including, but not limited to”.
  • the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “examples”, “specific examples” or “some examples” are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application.
  • the schematic representation of the above terms does not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.
  • the “same layer” in the embodiments of the present application refers to the relationship between multiple film layers formed by the same material after the same step (e.g., a one-step patterning process).
  • the “same layer” here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.
  • the polygons in this specification are not strictly defined, and can be approximate triangles, parallelograms, trapezoids, pentagons or hexagons, etc., and there may be some small deformations caused by tolerances.
  • the capacitive loads of the first data line and the last data line are inconsistent with those of other data lines.
  • the capacitive loads of the two data lines can be made consistent with those of other data lines, thereby avoiding the charging rate difference caused by the RC signal delay (RC Delay) difference and the problem of uneven display brightness caused by the charging rate difference.
  • FIG2 a schematic diagram of capacitance distribution in sub-pixels of a Z-inversion display product is provided; wherein, the left side is a normal data line in the display area, and the right side is the first or last data line in the display area; since sub-pixels are arranged on both sides of the data line on the left, and sub-pixels are arranged on only one side of the data line on the right, the data line on the right lacks the lateral capacitance between the data line itself and the gate of the transistor in a sub-pixel, lacks the overlapping capacitance between the gate and the source and drain of the transistor (such as Cgd-lateral marked in the dotted box), lacks the lateral capacitance between the data line and the common electrode of a sub-pixel (such as Cdc-lateral marked in the a
  • an embodiment of the present application provides a display panel and a display device.
  • the display panel includes: a first display area and at least one second display area, the second display area is located on one side of the first display area; the display panel also includes: a substrate; a plurality of sub-pixels arranged in an array on the substrate; each sub-pixel is located in the first display area, and the sub-pixel includes a common electrode; a plurality of gate lines and a plurality of data lines located on the substrate, the gate lines and the data lines intersect and are insulated, and the sub-pixels are located at positions defined by the gate lines and the data lines; at least one data line is located at the junction of the first display area and the second display area; a plurality of first conductive patterns, the first conductive pattern is at least located in the second display area, and the first conductive pattern is electrically connected to one of the gate lines or the common electrode; a plurality of second conductive patterns, located in the second display area and electrically connected to the data lines at the junction; wherein
  • overlapping capacitance is formed by arranging part of the projection of the first conductive pattern and the second conductive pattern to overlap, and the second conductive pattern is electrically connected to the data line at the junction, thereby increasing the capacitive load of the data line at the junction, and improving the load consistency between the data line at the junction and other data lines.
  • the charging rate difference caused by the RC signal delay (RC Delay) difference is avoided, and the problem of uneven display brightness caused by the charging rate difference is avoided, thereby taking into account both a narrow frame and a higher display effect.
  • FIG. 4, 5, 6 and 7 are respectively plan schematic diagrams of four display panels provided in the embodiments of the present application. It should be noted that Figures 4, 5, 6 and 7 do not show the entire display panel, but only illustrate a portion of the display panel. The embodiment of the present application does not show a cross-sectional schematic diagram of the layer structure of the display panel. The layer structure not shown can be referred to the relevant technology.
  • the display panel includes: a first display area AA1 and at least one second display area AA2 , wherein the second display area AA2 is located on one side of the first display area AA1 ; the display panel also includes:
  • a plurality of gate lines GL and a plurality of data lines DL are disposed on the substrate, the gate lines GL and the data lines DL intersect and are insulated, and the sub-pixels are disposed at positions defined by the gate lines GL and the data lines DL; at least one data line DL is disposed at the junction of the first display area AA1 and the second display area AA2;
  • a plurality of second conductive patterns 3 are located in the second display area AA2 and are electrically connected to the data lines DL at the junctions; wherein the orthographic projections of some first conductive patterns 2 on the substrate overlap with the orthographic projections of the second conductive patterns 3 on the substrate.
  • the display panel may be a liquid crystal display panel (Liquid Crystal Display, LCD).
  • the liquid crystal display panel may include a twisted nematic (TN) type, a vertical alignment (VA) type, an in-plane switching (IPS) type, and an advanced super-dimensional switch (ADS) type.
  • TN twisted nematic
  • VA vertical alignment
  • IPS in-plane switching
  • ADS advanced super-dimensional switch
  • the liquid crystal display panel may include an array substrate and a color filter substrate, the liquid crystal layer LC is located between the array substrate and the color filter substrate, the array substrate and the color filter substrate respectively include substrates, wherein the substrates mentioned in the embodiments of the present application all refer to the substrates in the array substrate.
  • the structures and components included in the array substrate and the color film substrate of the display panel are not limited here, and can be specifically determined according to the design of the product.
  • the display panel includes a display area AA and a peripheral area surrounding the display area AA
  • the display area AA includes a first display area AA1 and at least one second display area AA2, wherein the first display area AA1 includes sub-pixels, and the second display area AA2 does not include sub-pixels, each sub-pixel in the first display area AA1 is charged and displayed through a data line DL, and the structure in the second display area AA2 assists in improving the charging rate of the data line DL, so that the charging rate of the data line DL located at the junction of the first display area AA1 and the second display area AA2 tends to be consistent with the charging rate of the data line in the first display area AA1.
  • the display area AA may include a first display area AA1 and a second display area AA2, and the second display area AA2 is located on one side of the first display area AA1.
  • a data line DL is located at the junction of the first display area AA1 and the second display area AA2.
  • the display area AA may include a first display area AA1 and two second display areas AA2, and the two second display areas AA2 are respectively located on two opposite sides of the first display area AA1. At this time, there are two data lines DL respectively located at two junctions of the first display area AA1 and the second display area AA2.
  • the Dummy sub-pixels on one side as shown in FIG. 1 may be eliminated, and the structure in the second display area AA2 provided in the embodiments of the present application may be set; in other embodiments, the Dummy sub-pixels on both sides as shown in FIG. 1 may be eliminated, and the structure in the second display area AA2 provided in the embodiments of the present application may be set on both sides.
  • the substrate can be any one of silicon, glass, quartz, PET, plastic and the like.
  • the arrangement of the sub-pixels is not limited here and can be specifically determined according to the design of the actual product.
  • the sub-pixels may include sub-pixels of three colors, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • sub-pixels of the same color are located in the same row. For example, multiple red sub-pixels are located in the same row, multiple green sub-pixels are located in the same row, and multiple blue sub-pixels are located in the same row; for another example, multiple red sub-pixels are located in the same column, multiple green sub-pixels are located in the same column, and multiple blue sub-pixels are located in the same column.
  • the same row of sub-pixels includes sub-pixels of at least two colors.
  • the same row of sub-pixels may include sub-pixels of two colors, or the same row of sub-pixels may include sub-pixels of three colors.
  • the shape of the orthographic projection of the sub-pixel on the substrate is not limited here. Generally, the shape of the orthographic projection of the sub-pixel on the substrate is roughly a rectangle, a parallelogram, or a hexagon.
  • the specific structure of the gate lines GL and the data lines DL included in the display panel is not limited here.
  • the gate line GL may include a straight line segment, or include a bent structure formed by a plurality of straight line segments; the specific structure may be determined according to actual design.
  • the data line DL may include a straight line segment, or include a bent structure formed by a plurality of straight line segments, which may be determined according to actual design.
  • the specific materials of the gate lines GL and the data lines DL are not limited here.
  • the material of the gate line GL may include copper, and may be formed into a stacked structure such as MoNb/Cu/MoNb by sputtering, wherein the material on the side close to the substrate is MoNb with a thickness of about 1000 mm/s. It is mainly used to improve the adhesion between film layers.
  • the middle layer material of the laminated structure is Cu, which is the material of the electrical signal transmission channel.
  • the material on the side away from the substrate 1 is MoNb, with a thickness of about It can be used to protect the middle layer and prevent the surface of the middle layer with low resistivity from being exposed and oxidized.
  • a seed layer can be formed using MoNiTi to increase the nucleation density of metal grains in the subsequent electroplating process, and then copper with low resistivity is produced by electroplating, and then an anti-oxidation layer is produced.
  • the material can be MoNiTi.
  • the material of the data lines DL may be the same as that of the gate lines GL.
  • the specific position of the layer structure and the specific material of the first conductive pattern 2 in the display panel are not limited here.
  • the liquid crystal display panel includes a first light-transmitting conductive layer (e.g., 1ITO layer), a gate layer (Gate layer), a source-drain metal layer (SD layer), and a second light-transmitting conductive layer (e.g., 2ITO layer) located on a substrate;
  • a first light-transmitting conductive layer e.g., 1ITO layer
  • a gate layer e.g., Gate layer
  • SD layer source-drain metal layer
  • 2ITO layer second light-transmitting conductive layer located on a substrate
  • the first light-transmitting conductive layer (for example, the 1ITO layer) can be in direct contact with the gate layer (Gate layer).
  • the first light-transmitting conductive layer (for example, the 1ITO layer) can be located between the substrate and the gate layer (Gate layer) and in direct contact with the gate layer (Gate layer);
  • the gate layer (Gate layer) can be located between the substrate and the first light-transmitting conductive layer (for example, the 1ITO layer) and in direct contact with the gate layer (Gate layer);
  • the gate layer (Gate layer), the source-drain metal layer (SD layer) and the second light-transmitting conductive layer (for example, the 2ITO layer) are arranged in sequence in a direction away from the substrate, and insulating materials are provided between the gate layer (Gate layer) and the source-drain metal layer (SD layer), and between the source-drain metal layer (SD layer) and the second light-transmitting conductive layer (for example, the 2ITO layer).
  • the gate line GL is located in the gate layer (Gate layer), and the data line DL is located in the source-drain metal layer (SD layer).
  • an auxiliary wiring can be arranged under the gate line GL, and the auxiliary wiring can be arranged in the first light-transmitting conductive layer (for example, 1ITO layer), and the orthographic projection of the gate line GL on the substrate is located within the orthographic projection of the auxiliary wiring on the substrate.
  • the drawings provided in the embodiments of the present application are drawn by taking the arrangement of the auxiliary wiring under the gate line GL as an example.
  • the first conductive pattern 2 is located in the second display area AA, the first conductive pattern 2 can be disposed on the gate layer (Gate layer), and the first conductive pattern 2 is electrically connected to the gate line GL in the first display area AA1.
  • the first conductive pattern 2 here can be an integrated structure with the gate line GL.
  • a partial area of the first conductive pattern 2 is located in the first display area AA1, and a partial area of the first conductive pattern 2 is located in the second display area AA2.
  • the first conductive pattern 2 can be arranged in the first light-transmitting conductive layer (for example, 1ITO layer), and the first conductive pattern 2 is electrically connected to the common electrode 1 of the sub-pixel in the first display area AA1.
  • the first conductive pattern 2 here can be an integrated structure with the common electrode 1.
  • the material of the first conductive pattern 2 can be determined according to its specific position in the layer structure of the display panel.
  • the material of the first conductive pattern 2 may be the same as that of the gate layer, for example, including copper (Cu).
  • the material of the first conductive pattern 2 can be the same as the material of the first light-transmitting conductive layer, for example, including indium tin oxide (ITO). It should be noted that in the drawings provided in the embodiments of the present application, the materials of the first light-transmitting conductive layer and the second light-transmitting conductive layer are both indium tin oxide.
  • the second conductive pattern 3 may be located in a source-drain metal layer (SD layer).
  • SD layer source-drain metal layer
  • the shape of the orthographic projection of the second conductive pattern 3 on the substrate is not limited here.
  • the shape of the orthographic projection of the second conductive pattern 3 on the substrate can be designed as a rectangle as shown in Figure 6 or Figure 7, so that the second conductive pattern 3 and the first conductive pattern 2/21 can form an overlapping capacitor, simulating the overlapping capacitor formed between the film layers where the gate and source and drain of the transistor in the cancelled Dummy sub-pixel are located.
  • the shape of the orthographic projection figure of the above-mentioned second conductive pattern 3 on the substrate can be designed to be a structure similar to the source and drain of a transistor.
  • the structure similar to the source and drain of the transistor designed using the second conductive pattern 3 here may not be completely consistent with the actual structure of the transistor in the first display area AA1.
  • the shape of the orthographic projection figure of the above-mentioned second conductive pattern 3 on the substrate can be designed to be the same as the structure of the transistor in the first display area AA1 as shown in Figure 30, so that the second conductive pattern 3 and the first conductive pattern 2/21 can form a virtual transistor, so that the capacitive load of the data line DL at the junction is as close as possible to the capacitive load of the data line DL in the first display area AA1.
  • the orthographic projection of part of the first conductive pattern on the substrate overlaps with the orthographic projection of the second conductive pattern on the substrate, including but not limited to the following situations:
  • a portion of the orthographic projection of the first conductive pattern 2 on the substrate overlaps with a portion of the orthographic projection of the second conductive pattern 3 on the substrate.
  • the outer contour of a portion of the orthographic projection of the first conductive pattern 2 on the substrate overlaps with the outer contour of the orthographic projection of the second conductive pattern 3 on the substrate.
  • the part of the first conductive pattern 2 here refers to the first conductive pattern 2/21 which is completely located in the second display area AA2 and is arranged in the gate layer.
  • the capacitance on the first data line DL1 and the seventh data line DL7 is 258 pF
  • the capacitance on the second data line DL2 to the sixth data line DL6 is 410 pF
  • the capacitance load is quite different.
  • the charging rate on the first data line DL1 and the seventh data line DL7 is also much greater than the charging rate on other data lines, resulting in the brightness of the sub-pixels electrically connected to the first data line DL1 and the seventh data line DL7 being greater than the brightness of the sub-pixels electrically connected to other data lines, thereby causing the problem of uneven brightness.
  • the display panel provided in the embodiment of the present application forms an overlapping capacitor by arranging a portion of the projections of the first conductive pattern 2 and the second conductive pattern 3 to overlap, and the second conductive pattern 3 is electrically connected to the data line at the junction, thereby increasing the capacitive load of the data line at the junction, and improving the load consistency between the data line at the junction and other data lines. While reducing the size of the frame, it avoids the charging rate difference caused by the RC signal delay (RC Delay) difference, avoids the problem of uneven display brightness caused by the charging rate difference, and takes into account both a narrow frame and a higher display effect.
  • RC Delay RC signal delay
  • the size of the structure in the second display area AA2 is much smaller than the size of the sub-pixel, which greatly reduces the border size of the display panel and ensures a better display effect.
  • the plurality of first conductive patterns 2 include a first portion 2 / 21 ;
  • the first portion of the first conductive pattern 2/21 is located in the second display area AA2 and is electrically connected to the gate line GL; the orthographic projection of the second conductive pattern 3 on the substrate is located within the orthographic projection of the first portion of the first conductive pattern 2/21 on the substrate.
  • the orthographic projection of the second conductive pattern 3 on the substrate is located within the orthographic projection of the first conductive pattern 2/21 of the first part on the substrate, including but not limited to the following situations:
  • the outer contours of the orthographic projections of the first and second conductive patterns 3 on the substrate are located within the outer contour of the orthographic projection of the first conductive pattern 2/21 of the first part on the substrate;
  • the outer contour of the orthographic projection of the second conductive pattern 3 on the substrate overlaps with the outer contour of the orthographic projection of the first portion of the first conductive pattern 2/21 on the substrate.
  • the plurality of first conductive patterns 2 include a second portion 2 / 22 ;
  • the second portion of the first conductive pattern 2/22 extends from the first display area AA1 to the second display area AA2 and is electrically connected to the common electrode 1; the orthographic projection of the second portion of the first conductive pattern 2/22 on the substrate overlaps with the orthographic projection of the data line DL at the junction on the substrate.
  • the outer contour of the orthographic projection of the second conductive pattern 3 on the substrate is located within the outer contour of the orthographic projection of the first portion of the first conductive pattern 2/21 on the substrate.
  • the second display area AA2 includes multiple first virtual capacitors Dummy C1, the first part of the first conductive pattern 2/21 serves as the first electrode of the first virtual capacitor Dummy C1, and the second conductive pattern 3/32 serves as the second electrode of the first virtual capacitor Dummy C1.
  • a plurality of first virtual capacitors Dummy C1 are formed by arranging partial overlap of the projections of the first conductive pattern 2 and the second conductive pattern 3, and the second conductive pattern 3 is electrically connected to the data line at the junction, thereby increasing the capacitive load of the data line at the junction, and improving the load consistency between the data line at the junction and other data lines.
  • the charging rate difference caused by the RC signal delay (RC Delay) difference is avoided, and the problem of uneven display brightness caused by the charging rate difference is avoided, thereby taking into account both a narrow frame and a higher display effect.
  • the second display area includes a plurality of virtual transistors Dummy TFT, the gate of the virtual transistor Dummy TFT is electrically connected to the gate line GL, the first end of the virtual transistor Dummy TFT is electrically connected to the data line DL at the junction, and the second end of the virtual transistor Dummy TFT is isolated.
  • the above-mentioned isolated setting means that the second end of the virtual transistor Dummy TFT is a conductive island structure, and the conductive island structure is not electrically connected to other conductive structures.
  • first end may be a source electrode, and the second end may be a drain electrode; or the first end may be a drain electrode, and the second end may be a source electrode.
  • the description of the first end and the second end of the virtual transistor Dummy TFT or the transistor in the following text is similar to the meaning here, and will not be repeated.
  • an active layer may not be set in the above-mentioned virtual transistor Dummy TFT.
  • an active layer may be set in the above-mentioned virtual transistor Dummy TFT so that the capacitive load of the data line DL located at the junction of the first display area AA1 and the second display area AA2 is closer to the capacitive load of the data line DL located in the first display area AA1.
  • the structure and size of the virtual transistor Dummy TFT can be designed to be the same as the structure and size of the transistor in the first display area AA1.
  • a plurality of first virtual capacitors Dummy C1 as shown in FIGS. 6 and 7 may be provided in a local area, and a virtual transistor Dummy TFT as shown in FIGS. 4 and 5 may be provided in a local area.
  • a partial area of the first conductive pattern 2/21 is used as a gate of a dummy transistor Dummy TFT;
  • At least part of the second conductive pattern 3 includes a first conductive portion 311 and a second conductive portion 312.
  • the first conductive portion 311 and the second conductive portion 312 are disconnected.
  • the first conductive portion 311 serves as a first end of the virtual transistor Dummy TFT
  • the second conductive portion 312 serves as a second end of the virtual transistor Dummy TFT.
  • a planar graphic of a first end of the dummy transistor Dummy TFT is in an “M” shape
  • a planar graphic of a second end of the dummy transistor Dummy TFT includes two parts, and the two parts are not connected to each other.
  • the structure of the transistor located in the first display area AA1 can be the same as the structure of the virtual transistor Dummy TFT, but the two parts of the second end of the transistor in the first display area AA1 can be electrically connected together and connected to other conductive structures.
  • Dummy TFT is used to represent a virtual transistor, which does not limit the virtual transistor to a thin film transistor (TFT). It can also be a metal oxide semiconductor field effect transistor (MOSFET).
  • TFT thin film transistor
  • MOSFET metal oxide semiconductor field effect transistor
  • the virtual transistor Dummy TFT and the transistor of the sub-pixel in the first display area AA1 can be set to the same type.
  • the second conductive pattern 3 includes the first conductive portion 311 and the second conductive portion 312, including but not limited to the following:
  • the first and part of the second conductive pattern 3 include the first conductive part 311 and the second conductive part 312 as shown in FIG. 4 and FIG. 5 , and the first conductive part 311 and the second conductive part 312 are disconnected; part of the second conductive pattern 3 includes an integrated pattern as shown in FIG. 6 and FIG. 7 .
  • all the second conductive patterns 3 include the first conductive portion 311 and the second conductive portion 312 as shown in FIG. 4 and FIG. 5 , and the first conductive portion 311 and the second conductive portion 312 are disconnected.
  • a virtual transistor Dummy TFT is set in the second display area AA2, and the data line DL located at the junction of the first display area AA1 and the second display area AA2 is electrically connected to the first end of the virtual transistor Dummy TFT, so that the virtual transistor and the data line DL at the junction can simulate the capacitive load of the data line DL and the transistor in the first display area AA1 as much as possible, so that the capacitive load of the data line DL located at the junction of the first display area AA1 and the second display area AA2 is consistent with the capacitive load of the data line DL located in the first display area AA1, reducing the difference in the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, while reducing the frame size of the display panel, improving the brightness uniformity of different areas in the display panel, and improving the display effect.
  • the number of virtual transistors Dummy TFT is less than or equal to half the number of sub-pixel rows.
  • the number of dummy transistors Dummy TFT is equal to half the number of sub-pixel rows.
  • the number of dummy transistors Dummy TFT is less than half the number of sub-pixel rows.
  • a partial area of the data line DL (DL1 or DL7) located at the junction of the first display area AA1 and the second display area AA2 is electrically connected to the transistor located in the first display area AA1, and a partial area of the data line DL (DL1 or DL7) located at the junction of the first display area AA1 and the second display area AA2 is not connected to the transistor in the first display area AA1.
  • a virtual transistor Dummy TFT can be set to be electrically connected thereto.
  • a data line DL (DL1 or DL7) located at the junction of the first display area AA1 and the second display area AA2 of a Z-inversion display panel
  • half of the transistors in a column of sub-pixels adjacent thereto are electrically connected thereto, so at most half of the total number of dummy transistors Dummy TFTs in a column of sub-pixels can be set to be electrically connected to the data line DL at the junction.
  • the total number of sub-pixels in a column is the number of rows of sub-pixels.
  • each gate line GL divides the data line DL at the junction into multiple data line segments;
  • the first display area AA1 includes multiple transistors, some data line segments are electrically connected to the transistors, and at least a part of the data line segments not connected to the transistors are electrically connected to the virtual transistor Dummy TFT.
  • the data line DL at the junction is a continuous line.
  • one data line DL is regarded as a plurality of data line segments connected.
  • At least a portion of the data line segments not connected to the transistors are electrically connected to the dummy transistor Dummy TFT, including but not limited to the following:
  • a portion of the data line segments that are not connected to the transistors are electrically connected to the dummy transistor Dummy TFT;
  • each gate line GL divides the data line DL at the junction into multiple data line segments, such as data line segment DL-J1, data line segment DL-J2, data line segment DL-J3, and data line segment DL-J4, wherein the data line segment DL-J1 is electrically connected to the transistor in the first display area AA1, and the data line segment DL-J3 is electrically connected to the transistor in the first display area AA1; the data line segment DL-J2 and the data line segment DL-J4 are not electrically connected to the transistor in the first display area AA1, however, the data line segment DL-J2 is electrically connected to the dummy transistor Dummy TFT in the second display area AA2.
  • data line segment DL-J1 is electrically connected to the transistor in the first display area AA1
  • the data line segment DL-J3 is electrically connected to the transistor in the first display area AA1
  • the data line segment DL-J2 and the data line segment DL-J4 are not electrically connected to
  • the capacitive load of the data line segment DL-J2 is close to the capacitive load of the data line segment DL-2 in the first display area AA1, and the capacitive load of the data line DL at the junction is close to the capacitive load of the data line DL in the first display area AA1, so that the capacitive load of the data line DL located at the junction of the first display area AA1 and the second display area AA2 is consistent with the capacitive load of the data line DL located in the first display area AA1, reducing the difference in the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, while reducing the frame size of the display panel, improving the brightness uniformity of different areas in the display panel, and improving the display effect.
  • the number of virtual transistors Dummy TFT is equal to half the number of sub-pixel rows
  • the data line segments not connected to the transistors are electrically connected to the virtual transistors Dummy TFT
  • the data line segments electrically connected to the transistors and the data line segments electrically connected to the virtual transistors are arranged at intervals.
  • the capacitive load of each data line segment of the data line DL at the junction is close to the capacitive load of each data line segment of the data line DL in the first display area AA1
  • the overall capacitive load of the data line DL at the junction is close to the overall capacitive load of the data line DL in the first display area AA1
  • the capacitive load of the data line DL located at the junction of the first display area AA1 and the second display area AA2 is consistent with the capacitive load of the data line DL located in the first display area AA1, reducing the difference in the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, while reducing the frame size of the display panel, improving the brightness uniformity of different areas in the display panel, and improving the display effect.
  • the above interval setting means that for each data line segment of the data line DL at the junction, one of any two adjacent data line segments is electrically connected to the transistor in the first display area AA1, and the other is electrically connected to the dummy transistor Dummy TFT in the second display area AA2.
  • Adjacent means that there is no other data line segment between the two data line segments.
  • each gate line GL divides the data line DL at the junction into multiple data line segments;
  • the first display area AA1 includes multiple transistors, some data line segments are electrically connected to the transistors, and at least a portion of the data line segments not connected to the transistors are electrically connected to the first virtual capacitor Dummy C1.
  • At least a portion of the data line segment not connected to the transistor is electrically connected to the first virtual capacitor Dummy C1, including but not limited to the following situations:
  • each gate line GL divides the data line DL at the junction into multiple data line segments;
  • the first display area AA1 includes multiple transistors, some data line segments are electrically connected to the transistors, a portion of the data line segments not connected to the transistors are electrically connected to the first virtual capacitor Dummy C1, and a portion of the data line segments not connected to the transistors are electrically connected to the virtual transistor Dummy TFT.
  • the number of data line segments not connected to transistors is greater than or equal to the sum of the number of the first virtual capacitor Dummy C1 and the number of virtual transistors Dummy TFT.
  • the number of data line segments that are not connected to transistors is equal to the sum of the number of first virtual capacitors Dummy C1 and virtual transistors Dummy TFT.
  • the number of virtual transistors Dummy TFT can be set to be greater than or equal to the number of first virtual capacitors Dummy C1.
  • the overlapping capacitance formed between the gate and the source and drain of the virtual transistor Dummy TFT is closer to the overlapping capacitance between the gate and the source and drain of the transistor in the first display area AA1, so that the capacitive load of the data line DL located at the junction of the first display area AA1 and the second display area AA2 is consistent with the capacitive load of the data line DL located in the first display area AA1, reducing the difference between the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, while reducing the frame size of the display panel, improving the brightness uniformity of different areas in the display panel, and improving the display effect.
  • the second portion of the first conductive pattern 2 / 22 and the common electrode 1 are an integrated structure.
  • the integrated structure means that the same material is used and the structure is prepared and formed in one patterning process, and one patterning process refers to processes including masking, film formation, etching and the like.
  • the display panel includes a plurality of second virtual capacitors Dummy C2, the second portion of the first conductive pattern 2/22 serves as a first electrode of the second virtual capacitor Dummy C2 and is electrically connected to the common electrode 1, and a partial line segment of the data line DL at the junction serves as a second electrode of the second virtual capacitor Dummy C2.
  • the display panel includes multiple second virtual capacitors Dummy C2, the second portion of the first conductive pattern 2/22 serves as a first electrode of the second virtual capacitor Dummy C2 and is electrically connected to the gate line GL, and a partial line segment of the data line DL at the junction serves as a second electrode of the second virtual capacitor Dummy C2.
  • the second virtual capacitor Dummy C2 can be electrically connected to the common electrode so that the common electrode signal (Com signal) is used as an electrode of the second virtual capacitor Dummy C2 for compensation; or, the second virtual capacitor Dummy C2 can be electrically connected to the gate line GL so that the signal of the gate line GL (Gate signal) is used as an electrode of the second virtual capacitor Dummy C2 for compensation.
  • Com signal common electrode signal
  • Gate signal signal of the gate line GL
  • the second virtual capacitor Dummy C2 can be electrically connected to the common electrode so that the common electrode signal (Com signal) can be compensated as an electrode of the second virtual capacitor Dummy C2.
  • the compensation signal that can be selected for the third virtual capacitor Dummy C3 in the following text is similar to that of the second virtual capacitor Dummy C2 and will not be repeated here.
  • each gate line GL divides the data line DL at the junction into multiple data line segments; some data line segments are electrically connected to the virtual transistor Dummy TFT, and another part of the data line segments is provided with a second virtual capacitor Dummy C2, that is, a local area on the part of the data line segments can be used as the second electrode of the second virtual capacitor Dummy C2.
  • the second virtual capacitor Dummy C2 is not set on the data line segment electrically connected to the virtual transistor Dummy TFT, and the second virtual capacitor Dummy C2 is set on at least a part of the data line segments that are not electrically connected to the virtual transistor Dummy TFT.
  • a second virtual capacitor Dummy C2 may also be provided on the data line segment electrically connected to the virtual transistor Dummy TFT.
  • the second virtual capacitor Dummy C2 is not set on the data line segment electrically connected to the first virtual capacitor Dummy C1, and the second virtual capacitor Dummy C2 is set on at least a portion of the data line segments that are not electrically connected to the first virtual capacitor Dummy C1.
  • a second virtual capacitor Dummy C2 may also be set on the data line segment electrically connected to the first virtual capacitor Dummy C1.
  • the first electrode (the second part first conductive pattern 2/22) of the second virtual capacitor Dummy C2 can be in direct contact with the common electrode line CML (Common Line).
  • the common electrode line CML is disposed on the gate layer.
  • the first electrode of the second virtual capacitor Dummy C2 (the second part first conductive pattern 2/22) can be in direct contact with the common electrode line CML (Common Line), which means that the first electrode of the second virtual capacitor Dummy C2 (the second part first conductive pattern 2/22) is in direct contact with the common electrode line CML.
  • the common electrode line CML includes a portion located in the first light-transmitting conductive layer (e.g., 1ITO) and another portion located in the gate layer (Gate layer), that is, the common electrode line CML includes two film layers.
  • the first electrode (the second portion first conductive pattern 2/22) of the second virtual capacitor Dummy C2 can be in direct contact with the common electrode line CML (Common Line), which means that the first electrode (the second portion first conductive pattern 2/22) of the second virtual capacitor Dummy C2 is in direct contact with the portion of the common electrode line CML located in the first light-transmitting conductive layer (e.g., 1ITO).
  • the orthographic projection area S1 of the second portion of the first conductive pattern 2/22 located in the second display area AA2 on the substrate is larger than the orthographic projection area of the second portion of the first conductive pattern 2/22 located in the first display area AA1 on the substrate.
  • the capacitance value of the overlapping capacitance is affected by the area directly facing the two electrodes of the capacitor, while the capacitance value of the lateral capacitance is less affected by the area directly facing the two electrodes of the capacitor.
  • the actual position of the data line DL will be affected by the alignment deviation of the manufacturing process.
  • the second virtual capacitor Dummy C2 includes overlapping capacitance and lateral capacitance. Therefore, the overall capacitance value of the second virtual capacitor Dummy C2 will also be affected by the alignment deviation of the manufacturing process and fluctuate.
  • the embodiments of the present application provide a set of simulation analysis data.
  • FIG. 21 shows the capacitance changes of the lateral capacitance on the left side (the capacitance formed by the portion of the second part first conductive pattern 2/22 located in the second display area AA2 and the local area of the data line DL) and the lateral capacitance on the right side (the capacitance formed by the portion of the second part first conductive pattern 2/22 located in the first display area AA1 and the local area of the data line DL) of the second virtual capacitor Dummy C2 shown in FIG. 22 after the alignment deviation occurs.
  • the capacitance value of the lateral capacitance on the left side gradually increases as the data line shifts to the left (the first display area AA1 shifts in the direction of the second display area AA2); the capacitance value of the lateral capacitance on the right side gradually decreases as the data line shifts to the left (the first display area AA1 shifts in the direction of the second display area AA2).
  • the sum of the capacitance values of the two lateral capacitances is larger before the critical point M and smaller after the critical point M.
  • the embodiments of the present application compensate for the influence of the alignment deviation of the manufacturing process on the overall capacitance value by designing the facing area (or overlapping area) of the overlapping capacitance (the overlapping area where the projection of the first conductive pattern 2/22 in the second part overlaps with the data line DL at the junction) in the second virtual capacitor Dummy C2.
  • the orthographic projection shape of the second portion of the first conductive pattern 2/22 on the substrate includes a polygon, an arc, or a combination of a polygon and an arc.
  • polygons may include triangles, quadrilaterals, pentagons, etc.; arcs may include ellipses, semi-ellipses, semicircles, sectors, etc.; wherein, semi-ellipses and semicircles not only represent half of an ellipse or a circle, but may also be a part of an ellipse or a circle.
  • the orthographic projection figure of the second part of the first conductive pattern 2/22 on the substrate includes a first side L1 and a second side L2 that are relatively arranged, the first side L1 and the second side L2 have the same extension direction, the first side L1 is located in the second display area AA2, the second side L1 is located in the first display area AA1, and the length d1 of the first side L1 along the extension direction thereof is greater than or equal to the length d2 of the second side L2 along the extension direction thereof.
  • the length d1 of the first side L1 along the extending direction thereof may be set equal to the length d2 of the second side L2 along the extending direction thereof.
  • a length d1 of the first side L1 along its extending direction may be set to be greater than a length d2 of the second side L2 along its extending direction.
  • the orthographic projection figure of the second part first conductive pattern 2/22 on the substrate may include a right-angled trapezoid as shown in FIG15, an isosceles trapezoid as shown in FIG16, a figure formed by splicing a right-angled trapezoid and an arc as shown in FIG17, a figure obtained by removing an arc from a right-angled trapezoid, a figure formed by splicing an isosceles trapezoid and two arcs as shown in FIG18, and a figure formed by splicing a right-angled trapezoid and an arc as shown in FIG19.
  • FIG15 the length d1 of the first side L1 along its extension direction is greater than the length d2 of the second side L2 along its extension direction
  • the orthographic projection figure of the second part first conductive pattern 2/22 on the substrate may include a right-angled trapezoid as shown in FIG15, an isosceles trapezoid as
  • the distance between the second part first conductive pattern 2/22 and the data line DL at the junction is a first distance;
  • the orthographic projection figure of the second part first conductive pattern 2/22 on the substrate includes a right trapezoid, and the difference y between the size of the upper base and the lower base of the right trapezoid is proportional to the first distance.
  • the capacitance decreases by a for every 1um away from the Data line. That is, a is the difference in capacitance per unit distance, and b is the capacitance in the case of positive alignment.
  • the three parameters ⁇ 0 , ⁇ r , and d are constants for the same display panel, d is the distance between the two electrodes, that is, the thickness of the insulating layer between the second part first conductive pattern 2/22 and the data line DL at the junction; ⁇ r is the dielectric constant of the insulating layer between the two electrodes, and ⁇ 0 is a constant; as shown in FIG22 , in the case where the data line DL at the junction may be shifted, the orthographic projection figure of the second part first conductive pattern 2/22 on the substrate can be divided into a rectangle with a fixed overlapping area with the data line DL at the junction, and a triangle with a non-fixed overlapping area with the data line DL at the junction, assuming that the overlapping area of the rectangle with a fixed overlapping area and the data line DL at the junction is A1, and the overlapping area of the triangle with a non-fixed overlapping area and the data line DL at the junction is A2;
  • y is the difference between the upper base and the lower base of the orthographic projection figure (right trapezoid) of the first conductive pattern 2/22 of the second part on the substrate as shown in Figure 22. Since in the same area of the same display panel, a, ⁇ 0 and ⁇ r are all constants, the difference y between the sizes of the upper base and the lower base of the right trapezoid is proportional to the first distance d.
  • the orthographic projection figure of the second part first conductive pattern 2/22 on the substrate includes a right-angled trapezoid, and the difference y between the size of the upper base and the lower base of the right-angled trapezoid is proportional to the first distance.
  • the second virtual capacitor Dummy C2 provided in the embodiment of the present application can still provide a stable capacitive load, so that the capacitive load of the data line DL located at the junction of the first display area AA1 and the second display area AA2 is consistent with the capacitive load of the data line DL located in the first display area AA1, reducing the difference between the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, while reducing the frame size of the display panel, improving the brightness uniformity of different areas in the display panel, and improving the display effect.
  • the distance between the second part first conductive pattern 2/22 and the data line DL at the junction is a first distance;
  • the orthographic projection figure of the second part first conductive pattern 2/22 on the substrate includes a combination of a rectangle and a first figure, the first figure includes a plurality of right-angled trapezoids, and the right-angled sides of each right-angled trapezoid are in contact with the rectangle; the sum of the sizes of the upper base and the lower base of each right-angled trapezoid is proportional to the first distance.
  • the orthographic projection pattern of the second portion of the first conductive pattern 2/22 on the substrate can be split into a rectangle with a fixed overlapping area with the data line DL at the junction, and a first pattern with a non-fixed overlapping area with the data line DL at the junction.
  • the overlapping area of the rectangle with a fixed overlapping area and the data line DL at the junction is A1
  • the overlapping area of the first pattern with a non-fixed overlapping area and the data line DL at the junction is A2;
  • the first figure includes a combination of multiple right trapezoids
  • the position marked y1 can be the lower base of the first right trapezoid
  • the position marked y2 can be the upper base of the first right trapezoid or the lower base of the second right trapezoid
  • the position marked y3 can be the upper base of the second right trapezoid.
  • the capacitance decreases by a1 for every 1um away from the data line DL at the junction, and within the position range of the second right-angled trapezoid, the capacitance decreases by a2 for every 1um away from the data line DL at the junction.
  • y1+y2 is the sum of the sizes of the upper base and the lower base of the first right trapezoid
  • y2+y3 is the sum of the sizes of the upper base and the lower base of the second right trapezoid; since in the same area trapezoid of the same display panel, a1, a2, ⁇ 0 and ⁇ r are all constants, the sum of the sizes of the upper base and the lower base of each right trapezoid is proportional to the first distance d.
  • the orthographic projection pattern of the second part first conductive pattern 2/22 on the substrate includes a combination of a rectangle and a first pattern
  • the first pattern includes a plurality of right-angled trapezoids, and the right-angled sides of each right-angled trapezoid are in contact with the rectangle; the sum of the sizes of the upper base and the lower base of each right-angled trapezoid is proportional to the first distance.
  • the second virtual capacitor Dummy C2 provided in the embodiment of the present application can still provide a stable capacitive load, so that the capacitive load of the data line DL located at the junction of the first display area AA1 and the second display area AA2 is consistent with the capacitive load of the data line DL located in the first display area AA1, reducing the difference between the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, while reducing the frame size of the display panel, improving the brightness uniformity of different areas in the display panel, and improving the display effect.
  • the orthographic projection pattern of the second portion of the first conductive pattern 2/22 on the substrate includes a combination of a second pattern T2 and a third pattern T3 connected to each other, the second pattern T2 includes a corner-cut rectangle, and the third pattern T3 includes a polygon, an arc, or a combination of a polygon and an arc;
  • the second figure T2 extends from the first display area AA1 to the second display area AA2, the third figure T3 is located in the second display area AA2, and the part of the second portion of the first conductive pattern 2/22 that is projected as the third figure T3 is in direct contact with the common electrode line CML of the display panel, and the cut corner of the cut corner rectangle is located in the second display area AA2.
  • the size of the corner in the above-mentioned corner rectangle is not limited here. However, no matter what the size of the corner in the corner rectangle is, the area of the second graphic T2 located in the second display area AA2 is always larger than the area of the second graphic T2 located in the first display area AA1.
  • the capacitance value of the overlapping capacitance of the second virtual capacitor Dummy C2 is mainly determined by the size of the second graphic T2.
  • a cut angle can be set at the vertex closest to the conductive pattern with the gate signal (for example, the first conductive pattern 2/21 of the first part shown in Figure 32) in the rectangle.
  • the distance between the second graphic T2 and the conductive pattern with the gate signal can be increased to avoid interference of the gate signal on the signal in the second graphic T2; on the other hand, the probability of electrostatic breakdown due to sharp conductive patterns on the second part first conductive pattern 2/22 is avoided, thereby improving the signal transmission stability in the display panel and improving the product reliability of the display panel.
  • the third figure T3 includes a polygon, an arc, or a combination of a polygon and an arc;
  • polygons may include triangles, quadrilaterals (rectangles, rhombuses, parallelograms), pentagons, hexagons, etc.; arcs may include circles, ellipses, semicircles, semi-ellipses, etc.;
  • the combination of polygons and arcs includes: a figure formed by splicing polygons and arcs, or a figure formed by removing a local area from a polygon or an arc.
  • FIG3 is a local area of a display panel design layout. Since the common electrode line CML covers the third figure T3, part of the third figure T3 is blocked, so the part of the third figure T3 exposed in FIG3 is a triangle. In actual applications, the third figure T3 can be other shapes.
  • the part of the second part of the first conductive pattern 2/22 that is projected as the third figure T3 is mainly for direct contact and overlap with the common electrode line CML to achieve electrical connection.
  • the top corners of the orthographic projection pattern of the second portion of the first conductive pattern 2/22 on the substrate include rounded corners.
  • the second display area AA is arranged close to the non-display area, electrostatic breakdown is prone to occur in the non-display area, and the conductive pattern with a sharp structure will aggravate the electrostatic breakdown and cause damage to the display panel. Therefore, when designing the second part first conductive pattern 2/22, sharp corners are avoided as much as possible and designed to be rounded, thereby reducing the possibility of electrostatic breakdown in this area and improving the quality and reliability of the display panel.
  • the number of second virtual capacitors Dummy C2 is greater than or equal to half the number of sub-pixel rows.
  • the number of second virtual capacitors Dummy C2 can be set to be greater than half of the number of sub-pixel rows and less than or equal to the number of sub-pixel rows.
  • the number of second virtual capacitors Dummy C2 can be set equal to the number of sub-pixel rows.
  • the number of second virtual capacitors Dummy C2 can be set equal to half the number of sub-pixel rows.
  • each gate line GL divides the data line DL at the junction into multiple data line segments; the orthographic projection of at least part of the data line segments on the substrate overlaps with the orthographic projection of the second part of the first conductive pattern 2/22 on the substrate.
  • each gate line GL divides the data line DL at the junction into multiple data line segments, such as data line segment DL-J1, data line segment DL-J2, data line segment DL-J3, and data line segment DL-J4, wherein the data line segment DL-J3 is electrically connected to the transistor in the first display area AA1, and the data line segment DL-J3 is also electrically connected to the second virtual capacitor Dummy C2; the data line segment DL-J2 is electrically connected to the virtual transistor Dummy TFT in the second display area AA2, and the data line segment DL-J2 is not electrically connected to the second virtual capacitor Dummy C2.
  • the same data line segment can be electrically connected to both the virtual transistor Dummy TFT and the second virtual capacitor Dummy C2.
  • the same data line segment can be electrically connected to both the transistor in the first display area AA1 and the second virtual capacitor Dummy C2.
  • the same data line segment cannot be electrically connected to the transistor in the first display area AA1 and to the virtual transistor Dummy TFT at the same time.
  • the same data line segment can be electrically connected to both the first virtual capacitor Dummy C1 and the second virtual capacitor Dummy C2.
  • the same data line segment can be electrically connected to both the transistor in the first display area AA1 and the second virtual capacitor Dummy C2.
  • the same data line segment cannot be electrically connected to the transistor in the first display area AA1 and to the first virtual capacitor Dummy C1 at the same time.
  • the overlap of the orthographic projection of at least part of the data line segment on the substrate and the orthographic projection of the second part of the first conductive pattern 2/22 on the substrate includes but is not limited to the following situations:
  • the orthographic projection of a part of the data line segment on the substrate overlaps with the orthographic projection of the second part of the first conductive pattern 2/22 on the substrate, that is, a part of the data line segment can be electrically connected to the second virtual capacitor Dummy C2.
  • the orthographic projection of all data line segments on the substrate overlaps with the orthographic projection of the second part of the first conductive pattern 2/22 on the substrate, that is, all data line segments can be electrically connected to the second virtual capacitor Dummy C2.
  • a second virtual capacitor Dummy C2 is provided to simulate the lateral capacitance formed between the data line DL and the common electrode in the first display area AA, so that the capacitive load of the data line DL located at the junction of the first display area AA1 and the second display area AA2 is consistent with the capacitive load of the data line DL located in the first display area AA1, thereby reducing the difference in the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, thereby reducing the frame size of the display panel and improving the brightness uniformity of different areas in the display panel, thereby improving the display effect.
  • the number of second virtual capacitors Dummy C2 is equal to the number of sub-pixel rows, and the orthographic projection of each data line segment on the substrate overlaps with the orthographic projection of the second portion of the first conductive pattern 2/22 on the substrate.
  • a second virtual capacitor Dummy C2 is set on each data line segment at the junction of the first display area AA1 and the second display area AA2.
  • planar graphics of the first electrodes (the second part first conductive pattern 2/22) of each second virtual capacitor Dummy C2 disposed on each data line segment at the junction are the same in shape and size, and the planar graphics of each data line segment overlapping with the orthographic projection of the second part first conductive pattern 2/22 on the substrate are also the same in shape and size.
  • the capacitive load on each data line segment at the junction is close to the data line segment in the first display area AA1, so that the overall capacitive load of the data line DL at the junction is close to the capacitive load of the data line DL in the first display area AA1, thereby reducing the difference in charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, while reducing the frame size of the display panel, improving the brightness uniformity of different areas in the display panel, and improving the display effect.
  • the number of second virtual capacitors Dummy C2 is equal to half the number of sub-pixel rows, and the orthographic projection of half of the data line segments on the substrate overlaps with the orthographic projection of the second part of the first conductive pattern 2/22 on the substrate.
  • a second virtual capacitor Dummy C2 may be provided on each data line segment in a local area of the data line DL at the junction of the display panel; and no second virtual capacitor Dummy C2 may be provided in another local area of the data line DL at the junction.
  • a second virtual capacitor Dummy C2 is set on one of the data line segments, and a second virtual capacitor Dummy C2 is not set on the other data line segment.
  • a second virtual capacitor Dummy C2 can be set on the first data line segment, a second virtual capacitor Dummy C2 can be set on the second data line segment, the second virtual capacitor Dummy C2 can be not set on the third data line segment, a second virtual capacitor Dummy C2 can be set on the fourth data line segment, a second virtual capacitor Dummy C2 can be set on the fifth data line segment, and the second virtual capacitor Dummy C2 can be not set on the sixth data line segment, and the settings can be repeated in sequence.
  • a second virtual capacitor Dummy C2 can be set on the first data line segment, the second virtual capacitor Dummy C2 is not set on the second data line segment, the second virtual capacitor Dummy C2 is not set on the third data line segment, a second virtual capacitor Dummy C2 is set on the fourth data line segment, the second virtual capacitor Dummy C2 is not set on the fifth data line segment, and the second virtual capacitor Dummy C2 is not set on the sixth data line segment, and the settings are repeated in sequence.
  • each data line segment includes a first group and a second group, the orthographic projection of the first group of data line segments on the substrate overlaps with the orthographic projection of the second part of the first conductive pattern 2/22 on the substrate, and the orthographic projection of the second group of data line segments on the substrate does not overlap with the orthographic projection of the second part of the first conductive pattern 2/22 on the substrate; wherein, the first group of data line segments and the second group of data line segments are arranged at intervals; it can be understood that at this time, second virtual capacitors Dummy C2 are arranged at intervals on each data line segment; that is, a second virtual capacitor Dummy C2 is arranged on the first data line segment, the second virtual capacitor Dummy C2 is not arranged on the second data line segment, a second virtual capacitor Dummy C2 is arranged on the third data line segment, and the second virtual capacitor Dummy C2 is not arranged on the fourth data line segment.
  • a capacitance load difference between the data line at the junction and the data line in the first display area.
  • a second virtual capacitor Dummy C2 is arranged at intervals on each data line segment, a second virtual capacitor Dummy C2 can be set to compensate for the capacitance load difference of the two data line segments at the same time.
  • the capacitive load of the second virtual capacitor arranged on a data line segment at the junction can be 2R1, so that the sum of the capacitive loads of each data line segment included in a data line DL in the first display area AA1 and the sum of the capacitive loads of the second virtual capacitor Dummy C2 arranged on each data line segment DL at the junction tend to be equal, so that the overall capacitive load of the data line DL at the junction approaches the capacitive load of the data line DL in the first display area AA1, reduces the difference in the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, and improves the brightness uniformity of different areas in the display panel while reducing the frame size of the display panel, thereby improving the display effect.
  • the display panel also includes a third conductive pattern 6, the third conductive pattern 6 is electrically connected to the common electrode 1, the third conductive pattern 6 is at least located in the second display area AA2, and at least a portion of the third conductive pattern AA2 is located between the first portion of the first conductive pattern 2/21 and the data line DL at the junction; wherein, the orthographic projection of at least a portion of the third conductive pattern 6 on the substrate does not overlap with the orthographic projection of the data line DL at the junction on the substrate.
  • the third conductive pattern 6 may be disposed in the same layer as the pixel electrode 4 , wherein a slit Slit is disposed in the pixel electrode 4 .
  • the third conductive pattern 6 may be disposed in the same layer as the common electrode 1 .
  • the third conductive pattern 6 is at least located in the second display area AA2, including but not limited to the following situations:
  • the third conductive pattern 6 is located in the second display area AA2;
  • the third conductive pattern 6 is not only located in the second display area AA2, but also extends to the first display area AA1; at this time, the main part of the third conductive pattern 6 is located in the second display area AA2, and a part of the third conductive pattern 6 is located in the first display area AA1.
  • the third conductive pattern 6 is located between the first portion of the first conductive pattern 2/21 and the data line DL at the junction, including but not limited to the following situations:
  • a portion of the third conductive pattern 6 is located between the first portion of the first conductive pattern 2/21 and the data line DL at the junction;
  • the third conductive pattern 6 is completely located between the first conductive pattern 2 / 21 of the first portion and the data line DL at the junction.
  • orthographic projection of at least a portion of the third conductive pattern 6 on the substrate and the orthographic projection of the data line DL at the junction on the substrate do not overlap each other, including but not limited to the following situations:
  • the orthographic projection of a partial area of the third conductive pattern 6 on the substrate does not overlap with the orthographic projection of the data line DL at the junction on the substrate;
  • the orthographic projection of the third conductive pattern 6 on the substrate does not overlap with the orthographic projection of the data line DL at the junction on the substrate.
  • the display panel also includes a third virtual capacitor Dummy C3, the third conductive pattern 6 serves as the first electrode of the third virtual capacitor Dummy C3 and is electrically connected to the common electrode 1, and a partial line segment of the data line DL at the junction serves as the second electrode of the third virtual capacitor Dummy C3.
  • the third virtual capacitor Dummy C3 includes a lateral capacitor.
  • the third virtual capacitor Dummy C3 includes lateral capacitance and overlapping capacitance.
  • the orthographic projection of the third conductive pattern 6 on the substrate and the orthographic projection of the data line DL at the junction on the substrate do not overlap with each other.
  • the number of third virtual capacitors Dummy C3 is less than or equal to the number of rows of sub-pixels.
  • the number of third virtual capacitors Dummy C3 is equal to the number of rows of sub-pixels.
  • the number of third virtual capacitors Dummy C3 is less than the number of rows of sub-pixels.
  • each gate line GL divides the data line DL at the junction into multiple data line segments, and a third virtual capacitor Dummy C3 can be set at a position between each first part first conductive pattern 2/21 and the data line segment.
  • a data line segment can be set in a partial area of the display panel to be electrically connected to the virtual transistor Dummy TFT, and a data line segment can be set in a partial area to be electrically connected to the third virtual capacitor Dummy C3.
  • a data line segment can be set in a partial area of the display panel to be electrically connected to the first virtual capacitor Dummy C1, and a data line segment can be set in a partial area to be electrically connected to the third virtual capacitor Dummy C3.
  • a data line segment can be set in a partial area of the display panel to be electrically connected to the first virtual capacitor Dummy C1
  • a data line segment can be set in a partial area to be electrically connected to the virtual transistor Dummy TFT
  • a data line segment can be set in a partial area to be electrically connected to the third virtual capacitor Dummy C3.
  • a data line segment can be set in a partial area of the display panel to be electrically connected to the first virtual capacitor Dummy C1, a data line segment can be set in a partial area to be electrically connected to the virtual transistor Dummy TFT, a data line segment can be set in a partial area to be electrically connected to the second virtual capacitor Dummy C2, and a data line segment can be set in a partial area to be electrically connected to the third virtual capacitor Dummy C3.
  • the same data line segment can be electrically connected to both the second virtual capacitor Dummy C2 and the third virtual capacitor Dummy C3. It should be noted that when the second virtual capacitor Dummy C2 and the third virtual capacitor Dummy C3 are simultaneously set at the corresponding position of the same data line segment, there is a certain distance between the plane figures of the second virtual capacitor Dummy C2 and the third virtual capacitor Dummy C3 to avoid electrical signal interference between the two virtual capacitors.
  • a third virtual capacitor Dummy C3 is set on one of the data line segments, and a third virtual capacitor Dummy C3 is not set on the other data line segment.
  • a third virtual capacitor Dummy C3 can be set on the first data line segment, a third virtual capacitor Dummy C3 can be set on the second data line segment, the third virtual capacitor Dummy C3 can be not set on the third data line segment, a third virtual capacitor Dummy C3 can be set on the fourth data line segment, a third virtual capacitor Dummy C3 can be set on the fifth data line segment, and the third virtual capacitor Dummy C3 can be not set on the sixth data line segment, and the settings can be repeated in sequence.
  • a third virtual capacitor Dummy C3 can be set on the first data line segment, the third virtual capacitor Dummy C3 is not set on the second data line segment, the third virtual capacitor Dummy C3 is not set on the third data line segment, a third virtual capacitor Dummy C3 is set on the fourth data line segment, the third virtual capacitor Dummy C3 is not set on the fifth data line segment, and the third virtual capacitor Dummy C3 is not set on the sixth data line segment, and the settings are repeated in sequence.
  • the third virtual capacitor Dummy C3 electrically connected to the data line DL at the junction can simulate the lateral capacitance formed between the common electrode 1 and the data line DL in the first display area AA1, so that the overall capacitive load of the data line DL at the junction is close to the capacitive load of the data line DL in the first display area AA1, thereby reducing the difference in the charging rate of the data line DL at the junction and the charging rate of the data line DL in the first display area AA1, while reducing the frame size of the display panel and improving the brightness uniformity of different areas in the display panel, thereby improving the display effect.
  • sub-pixels in the same row are connected to the same gate line GL;
  • a column of sub-pixels is arranged between every two adjacent data lines DL, and the sub-pixels in the same column include a first category and a second category. Any first category sub-pixel is located between two second category sub-pixels, wherein the first category of sub-pixels in the same column is electrically connected to one data line DL, and the second category of sub-pixels in the same column is electrically connected to another data line DL.
  • the first row of sub-pixels is connected to the first gate line GL1
  • the second row of sub-pixels is connected to the second gate line GL2
  • the third row of sub-pixels is connected to the third gate line GL3
  • the fourth row of sub-pixels is connected to the fourth gate line GL4 .
  • the first sub-pixel and the third sub-pixel in the first column of sub-pixels are connected to the first data line DL1, and the second sub-pixel and the fourth sub-pixel in the first column of sub-pixels are connected to the second data line DL2; the first sub-pixel and the third sub-pixel in the second column of sub-pixels are connected to the second data line DL2, and the second sub-pixel and the fourth sub-pixel in the second column of sub-pixels are connected to the third data line DL3; the first sub-pixel and the third sub-pixel in the third column of sub-pixels are connected to the third data line DL2, and the second sub-pixel and the fourth sub-pixel in the third column of sub-pixels are connected to the fourth data line DL4.
  • the display panel shown in FIG28 is a display panel using a Z-inversion technology. The specific introduction of the display panel using the Z-inversion technology can be referred to the relevant technology, which will not be repeated here.
  • the first data line DL1 and the fourth data line DL4 are data lines located at the junction of the first display area AA1 and the second display area AA2, respectively, and the number of transistors of sub-pixels electrically connected to the two data lines is half the number of transistors of sub-pixels connected to other data lines.
  • the first row of sub-pixels may be set as red sub-pixels
  • the second row of sub-pixels may be set as green sub-pixels
  • the third row of sub-pixels may be set as green sub-pixels
  • the fourth row of sub-pixels may be set as red sub-pixels.
  • the sub-pixels in the first column may be set as red sub-pixels
  • the sub-pixels in the second column may be set as green sub-pixels
  • the sub-pixels in the third column may be set as green sub-pixels.
  • the plurality of gate lines GL also divide the data line DL located in the first display area AA1 into a plurality of data line segments, and in each data line segment, part of the data line segments includes a support portion PSZ, a first connection portion, and a second connection portion, and the support portion PSZ is located between the first connection portion and the second connection portion;
  • the orthographic projection of the first connecting portion on the substrate overlaps with the orthographic projection of one gate line GL on the substrate, and the orthographic projection of the second connecting portion on the substrate overlaps with the orthographic projection of another gate line GL on the substrate.
  • the dimension of the support portion PSZ along the direction perpendicular to the data line segment is greater than the dimension of the first connection portion along the direction perpendicular to the data line segment, and the dimension of the support portion along the direction perpendicular to the data line segment is greater than the dimension of the second connection portion along the direction perpendicular to the data line segment. It can be understood that the line width (Line Width) of the support portion in the data line segment is greater than the line width of the first connection portion, and the line width (Line Width) of the support portion is greater than the line width of the second connection portion.
  • a line width of the first connection portion may be the same as a line width of the second connection portion.
  • a support portion PSZ, a first connection portion, and a second connection portion are disposed on two connected data line segments.
  • the support portion PSZ, the first connection portion, and the second connection portion may be disposed at intervals.
  • the first data line segment is provided with a support portion PSZ, a first connection portion, and a second connection portion
  • the second data line segment is not provided with a support portion PSZ, a first connection portion, and a second connection portion
  • the third data line segment is provided with a support portion PSZ, a first connection portion, and a second connection portion
  • the first data line segment is provided with a support portion PSZ, a first connection portion, and a second connection portion
  • the second data line segment is not provided with a support portion PSZ, a first connection portion, and a second connection portion
  • the third data line segment is not provided with a support portion PSZ, a first connection portion, and a second connection portion
  • the fourth data line segment is not provided with a support portion PSZ, a first connection portion, and a second connection portion
  • the fifth data line segment is not provided with a support portion PSZ, a first connection portion, and a second connection portion
  • the sixth data line segment is provided with a support part PSZ, a first connection part, and a second connection part
  • the seventh data line segment is not provided with a support part PSZ, a first connection part, and a second connection part
  • the eighth data line segment is not provided with a support part PSZ, a first connection part, and a second connection part
  • the ninth data line segment is not provided with a support part PSZ, a first connection part, and a second connection part is not provided with a support part PSZ, a first connection part, and a second connection part is not provided with a tenth data line segment.
  • the support portion PSZ provided in the embodiment of the present application is used to place a spacer PS.
  • the spacer PS is arranged on the side of the support portion PSZ away from the substrate to support the array substrate and the color film substrate and improve the display performance of the display panel.
  • the design space can be saved to a great extent, and the aperture ratio of the display panel can be increased, thereby improving the light transmittance of the display panel, improving the display effect, and reducing power consumption.
  • the display panel also includes a spacer PS and a protective portion PSB, the spacer PS is located on the side of part of the supporting portion PSB away from the substrate, and the protective portion PSB is located on at least one side of each supporting portion PSZ; the height of the protective portion PSB along the plane perpendicular to the substrate is greater than the height of the supporting portion PSZ along the plane perpendicular to the substrate.
  • spacers PS do not need to be provided on all the support parts PSZ.
  • the outer contour of the orthographic projection of the spacer PS on the substrate is located within the outer contour of the orthographic projection of the support portion PSZ on the substrate.
  • a spacer PS is disposed on the support portion PSZ in a local area, and no spacer PS is disposed on the support portion PSZ in a local area.
  • no spacer PS is disposed on the supporting portion PSZ of the data line DL at the boundary between the first display area AA1 and the second display area AA2 , and a spacer PS is disposed on the supporting portion PSZ of the data line DL in the first display area AA1 .
  • the spacers PS include a main spacer MPS and an auxiliary spacer SPS.
  • the number and distribution pattern of the main spacers MPS and the auxiliary spacers SPS are not limited here.
  • a support portion PSZ, a first connection portion and a second connection portion are provided on two connected data line segments, and a main spacer MPS and an auxiliary spacer SPS are respectively provided on the two support portions PSZ.
  • main spacer MPS and the auxiliary spacer SPS can refer to the description in the relevant technology, which will not be repeated here.
  • a protective portion PSB is provided on both sides of each supporting portion PSZ in the first display area AA1, and a protective portion PSB is provided on the side of each supporting portion PSZ close to the first display area AA1 in the second display area AA2.
  • the protective portion PSB is provided in the sub-pixel. When the spacer PS is shifted or damaged, the protective portion PSB can protect the film layer structure in the sub-pixel from being scratched by the spacer PS, thereby avoiding damage to the sub-pixel.
  • the thickness of the support portion PSZ is the same as that of the data line DL, and the thicknesses thereof are both determined according to the thickness of the source-drain metal layer (SD layer).
  • the protection part PSB includes a first sublayer and a second sublayer, wherein the first sublayer is located in the gate layer (Gate layer), and the second sublayer is located in the source-drain metal layer (SD layer), and the thickness of the protection part PSB is the sum of the thicknesses of the gate layer (Gate layer) and the source-drain metal layer (SD layer).
  • the extension direction of the protection portion PSB is consistent with the extension direction of the side of the support portion PSZ, so as to reasonably utilize the space as much as possible and reduce the difficulty of design.
  • a protection layer PSB may be disposed on both sides of the support portion PSZ, and the protection layer PSB half surrounds the support portion PSZ.
  • two groups of protection parts PSB can be respectively arranged on both sides of the support part PSZ, and the two groups of protection parts PSB are symmetrically arranged, and one group of protection parts PSB includes a larger protection part PSB and a smaller protection part PSB, wherein the smaller protection part PSB is located on the side of the larger protection part PSB away from the support part PSZ.
  • the positive projection figure of the first conductive pattern 2/21 of the first part of the display panel on the substrate is a rectangle, wherein, as shown in FIG. 29, a plurality of vias Via are provided in the upper half of the rectangle, and the vias are used to electrically connect the output terminal Gout of the GOA circuit in the peripheral area BB with the gate line GL in the display area AA; a virtual transistor Dummy TFT or a first virtual capacitor Dummy C1 may be provided in the lower half of the rectangle.
  • the peripheral area BB of the display panel further includes a common line BSL, one end of which is electrically connected to the binding terminal of the display panel, and the other end of which is electrically connected to the common electrode line CML in the display area AA.
  • the common line BSL is also provided with a plurality of coding patterns N0.1 for marking the number of rows of sub-pixels in the display panel.
  • other regions of the peripheral area BB also include a plurality of coding patterns N0.2 for marking the number of columns of sub-pixels in the display panel.
  • An embodiment of the present application provides a display device, including the display panel described above.
  • the above-mentioned display device can be a liquid crystal display device (Liquid Crystal Display, LCD).
  • the liquid crystal display device can include a twisted nematic (Twisted Nematic, TN) type, a vertical alignment (Vertical Alignment, VA) type, an in-plane switching (In Plane Switching, IPS) type and an advanced super dimensional switch (ADS, Advanced Super Dimension Switch) type.
  • TN twisted nematic
  • VA Vertical Alignment
  • IPS in-plane switching
  • ADS Advanced Super dimensional switch
  • the above-mentioned display device can be a display device such as an LCD display, as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. that includes these display devices.
  • the display device provided by the embodiment of the present application forms an overlapping capacitor by arranging the projection overlap of part of the first conductive pattern 2 and the second conductive pattern 3, and the second conductive pattern 3 is electrically connected to the data line at the junction, thereby increasing the capacitive load of the data line at the junction, improving the load consistency of the data line at the junction with other data lines, and reducing the size of the frame while avoiding the charging rate difference caused by the difference in RC signal delay (RC Delay), avoiding the problem of uneven display brightness caused by the difference in charging rate, and taking into account both narrow frame and high display effect.
  • RC Delay RC signal delay
  • the size of the structure in the second display area AA2 is much smaller than the size of the sub-pixel, which greatly reduces the frame size of the display panel and ensures a better display effect.

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Abstract

本申请提供了一种显示面板、显示装置，涉及显示技术领域，该显示面板包括：第一显示区和至少一个第二显示区，衬底；位于衬底上的多个子像素；各子像素均位于第一显示区；子像素包括公共电极；栅线和数据线，至少一条数据线位于第一显示区和第二显示区的交界处；多个第一导电图案，第一导电图案至少位于第二显示区，且第一导电图案与栅线或公共电极中的一个电连接；多个第二导电图案，位于第二显示区且与交界处的数据线电连接；其中，部分第一导电图案在衬底上的正投影与第二导电图案在衬底上的正投影存在交叠。该显示面板的交界处数据线与其它数据线的负载一致性高，显示效果好。

Description

显示面板、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、显示装置。
背景技术
对于Z-反转技术的显示产品，为了实现极致窄边框的效果，将设置在显示区中靠近周边区的Dummy Pixel取消，这样，相较于显示区中其它的数据线，对于显示区中靠近周边区的数据线上，只有连接一半的晶体管，只设置有单侧的像素电极和公共电极，这样，导致该数据线与显示区中其它数据线的电容负载差异较大，从而造成该数据线与其它数据线的充电率差异较大，严重降低显示效果。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请至少一个实施例提供一种显示面板，包括：第一显示区和至少一个第二显示区，所述第二显示区位于所述第一显示区的一侧；所述显示面板还包括：
衬底；
位于所述衬底上阵列排布的多个子像素；各所述子像素均位于所述第一显示区；所述子像素包括公共电极；
位于所述衬底上的多条栅线和多条数据线，所述栅线和所述数据线相交且绝缘，所述子像素位于所述栅线和所述数据线限定的位置处；至少一条所述数据线位于所述第一显示区和所述第二显示区的交界处；
多个第一导电图案，所述第一导电图案至少位于所述第二显示区，且所述第一导电图案与所述栅线或所述公共电极中的一个电连接；
多个第二导电图案，位于所述第二显示区且与所述交界处的所述数据线电连接；其中，部分所述第一导电图案在所述衬底上的正投影与所述第二导电图案在所述衬底上的正投影存在交叠。
在本申请一实施例提供的显示面板中，所述多个第一导电图案包括第一部分；
第一部分所述第一导电图案位于所述第二显示区，且与所述栅线电连接；所述第二导电图案在所述衬底上的正投影位于第一部分所述第一导电图案在所述衬底上的正投影以内。
在本申请一实施例提供的显示面板中，所述多个第一导电图案包括第二部分；
第二部分所述第一导电图案从所述第一显示区延伸至所述第二显示区，且与所述公共电极电连接；第二部分所述第一导电图案在所述衬底上的正投影与所述交界处的所述数据线在所述衬底上的正投影存在交叠。
在本申请一实施例提供的显示面板中，所述第二导电图案在所述衬底上的正投影的外轮廓位于第一部分所述第一导电图案在所述衬底上的正投影的外轮廓以内。
在本申请一实施例提供的显示面板中，所述第二显示区包括多个第一虚拟电容，第一部分所述第一导电图案作为所述第一虚拟电容的第一电极，所述第二导电图案作为所述第一虚拟电容的第二电极。
在本申请一实施例提供的显示面板中，所述第二显示区包括多个虚拟晶体管，所述虚拟晶体管的栅极与所述栅线电连接，所述虚拟晶体管的第一端与所述交界处的所述数据线电连接，所述虚拟晶体管的第二端孤立设置。
在本申请一实施例提供的显示面板中，第一部分所述第一导电图案的部分区域作为所述虚拟晶体管的栅极；
至少部分所述第二导电图案包括第一导电部和第二导电部，所述第一导电部和所述第二导电部断开设置，所述第一导电部作为所述虚拟晶体管的第一端，所述第二导电部作为所述虚拟晶体管的第二端。
在本申请一实施例提供的显示面板中，所述虚拟晶体管的数量小于或等于所述子像素行数的一半。
在本申请一实施例提供的显示面板中，各所述栅线将所述交界处的所述数据线划分为多个数据线段；所述第一显示区包括多个晶体管，部分所述数据线段与所述晶体管电连接，未连接所述晶体管的所述数据线 段中的至少一部分与所述虚拟晶体管电连接。
在本申请一实施例提供的显示面板中，所述虚拟晶体管的数量等于所述子像素行数的一半，未连接所述晶体管的所述数据线段均与所述虚拟晶体管电连接，且所述晶体管电连接的所述数据线段和所述虚拟晶体管电连接的所述数据线段间隔设置。
在本申请一实施例提供的显示面板中，第二部分所述第一导电图案与所述公共电极为一体化结构。
在本申请一实施例提供的显示面板中，所述显示面板包括多个第二虚拟电容，第二部分所述第一导电图案作为所述第二虚拟电容的第一电极，所述交界处的所述数据线的部分线段作为所述第二虚拟电容的第二电极；
其中，第二部分所述第一导电图案位于所述第二显示区的部分在所述衬底上的正投影面积大于第二部分所述第一导电图案位于所述第一显示区的部分在所述衬底上的正投影面积。
在本申请一实施例提供的显示面板中，第二部分所述第一导电图案在所述衬底上的正投影图形包括多边形、弧形或者多边形与弧形的组合。
在本申请一实施例提供的显示面板中，第二部分所述第一导电图案在所述衬底上的正投影图形包括相对设置的第一边和第二边，所述第一边和所述第二边的延伸方向相同，所述第一边位于所述第二显示区，所述第二边位于所述第一显示区，所述第一边沿其延伸方向上的长度大于或等于所述第二边沿其延伸方向上的长度。
在本申请一实施例提供的显示面板中，沿垂直于衬底所在的平面的方向上，第二部分所述第一导电图案到所述交界处的所述数据线之间的距离为第一距离；
第二部分所述第一导电图案在所述衬底上的正投影图形包括直角梯形，所述直角梯形的上底与下底的尺寸的差值与所述第一距离成正比。
在本申请一实施例提供的显示面板中，沿垂直于衬底所在的平面的方向上，第二部分所述第一导电图案到所述交界处的所述数据线之间的距离为第一距离；
第二部分所述第一导电图案在所述衬底上的正投影图形包括矩形与第一图形的组合，所述第一图形包括多个直角梯形，且各所述直角梯形的直角边与所述矩形接触；各所述直角梯形的上底与下底的尺寸之和与所述第一距离成正比。
在本申请一实施例提供的显示面板中，第二部分所述第一导电图案在所述衬底上的正投影图形包括相连的第二图形和第三图形的组合，所述第二图形包括切角矩形，所述第三图形包括多边形、弧形或多边形与弧形的组合；
其中，所述第二图形从所述第一显示区延伸至所述第二显示区，所述第三图形位于所述第二显示区，且第二部分所述第一导电图案中正投影为所述第三图形的部分与所述显示面板的公共电极线直接接触，所述切角矩形的切角位于所述第二显示区。
在本申请一实施例提供的显示面板中，第二部分所述第一导电图案在所述衬底上的正投影图形的顶角包括圆角。
在本申请一实施例提供的显示面板中，所述第二虚拟电容的数量大于或等于所述子像素行数的一半。
在本申请一实施例提供的显示面板中，各所述栅线将所述交界处的所述数据线划分为多个数据线段；至少部分所述数据线段在所述衬底上的正投影与第二部分所述第一导电图案在所述衬底上的正投影交叠。
在本申请一实施例提供的显示面板中，所述第二虚拟电容的数量等于所述子像素行数，各所述数据线段在所述衬底上的正投影均与第二部分所述第一导电图案在所述衬底上的正投影交叠。
在本申请一实施例提供的显示面板中，所述第二虚拟电容的数量等于所述子像素行数的一半，一半所述数据线段在所述衬底上的正投影与第二部分所述第一导电图案在所述衬底上的正投影交叠。
在本申请一实施例提供的显示面板中，各所述数据线段包括第一组和第二组，第一组所述数据线段在所述衬底上的正投影与第二部分所述第一导电图案在所述衬底上的正投影存在交叠，第二组所述数据线段在所述衬底上的正投影与第二部分所述第一导电图案在所述衬底上的正 投影互不交叠；其中，第一组所述数据线段与第二组所述数据线段间隔设置。
在本申请一实施例提供的显示面板中，所述交界处的所述数据线与所述第一显示区中的所述数据线之间存在电容负载差异，一个所述第二虚拟电容被配置为能够补偿两个所述数据线段的电容负载差异。
在本申请一实施例提供的显示面板中，所述显示面板还包括第三导电图案，所述第三导电图案与所述公共电极电连接，所述第三导电图案至少位于所述第二显示区，且所述第三导电图案的至少部分区域位于第一部分所述第一导电图案与所述交界处的所述数据线之间；
其中，所述第三导电图案的至少部分区域在所述衬底上的正投影与所述交界处的所述数据线在所述衬底上的正投影互不交叠。
在本申请一实施例提供的显示面板中，所述显示面板还包括第三虚拟电容，所述第三导电图案作为所述第三虚拟电容的第一电极且与所述公共电极电连接，所述交界处的所述数据线的部分线段作为所述第三虚拟电容的第二电极。
在本申请一实施例提供的显示面板中，所述第三导电图案在所述衬底上的正投影与所述交界处的所述数据线在所述衬底上的正投影互不交叠。
在本申请一实施例提供的显示面板中，同一行所述子像素连接同一条所述栅线；
每相邻两条所述数据线之间设置有一列所述子像素，同一列所述子像素包括第一类和第二类，任意一个第一类所述子像素位于两个第二类所述子像素之间，其中，同一列所述子像素中的第一类与一条所述数据线电连接，同一列所述子像素中的第二类与另一条所述数据线电连接。
在本申请一实施例提供的显示面板中，多条栅线将位于所述第一显示区的所述数据线也划分为多个数据线段，各所述数据线段中，部分所述数据线段包括支撑部、第一连接部和第二连接部，所述支撑部位于所述第一连接部和所述第二连接部之间；
其中，所述支撑部沿垂直于所述数据线段延伸方向上的尺寸大于所 述第一连接部沿垂直于所述数据线段延伸方向上的尺寸，所述支撑部沿垂直于所述数据线段延伸方向上的尺寸大于所述第二连接部沿垂直于所述数据线段延伸方向上的尺寸。
在本申请一实施例提供的显示面板中，所述显示面板还包括隔垫物和保护部，所述隔垫物位于部分所述支撑部远离所述衬底的一侧，所述保护部位于各所述支撑部的至少一侧；所述保护部在沿垂直于所述衬底所在平面上的高度大于所述支撑部在沿垂直于所述衬底所在平面上的高度。
第二方面，本申请的实施例提供了一种显示装置，包括第一方面中所述的显示面板。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述内容和其目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1和图3为本申请实施例提供的两种相关技术中的显示面板的结构示意图；
图2为图3所示的显示面板的数据线上的电容负载分布示意图；
图4-图12为本申请实施例提供的九种显示面板的局部平面结构示意图；
图13-图20为本申请的实施例提供的八种第二虚拟电容的平面结构示意图；
图21为本申请的实施例提供的一种数据线的对位偏差对电容负载的影响分析曲线；
图22-图23为本申请的实施例又提供的两种第二虚拟电容的平面结构示意图；
图24-图27为本申请实施例又提供的四种显示面板的局部平面结构示意图；
图28为本申请的实施例提供的一种Z反转技术的显示面板的结构示意图；
图29为本申请的实施例提供的一种显示面板的平面设计版图；
图30为本申请的实施例提供的一种显示面板的第一显示区中的结构示意图；
图31和图32为本申请的实施例又提供的两种显示面板的局部平面结构示意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本申请的示意性图解，并非一定是按比例绘制。
在本申请的实施例中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的结构或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特 征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
本申请实施例中使用的“平行”、“垂直”以及“相同”等特征均包括严格意义的“平行”、“垂直”、“相同”等特征，以及“大致平行”、“大致垂直”、“大致相同”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(例如，测量***的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。例如，“大致”能够表示在一个或多个标准偏差内，或者在所述值的10％或者5％内。“至少一个”指一个或多个，“多个”指至少两个。
本申请实施例中的“同层”指同一材料在经过同一步骤(例如一步图案化工艺)后形成的多个膜层之间的关系。这里的“同层”并不总是指多个膜层的厚度相同或者多个膜层在截面图中的高度相同。本说明书中多边形并非严格意义上的，可以是近似的三角形、平行四边形、梯形、五边形或六边形等，可以存在公差导致的一些小变形。
随着显示技术的不断发展，人们对于显示品质的追求也越来越高。对于Z反转(Z-Inversion)技术的显示产品，为了进一步降低该类显示产品的边框尺寸，实现极致窄边框的产品目标，将如图1所示的显示面板中第一条数据线与最后一条数据线外侧的Dummy子像素(Dummy Pixel)取消，得到如图3所示的显示面板，需要说明的是，上述外侧指的是显示面板中靠近周边区的一侧，Dummy子像素在实际中并不能显示。
另外，在实际应用中，由于Z反转技术的显示产品的特殊设计，第一条数据线与最后一条数据线相较于其他数据线的电容负载不一致，通 过设计Dummy子像素能够使得该两条数据线与其它数据线的电容负载趋于一致，从而避免RC信号延迟(RC Delay)差异造成的充电率差异，避免充电率差异造成的显示亮度不均的问题。
然而，为了进一步降低该类显示产品的边框尺寸，取消第一条数据线与最后一条数据线外侧的Dummy子像素之后，电容负载差异变大；具体的，如图2所示，提供了一种Z反转类显示产品子像素中的电容分布示意图；其中，左侧为显示区中正常的数据线，右侧为显示区中第一条或最后一条数据线；由于左侧的数据线的两侧均设置有子像素，而右侧的数据线只有一侧设置有子像素，则右侧的数据线缺少数据线本身与一个子像素中晶体管的栅极之间的侧向电容、缺少晶体管的栅极与源漏极之间的交叠电容(如虚线框中标记的Cgd-lateral)，还缺少数据线与一个子像素的公共电极之间的侧向电容(如虚线框中标记的Cdc-lateral)，还缺少一个子像素的像素电极与数据线之间的侧向电容(如虚线框中标记的Cpd-lateral)。电容负载差异变大造成两种数据线的充电率差异变大，显示亮度不均的问题仍旧存在，目前，窄边框与显示亮度均一难以同时兼顾。
对此，本申请的实施例提供了一种显示面板、显示装置。该显示面板包括：第一显示区和至少一个第二显示区，第二显示区位于第一显示区的一侧；显示面板还包括：衬底；位于衬底上阵列排布的多个子像素；各子像素均位于第一显示区，子像素包括公共电极；位于衬底上的多条栅线和多条数据线，栅线和数据线相交且绝缘，子像素位于栅线和数据线限定的位置处；至少一条数据线位于第一显示区和第二显示区的交界处；多个第一导电图案，第一导电图案至少位于第二显示区，且第一导电图案与栅线或公共电极中的一个电连接；多个第二导电图案，位于第二显示区且与交界处的数据线电连接；其中，部分第一导电图案在衬底上的正投影与第二导电图案在衬底上的正投影存在交叠。这样，通过设置部分第一导电图案与第二导电图案的投影交叠，形成交叠电容，且第二导电图案与交界处的数据线电连接，从而增加了交界处数据线的电容负载，提高交界处数据线与其它数据线的负载一致性，在降低边框尺寸 的同时，避免了RC信号延迟(RC Delay)差异造成的充电率差异，避免充电率差异造成的显示亮度不均的问题，兼顾了窄边框和较高的显示效果。
下面，结合附图对本申请实施例提供的显示面板和显示装置进行详细的说明。
本申请至少一个实施例提供一种显示面板。图4、图5、图6和图7分别为本申请的实施例提供的四种显示面板的平面示意图。需要说明的是，图4、图5、图6和图7并未示出整个显示面板，而仅仅示意出显示面板的局部。本申请的实施例并未示出显示面板的层结构的剖面示意图，未示出的层结构可参见相关技术。
如图4、图5、图6或图7所示，该显示面板包括：第一显示区AA1和至少一个第二显示区AA2，第二显示区AA2位于第一显示区AA1的一侧；显示面板还包括：
衬底；
位于衬底上阵列排布的多个子像素；各子像素均位于第一显示区AA1；子像素包括公共电极1；
位于衬底上的多条栅线GL和多条数据线DL，栅线GL和数据线DL相交且绝缘，子像素位于栅线GL和数据线DL限定的位置处；至少一条数据线DL位于第一显示区AA1和第二显示区AA2的交界处；
多个第一导电图案2，第一导电图案2至少位于第二显示区AA2，且第一导电图案2与栅线GL或公共电极1中的一个电连接；
多个第二导电图案3，位于第二显示区AA2且与交界处的数据线DL电连接；其中，部分第一导电图案2在衬底上的正投影与第二导电图案3在衬底上的正投影存在交叠。
在示例性的实施例中，上述显示面板可以为液晶显示面板(Liquid Crystal Display，LCD)，示例性的，液晶显示面板可以包括扭曲向列(Twisted Nematic，TN)型、垂直配向(Vertical Alignment，VA)型、平面转换(In Plane Switching，IPS)型和高级超维场开关(ADS，Advanced Super Dimension Switch)型。
液晶显示面板可以包括阵列基板和彩膜基板，液晶层LC位于阵列基板和彩膜基板之间，阵列基板和彩膜基板分别包括衬底，其中，本申请的实施例中提到的衬底均指的是阵列基板中的衬底。
这里对于上述显示面板的阵列基板和彩膜基板中包括的结构和部件不进行限定，具体可以根据产品的设计决定。
在本申请的一些实施例中，显示面板包括显示区AA和围绕所述显示区AA的周边区，显示区AA包括第一显示区AA1和至少一个第二显示区AA2，其中，第一显示区AA1中包括子像素，第二显示区AA2中不包括子像素，第一显示区AA1中各子像素通过数据线DL充电并进行显示，第二显示区AA2中的结构辅助改善数据线DL的充电率，使得位于第一显示区AA1和第二显示区AA2交界处的数据线DL的充电率与第一显示区AA1中的数据线的充电率趋于一致。
在本申请的一些实施例中，显示区AA可以包括一个第一显示区AA1和一个第二显示区AA2，第二显示区AA2位于第一显示区AA1的一侧。此时，有一条数据线DL位于第一显示区AA1和第二显示区AA2交界处。
在本申请的另一些实施例中，显示区AA可以包括一个第一显示区AA1和两个第二显示区AA2，两个第二显示区AA2分别位于第一显示区AA1相对的两侧，此时，有两条数据线DL分别位于第一显示区AA1和第二显示区AA2的两个交界处。
在本申请的一些实施例中，可以取消如图1中所示的一侧的Dummy子像素，设置本申请的实施例中提供的第二显示区AA2中的结构；在另一些实施例中，可以取消如图1中所示的两侧的Dummy子像素，并在两侧均设置本申请的实施例中提供的第二显示区AA2中的结构。
这里对于上述衬底的具体材料不进行限定。示例性的，上述衬底可以为硅、玻璃、石英、PET、塑料等材料中的任意一种。
这里对于上述子像素的排布方式不进行限定。具体可以根据实际产品的设计确定。
示例性的，上述子像素可以包括三种颜色的子像素，例如，红色子 像素、绿色子像素和蓝色子像素。
在一些实施例中，相同颜色的子像素位于同一排。例如，多个红色子像素位于同一行，多个绿色子像素位于同一行，多个蓝色子像素位于同一行；再例如，多个红色子像素位于同一列，多个绿色子像素位于同一列，多个蓝色子像素位于同一列。
在另一些实施例中，同一排子像素中包括至少两种颜色的子像素。例如，同一排子像素中可以包括两种颜色的子像素，或者，同一排子像素中可以包括三种颜色的子像素。
这里对于上述子像素在衬底上的正投影图形的形状不进行限定。一般的，子像素在衬底上的正投影图形的形状大致为矩形、平行四边形、六边形。
这里对于上述显示面板包括的栅线GL和数据线DL的具体结构不进行限定。
示例性的，上述栅线GL可以包括直线段，或者包括多条直线段形成的弯折结构；具体可以根据实际设计确定。
示例性的，上述数据线DL可以包括直线段，或者包括多条直线段形成的弯折结构，具体可以根据实际设计确定。
这里对于上述栅线GL和数据线DL的具体材料不进行限定。
示例性的，栅线GL的材料可以包括铜，例如可以通过溅射的方式形成例如MoNb/Cu/MoNb的叠层结构，其中，靠近衬底的一侧材料为MoNb，厚度大约在
Figure PCTCN2022122820-appb-000001
左右，主要用于提高膜层间的粘附力，叠层结构的中间层材料为Cu，为电信号传递通道的材料，远离衬底1一侧的材料为MoNb，厚度大约在
Figure PCTCN2022122820-appb-000002
左右，可以用于保护中间层，防止电阻率低的中间层表面暴露发生氧化。由于单次溅射的厚度一般不超过1μm，因此在制作超过厚度1μm的栅线GL时，需要多次溅射来形成。此外，还可以通过电镀的方式形成，具体地，可以先利用MoNiTi形成种子层，以提高后续电镀工艺中金属晶粒的成核密度，之后再通过电镀制作电阻率低的铜，之后再制作防氧化层，材料可以为MoNiTi。
示例性的，数据线DL的材料可以和栅线GL的材料相同。
这里对于第一导电图案2在显示面板中具体的层结构的位置以及具体的材料均不进行限定。
在示例性的实施例中，以显示面板为液晶显示面板(Liquid Crystal Display，LCD)为例，液晶显示面板中包括位于衬底上的第一透光导电层(例如1ITO层)、栅极层(Gate层)、源漏金属层(SD层)和第二透光导电层(例如2ITO层)；
第一透光导电层(例如1ITO层)可以和栅极层(Gate层)直接接触，例如，第一透光导电层(例如1ITO层)可以位于衬底和栅极层(Gate层)之间并与栅极层(Gate层)直接接触；再例如，栅极层(Gate层)可以位于衬底和第一透光导电层(例如1ITO层)之间并与栅极层(Gate层)直接接触；另外，栅极层(Gate层)、源漏金属层(SD层)和第二透光导电层(例如2ITO层)沿背离衬底的方向依次设置，且栅极层(Gate层)和源漏金属层(SD层)之间、源漏金属层(SD层)和第二透光导电层(例如2ITO层)之间均设置有绝缘材料。栅线GL位于栅极层(Gate层)，数据线DL位于源漏金属层(SD层)，在一些实施例中，为了提高栅线GL的导电率，可以在栅线GL下设置辅助走线，该辅助走线可以位于第一透光导电层(例如1ITO层)，且栅线GL在衬底上的正投影位于辅助走线在衬底上的正投影以内。本申请的实施例提供的附图中以在栅线GL下方设置辅助走线为例进行绘制。
其中，在一些实施例中，如图4-图7中标记2/21的位置处所示，第一导电图案2位于第二显示区AA中，第一导电图案2可以设置在栅极层(Gate层)上，且该第一导电图案2与第一显示区AA1中的栅线GL电连接。在实际应用中，此处的第一导电图案2可以和栅线GL为一体化结构。
在另一些实施例中，如图4-图7中标记2/22的位置处所示，第一导电图案2的部分区域位于第一显示区AA1中，第一导电图案2的部分区域位于第二显示区AA2中，此时，第一导电图案2可以设置在第一透光导电层(例如1ITO层)中，且该第一导电图案2与第一显示区AA1中子像素的公共电极1电连接，在实际应用中，此处的第一导电 图案2可以和公共电极1为一体化结构。
在实际应用中，可以根据第一导电图案2在显示面板中具体的层结构的位置确定其材料。
示例性的，当第一导电图案2位于栅极层(Gate层)时，第一导电图案2的材料可以与栅极层的材料相同，例如，包括铜(Cu)。
示例性的，当第一导电图案2位于第一透光导电层时，第一导电图案2的材料可以与第一透光导电层的材料相同，例如，包括氧化铟锡(ITO)。需要说明的是，在本申请的实施例提供的附图中，以第一透光导电层和第二透光导电层的材料均为氧化铟锡为例进行绘制。
在示例性的实施例中，第二导电图案3可以位于源漏金属层(SD层)中。
这里对于上述第二导电图案3在衬底上的正投影图形的形状不进行限定。
在一些实施例中，上述第二导电图案3在衬底上的正投影图形的形状可以设计为如图6或如图7所示的矩形，以使得第二导电图案3与第一导电图案2/21可以形成交叠电容，模拟被取消的Dummy子像素中的晶体管的栅极和源漏极所在膜层之间形成的交叠电容。
在另一些实施例中，上述第二导电图案3在衬底上的正投影图形的形状可以设计成与晶体管的源极和漏极相似的结构，当然，这里采用第二导电图案3设计的类似于晶体管的源极和漏极的结构可以与第一显示区AA1中的晶体管的实际结构不完全一致。
在另一些实施例中，如图4和如图5所示，上述第二导电图案3在衬底上的正投影图形的形状可以设计成和如图30中所示的第一显示区AA1中的晶体管的结构相同的形状，以使得第二导电图案3与第一导电图案2/21可以形成虚拟的晶体管，使得交界处的数据线DL的电容负载尽可能趋向于第一显示区AA1中的数据线DL的电容负载。
其中，部分第一导电图案在衬底上的正投影与第二导电图案在衬底上的正投影存在交叠包括但不限于如下情况：
第一、部分第一导电图案2在衬底上的正投影与第二导电图案3在 衬底上的正投影部分交叠。
第二、部分第一导电图案2在衬底上的正投影的外轮廓与第二导电图案3在衬底上的正投影的外轮廓重叠。
其中，这里部分第一导电图案2指的是完全位于第二显示区AA2中的、且设置在栅极层中的第一导电图案2/21。
在相关技术中，以图3所示的显示面板为例，在未设置电容补偿之前，第一条数据线DL1和第七条数据线DL7上的电容为258pF，第二条数据线DL2到第六条数据线DL6上的电容为410pF，电容负载相差较多，这样，第一条数据线DL1和第七条数据线DL7上的充电率也比其它数据线上的充电率大很多，导致与第一条数据线DL1和第七条数据线DL7电连接的子像素的亮度大于其它数据线电连接的子像素的亮度，从而出现亮度不均的问题。
本申请的实施例提供的显示面板，通过设置部分第一导电图案2与第二导电图案3的投影交叠，形成交叠电容，且第二导电图案3与交界处的数据线电连接，从而增加了交界处数据线的电容负载，提高交界处数据线与其它数据线的负载一致性，在降低边框尺寸的同时，避免了RC信号延迟(RC Delay)差异造成的充电率差异，避免充电率差异造成的显示亮度不均的问题，兼顾了窄边框和较高的显示效果。
另外，通过在第二显示区AA2中第一导电图案2与第二导电图案3，且设置部分第一导电图案2与第二导电图案3的投影交叠，形成交叠电容，替代了相关技术中的Dummy子像素，结合图29所示，第二显示区AA2中的结构的尺寸远小于子像素的尺寸，很大程度上降低了显示面板的边框尺寸，还确保了较好的显示效果。
在本申请一实施例提供的显示面板中，如图4-图7所示，多个第一导电图案2包括第一部分2/21；
第一部分第一导电图案2/21位于第二显示区AA2，且与栅线GL电连接；第二导电图案3在衬底上的正投影位于第一部分第一导电图案2/21在衬底上的正投影以内。
其中，第二导电图案3在衬底上的正投影位于第一部分第一导电图 案2/21在衬底上的正投影以内包括但不限于以下情况：
第一、第二导电图案3在衬底上的正投影的外轮廓位于第一部分第一导电图案2/21在衬底上的正投影的外轮廓以内；
第二、第二导电图案3在衬底上的正投影的外轮廓与第一部分第一导电图案2/21在衬底上的正投影的外轮廓重叠。
在本申请一实施例提供的显示面板中，如图4-图7所示，多个第一导电图案2包括第二部分2/22；
第二部分第一导电图案2/22从第一显示区AA1延伸至第二显示区AA2，且与公共电极1电连接；第二部分第一导电图案2/22在衬底上的正投影与交界处的数据线DL在衬底上的正投影存在交叠。
在本申请一实施例提供的显示面板中，如图4-图7所示，第二导电图案3在衬底上的正投影的外轮廓位于第一部分第一导电图案2/21在衬底上的正投影的外轮廓以内。
在本申请一实施例提供的显示面板中，如图6和图7所示，第二显示区AA2包括多个第一虚拟电容Dummy C1，第一部分第一导电图案2/21作为第一虚拟电容Dummy C1的第一电极，第二导电图案3/32作为第一虚拟电容Dummy C1的第二电极。
在本申请的实施例中，通过设置部分第一导电图案2与第二导电图案3的投影交叠，形成多个第一虚拟电容Dummy C1，且第二导电图案3与交界处的数据线电连接，从而增加了交界处数据线的电容负载，提高交界处数据线与其它数据线的负载一致性，在降低边框尺寸的同时，避免了RC信号延迟(RC Delay)差异造成的充电率差异，避免充电率差异造成的显示亮度不均的问题，兼顾了窄边框和较高的显示效果。
在本申请一实施例提供的显示面板中，如图4和图5所示，第二显示区包括多个虚拟晶体管Dummy TFT，虚拟晶体管Dummy TFT的栅极与栅线GL电连接，虚拟晶体管Dummy TFT的第一端与交界处的数据线DL电连接，虚拟晶体管Dummy TFT的第二端孤立设置。
上述孤立设置指的是虚拟晶体管Dummy TFT的第二端为一个导电岛结构，且该导电岛结构与其它导电结构均不电连接。
需要说明的是，上述第一端可以为源极，上述第二端可以为漏极；或者，上述第一端可以为漏极，上述第二端可以为源极。后文中关于虚拟晶体管Dummy TFT或者晶体管的第一端和第二端的描述与此处的含义类似，不再赘述。
在一些实施例中，为了简化设计，降低制备工艺复杂度，上述虚拟晶体管Dummy TFT中可以不设置有源层(Active layer)。
在另一些实施例中，为了更贴近于第一显示区AA1中晶体管的设计，使得位于第一显示区AA1和第二显示区AA2交界处的数据线DL的电容负载趋近于位于第一显示区AA1中的数据线DL的电容负载，上述虚拟晶体管Dummy TFT中可以设置有源层(Active layer)。
进一步的，可以设计虚拟晶体管Dummy TFT的结构和尺寸与第一显示区AA1中晶体管的结构和尺寸相同。
在本申请一实施例提供的显示面板中，可以在局部区域设置有如图6和图7所示的多个第一虚拟电容Dummy C1，在局部区域设置有如图4和图5所示的虚拟晶体管Dummy TFT。
在本申请一实施例提供的显示面板中，第一部分第一导电图案2/21的部分区域作为虚拟晶体管Dummy TFT的栅极；
至少部分第二导电图案3包括第一导电部311和第二导电部312，第一导电部311和第二导电部312断开设置，第一导电部311作为虚拟晶体管Dummy TFT的第一端，第二导电部312作为虚拟晶体管Dummy TFT的第二端。
在示例性的实施例中，如图5所示，虚拟晶体管Dummy TFT的第一端的平面图形为“M”形，虚拟晶体管Dummy TFT的第二端的平面图形包括两部分，且这两部分互不连接。
在实际应用中，位于第一显示区AA1中的晶体管的结构可以和该虚拟晶体管Dummy TFT的结构相同，然而第一显示区AA1中的晶体管的第二端的两部分可以电连接在一起并与其它导电结构连接。
需要说明的是，在本申请的实施例中，用Dummy TFT代表虚拟晶体管，并不是限定该虚拟晶体管为薄膜晶体管(Thin Film Transistor， TFT)，其还可以为金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)，本申请的实施例和附图中均以虚拟晶体管为薄膜晶体管为例进行说明。
这里对于上述位于第二显示区AA2中的虚拟晶体管Dummy TFT和位于第一显示区AA1中的子像素的晶体管的类型是否相同不进行限定。
在实际应用中，一方面，为了降低制备工艺难度，另一方面，为了使得交界处的数据线的电容负载更趋近于第二显示区AA2中的数据线的电容负载，可以设置上述虚拟晶体管Dummy TFT和第一显示区AA1中的子像素的晶体管的类型相同。
其中，至少部分第二导电图案3包括第一导电部311和第二导电部312包括但不限于如下情况：
第一、部分第二导电图案3包括如图4和如图5所示的第一导电部311和第二导电部312，且第一导电部311和第二导电部312断开设置；部分第二导电图案3包括如图6和如图7所示的一体化图案。
第二、所有第二导电图案3均包括如图4和如图5所示的第一导电部311和第二导电部312，且第一导电部311和第二导电部312断开设置。
在本申请的实施例提供想显示面板中，通过在第二显示区AA2中设置虚拟晶体管Dummy TFT，并使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL与该虚拟晶体管Dummy TFT的第一端电连接，这样，该虚拟晶体管与交界处的数据线DL能够尽可能的模拟出第一显示区AA1中的数据线DL与晶体管的电容负载，从而使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL的电容负载与位于第一显示区AA1中的数据线DL的电容负载趋于一致，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，虚拟晶体管Dummy TFT的 数量小于或等于子像素行数的一半。
在示例性的实施例中，虚拟晶体管Dummy TFT的数量等于子像素行数的一半。
在示例性的实施例中，虚拟晶体管的数量Dummy TFT小于子像素行数的一半。
在本申请的实施例提供的显示面板中，如图3所示，位于第一显示区AA1与第二显示区AA2的交界处的数据线DL(DL1或DL7)的部分区域与位于第一显示区AA1中的晶体管电连接，位于第一显示区AA1与第二显示区AA2的交界处的数据线DL(DL1或DL7)的部分区域未连接第一显示区AA1中的晶体管，这样，对于交界处的数据线DL未连接第一显示区AA1中的晶体管的部分线段，可以设置虚拟晶体管Dummy TFT与其电连接。
在实际应用中，在Z反转类显示面板的位于第一显示区AA1与第二显示区AA2的交界处的数据线DL(DL1或DL7)中，与其相邻的一列子像素中有一半的晶体管与其电连接，故而，最多可以设置一列子像素的总数量一半的虚拟晶体管Dummy TFT与交界处的数据线DL电连接。其中，一列子像素的总数量即为子像素的行数。
在本申请一实施例提供的显示面板中，各栅线GL将交界处的数据线DL划分为多个数据线段；第一显示区AA1包括多个晶体管，部分数据线段与晶体管电连接，未连接晶体管的数据线段中的至少一部分与虚拟晶体管Dummy TFT电连接。
需要说明的是，在实际应用中，交界处的数据线DL为一条连续的走线，在本说明书中，为了便于描述发明点，将一条数据线DL看作多个数据线段连接而成。
在示例性的实施例中，未连接晶体管的数据线段中的至少一部分与虚拟晶体管Dummy TFT电连接包括但不限于如下情况：
第一、未连接晶体管的数据线段中的一部分数据线段与虚拟晶体管Dummy TFT电连接；
第二、所有未连接晶体管的数据线段均与虚拟晶体管Dummy TFT 电连接。
在本申请的一些实施例中，如图29所示，各栅线GL将交界处的数据线DL划分为多个数据线段，例如数据线段DL-J1、数据线段DL-J2、数据线段DL-J3、数据线段DL-J4，其中，数据线段DL-J1和第一显示区AA1中的晶体管电连接，数据线段DL-J3和第一显示区AA1中的晶体管电连接；数据线段DL-J2和数据线段DL-J4均未与第一显示区AA1中的晶体管电连接，然而，数据线段DL-J2与第二显示区AA2中的虚拟晶体管Dummy TFT电连接在一起。
这样，数据线段DL-J2的电容负载就趋近于第一显示区AA1中的数据线段DL-2的电容负载，交界处的数据线DL的电容负载就趋近于第一显示区AA1中的数据线DL的电容负载，从而使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL的电容负载与位于第一显示区AA1中的数据线DL的电容负载趋于一致，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，如图11所示，虚拟晶体管Dummy TFT的数量等于子像素行数的一半，未连接晶体管的数据线段均与虚拟晶体管Dummy TFT电连接，且晶体管电连接的数据线段和虚拟晶体管电连接的数据线段间隔设置。
这样，交界处数据线DL的各数据线段的电容负载就趋近于第一显示区AA1中数据线DL的各数据线段的电容负载，交界处的数据线DL整体的电容负载就趋近于第一显示区AA1中的数据线DL整体的电容负载，从而使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL的电容负载与位于第一显示区AA1中的数据线DL的电容负载趋于一致，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
上述间隔设置指的是：对于交界处的数据线DL的每个数据线段， 任意相邻两个数据线段中的其中一个与第一显示区AA1中的晶体管电连接，另一个与第二显示区AA2中的虚拟晶体管Dummy TFT电连接。其中，相邻指的是两个数据线段之间没有其它数据线段。
在本申请的一些实施例中，如图11所示，各栅线GL将交界处的数据线DL划分为多个数据线段；第一显示区AA1包括多个晶体管，部分数据线段与晶体管电连接，未连接晶体管的数据线段中的至少一部分与第一虚拟电容Dummy C1电连接。
其中，未连接晶体管的数据线段中的至少一部分与第一虚拟电容Dummy C1电连接包括但不限于如下情况：
第一、未连接晶体管的数据线段中的一部分数据线段与第一虚拟电容Dummy C1电连接。
第二、所有未连接晶体管的数据线段均与第一虚拟电容Dummy C1电连接。
在本申请的一些实施例中，各栅线GL将交界处的数据线DL划分为多个数据线段；第一显示区AA1包括多个晶体管，部分数据线段与晶体管电连接，未连接晶体管的数据线段中的一部分与第一虚拟电容Dummy C1电连接，未连接晶体管的数据线段中的一部分与虚拟晶体管Dummy TFT电连接。
其中，未连接晶体管的数据线段的数量大于或等于第一虚拟电容Dummy C1与虚拟晶体管Dummy TFT的数量之和。
示例性的，未连接晶体管的数据线段的数量等于第一虚拟电容Dummy C1与虚拟晶体管Dummy TFT的数量之和。
在一些实施例中，可以设置虚拟晶体管Dummy TFT的数量大于或等于第一虚拟电容Dummy C1的数量。这样，虚拟晶体管Dummy TFT的栅极与源漏极之间形成的交叠电容更趋近于第一显示区AA1中的晶体管的栅极与源漏极之间的交叠电容，从而使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL的电容负载与位于第一显示区AA1中的数据线DL的电容负载趋于一致，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小 了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，如图4、图6和图7所示，第二部分第一导电图案2/22与公共电极1为一体化结构。
其中，一体化结构的含义为：采用相同的材料，在一次构图工艺中制备形成，一次构图工艺指的是包括掩膜、成膜、刻蚀等工艺。
在本申请一实施例提供的显示面板中，如图4-图10所示，显示面板包括多个第二虚拟电容Dummy C2，第二部分第一导电图案2/22作为第二虚拟电容Dummy C2的第一电极且与公共电极1电连接，交界处的数据线DL的部分线段作为第二虚拟电容Dummy C2的第二电极。
在一些实施例中，显示面板包括多个第二虚拟电容Dummy C2，第二部分第一导电图案2/22作为第二虚拟电容Dummy C2的第一电极且与栅线GL电连接，交界处的数据线DL的部分线段作为第二虚拟电容Dummy C2的第二电极。
需要说明的是，第二虚拟电容Dummy C2可以与公共电极电连接，以使得公共电极信号(Com信号)作为第二虚拟电容Dummy C2的一个电极进行补偿；或者，第二虚拟电容Dummy C2可以与栅线GL电连接，以使得栅线GL的信号(Gate信号)作为第二虚拟电容Dummy C2的一个电极进行补偿。
在实际应用中，由于公共电极信号(Com信号)较栅线的信号(Gate信号)更为稳定，故采用第二虚拟电容Dummy C2可以与公共电极电连接，以使得公共电极信号(Com信号)作为第二虚拟电容Dummy C2的一个电极进行补偿。
后文中第三虚拟电容Dummy C3可以选择的补偿信号与第二虚拟电容Dummy C2类似，不再赘述。
在一些实施例中，各栅线GL将交界处的数据线DL划分为多个数据线段；部分数据线段与虚拟晶体管Dummy TFT电连接，另一部分数据线段上设置有第二虚拟电容Dummy C2，即该部分数据线段上的局部区域可以作为第二虚拟电容Dummy C2的第二电极。
在一些实施例中，如图4、图5、图8、图10所示，与虚拟晶体管Dummy TFT电连接的数据线段上未设置第二虚拟电容Dummy C2，未与虚拟晶体管Dummy TFT电连接的数据线段中的至少一部分数据线段上设置有第二虚拟电容Dummy C2。
在一些实施例中，与虚拟晶体管Dummy TFT电连接的数据线段上也可以设置有第二虚拟电容Dummy C2。
在一些实施例中，如图6、图7和图9所示，与第一虚拟电容Dummy C1电连接的数据线段上未设置第二虚拟电容Dummy C2，未与第一虚拟电容Dummy C1电连接的数据线段中的至少一部分数据线段上设置有第二虚拟电容Dummy C2。
在一些实施例中，与第一虚拟电容Dummy C1电连接的数据线段上也可以设置第二虚拟电容Dummy C2。
在一些实施例中，如图4-图10所示，第二虚拟电容Dummy C2的第一电极(第二部分第一导电图案2/22)可以与公共电极线CML(Common Line)直接接触。
需要说明的是，在一些实施例中，公共电极线CML设置在栅极层(Gate层)上。此时，第二虚拟电容Dummy C2的第一电极(第二部分第一导电图案2/22)可以与公共电极线CML(Common Line)直接接触指的是：第二虚拟电容Dummy C2的第一电极(第二部分第一导电图案2/22)与公共电极线CML直接接触。
在另一些实施例中，公共电极线CML包括位于第一透光导电层(例如1ITO)的部分和位于栅极层(Gate层)的另一部分，即公共电极线CML包括两个膜层。此时，第二虚拟电容Dummy C2的第一电极(第二部分第一导电图案2/22)可以与公共电极线CML(Common Line)直接接触指的是：第二虚拟电容Dummy C2的第一电极(第二部分第一导电图案2/22)与公共电极线CML中位于第一透光导电层(例如1ITO)的部分直接接触。
在一些实施例中，第二虚拟电容Dummy C2的第一电极(第二部分第一导电图案2/22)与公共电极线CML(Common Line)之间可以存在 间隙，第二虚拟电容Dummy C2的第一电极(第二部分第一导电图案2/22)通过公共电极1与公共电极线CML电连接。
其中，如图4-图9、图13或图14所示，第二部分第一导电图案2/22位于第二显示区AA2的部分在衬底上的正投影面积S1大于第二部分第一导电图案2/22位于第一显示区AA1的部分在衬底上的正投影面积。
需要说明的是，交叠电容的电容值受到电容的两个电极正对面积的影响，而侧向电容的电容值受电容的两个电极正对面积的影响较小，在实际应用中，数据线DL的实际位置会受到制备工艺的对位偏差的影响，第二虚拟电容Dummy C2处包括交叠电容和侧向电容，因此，第二虚拟电容Dummy C2的整体的电容值也会受到制备工艺的对位偏差的影响而产生波动，为了平衡和降低对位偏差对第二虚拟电容Dummy C2的整体的电容值的影响，本申请的实施例提供一组模拟分析数据。
图21为图22中所示的第二虚拟电容Dummy C2的左侧的侧向电容(第二部分第一导电图案2/22位于第二显示区AA2的部分与数据线DL的局部区域形成的电容)、右侧的侧向电容(第二部分第一导电图案2/22位于第一显示区AA1的部分与数据线DL的局部区域形成的电容)在发生对位偏差后的电容变化。其中，左侧的侧向电容的电容值随着数据线向左侧偏移(第一显示区AA1指向第二显示区AA2的方向偏移)，其电容值逐渐增大；右侧的侧向电容的电容值随着数据线向左侧偏移(第一显示区AA1指向第二显示区AA2的方向偏移)，其电容值逐渐减小。两个侧向电容的电容值之和在临界点M之前较大，在临界点M之后偏小。
为此，本申请的实施例通过设计第二虚拟电容Dummy C2中交叠电容(第二部分第一导电图案2/22与交界处数据线DL投影交叠处)的正对面积(或者叫做交叠面积)，来弥补制备工艺的对位偏差对整体电容值的影响。
由于交界处数据线DL越远离公共电极1，侧向电容的电容值越小；交界处数据线DL越靠近公共电极1，侧向电容的电容值越大；则可以 设计第二虚拟电容Dummy C2中交叠电容越远离公共电极1，其电容值越大，第二虚拟电容Dummy C2中交叠电容越靠近公共电极1，其电容值越下；由于第二虚拟电容Dummy C2中交叠电容的电容值主要取决于交叠面积，交界处数据线DL的结构设计是确定的，则通过设计第二部分第一导电图案2/22的形状和尺寸，使得第二部分第一导电图案2/22位于第二显示区AA2的部分在衬底上的正投影面积S1大于第二部分第一导电图案2/22位于第一显示区AA1的部分在衬底上的正投影面积；这样，即使在制备工艺的对位偏差造成交界处数据线DL位置偏移时，本申请的实施例提供的第二虚拟电容Dummy C2仍然能够提供稳定的电容负载，从而使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL的电容负载与位于第一显示区AA1中的数据线DL的电容负载趋于一致，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，如图13-图20所示，第二部分第一导电图案2/22在衬底上的正投影图形包括多边形、弧形或者多边形与弧形的组合。
示例性的，多边形可以包括三角形、四边形、五边形等；弧形可以包括椭圆、半椭圆、半圆、扇形等；其中，半椭圆、半圆不仅仅代表椭圆或圆形的一半，还可以是椭圆或圆形的一部分。
在本申请一实施例提供的显示面板中，如图15-图20所示，第二部分第一导电图案2/22在衬底上的正投影图形包括相对设置的第一边L1和第二边L2，第一边L1和第二边L2的延伸方向相同，第一边L1位于第二显示区AA2，第二边L1位于第一显示区AA1，第一边L1沿其延伸方向上的长度d1大于或等于第二边L2沿其延伸方向上的长度d2。
在一些实施例中，可以设置第一边L1沿其延伸方向上的长度d1等于第二边L2沿其延伸方向上的长度d2。
在一些实施例中，可以设置第一边L1沿其延伸方向上的长度d1大于第二边L2沿其延伸方向上的长度d2。
示例性的，在第一边L1沿其延伸方向上的长度d1大于第二边L2沿其延伸方向上的长度d2的情况下，第二部分第一导电图案2/22在衬底上的正投影图形可以包括如图15所示的直角梯形、如图16所示的等腰梯形、如图17所示的直角梯形与弧形拼接而成的图形、在直角梯形上挖除一个弧形得到的图形、如图18所示的等腰梯形与两个弧形拼接而成的图形、如图19所示的直角梯形与弧形拼接而成的图形。当然，还可以包括其它设计的图形，这里不再一一赘述。
在本申请一实施例提供的显示面板中，如图22所示，沿垂直于衬底所在的平面的方向上，第二部分第一导电图案2/22到交界处的数据线DL之间的距离为第一距离；第二部分第一导电图案2/22在衬底上的正投影图形包括直角梯形，直角梯形的上底与下底的尺寸的差值y与第一距离成正比。
在示例性的实施例中，以侧向电容大小随交界处Data线距离而变化的曲线拟合公式为C＝a*x+b来算，其中，x为距离，C为电容值，则每远离Data线1um，电容减小a。即a为单位距离下电容的差异，b为在正对位情况下时的电容。
已知交叠电容公式如下公式(1)：
Figure PCTCN2022122820-appb-000003
其中ε 0，εr，d这三个参数对同一个显示面板而言为定值，d为两电极之间的距离，即第二部分第一导电图案2/22与交界处的数据线DL之间的绝缘层的厚度；εr为两个电极之间的绝缘层的介电常数，ε0为常数；如图22所示，在交界处数据线DL可能发生位置偏移的情况下，第二部分第一导电图案2/22在衬底上的正投影图形可以拆分为一个与交界处数据线DL的交叠面积固定的矩形、以及一个与交界处数据线DL的交叠面积不固定的三角形，假设交叠面积固定的矩形与交界处数据线DL的交叠面积为A1，交叠面积不固定的三角形与交界处数据线DL的交叠面积为A2；
由于侧向电容减小的电容值需要交叠电容来补充，则可以得到如下公式(2)，其中，A＝A1+A2：
Figure PCTCN2022122820-appb-000004
根据公式(2)，可以计算得到如下公式：
Figure PCTCN2022122820-appb-000005
Figure PCTCN2022122820-appb-000006
根据公式(3)和公式(4)，可以计算得到
A2＝bd/(ε 0*εr)＝x*y/2   公式(5)
将公式(4)带入公式(5)中，可以得到如下公式(6)：
y＝2*a*d/(ε 0*ε r)   公式(6)
其中，y为如图22所示的第二部分第一导电图案2/22在衬底上的正投影图形(直角梯形)的上底与下底的差值，由于在同一个显示面板的同一个区域中，a、ε0和εr均为定值，则直角梯形的上底与下底的尺寸的差值y与第一距离d成正比。
在本申请的实施例提供的一显示面板中，通过设置第二部分第一导电图案2/22在衬底上的正投影图形包括直角梯形，且该直角梯形的上底与下底的尺寸的差值y与第一距离成正比。这样，在制备工艺的对位偏差造成交界处数据线DL位置偏移时，本申请的实施例提供的第二虚拟电容Dummy C2仍然能够提供稳定的电容负载，从而使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL的电容负载与位于第一显示区AA1中的数据线DL的电容负载趋于一致，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区 域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，如图23所示，沿垂直于衬底所在的平面的方向上，第二部分第一导电图案2/22到交界处的数据线DL之间的距离为第一距离；第二部分第一导电图案2/22在衬底上的正投影图形包括矩形与第一图形的组合，第一图形包括多个直角梯形，且各直角梯形的直角边与矩形接触；各直角梯形的上底与下底的尺寸之和与第一距离成正比。
如图23所示，在交界处数据线DL可能发生位置偏移的情况下，第二部分第一导电图案2/22在衬底上的正投影图形可以拆分为一个与交界处数据线DL的交叠面积固定的矩形、以及一个与交界处数据线DL的交叠面积不固定的第一图形，假设交叠面积固定的矩形与交界处数据线DL的交叠面积为A1，交叠面积不固定的第一图形与交界处数据线DL的交叠面积为A2；
其中，第一图形包括多个直角梯形的组合，标记y1的位置处可以为第一个直角梯形的下底，标记y2的位置处可以为第一个直角梯形的上底或者第二个直角梯形的下底，标记y3的位置处可以为第二个直角梯形的上底。
假设在第一个直角梯形的位置范围内，每远离交界处的数据线DL1um，电容减小a1，在第二个直角梯形的位置范围内，每远离交界处的数据线DL1um，电容减小a2。
采用与前文类似的算法，可以得到：
y1+y2＝2*a1*d/(ε 0*ε r)   公式(7)
y2+y3＝2*a2*d/(ε 0*ε r)   公式(8)
其中，y1+y2为第一个直角梯形的上底与下底的尺寸之和，y2+y3为第二个直角梯形的上底与下底的尺寸之和；，由于在同一个显示面板的同一个区域梯形中，a1、a2、ε0和εr均为定值，则各直角梯形的上底与下底的尺寸之和与第一距离d成正比。
在本申请的实施例提供的一显示面板中，通过设置第二部分第一导 电图案2/22在衬底上的正投影图形包括矩形与第一图形的组合，第一图形包括多个直角梯形，且各直角梯形的直角边与矩形接触；各直角梯形的上底与下底的尺寸之和与第一距离成正比。这样，在制备工艺的对位偏差造成交界处数据线DL位置偏移时，本申请的实施例提供的第二虚拟电容Dummy C2仍然能够提供稳定的电容负载，从而使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL的电容负载与位于第一显示区AA1中的数据线DL的电容负载趋于一致，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，如图31和图32所示，第二部分第一导电图案2/22在衬底上的正投影图形包括相连的第二图形T2和第三图形T3的组合，第二图形T2包括切角矩形，第三图形T3包括多边形、弧形或多边形与弧形的组合；
其中，第二图形T2从第一显示区AA1延伸至第二显示区AA2，第三图形T3位于第二显示区AA2，且第二部分第一导电图案2/22中正投影为第三图形T3的部分与显示面板的公共电极线CML直接接触，切角矩形的切角位于第二显示区AA2。
这里对于上述切角矩形中切角的尺寸大小不进行限定，然而，无论切角矩形中切角的大小如何，第二图形T2位于第二显示区AA2的部分的面积始终大于第二图形T2位于第一显示区AA1的部分的面积。
另外，需要说明的是，在实际应用中，即使由于制备工艺过程中对位偏差，交界线处的数据线DL的位置发生偏移，交界线处的数据线DL几乎不会偏移到第三图形T3所在位置处，故而，第二虚拟电容Dummy C2的交叠电容的电容值大小主要由第二图形T2的尺寸决定。
在本申请的实施例中，对于第二图形T2位于第二显示区AA2的部分，在第二图形T2为矩形时，可以在矩形中距离具有栅极信号的导电图案(例如图32中所示的第一部分第一导电图案2/21)最近的顶角处设置切角，一方面，能够增加第二图形T2到具有栅极信号的导电图案 之间的距离，避免栅极信号对第二图形T2中信号的干扰；另一方面，避免第二部分第一导电图案2/22上具有尖锐的导电图形增大发生静电击穿的概率，提高了显示面板中信号传输稳定性，提高了显示面板的产品可靠性。
另外，第三图形T3包括多边形、弧形或多边形与弧形的组合；
其中，多边形可以包括三角形、四边形(矩形、菱形、平行四边形)、五边形、六边形等；弧形可以包括圆形、椭圆形、半圆形、半椭圆形等；
多边形与弧形的组合包括：多边形与弧形拼接形成的图形，或者，在多边形或弧形上去除局部区域后形成的图形。
需要说明的是，图3为一显示面板设计版图的局部区域，由于公共电极线CML覆盖在第三图形T3上，第三图形T3的部分区域被遮挡住，故而在图3中漏出的第三图形T3的部分为三角形，在实际应用中，第三图形T3可以为其它形状，第二部分第一导电图案2/22中正投影为第三图形T3的部分的主要为了与公共电极线CML直接接触并搭接在一起，实现电连接的目的。
在本申请一实施例提供的显示面板中，如图20所示，第二部分第一导电图案2/22在衬底上的正投影图形的顶角包括圆角。
在本申请的实施例中，由于第二部分第一导电图案2/22的部分区域位于第二显示区AA中，第二显示区AA靠近非显示区设置，非显示区中容易发生静电击穿，而具有尖锐结构的导电图案会加剧静电击穿，造成显示面板损坏，故而，在设计第二部分第一导电图案2/22时，尽可能避免尖角，设计成圆角，从而降低此区域发生静电击穿的可能性，提高显示面板的品质和可靠性。
在本申请一实施例提供的显示面板中，第二虚拟电容Dummy C2的数量大于或等于子像素行数的一半。
在示例性的实施例中，可以设置第二虚拟电容Dummy C2的数量大于子像素行数的一半、且小于等于子像素的行数。
示例性的，可以设置第二虚拟电容Dummy C2的数量等于子像素行数。
在示例性的实施例中，可以设置第二虚拟电容Dummy C2的数量等于子像素行数的一半。
在本申请一实施例提供的显示面板中，结合图8、图9以及图29所示，各栅线GL将交界处的数据线DL划分为多个数据线段；至少部分数据线段在衬底上的正投影与第二部分第一导电图案2/22在衬底上的正投影交叠。
在本申请的一些实施例中，如图29所示，各栅线GL将交界处的数据线DL划分为多个数据线段，例如数据线段DL-J1、数据线段DL-J2、数据线段DL-J3、数据线段DL-J4，其中，数据线段DL-J3和第一显示区AA1中的晶体管电连接、且数据线段DL-J3还和第二虚拟电容Dummy C2电连接；数据线段DL-J2与第二显示区AA2中的虚拟晶体管Dummy TFT电连接、且数据线段DL-J2未与第二虚拟电容Dummy C2电连接。
在本申请的一些实施例中，同一个数据线段可以既与虚拟晶体管Dummy TFT电连接，又与第二虚拟电容Dummy C2电连接。
在本申请的一些实施例中，同一个数据线段可以既与第一显示区AA1中的晶体管电连接，又与第二虚拟电容Dummy C2电连接。
然而，同一个数据线段不能同时与第一显示区AA1中的晶体管电连接，又与虚拟晶体管Dummy TFT电连接。
在本申请的一些实施例中，同一个数据线段可以既与第一虚拟电容Dummy C1电连接，又与第二虚拟电容Dummy C2电连接。
在本申请的一些实施例中，同一个数据线段可以既与第一显示区AA1中的晶体管电连接，又与第二虚拟电容Dummy C2电连接。
然而，同一个数据线段不能同时与第一显示区AA1中的晶体管电连接，又与第一虚拟电容Dummy C1电连接。
其中，至少部分数据线段在衬底上的正投影与第二部分第一导电图案2/22在衬底上的正投影交叠包括但不限于如下情况：
第一、部分数据线段在衬底上的正投影与第二部分第一导电图案2/22在衬底上的正投影交叠，也就是说，部分数据线段可以与第二虚拟 电容Dummy C2电连接。
第二、所有数据线段在衬底上的正投影与第二部分第一导电图案2/22在衬底上的正投影交叠，也就是说，所有数据线段可以与第二虚拟电容Dummy C2电连接。
在本申请的实施例中，通过设置第二虚拟电容Dummy C2来模拟第一显示区AA中数据线DL与公共电极之间形成的侧向电容，从而使得位于第一显示区AA1与第二显示区AA2的交界处的数据线DL的电容负载与位于第一显示区AA1中的数据线DL的电容负载趋于一致，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，第二虚拟电容Dummy C2的数量等于子像素行数，各数据线段在衬底上的正投影均与第二部分第一导电图案2/22在衬底上的正投影交叠。此时，第一显示区AA1与第二显示区AA2的交界处的每个数据线段上设置第二虚拟电容Dummy C2。
在示例性的实施例中，交界处的每个数据线段上设置各第二虚拟电容Dummy C2的第一电极(第二部分第一导电图案2/22)的平面图形的形状和尺寸均相同，与第二部分第一导电图案2/22在衬底上的正投影交叠的各数据线段的平面图形的形状和尺寸也均相同。
需要说明的是，通过在第一显示区AA1与第二显示区AA2的交界处的每个数据线段上设置第二虚拟电容Dummy C2，使得每个交界处数据线段上的电容负载趋近于第一显示区AA1中的数据线段，从而使得交界处的数据线DL的整体的电容负载趋近于位于第一显示区AA1中的数据线DL的电容负载，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，第二虚拟电容Dummy C2的数量等于子像素行数的一半，一半数据线段在衬底上的正投影与第二部 分第一导电图案2/22在衬底上的正投影交叠。
在一些实施例中，可以在显示面板的交界处的数据线DL的局部区域中，每个数据线段上都设置一个第二虚拟电容Dummy C2；在交界处的数据线DL的另一个局部区域中，均不设置第二虚拟电容Dummy C2。
在一些实施例中，对于交界处的数据线DL的每相邻两个数据线段，在其中一个数据线段上设置一个第二虚拟电容Dummy C2，在另一个数据线段上不设置一个第二虚拟电容Dummy C2。
在一些实施例中，对于交界处的数据线DL的各数据线段，可以在第一个数据线段上设置一个第二虚拟电容Dummy C2，在第二个数据线段上设置一个第二虚拟电容Dummy C2，在第三个数据线段上不设置第二虚拟电容Dummy C2，第四个数据线段上设置一个第二虚拟电容Dummy C2，在第五个数据线段上设置一个第二虚拟电容Dummy C2，在第六个数据线段上不设置第二虚拟电容Dummy C2，依次循环设置。
在一些实施例中，对于交界处的数据线DL的各数据线段，可以在第一个数据线段上设置一个第二虚拟电容Dummy C2，在第二个数据线段上不设置第二虚拟电容Dummy C2，在第三个数据线段上不设置第二虚拟电容Dummy C2，第四个数据线段上设置一个第二虚拟电容Dummy C2，在第五个数据线段上不设置第二虚拟电容Dummy C2，在第六个数据线段上不设置第二虚拟电容Dummy C2，依次循环设置。
在本申请一实施例提供的显示面板中，如图10、图12、图29所示，各数据线段包括第一组和第二组，第一组数据线段在衬底上的正投影与第二部分第一导电图案2/22在衬底上的正投影存在交叠，第二组数据线段在衬底上的正投影与第二部分第一导电图案2/22在衬底上的正投影互不交叠；其中，第一组数据线段与第二组数据线段间隔设置；可以理解，此时，各个数据线段上间隔设置有第二虚拟电容Dummy C2；即第一个数据线段上设置一个第二虚拟电容Dummy C2，在第二个数据线段上不设置第二虚拟电容Dummy C2，在第三个数据线段上设置一个第二虚拟电容Dummy C2，第四个数据线段上不设置第二虚拟电容Dummy C2。
在本申请一实施例提供的显示面板中，交界处的数据线与第一显示区中的数据线之间存在电容负载差异，在各个数据线段上间隔设置有第二虚拟电容Dummy C2的情况下，可以设置一个第二虚拟电容Dummy C2能够同时补偿两个数据线段的电容负载差异。
举例来说，假如位于第一显示区AA1中的一个数据线段与公共电极之间的电容负载为R1，在各个数据线段上间隔设置有第二虚拟电容Dummy C2的情况下，则位于交界处的一个数据线段上设置的第二虚拟电容的电容负载可以为2R1，这样，位于第一显示区AA1中的一条数据线DL包括的各个数据线段的电容负载之和与位于交界处的各数据线段DL上设置的第二虚拟电容Dummy C2的电容负载之和趋于相等，这样，使得交界处的数据线DL的整体的电容负载趋近于位于第一显示区AA1中的数据线DL的电容负载，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，如图24-图27所示，显示面板还包括第三导电图案6，第三导电图案6与公共电极1电连接，第三导电图案6至少位于第二显示区AA2，且第三导电图案AA2的至少部分区域位于第一部分第一导电图案2/21与交界处的数据线DL之间；其中，第三导电图案6的至少部分区域在衬底上的正投影与交界处的数据线DL在衬底上的正投影互不交叠。
示例性的，如图24-图27所示，第三导电图案6可以与像素电极4同层设置，其中，像素电极4中设置有狭缝Slit。
示例性的，第三导电图案6可以与公共电极1同层设置。
其中，第三导电图案6至少位于第二显示区AA2包括但不限于如下情况：
第一、如图24和图26所示，第三导电图案6位于第二显示区AA2中；
第二、如图25和图27所示，第三导电图案6不仅位于第二显示区 AA2中，还从延伸至第一显示区AA1中；此时，第三导电图案6的主要部分位于第二显示区AA2，第三导电图案6的局部位于第一显示区AA1中。
另外，第三导电图案6的至少部分区域位于第一部分第一导电图案2/21与交界处的数据线DL之间包括但不限于以下情况：
第一、如图25和图27所示，第三导电图案6的部分区域位于第一部分第一导电图案2/21与交界处的数据线DL之间；
第二、如图24和图26所示，第三导电图案6完全位于第一部分第一导电图案2/21与交界处的数据线DL之间。
还需要说明的是，第三导电图案6的至少部分区域在衬底上的正投影与交界处的数据线DL在衬底上的正投影互不交叠包括但不限于以下情况：
第一、如图25和图27所示，第三导电图案6的部分区域在衬底上的正投影与交界处的数据线DL在衬底上的正投影互不交叠；
第二、如图24和图26所示，第三导电图案6在衬底上的正投影与交界处的数据线DL在衬底上的正投影互不交叠。
在本申请一实施例提供的显示面板中，如图24-图27所示，显示面板还包括第三虚拟电容Dummy C3，第三导电图案6作为第三虚拟电容Dummy C3的第一电极且与公共电极1电连接，交界处的数据线DL的部分线段作为第三虚拟电容Dummy C3的第二电极。
在本申请的一些实施例中，如图24和图26所示，第三虚拟电容Dummy C3包括侧向电容。
在本申请的一些实施例中，如图25和图27所示，第三虚拟电容Dummy C3包括侧向电容和交叠电容。
在本申请一实施例提供的显示面板中，如图24和图26所示，第三导电图案6在衬底上的正投影与交界处的数据线DL在衬底上的正投影互不交叠。
在本申请的一些实施例中，第三虚拟电容Dummy C3的数量小于或等于子像素的行数。
示例性的，第三虚拟电容Dummy C3的数量等于子像素的行数。
示例性的，第三虚拟电容Dummy C3的数量小于子像素的行数。
在本申请一实施例提供的显示面板中，各栅线GL将交界处的数据线DL划分为多个数据线段，可以在每一个第一部分第一导电图案2/21与数据线段之间的位置处设置一个第三虚拟电容Dummy C3。
在一些实施例中，如图24和图25所示，可以在显示面板的部分区域设置数据线段与虚拟晶体管Dummy TFT电连接，在部分区域设置数据线段与第三虚拟电容Dummy C3电连接。
在一些实施例中，如图26和图27所示，可以在显示面板的部分区域设置数据线段与第一虚拟电容Dummy C1电连接，在部分区域设置数据线段与第三虚拟电容Dummy C3电连接。
在一些实施例中，可以在显示面板的部分区域设置数据线段与第一虚拟电容Dummy C1电连接，在部分区域设置数据线段与虚拟晶体管Dummy TFT电连接，在部分区域设置数据线段与第三虚拟电容Dummy C3电连接。
在一些实施例中，可以在显示面板的部分区域设置数据线段与第一虚拟电容Dummy C1电连接，在部分区域设置数据线段与虚拟晶体管Dummy TFT电连接，在部分区域设置数据线段与第二虚拟电容Dummy C2电连接，在部分区域设置数据线段与第三虚拟电容Dummy C3电连接。
在一些实施例中，可以设置同一个数据线段既与第二虚拟电容Dummy C2电连接，又与第三虚拟电容Dummy C3电连接。需要说明的是，在同一数据线段对应位置处同时设置第二虚拟电容Dummy C2和第三虚拟电容Dummy C3的情况下，第二虚拟电容Dummy C2和第三虚拟电容Dummy C3的平面图形之间具有一定距离，以避免两个虚拟电容之间的电信号干扰。
在一些实施例中，对于交界处的数据线DL的每相邻两个数据线段，在其中一个数据线段上设置一个第三虚拟电容Dummy C3，在另一个数据线段上不设置一个第三虚拟电容Dummy C3。
在一些实施例中，对于交界处的数据线DL的各数据线段，可以在第一个数据线段上设置一个第三虚拟电容Dummy C3，在第二个数据线段上设置一个第三虚拟电容Dummy C3，在第三个数据线段上不设置第三虚拟电容Dummy C3，第四个数据线段上设置一个第三虚拟电容Dummy C3，在第五个数据线段上设置一个第三虚拟电容Dummy C3，在第六个数据线段上不设置第三虚拟电容Dummy C3，依次循环设置。
在一些实施例中，对于交界处的数据线DL的各数据线段，可以在第一个数据线段上设置一个第三虚拟电容Dummy C3，在第二个数据线段上不设置第三虚拟电容Dummy C3，在第三个数据线段上不设置第三虚拟电容Dummy C3，第四个数据线段上设置一个第三虚拟电容Dummy C3，在第五个数据线段上不设置第三虚拟电容Dummy C3，在第六个数据线段上不设置第三虚拟电容Dummy C3，依次循环设置。
本申请的实施例提供的与交界处的数据线DL电连接的第三虚拟电容Dummy C3能够模拟位于第一显示区AA1中的公共电极1与数据线DL之间形成的侧向电容，这样，使得位于交界处的数据线DL的整体的电容负载趋近于位于第一显示区AA1中的数据线DL的电容负载，降低了交界处数据线DL的充电率与第一显示区AA1中的数据线DL的充电率的差异，在减小了显示面板的边框尺寸的同时，提高了显示面板中不同区域的亮度均一性，提高了显示效果。
在本申请一实施例提供的显示面板中，同一行子像素连接同一条栅线GL；
每相邻两条数据线DL之间设置有一列子像素，同一列子像素包括第一类和第二类，任意一个第一类子像素位于两个第二类子像素之间，其中，同一列子像素中的第一类与一条数据线DL电连接，同一列子像素中的第二类与另一条数据线DL电连接。
如图28所示，第一行子像素连接第一条栅线GL1，第二行子像素连接第二条栅线GL2，第三行子像素连接第三条栅线GL3，第四行子像素连接第四条栅线GL4。
如图28所示，第一列子像素中的第一个子像素和第三个子像素连 接第一条数据线DL1，第一列子像素中的第二个子像素和第四个子像素连接第二条数据线DL2；第二列子像素中的第一个子像素和第三个子像素连接第二条数据线DL2，第二列子像素中的第二个子像素和第四个子像素连接第三条数据线DL3；第三列子像素中的第一个子像素和第三个子像素连接第三条数据线DL2，第三列子像素中的第二个子像素和第四个子像素连接第四条数据线DL4。如图28所示的显示面板为一种Z反转技术的显示面板，Z反转技术的显示面板的具体介绍可以参见相关技术，这里不再赘述。
其中，第一条数据线DL1与第四条数据线DL4分别为位于第一显示区AA1和第二显示区AA2交界处的数据线，且该两条数据线上电连接的子像素的晶体管的数量为其它数据线连接的子像素的晶体管的数量的一半。对于Z反转技术的显示面板，存在至少一条位于交界处的数据线，其电连接的子像素的晶体管的数量为其它数据线连接的子像素的晶体管的数量的一半。
在本申请的一些实施例中，可以设置第一行子像素为红色子像素，第二行子像素为绿色子像素，第三行子像素为绿色子像素，第四行为红色子像素。
在本申请的一些实施例中，还可以设置第一列子像素为红色子像素，第二列子像素为绿色子像素，第三列子像素为绿色子像素。
在本申请一实施例提供的显示面板中，结合图4-图7以及图29所示，多条栅线GL将位于第一显示区AA1的数据线DL也划分为多个数据线段，各数据线段中，部分数据线段包括支撑部PSZ、第一连接部和第二连接部，支撑部PSZ位于第一连接部和第二连接部之间；
其中，第一连接部在衬底上的正投影与一条栅线GL在衬底上的正投影交叠，第二连接部在衬底上的正投影与另一条栅线GL在衬底上的正投影交叠。
支撑部PSZ沿垂直于数据线段延伸方向上的尺寸大于第一连接部沿垂直于数据线段延伸方向上的尺寸，支撑部沿垂直于数据线段延伸方向上的尺寸大于第二连接部沿垂直于数据线段延伸方向上的尺寸，可以 理解，数据线段中支撑部的线宽(Line Width)大于第一连接部的线宽，且支撑部的线宽(Line Width)大于第二连接部的线宽。
在示例性的实施例中，第一连接部的线宽与第二连接部的线宽可以相同。
在一些实施例中，如图29所示，在数据线DL的局部区域，相连接的两个数据线段上均设置有支撑部PSZ、第一连接部和第二连接部。
在一些实施例中，在数据线DL的局部区域，可以间隔设置支撑部PSZ、第一连接部和第二连接部。
例如，对于同一条数据线DL，第一个数据线段上设置有支撑部PSZ、第一连接部和第二连接部，第二个数据线段上不设置支撑部PSZ、第一连接部和第二连接部，第三个数据线段上设置有支撑部PSZ、第一连接部和第二连接部；
再例如，第一个数据线段上设置有支撑部PSZ、第一连接部和第二连接部，第二个数据线段上不设置支撑部PSZ、第一连接部和第二连接部，第三个数据线段上不设置支撑部PSZ、第一连接部和第二连接部，第四个数据线段上不设置支撑部PSZ、第一连接部和第二连接部，第五个数据线段上不设置支撑部PSZ、第一连接部和第二连接部；
第六个数据线段上设置有支撑部PSZ、第一连接部和第二连接部，第七个数据线段上不设置支撑部PSZ、第一连接部和第二连接部，第八个数据线段上不设置支撑部PSZ、第一连接部和第二连接部，第九个数据线段上不设置支撑部PSZ、第一连接部和第二连接部，第十个数据线段上不设置支撑部PSZ、第一连接部和第二连接部。
当然，还可以有其它设置还排布方式，这里不再赘述。
需要说明的是，本申请的实施例提供的支撑部PSZ是用于放置隔垫物PS，隔垫物PS设置在支撑部PSZ远离衬底的一侧，以起到支撑阵列基板和彩膜基板的作用，并提高显示面板的显示性能，在本申请的实施例中，通过将用于放置隔垫物PS的支撑部PSZ设置在数据线DL上，能够很大程度上节省设计空间，并提高显示面板的开口率，从而提高显示面板的透光率，提高显示效果，降低功耗。
在本申请一实施例提供的显示面板中，显示面板还包括隔垫物PS和保护部PSB，隔垫物PS位于部分支撑部PSB远离衬底的一侧，保护部PSB位于各支撑部PSZ的至少一侧；保护部PSB在沿垂直于衬底所在平面上的高度大于支撑部PSZ在沿垂直于衬底所在平面上的高度。
需要说明的是，并非在所有的支撑部PSZ上都要设置隔垫物PS。
其中，隔垫物PS在衬底上的正投影的外轮廓位于支撑部PSZ在衬底上的正投影的外轮廓以内。
示例性的，在一些实施例中，在局部区域的支撑部PSZ上设置隔垫物PS，在局部区域的支撑部PSZ上不设置隔垫物PS。
例如，如图29所示，在位于第一显示区AA1和第二显示区AA2的交界处的数据线DL的支撑部PSZ上不设置隔垫物PS，在第一显示区AA1中的数据线DL的支撑部PSZ上设置隔垫物PS。
其中，隔垫物PS包括主隔垫物MPS和辅助隔垫物SPS。
这里对于主隔垫物MPS和辅助隔垫物SPS的数量和分布规律不进行限定。
示例性的，如图29所示，在数据线DL的局部区域，相连接的两个数据线段上均设置有支撑部PSZ、第一连接部和第二连接部，在这两个支撑部PSZ分别设置一个主隔垫物MPS和一个辅助隔垫物SPS。
主隔垫物MPS和辅助隔垫物SPS的具体结构和尺寸的设计可以参考相关技术中的说明，这里不再赘述。
在示例性的实施例中，在第一显示区AA1中各支撑部PSZ的两侧均设置有保护部PSB，在第二显示区AA2中各支撑部PSZ靠近第一显示区AA1的一侧设置有保护部PSB，保护部PSB设置在子像素中，在隔垫物PS的位置发生偏移或发生损坏的情况下，保护部PSB能够保护子像素中的膜层结构不被隔垫物PS剐蹭，从而避免子像素损坏。
在示例性的实施例中，支撑部PSZ的厚度与数据线DL的厚度相同，其厚度均根据源漏金属层(SD层)的厚度确定。
在示例性的实施例中，保护部PSB包括第一子层和第二子层，其中，第一子层位于栅极层(Gate层)中，第二子层位于源漏金属层(SD 层)中，保护部PSB的厚度为栅极层(Gate层)与源漏金属层(SD层)的厚度之和。
在示例性的实施例中，保护部PSB的延伸方向与支撑部PSZ的侧边的延伸方向一致，以尽可能合理利用空间，降低设计难度。
在一些实施例中，可以在支撑部PSZ的两侧分别设置一个保护部PSB，且该保护层PSB半包围该支撑部PSZ。
在一些实施例中，如图29所示，可以在支撑部PSZ的两侧分别设置两组保护部PSB，这两组保护部PSB对称设置，且一组保护部PSB中包括一个尺寸较大的保护部PSB和一个尺寸较小的保护部PSB，其中，尺寸较小的保护部PSB位于尺寸较大的保护部PSB远离支撑部PSZ的一侧。
在示例性的实施例中，显示面板的第一部分第一导电图案2/21在衬底上的正投影图形为矩形，其中，如图29所示，该矩形的上半部分设置有多个过孔Via，该过孔用于将周边区BB中的GOA电路的输出端Gout与显示区AA中的栅线GL电连接在一起；该矩形的下半部分可以设置虚拟晶体管Dummy TFT或者第一虚拟电容Dummy C1。
在示例性的实施例中，显示面板的周边区BB还包括公共线BSL，该公共线BSL的一端与显示面板的绑定端子电连接，另一端与显示区AA中的公共电极线CML电连接。
其中，该公共线BSL上还设置有多个编码图案N0.1，用于标记显示面板中子像素的行数。当然，在周边区BB的其它区域，还包括多个编码图案N0.2，用于标记显示面板中子像素的列数。
本申请的实施例提供了一种显示装置，包括前文中所述的显示面板。
上述显示面板的具体结构可以参考前文中的描述，这里不再赘述。
上述显示装置可以为液晶显示装置(Liquid Crystal Display，LCD)，示例性的，液晶显示装置可以包括扭曲向列(Twisted Nematic，TN)型、垂直配向(Vertical Alignment，VA)型、平面转换(In Plane Switching，IPS)型和高级超维场开关(ADS，Advanced Super Dimension Switch)型。
上述显示装置可以是LCD显示器等显示器件以及包括这些显示器 件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
本申请的实施例提供的显示装置，通过设置部分第一导电图案2与第二导电图案3的投影交叠，形成交叠电容，且第二导电图案3与交界处的数据线电连接，从而增加了交界处数据线的电容负载，提高交界处数据线与其它数据线的负载一致性，在降低边框尺寸的同时，避免了RC信号延迟(RC Delay)差异造成的充电率差异，避免充电率差异造成的显示亮度不均的问题，兼顾了窄边框和较高的显示效果。另外，通过在第二显示区AA2中第一导电图案2与第二导电图案3，且设置部分第一导电图案2与第二导电图案3的投影交叠，形成交叠电容，替代了相关技术中的Dummy子像素，结合图29所示，第二显示区AA2中的结构的尺寸远小于子像素的尺寸，很大程度上降低了显示面板的边框尺寸，还确保了较好的显示效果。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (30)

  1. 一种显示面板，其中，包括：第一显示区和至少一个第二显示区，所述第二显示区位于所述第一显示区的一侧；所述显示面板还包括：
    衬底；
    位于所述衬底上阵列排布的多个子像素；各所述子像素均位于所述第一显示区；所述子像素包括公共电极；
    位于所述衬底上的多条栅线和多条数据线，所述栅线和所述数据线相交且绝缘，所述子像素位于所述栅线和所述数据线限定的位置处；至少一条所述数据线位于所述第一显示区和所述第二显示区的交界处；
    多个第一导电图案，所述第一导电图案至少位于所述第二显示区，且所述第一导电图案与所述栅线或所述公共电极中的一个电连接；
    多个第二导电图案，位于所述第二显示区且与所述交界处的所述数据线电连接；其中，部分所述第一导电图案在所述衬底上的正投影与所述第二导电图案在所述衬底上的正投影存在交叠。
  2. 根据权利要求1所述的显示面板，其中，所述多个第一导电图案包括第一部分；
    第一部分所述第一导电图案位于所述第二显示区，且与所述栅线电连接；所述第二导电图案在所述衬底上的正投影位于第一部分所述第一导电图案在所述衬底上的正投影以内。
  3. 根据权利要求1所述的显示面板，其中，所述多个第一导电图案包括第二部分；
    第二部分所述第一导电图案从所述第一显示区延伸至所述第二显示区，且与所述公共电极电连接；第二部分所述第一导电图案在所述衬底上的正投影与所述交界处的所述数据线在所述衬底上的正投影存在交叠。
  4. 根据权利要求2所述的显示面板，其中，
    所述第二导电图案在所述衬底上的正投影的外轮廓位于第一部分所述第一导电图案在所述衬底上的正投影的外轮廓以内。
  5. 根据权利要求4所述的显示面板，其中，所述第二显示区包括 多个第一虚拟电容，第一部分所述第一导电图案作为所述第一虚拟电容的第一电极，所述第二导电图案作为所述第一虚拟电容的第二电极。
  6. 根据权利要求4所述的显示面板，其中，所述第二显示区包括多个虚拟晶体管，所述虚拟晶体管的栅极与所述栅线电连接，所述虚拟晶体管的第一端与所述交界处的所述数据线电连接，所述虚拟晶体管的第二端孤立设置。
  7. 根据权利要求6所述的显示面板，其中，第一部分所述第一导电图案的部分区域作为所述虚拟晶体管的栅极；
    至少部分所述第二导电图案包括第一导电部和第二导电部，所述第一导电部和所述第二导电部断开设置，所述第一导电部作为所述虚拟晶体管的第一端，所述第二导电部作为所述虚拟晶体管的第二端。
  8. 根据权利要求7所述的显示面板，其中，所述虚拟晶体管的数量小于或等于所述子像素行数的一半。
  9. 根据权利要求8所述的显示面板，其中，各所述栅线将所述交界处的所述数据线划分为多个数据线段；所述第一显示区包括多个晶体管，部分所述数据线段与所述晶体管电连接，未连接所述晶体管的所述数据线段中的至少一部分与所述虚拟晶体管电连接。
  10. 根据权利要求9所述的显示面板，其中，所述虚拟晶体管的数量等于所述子像素行数的一半，未连接所述晶体管的所述数据线段均与所述虚拟晶体管电连接，且所述晶体管电连接的所述数据线段和所述虚拟晶体管电连接的所述数据线段间隔设置。
  11. 根据权利要求3所述的显示面板，其中，第二部分所述第一导电图案与所述公共电极为一体化结构。
  12. 根据权利要求3所述的显示面板，其中，所述显示面板包括多个第二虚拟电容，第二部分所述第一导电图案作为所述第二虚拟电容的第一电极，所述交界处的所述数据线的部分线段作为所述第二虚拟电容的第二电极；
    其中，第二部分所述第一导电图案位于所述第二显示区的部分在所述衬底上的正投影面积大于第二部分所述第一导电图案位于所述第一 显示区的部分在所述衬底上的正投影面积。
  13. 根据权利要求12所述的显示面板，其中，第二部分所述第一导电图案在所述衬底上的正投影图形包括多边形、弧形或者多边形与弧形的组合。
  14. 根据权利要求12所述的显示面板，其中，第二部分所述第一导电图案在所述衬底上的正投影图形包括相对设置的第一边和第二边，所述第一边和所述第二边的延伸方向相同，所述第一边位于所述第二显示区，所述第二边位于所述第一显示区，所述第一边沿其延伸方向上的长度大于或等于所述第二边沿其延伸方向上的长度。
  15. 根据权利要求14所述的显示面板，其中，沿垂直于衬底所在的平面的方向上，第二部分所述第一导电图案到所述交界处的所述数据线之间的距离为第一距离；
    第二部分所述第一导电图案在所述衬底上的正投影图形包括直角梯形，所述直角梯形的上底与下底的尺寸的差值与所述第一距离成正比。
  16. 根据权利要求14所述的显示面板，其中，沿垂直于衬底所在的平面的方向上，第二部分所述第一导电图案到所述交界处的所述数据线之间的距离为第一距离；
    第二部分所述第一导电图案在所述衬底上的正投影图形包括矩形与第一图形的组合，所述第一图形包括多个直角梯形，且各所述直角梯形的直角边与所述矩形接触；各所述直角梯形的上底与下底的尺寸之和与所述第一距离成正比。
  17. 根据权利要求12所述的显示面板，其中，第二部分所述第一导电图案在所述衬底上的正投影图形包括相连的第二图形和第三图形的组合，所述第二图形包括切角矩形，所述第三图形包括多边形、弧形或多边形与弧形的组合；
    其中，所述第二图形从所述第一显示区延伸至所述第二显示区，所述第三图形位于所述第二显示区，且第二部分所述第一导电图案中正投影为所述第三图形的部分与所述显示面板的公共电极线直接接触，所述切角矩形的切角位于所述第二显示区。
  18. 根据权利要求12所述的显示面板，其中，所述第二虚拟电容的数量大于或等于所述子像素行数的一半。
  19. 根据权利要求18所述的显示面板，其中，各所述栅线将所述交界处的所述数据线划分为多个数据线段；至少部分所述数据线段在所述衬底上的正投影与第二部分所述第一导电图案在所述衬底上的正投影交叠。
  20. 根据权利要求19所述的显示面板，其中，所述第二虚拟电容的数量等于所述子像素行数，各所述数据线段在所述衬底上的正投影均与第二部分所述第一导电图案在所述衬底上的正投影交叠。
  21. 根据权利要求19所述的显示面板，其中，所述第二虚拟电容的数量等于所述子像素行数的一半，一半所述数据线段在所述衬底上的正投影与第二部分所述第一导电图案在所述衬底上的正投影交叠。
  22. 根据权利要求21所述的显示面板，其中，各所述数据线段包括第一组和第二组，第一组所述数据线段在所述衬底上的正投影与第二部分所述第一导电图案在所述衬底上的正投影存在交叠，第二组所述数据线段在所述衬底上的正投影与第二部分所述第一导电图案在所述衬底上的正投影互不交叠；其中，第一组所述数据线段与第二组所述数据线段间隔设置。
  23. 根据权利要求21所述的显示面板，其中，所述交界处的所述数据线与所述第一显示区中的所述数据线之间存在电容负载差异，一个所述第二虚拟电容被配置为能够补偿两个所述数据线段的电容负载差异。
  24. 根据权利要求2所述的显示面板，其中，所述显示面板还包括第三导电图案，所述第三导电图案与所述公共电极电连接，所述第三导电图案至少位于所述第二显示区，且所述第三导电图案的至少部分区域位于第一部分所述第一导电图案与所述交界处的所述数据线之间；
    其中，所述第三导电图案的至少部分区域在所述衬底上的正投影与所述交界处的所述数据线在所述衬底上的正投影互不交叠。
  25. 根据权利要求24所述的显示面板，其中，所述显示面板还包 括第三虚拟电容，所述第三导电图案作为所述第三虚拟电容的第一电极且与所述公共电极电连接，所述交界处的所述数据线的部分线段作为所述第三虚拟电容的第二电极。
  26. 根据权利要求24所述的显示面板，其中，所述第三导电图案在所述衬底上的正投影与所述交界处的所述数据线在所述衬底上的正投影互不交叠。
  27. 根据权利要求1-26中任一项所述的显示面板，其中，同一行所述子像素连接同一条所述栅线；
    每相邻两条所述数据线之间设置有一列所述子像素，同一列所述子像素包括第一类和第二类，任意一个第一类所述子像素位于两个第二类所述子像素之间，其中，同一列所述子像素中的第一类与一条所述数据线电连接，同一列所述子像素中的第二类与另一条所述数据线电连接。
  28. 根据权利要求9或19所述的显示面板，其中，多条栅线将位于所述第一显示区的所述数据线也划分为多个数据线段，各所述数据线段中，部分所述数据线段包括支撑部、第一连接部和第二连接部，所述支撑部位于所述第一连接部和所述第二连接部之间；
    其中，所述支撑部沿垂直于所述数据线段延伸方向上的尺寸大于所述第一连接部沿垂直于所述数据线段延伸方向上的尺寸，所述支撑部沿垂直于所述数据线段延伸方向上的尺寸大于所述第二连接部沿垂直于所述数据线段延伸方向上的尺寸。
  29. 根据权利要求28所述的显示面板，其中，所述显示面板还包括隔垫物和保护部，所述隔垫物位于部分所述支撑部远离所述衬底的一侧，所述保护部位于各所述支撑部的至少一侧；所述保护部在沿垂直于所述衬底所在平面上的高度大于所述支撑部在沿垂直于所述衬底所在平面上的高度。
  30. 一种显示装置，其中，包括如权利要求1-29中任一项所述的显示面板。
PCT/CN2022/122820 2022-09-29 2022-09-29 显示面板、显示装置 WO2024065465A1 (zh)

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JP2011227263A (ja) * 2010-04-19 2011-11-10 Casio Comput Co Ltd 液晶表示装置
CN109817146A (zh) * 2019-03-08 2019-05-28 京东方科技集团股份有限公司 一种显示面板、显示装置及驱动方法
CN112764281A (zh) * 2021-01-28 2021-05-07 Tcl华星光电技术有限公司 一种阵列基板及显示面板
CN214897561U (zh) * 2021-03-22 2021-11-26 绵阳惠科光电科技有限公司 一种显示区的数据线电容补偿电路、显示面板及显示装置

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Publication number Priority date Publication date Assignee Title
JP2011227263A (ja) * 2010-04-19 2011-11-10 Casio Comput Co Ltd 液晶表示装置
CN109817146A (zh) * 2019-03-08 2019-05-28 京东方科技集团股份有限公司 一种显示面板、显示装置及驱动方法
CN112764281A (zh) * 2021-01-28 2021-05-07 Tcl华星光电技术有限公司 一种阵列基板及显示面板
CN214897561U (zh) * 2021-03-22 2021-11-26 绵阳惠科光电科技有限公司 一种显示区的数据线电容补偿电路、显示面板及显示装置

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