WO2024060367A1 - 存储器和存储*** - Google Patents

存储器和存储*** Download PDF

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Publication number
WO2024060367A1
WO2024060367A1 PCT/CN2022/130570 CN2022130570W WO2024060367A1 WO 2024060367 A1 WO2024060367 A1 WO 2024060367A1 CN 2022130570 W CN2022130570 W CN 2022130570W WO 2024060367 A1 WO2024060367 A1 WO 2024060367A1
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Prior art keywords
memory
control circuit
layer
blocks
control
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PCT/CN2022/130570
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English (en)
French (fr)
Inventor
唐衍哲
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长鑫存储技术有限公司
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Priority to US18/530,200 priority Critical patent/US20240105256A1/en
Publication of WO2024060367A1 publication Critical patent/WO2024060367A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a memory and storage system.
  • DRAM Dynamic Random Access Memory
  • Random access memory has a memory array composed of many repeated memory cells.
  • Each memory cell includes a selection transistor and a storage node connected to the selection transistor. Different states of the storage node are used to represent storage information, that is, "0" or "1".
  • semiconductor devices are required to have higher storage density and smaller feature sizes. How to integrate more memory cells per unit area and reduce the area occupied by each device, as well as how to simplify the wiring design and manufacturing process of the memory, have become issues that need to be solved urgently in the industry.
  • embodiments of the present disclosure provide a memory and a storage system.
  • an embodiment of the present disclosure provides a memory, including: a substrate; a control circuit layer located in the substrate; at least part of the control circuit of the memory included in the control circuit layer; at least two storage Structural layer; the at least two storage structure layers are stacked on the control circuit layer in sequence; the storage structure layer includes a plurality of memory blocks arranged in an array; the memory blocks include a plurality of parallel strips extending along the first direction. word lines; the first direction is parallel to the surface of the substrate; wherein there are openings between adjacent memory blocks located in the same memory structure layer; the openings located in different memory structure layers penetrate each other; at least Each word line in one of the memory structure layers is connected to the control circuit layer through the through opening.
  • the width of the openings located in different storage structure layers decreases in an upward direction from the substrate.
  • the memory further includes: a plurality of connection structures, the connection structures connecting the word line and the control circuit layer in a direction perpendicular to the substrate surface.
  • the memory further includes: a compensation resistor connected correspondingly to each of the connection structures, and the resistance of the compensation resistor is inversely proportional to the length of the connection structure.
  • the opening is located between adjacent memory blocks in a first direction
  • the connection structure includes: a first connection structure, the first connection structure is in a direction perpendicular to the substrate surface. At least one of the openings passes through; the word line in the storage structure layer located above the lowest storage structure layer is connected to the control circuit layer through the first connection structure; a second connection structure, Located between the storage structure layer at the bottom and the control circuit layer; the word line in the storage structure layer at the bottom is connected to the control circuit layer through the second connection structure.
  • the first connection structure is connected to the control circuit layer from under the word line through the opening in a direction perpendicular to the substrate; or, the first connection structure is connected to the control circuit layer by the word line.
  • One end of the line close to the opening extends to the opening along the first direction, and is connected to the control circuit layer through the opening in a direction perpendicular to the substrate.
  • control circuit layer includes: a plurality of control blocks correspondingly connected to each of the memory blocks.
  • the memory block includes: a plurality of memory cells arranged in an array, each of the word lines connecting a plurality of the memory cells arranged along the first direction; at least one of the memory structures.
  • the memory cells in a layer are connected to the control block through the openings through the word lines.
  • the memory further includes: a bit line structure layer located between the control circuit layer and at least two of the memory structure layers; the bit line structure layer includes a plurality of lines extending along the second direction. bit lines; there is an angle between the second direction and the first direction, and the second direction is parallel to the surface of the substrate; each of the bit lines is connected to a plurality of bit lines arranged along the second direction.
  • a group of memory cells wherein each group of memory cells is a plurality of memory cells stacked in a direction perpendicular to the substrate surface and connected through a first connection line.
  • control block includes: a first control block connected to the word line; and a second control block connected to the bit line.
  • bit lines connecting two adjacent memory blocks in the second direction are connected to the same second control block.
  • the memory further includes: a data input and output module connected to the second control block, and the data input and output module is configured to write or read data to the storage unit through the second control block. Pick.
  • the memory further includes: a power module connected to a plurality of the control blocks for providing power signals; the power module is located in the substrate, and the power module is connected to the control circuit Layers are within the same structural layer.
  • control circuit layer further includes: a global control circuit; the global control circuit is connected to a plurality of the control blocks; the global control circuit is at least used to provide control signals to a plurality of the control blocks .
  • the global control circuit includes: a global word line driving module connected to the plurality of the first control blocks, and configured to provide control signals for the plurality of word lines in the storage blocks connected to the plurality of the first control blocks.
  • the area where the global control circuit is located is outside the projection area of any memory block on the control circuit layer.
  • an embodiment of the present disclosure provides a storage system, including: a memory as described in any one of the above embodiments; and a storage controller.
  • At least two storage structure layers are stacked on the control circuit layer in sequence, and each word line in at least one storage structure layer is connected to the control circuit layer through a through opening.
  • the stacked storage structure layer and the control circuit layer occupy a smaller area, which improves the integration of the memory; on the other hand, the through opening facilitates the word lines in each storage structure layer to be drawn out and connected to the control circuit. layer, simplifying the wiring design and manufacturing process of the memory.
  • Figure 1 is a schematic diagram of a memory provided by an embodiment of the present disclosure
  • FIG2 is a top view of a storage structure layer in a memory provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a connection structure in a memory provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of a control block in a memory provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of a bit line structure layer in a memory provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of a sub-word line driving circuit in a memory provided by an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of a sensing amplification circuit in a memory provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of a global control circuit in a memory provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of a storage system provided by an embodiment of the present disclosure.
  • terms can be understood, at least in part, from context of use.
  • the term "one or more” as used herein may be used in the singular to describe any feature, structure or characteristic, or may be used in the plural to describe a combination of features, structures or characteristics.
  • terms such as “a” or “the” may equally be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context.
  • the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on context.
  • a memory 10 including:
  • the memory structure layer 120 includes a plurality of memory blocks 121 arranged in an array;
  • the memory blocks 121 include a plurality of parallel word lines WL extending along the first direction;
  • the first direction is parallel to the surface of the substrate 100; there are openings 122 between adjacent memory blocks 121 in the same memory structure layer 120; the openings 122 in different memory structure layers 120 penetrate each other. ;
  • Each word line WL in at least one of the memory structure layers 120 is connected to the control circuit layer 110 through the through opening 122.
  • the memory 10 may include but is not limited to DRAM, static random access memory (Static Random Access Memory, SRAM), ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM), magnetic random access memory (Magnetoresistive Random Access Memory, MRAM), Phase Change Random Access Memory (Phase Change Random Access Memory, PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (Nano Random Access Memory , NRAM) etc.
  • the material of the substrate 100 may include elemental semiconductor materials, such as silicon (Si), germanium (Ge), etc., or compound semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP).
  • the substrate 100 may also be doped, or include a doped region and an undoped region in the substrate. It should be understood that in order to clearly show the structure of each layer in the figure, the dimensional proportional relationship of the structure of each layer may not be consistent with the actual structure. It is worth noting that the horizontal direction in this disclosure refers to the direction parallel to the surface of the substrate 100, including but not limited to the X direction and the Y direction, while the vertical direction refers to the direction perpendicular to the surface of the substrate 100, such as Z direction.
  • the memory block in the embodiment of the present disclosure may be composed of a plurality of memory cells having a "1T1C" (one selection transistor T and one storage capacitor C) structure.
  • the selection transistor is used to control the signal on and off between the storage unit and the control circuit.
  • the selection transistor needs to be switched to a conductive state to realize charge transfer between the storage capacitor and the external connection.
  • the storage capacitor stores data based on the stored charge. Since the electrodes of the storage capacitor show different potentials when the charges stored in the storage capacitor are different, binary data can be read and written by switching the storage state of the storage capacitor.
  • the storage capacitor when the storage capacitor is in a charged state, it represents data "1", and when the storage capacitor is in a discharged state (uncharged state), it represents data "0".
  • the storage capacitor By detecting the voltage on the electrode of the storage capacitor, it can be determined whether its state is a charged state or a discharged (uncharged state), thereby enabling data to be read.
  • control circuit in the memory and the plurality of array-arranged memory blocks are located in the same plane parallel to the substrate surface, and the control circuit is located in the horizontal direction around the plurality of array-arranged memory blocks, This makes the memory occupy a larger area in the horizontal direction and has a lower integration level. It is understandable that in this case, in order to obtain higher storage density, the size of the memory unit needs to be further reduced, and the manufacturing process is relatively difficult.
  • the control circuit layer 110 is located in the substrate 100 , and the control circuit layer 110 has at least part of the control circuit of the memory 10 .
  • the control circuit layer 110 includes but is not limited to a sub wordline driver circuit (Sub Wordline Driver, SWD), a sense amplifier circuit (Sense Amplifier, SA), a row decoder, a column decoder, a fuse repair circuit, Power module, data input and output circuit, etc.
  • the control circuit layer 110 can be used to decode, detect the memory unit, and control the memory unit to perform operations such as writing and reading data.
  • At least two sequentially stacked memory structure layers 120 are located on the control circuit layer 110 , that is, at least two memory structure layers 120 are located on the surface of the control circuit layer 110 away from the substrate 100 , and are stacked along the Z direction.
  • the storage structure layer 120 is used to perform operations such as writing and reading data according to the control signal sent by the control circuit layer 110 .
  • Figure 2 shows a top view of a storage structure layer 120.
  • Each storage structure layer 120 includes a plurality of storage blocks 121 arranged in an array.
  • the storage blocks 121 here can be memory array tiles (Memory Array Tile, MAT).
  • the memory block 121 may include a plurality of parallel word lines WL extending along a first direction, where the first direction may be the X direction, and the first direction is parallel to the surface of the substrate 100 .
  • the word line WL here can be a local word line (Local Word Line), and one word line WL can connect the selection transistors of multiple memory cells in the memory block 121 in its extension direction, so as to control the selection transistor according to the control circuit layer 110
  • the control signal sent turns multiple selection transistors on or off to complete operations such as writing and reading data.
  • each memory structure layer 120 can be formed on the control circuit layer 110 in sequence without being limited by process processes such as conductive plugs, shallow trench isolation (Shallow Trench Isolation, STI), metal silicide, etc., so memory can be saved. 10 manufacturing cost, and ensures better performance of each transistor in the control circuit and memory block.
  • FIG. 1 there are openings 122 between adjacent memory blocks 121 in the same memory structure layer 120 .
  • the adjacent storage blocks 121 here may refer to two adjacent storage blocks 121 in the X direction, or may also be two adjacent storage blocks 121 in the Y direction.
  • the openings 122 located in different memory structure layers 120 penetrate each other, that is, the projection of each opening 122 in the Z direction on the substrate 100 at least partially overlaps, thereby forming a channel structure that runs through multiple memory structure layers 120 .
  • Each word line WL in at least one storage structure layer 120 is connected to the control circuit layer 110 through a through opening 122.
  • each storage structure layer 120 located at the opening 122 can be used as a lead-out area for the word line WL, which facilitates the convenience of each layer.
  • the plurality of word lines WL in are connected to the control circuits in the control circuit layer 110, thereby simplifying the wiring design and manufacturing process.
  • the lead-out area of the word line WL occupies a smaller area, further improving the integration level of the memory 10 .
  • the widths of the openings 122 located in different memory structure layers 120 gradually decrease from the upward direction of the substrate 100 .
  • the width of the opening 122 in each memory structure layer 120 decreases layer by layer from the upward direction of the substrate 100.
  • the width of the opening 122 refers to the X direction or the Y direction.
  • the edge of each storage structure layer 120 at the opening 122 is stepped, and the length of the word line WL in each storage structure layer 120 at the opening 122 increases layer by layer from bottom to top, so that the word line WL can be directly connected from where it is.
  • the lower surface of the memory structure layer 120 is led out and connected to the control circuit layer 110, which simplifies the manufacturing process of the memory 10 and reduces the horizontal area occupied by the word line WL lead-out area.
  • the memory 10 further includes: a plurality of connection structures 130 that connect the word line WL and the word line WL in a direction perpendicular to the surface of the substrate 100 .
  • Control circuit layer 110 a plurality of connection structures 130 that connect the word line WL and the word line WL in a direction perpendicular to the surface of the substrate 100 .
  • the memory 10 also includes a plurality of connection structures 130.
  • the materials of the connection structures 130 include but are not limited to conductive materials such as copper, tungsten, and doped polysilicon.
  • the connection structure 130 has a portion extending along the Z direction, and is used to connect the word lines WL in each memory structure layer 120 with the control circuit layer 110 along the Z direction, so that the control circuit layer 110 can control multiple memories through the word lines WL.
  • the on and off transistors in the unit are selected to realize the reading and writing operations of data.
  • the memory further includes: a plurality of compensation resistors correspondingly connected to each of the connection structures, and the resistance of the compensation resistor is inversely proportional to the length of the connection structure.
  • each connection structure may also be connected to a compensation resistor.
  • word lines located in different storage structure layers can be connected to the control circuit layer through connection structures of different lengths, which results in the control circuit layer having different driving capabilities for the word lines in each storage structure layer.
  • a compensation resistor connected to each connection structure can be set, and the resistance of the compensation resistor is inversely proportional to the length of the connection structure. That is to say, the shorter the connection structure, the greater the resistance of the compensation resistor, so that the connection structure connected to the word line in each memory structure layer is basically consistent with the total resistance of the compensation resistor, so as to realize the control circuit layer's control of each word line.
  • the driving capabilities are basically the same. It can be understood that the resistance of the compensation resistor can also be determined by the length of the connection structure and the length of the word line to further ensure that the control circuit layer has consistent driving capabilities for the word lines in each storage structure layer.
  • the opening 122 is located between adjacent storage blocks 121 in a first direction
  • the connection structure 130 includes: a first connection structure 131, the first connection structure 131 passes through at least one of the openings 122 in a direction perpendicular to the surface of the substrate 100; the word line WL in the storage structure layer 120 located above the bottom storage structure layer 120 is connected to the control circuit layer 110 through the first connection structure 131; a second connection structure 132, located between the bottom storage structure layer 120 and the control circuit layer 110; the word line WL in the bottom storage structure layer 120 is connected to the control circuit layer 110 through the second connection structure 132.
  • the opening 122 may be located between two adjacent storage blocks 121 in the X direction.
  • the connection structure 130 includes a first connection structure 131 and a second connection structure 132 .
  • the first connection structure 131 penetrates at least one opening 122 along the Z direction, that is, the portion of the first connection structure 131 extending along the Z direction is located in the plurality of through openings 122 .
  • the word lines WL in each memory structure layer 120 located above the bottom memory structure layer 120 can be connected to the control circuit layer 110 through the first connection structure 131 and through the plurality of openings 122 . That is to say, the word line WL in the storage structure layer 120 above the bottom layer can be connected to the first connection structure 131 in the stepped word line lead-out area.
  • This connection method is relatively simple and helps to simplify the manufacturing process.
  • the second connection structure 132 is located between the lowest storage structure layer 120 and the control circuit layer 110, and directly connects the word line WL in the lowest storage structure layer 120 to the control circuit layer 110. That is to say, the second connection structure 132 may not be located in the opening 122 , and the word line WL in the lowest storage structure layer 120 may directly pass through the second connection structure 132 and approach the control circuit layer 110 from the lowest storage structure layer 120 The surface of one side is led out and connected to the control circuit layer 110 . It can be understood that since the second connection structure 132 does not pass through the opening 122, its length is shorter, which is beneficial to simplifying the manufacturing process and saving costs.
  • the first connection structure 131 is connected to the control circuit layer 110 from under the word line WL through the opening 122 in a direction perpendicular to the substrate 100; or, the first connection The structure 131 extends from an end of the word line WL close to the opening 122 to the opening 122 along the first direction, and is connected to the control circuit layer through the opening 122 in a direction perpendicular to the substrate 100 110.
  • the first connection structure 131 can be connected to the word line WL along the Z direction; the first connection structure 131 can also be connected to an end of the word line WL close to the opening 122 along the X direction.
  • multiple memory blocks 121 can be staggered and stacked in the Z direction.
  • the first connection structure 131 can be directly connected below the word line WL, and through the A plurality of openings 122 are connected to the control circuit layer 110 .
  • the projections of the multiple memory blocks 121 stacked in the Z direction on the substrate 100 can overlap, that is, the multiple memory blocks 121 are stacked without misalignment.
  • the first connection structure can connect one end of the word line WL close to the opening 122 , that is, the first connection structure can first extend into the opening 122 along the X direction, and then be bent and vertically connected to the control circuit through a plurality of through openings 122 Layer 110. It is worth noting that the extending direction and bending manner of the first connecting structure are not limited to those shown in the drawings.
  • the first connection structure 131 includes: a first conductor 133 parallel to the surface of the substrate 100 ; a first conductor 133 of the first conductor 133 .
  • One end 133a is connected to the word line WL in the memory structure layer 120, and the second end 133b of the first conductor 133 is located in the opening 122 of the memory structure layer 120 where the first end 133a is located;
  • Two conductors 134 pass through at least one of the openings 122 , and the second conductors 134 connect the second end 133 b of the first conductor 133 and the control circuit layer 110 .
  • the first connection structure 131 includes a first conductive wire 133 and a second conductive wire 134.
  • the first conductor 133 may be parallel to the surface of the substrate 100, and the first end 133a of the first conductor 133 is connected to the word line WL, and the second end 133b is located in the opening 122 of the same memory structure layer 120.
  • the second end 133b of 133 is connected to the second conductive line 134, and the word line WL is connected to the control circuit layer 110 via the first conductive line 133 and the second conductive line 134.
  • the first conductor 133 here is used to extend the word line WL into the opening 122 in the horizontal direction, so that the word line WL is connected to the control circuit layer 110 through the second conductor 134 penetrating at least one opening 122 .
  • the first connection structure 131 may not have the first conductor 133 .
  • the word line WL can be directly connected to the second conductive line 134 through the surface of the memory structure layer 120 on the side close to the substrate 100 , that is, the word line WL does not pass through the opening 122 in the memory structure layer 120 where the word line WL is located, so that The wiring design of the memory 10 is further simplified.
  • the second conductor 134 includes: a first portion 135 located within at least one of the openings 122 , the first portion 135 being perpendicular to the surface of the substrate 100 ;
  • the first part 135 is connected to the second end 133b of the first conductor 133;
  • the second part 136 is located below the lowest storage structure layer 120;
  • the second part 136 is parallel to the surface of the substrate 100 , the second part 136 connects the first part 135 and the control circuit layer 110 .
  • the second conductor 134 includes a first portion 135 and a second portion 136 .
  • the first part 135 is located in the opening 122 and extends along the Z direction. It can be understood that the first part 135 can be connected to the second end 133b of the first wire 133, or can be directly in the storage structure layer 120 close to the substrate 100.
  • the surface is connected to word line WL.
  • the second part 136 is located below the bottom memory structure layer 120 and connects the first part 135 and the control circuit layer 110. That is to say, the second part 136 can extend in the horizontal direction, thereby changing the connection between the second conductor 134 and the control circuit layer 110.
  • the contact position of the circuit layer 110 realizes flexible connection between the word line WL and the control circuit layer 110.
  • control circuit layer 110 includes: a plurality of control blocks 111 connected correspondingly to each of the storage blocks 121 .
  • the storage block 121 may be connected to the control block 111 in the control circuit layer 110.
  • the control block 111 may perform operations such as writing and reading on multiple storage cells in the storage block 121 through word lines, bit lines and other connection structures. It is understood that the connection relationship between the control block 111 and the storage block 121 may be a one-to-one relationship, or a one-to-many, many-to-one or many-to-many relationship.
  • the area where the control block 111 is located at least partially coincides with the projection area of the memory block 121 connected to the control block 111 on the control circuit layer 110 . That is to say, at least part of the area of each control block 111 is located below the storage block 121 to which it is connected, thereby facilitating wiring planning and improving the space utilization of each connection structure.
  • the memory block 121 includes: a plurality of memory cells 123 arranged in an array, and each of the word lines WL connects a plurality of the memory cells 123 arranged along the first direction.
  • Memory unit 123; the memory unit 123 in at least one of the memory structure layers 120 is connected to the control block 111 through the word line WL through the through opening 122.
  • each word line WL in the memory block 121 connects a plurality of memory cells 123 arranged along the first direction, that is, the X direction.
  • the memory cells 123 in at least one memory structure layer 120 can be connected to the control block 111 through the word line WL, and the connection structure in the above embodiment, through the through opening 122, so that one control block 111 can be connected to the control block 111 through a word line WL.
  • the selection transistors in the plurality of memory cells 123 are controlled to be turned on or off.
  • each storage block 121 may be individually connected to and controlled by the control block 111 .
  • the word line WL of one memory block 121 may be independent and not connected to the word lines WL in other memory blocks 121.
  • a plurality of memory blocks 121 arranged in parallel may share a word line WL.
  • the memory 10 further includes: a bit line structure layer 140 located between the control circuit layer 110 and at least two of the memory structure layers. 120; the bit line structure layer 140 includes a plurality of bit lines BL extending along the second direction; there is an angle between the second direction and the first direction, and the second direction is parallel to the The surface of the substrate 100; each bit line BL connects a plurality of groups of memory cells 123 arranged along the second direction, wherein each group of memory cells 123 is connected by a first connection line along a direction perpendicular to the substrate.
  • a plurality of storage units 123 are stacked in the direction of the surface 100 .
  • the bit line structure layer 140 is located between the bottommost storage structure layer 120 and the control circuit layer 110, and the bit line structure layer 140 has a plurality of bit lines BL extending along the second direction.
  • the second direction here can be the Y direction, or other directions that form a certain angle with the X direction.
  • At least two memory structure layers 120 have multiple groups of memory cells 123 arranged along the Y direction.
  • the group of memory cells 123 here refers to a plurality of memory cells 123 stacked along the Z direction and connected by the first connection lines 141 . That is to say, multiple memory cells 123 in each group of memory cells are located in different memory structure layers 120 and are connected together by first connection lines 141 extending along the Z direction.
  • the selection transistors in two adjacent memory cells 123 in the same memory structure layer 120 in the Y direction are connected to the same first connection line 141 , and multiple first connection lines located on the same straight line in the Z direction are connected to the same first connection line 141 .
  • the connection line 141 is connected to the same bit line BL; the bit line BL is connected to the control circuit layer 110 through the second connection line 142 .
  • first connection lines 141 penetrating the memory structure layer 120 may be connected to the same bit line BL.
  • the same bit line BL can provide electrical connection to multiple groups of memory cells 123 arranged in the Y direction.
  • each group of memory cells 123 is a plurality of memory cells 123 connected to the same first connection line 141 .
  • the memory cells 123 in the embodiment of the present disclosure are arranged in a three-dimensional structural array on the substrate 100 and the control circuit layer 110 . That is, the memory cell 123 connected to the bit line BL includes a plurality of memory cells 123 on one surface.
  • each memory cell 123 With respect to the memory cells 123 connected to the same bit line BL, individual control of each memory cell 123 can be achieved by individually strobing the selection transistor of each memory cell 123 .
  • the control circuit layer 110 may include circuits and devices that connect the bit lines BL and perform read and write operations on each storage unit 123 through the bit lines BL. Since the bit lines BL extend along a first direction parallel to the surface of the substrate 100, a second connection line 142 perpendicular to the substrate is also required to be connected between the bit lines BL and the control circuit layer 110.
  • control block 111 includes: a first control block connected to the word line WL; and a second control block connected to the bit line BL.
  • the control block 111 may include a first control block connected to the word line WL.
  • the first control block here includes but is not limited to the SWD in FIG. 6 .
  • the SWD may be used to drive the local memory block of each memory block 121 .
  • the word line WL is used to provide a strobe signal to each memory cell 123 .
  • the sub-word line connected by SWD is a concept for the local word line of the memory block 121, that is, the above-mentioned word line WL.
  • Global Word Line Global Word Line
  • one SWD can be connected to one word line WL and used to turn on the selection transistor of each memory cell 123 connected to the word line WL.
  • the drive signal only needs to be provided through the SWD corresponding to the target memory unit, and the word line WL connected thereto is turned on to the word line WL where the target memory unit is located. storage unit 123. At the same time, the corresponding data signal is provided to the bit line connected to the target memory unit, thereby achieving the purpose of independent read and write operations on the target memory unit.
  • the control block 111 may include a second control block connected to the bit line BL.
  • the second control block here includes but is not limited to SA in Figure 7.
  • SA is also called a sense amplifier and is used to store During the reading and writing process, the unit 123 amplifies the small potential difference between the target bit line and the reference bit line.
  • the target bit line may be the bit line BL connected to the selection transistor of the memory cell 123 currently being read or written
  • the reference bit line may be any other bit line BL connected to the same SA as the target bit line.
  • the memory cell 123 connected to the reference bit line does not participate in data reading and writing at this time.
  • every two bit lines BL can be connected to the same SA. When reading and writing data to the memory unit 123 connected to the first bit line BL, this bit line is the target bit line.
  • the other bit line BL can be used as a reference bit line.
  • the selection transistor of the memory unit 123 when reading data from the memory unit 123, the selection transistor of the memory unit 123 is turned on. At this time, the charge stored in the memory unit 123 will affect the potential of the target bit line connected to it, thereby causing the target bit line of the entry to be A small potential difference is generated between the bit line and the reference bit line. SA amplifies the potential difference and reflects it on the target bit line and the reference bit line. In this way, data can be read by detecting the voltage difference between the target bit line and the reference bit line.
  • bit line BL may be connected to the SA in the control block 111 through the second connection line 142 .
  • bit lines BL connecting two adjacent memory blocks 121 in the second direction are connected to the same second control block.
  • bit lines BL located in the same memory structure layer 120 and connected to two adjacent memory blocks 121 in the Y direction may be connected to the same SA.
  • the bit line BL connected to the other memory block 121 serves as the reference bit line
  • the bit line connected to the memory block 121 in the working state serves as the target bit line of SA.
  • the two storage blocks can be alternately performed for reading and writing operations, improving the usage efficiency of SA and reducing the area occupied by SA.
  • two adjacent memory blocks 121 in different memory structure layers 120 can also be connected to the same SA.
  • the bit lines connected to the two memory blocks 121 cannot be shared. Instead, two sets of bit lines are used. , and serve as the target bit line and reference bit line respectively during operation.
  • the memory further includes: a data input and output (I/O) module connected to the second control block, and the data input and output module is configured to perform data processing on the storage unit through the second control block. writing or reading.
  • I/O data input and output
  • Data input and output modules can be configured to exchange data with components other than memory.
  • the data input and output module can be connected to the SA, and perform operations such as reading and writing data on the storage unit through the SA.
  • the memory further includes: a power module connected to a plurality of the control blocks for providing power signals; the power module is located in the substrate, and the power module is connected to the control circuit Layers are within the same structural layer.
  • the power module can generate different voltages to meet the needs of various devices in the memory during write, read, etc. operations.
  • the power module and the control circuit layer are located at substantially the same depth in the substrate to optimize the device and circuit layout of the memory.
  • control circuit layer 110 further includes: a global control circuit 112 ; the global control circuit 112 is connected to the plurality of control blocks 111 ; the global control circuit 112 is at least used to provide control signals to the plurality of control blocks 111 .
  • the global control circuit 112 may connect part of the memory blocks 121 or all memory blocks 121 of the memory 10 through multiple control blocks 111 and be used to provide control signals to the multiple memory blocks 121 .
  • the global control circuit 112 includes: a global word line driver module, connected to a plurality of the first control blocks, and configured to provide a plurality of the memory blocks 121 connected to a plurality of the first control blocks. word line control signals.
  • the global word line driver module is connected to multiple first control blocks, and is connected to multiple word lines WL in multiple memory blocks 121 through the multiple first control blocks.
  • the global word line driver module can also be connected to to the row decoder to control the on and off of the selection transistors in the plurality of memory blocks 121.
  • the global control circuit 112 may further include a global sense amplifier circuit (Global Sense Amplifier), which may be connected to multiple second control blocks, and connected to multiple bit lines BL through multiple second control blocks, so as to control the storage cells 123 in multiple storage blocks 121 to perform operations such as reading and writing. It is understandable that the global control circuit 112 may also include a row/column decoder, a fuse repair circuit, a buffer, etc.
  • Global Sense Amplifier Global Sense Amplifier
  • the area where the global control circuit 112 is located is outside the projection area of any memory block 121 on the control circuit layer 110 .
  • the global control circuit 112 may be located in a peripheral area of the control circuit layer 110 , that is, outside the projection area of the storage structure layer 120 .
  • the global control circuit 112 may connect multiple control blocks 111 to provide control signals to the multiple control blocks 111 .
  • the global control circuit 112 may also be located between some control blocks 111 , for example, in a gap between two control blocks 111 among multiple parallel control blocks 111 .
  • Multiple control blocks 111 connected to the global control circuit 112 can be controlled in time-sharing or synchronously, depending on the functions and connection relationships between the global control circuit and the corresponding control blocks 111, which are not limited here.
  • an embodiment of the present disclosure also provides a storage system 20, including: the memory 10 described in any of the above embodiments; and a storage controller 21.
  • the memory system 20 can be any kind of memory chip.
  • the memory controller 21 can control the memory 10 to perform various operations according to signals sent by the host. It can be understood that due to the stacked storage structure layer and control circuit layer, the integration level of the memory system 20 is relatively high; in addition, the through openings in the memory 10 facilitate the word lines in each storage structure layer to be drawn out and connected to Control circuit layer, simplifying wiring design and manufacturing process.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the units is only a logical function division.
  • the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.
  • the units described above as separate components may or may not be physically separated; the components shown as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure can be all integrated into one processing unit, or each unit can be separately used as a unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • At least two storage structure layers are stacked on the control circuit layer in sequence, and each word line in at least one storage structure layer is connected to the control circuit layer through a through opening.
  • the stacked storage structure layer and the control circuit layer occupy a smaller area, which improves the integration of the memory; on the other hand, the through opening facilitates the word lines in each storage structure layer to be drawn out and connected to the control circuit. layer, simplifying the wiring design and manufacturing process of the memory.

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Abstract

本公开实施例提供一种存储器和存储***，所述存储器包括：衬底；位于所述衬底内的控制电路层；所述控制电路层中包括所述存储器的至少部分控制电路；至少两个存储结构层；所述至少两个存储结构层依次堆叠在所述控制电路层上；所述存储结构层包括多个阵列排布的存储块；所述存储块包括沿第一方向延伸的多条平行的字线；所述第一方向平行于所述衬底的表面；其中，位于同一存储结构层中相邻的存储块之间具有开口；位于不同存储结构层中的所述开口相互贯通；至少一个所述存储结构层中的各字线通过贯通的所述开口连接至所述控制电路层。

Description

存储器和存储***
相关申请的交叉引用
本公开基于申请号为202211139262.7、申请日为2022年09月19日、发明名称为“存储器和存储***”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种存储器和存储***。
背景技术
随着当今科学技术的不断发展，半导体器件被广泛地应用于各种电子设备和电子产品。其中，动态随机存取存储器(Dynamic Random Access Memory，DRAM)作为一种易失性存储器，是计算机中常用的半导体存储器件。
随机存取存储器中具有由许多重复的存储单元组成的存储阵列。每个存储单元包括选择晶体管和连接至选择晶体管的存储节点，存储节点的不同状态用于代表存储信息，即“0”或“1”。为了提高存储器的存储能力，要求半导体器件具有更高的存储密度和更小的特征尺寸。如何在单位面积内集成更多的存储单元并减小各个器件的占用面积，以及如何简化存储器的布线设计和制造工艺，成为了业界亟待解决的问题。
发明内容
有鉴于此，本公开实施例提供了一种存储器和存储***。
第一方面，本公开实施例提供了一种存储器，包括：衬底；位于所述衬底内的控制电路层；所述控制电路层中包括所述存储器的至少部分控制电路；至少两个存储结构层；所述至少两个存储结构层依次堆叠在所述控制电路层上；所述存储结构层包括多个阵列排布的存储块；所述存储块包括沿第一方向延伸的多条平行的字线；所述第一方向平行于所述衬底的表面；其中，位于同一存储结构层中相邻的存储块之间具有开口；位于不同存储结构层中的所述开口相互贯通；至少一个所述存储结构层中的各字线通过贯通的所述开口连接至所述控制电路层。
在一些实施例中，位于不同所述存储结构层中的所述开口的宽度由所述衬底向上的方向依次减小。
在一些实施例中，所述存储器还包括：多个连接结构，所述连接结构沿垂直于所述衬底表面的方向连接所述字线和所述控制电路层。
在一些实施例中，所述存储器还包括：与每个所述连接结构对应连接的补偿电阻，所述补偿电阻的阻值与所述连接结构的长度成反比。
在一些实施例中，所述开口位于在第一方向上相邻的存储块之间，所述连接结构包括：第一连接结构，所述第一连接结构在垂直于所述衬底表面的方向上贯穿至少一个所述开口；位于最底层的所述存储结构层上方的所述存储结构层中的所述字线通过所述第一连接结构连接至所述控制电路层；第二连接结构，位于最底层的所述存储结构层与所述控制电路层之间；最底层的所述存储结构层中的所述字线通过所述第二连接结构连接至所述控制电路层。
在一些实施例中，所述第一连接结构由所述字线下通过所述开口沿垂直所述衬底的方向连接至所述控制电路层；或者，所述第一连接结构由所述字线靠近所述开口的一端沿所述第一方向延伸至所述开口，并通过所述开口沿垂直所述衬底的方向连接至所述控制电路层。
在一些实施例中，所述控制电路层包括：与每个所述存储块对应连接的多个控制块。
在一些实施例中，所述存储块包括：多个阵列排布的存储单元，每条所述字线连接多个沿所述第一方向排布的所述存储单元；至少一个所述存储结构层中的所述存储单元通过所述字线经由贯通的所述开口连接至所述控制块。
在一些实施例中，所述存储器还包括：位线结构层，位于所述控制电路层与至少两个所述存储结构层之间；所述位线结构层中包括多条沿第二方向延伸的位线；所述第二方向与所述第一方向之间具有夹角，所述第二方向平行于所述衬底的表面；每条所述位线连接沿第二方向排布的多组存储单元，其中，每组存储单元是通过第一连接线连接的沿垂直于所述衬底表面的方向上堆叠设置的多个存储单元。
在一些实施例中，所述控制块包括：与所述字线连接的第一控制块；与所述位线连接的第二控制块。
在一些实施例中，在第二方向上相邻的两个所述存储块连接的所述位线连接至同一个所述第二控制块。
在一些实施例中，所述存储器还包括：数据输入输出模块，连接所述第二控制块，所述数据输入输出模块配置为通过所述第二控制块对存储单元进行数据的写入或读取。
在一些实施例中，所述存储器还包括：电源模块，连接多个所述控制块，用于提供电源信号；所述电源模块位于所述衬底中，且所述电源模块与所述控制电路层位于同一结构层内。
在一些实施例中，所述控制电路层还包括：全局控制电路；所述全局 控制电路与多个所述控制块连接；所述全局控制电路至少用于向多个所述控制块提供控制信号。
在一些实施例中，所述全局控制电路包括：全局字线驱动模块，连接多个所述第一控制块，用于提供多个所述第一控制块连接的所述存储块中多条字线的控制信号。
在一些实施例中，所述全局控制电路所在的区域位于任意的所述存储块在所述控制电路层上的投影区域以外。
第二方面，本公开实施例提供了一种存储***，包括：上述实施例中任一所述的存储器；存储控制器。
在本公开实施例提供的存储器中，至少两个存储结构层依次堆叠在控制电路层上，至少一个存储结构层中的各字线通过贯通的开口连接至控制电路层。如此，一方面，堆叠设置的存储结构层与控制电路层的占用面积较小，提高了存储器的集成度；另一方面，贯通的开口便于各存储结构层中的字线引出并连接至控制电路层，简化了存储器的布线设计和制造工艺。
附图说明
图1为本公开实施例提供的一种存储器的示意图；
图2为本公开实施例提供的一种存储器中存储结构层的俯视图；
图3为本公开实施例提供的一种存储器中连接结构的示意图；
图4为本公开实施例提供的一种存储器中控制块的示意图；
图5为本公开实施例提供的一种存储器中位线结构层的示意图；
图6为本公开实施例提供的一种存储器中子字线驱动电路的示意图；
图7为本公开实施例提供的一种存储器中感测放大电路的示意图；
图8为本公开实施例提供的一种存储器中全局控制电路的示意图；
图9为本公开实施例提供的一种存储***的示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在一些实施例中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即这里可以不描述实际实施例的全部特征，不详细描述公知的功能和结构。
一般地，术语可以至少部分地从上下文中的使用来理解。例如，至少部分地取决于上下文，如本文中所用的术语“一个或多个”可以用于以单数意义描述任何特征、结构或特性，或者可以用于以复数意义描述特征、结构或特性的组合。类似地，诸如“一”或“所述”的术语同样可以被理解为传达单数用法或传达复数用法，这至少部分地取决于上下文。另外，属于“基于”可以被理解为不一定旨在传达排他的一组因素，并且可以替代地允许存在不一定明确地描述的附加因素，这同样至少部分地取决于上下文。
除非另有定义，本文所使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
如图1和图2所示，本公开实施例提供了一种存储器10，包括：
衬底100；位于所述衬底100内的控制电路层110；所述控制电路层110中包括所述存储器10的至少部分控制电路；至少两个存储结构层120；所述至少两个存储结构层120依次堆叠在所述控制电路层110上；所述存储结构层120包括多个阵列排布的存储块121；所述存储块121包括沿第一方向延伸的多条平行的字线WL；所述第一方向平行于所述衬底100的表面；其中，位于同一存储结构层120中相邻的存储块121之间具有开口122；位于不同存储结构层120中的所述开口122相互贯通；至少一个所述存储结构层120中的各字线WL通过贯通的所述开口122连接至所述控制电路层110。
在本公开实施例中，存储器10可以包括但不限于DRAM、静态随机存取存储器(Static Random Access Memory，SRAM)、铁电随机存取存储器(Ferroelectric Random Access Memory，FRAM)、磁性随机存取存储器(Magnetoresistive Random Access Memory，MRAM)、相变随机存取存储器(Phase Change Random Access Memory，PCRAM)、阻变随机存取存储器(Resistive Random Access Memory，RRAM)、纳米随机存取存储器(Nano Random Access Memory，NRAM)等。其中，衬底100的材料可以包括单质半导体材料，例如硅(Si)、锗(Ge)等，或者化合物半导体材料，例如氮化镓(GaN)、砷化镓(GaAs)或磷化铟(InP)等，衬底100还可以是掺杂的，或者在衬底中包括掺杂区域和未掺杂区域。应当理解，图中为了 使得各层结构均能被清晰示出，可能造成各层结构的尺寸比例关系与实际结构不符。值得注意的是，本公开中的水平方向指的是平行于衬底100表面的方向，包括但不限于X方向和Y方向，而垂直方向指的是垂直于衬底100表面的方向，如Z方向。
示例性地，本公开实施例中的存储块可以由多个具有“1T1C”(一个选择晶体管T与一个存储电容C)结构的存储单元构成。选择晶体管用于控制存储单元与控制电路之间的信号通断，在向存储单元写入数据以及读取数据时需要将选择晶体管切换为导通状态，以实现存储电容与外接的电荷传递。存储电容则基于存储电荷达到存储数据的作用，由于存储电容存储的电荷不同的情况下，其电极表现出的电位不同，故可以通过切换存储电容的存储状态，实现二进制数据的读写。例如，当存储电容处于充电后的状态时表示数据“1”，当存储电容处于放电后的状态(未充电的状态)时表示数据“0”。通过检测存储电容的电极上的电压，可以确定其状态为充电后的状态或者放电后(未充电的状态)的状态，进而实现数据的读取。
在一些实施例中，存储器中的控制电路与多个阵列排布的存储块位于平行于衬底表面的同一平面内，且控制电路在水平方向上位于多个阵列排布的存储块的周围，这就使得存储器在水平方向上的占用面积较大，集成度较低。可以理解的是，这种情况下为了获得更高的存储密度，需要进一步地缩小存储单元的尺寸，制程工艺难度较大。此外，由于控制电路与多个存储块在垂直方向上的高度差较大，且控制电路与多个存储块在同一道工艺中形成，故控制电路中的导电插塞(Local Interconnect Contact，Licon)高度较高，接触电阻较大，会影响晶体管的驱动电流，使得存储器的性能较差。
在本公开实施例中，如图1所示，控制电路层110位于衬底100内，控制电路层110中具有存储器10的至少部分控制电路。示例性地，控制电路层110中包括但不限于子字线驱动电路(Sub Wordline Driver，SWD)、感测放大电路(Sense Amplifier，SA)、行解码器、列解码器、熔丝修复电路、电源模块、数据输入输出电路等。控制电路层110可以用于解码、检测存储单元以及控制存储单元进行写入和读取数据等操作。
至少两个依次堆叠的存储结构层120位于控制电路层110上，即至少两个存储结构层120位于控制电路层110远离衬底100一侧的表面，且沿Z方向堆叠。存储结构层120用于根据控制电路层110发出的控制信号，进行数据的写入和读取等操作。如图2所示为一个存储结构层120的俯视图，每一个存储结构层120中包括多个阵列排布的存储块121，这里的存储块121可以为内存数组片(Memory Array Tile，MAT)。存储块121中可以包括沿第一方向延伸的多条平行的字线WL，这里的第一方向可以为X方向，且第一方向平行于衬底100的表面。示例性地，这里的字线WL可以为本地字线(Local Word Line)，一条字线WL可以连接存储块121中位于其延 伸方向上的多个存储单元的选择晶体管，从而根据控制电路层110发出的控制信号，使得多个选择晶体管导通或截止，以完成数据的写入和读取等操作。如此，至少两个存储结构层120在垂直于衬底100表面的方向上堆叠于控制电路层110上，从而构成了三维立体的存储结构，可以在不进一步缩小存储单元尺寸的前提下，减小存储器10在水平方向上占用的面积，有利于提高集成度。另一方面，各个存储结构层120可以依次形成在控制电路层110上，不会受到导电插塞、浅槽隔离(Shallow Trench Isolation，STI)、金属硅化物等工艺制程的限制，因此可以节省存储器10的制造成本，并保证控制电路和存储块中的各个晶体管具有较好的性能。
在本公开实施例中，如图1所示，位于同一存储结构层120中相邻的存储块121之间具有开口122。可以理解的是，这里相邻的存储块121可以指在X方向相邻的两个存储块121，也可以是在Y方向上相邻的两个存储块121。位于不同存储结构层120中的开口122相互贯通，即在Z方向上的各个开口122在衬底100上的投影至少部分重合，从而形成贯穿多个存储结构层120的通道结构。至少一个存储结构层120中的各字线WL通过贯通的开口122连接至控制电路层110，由此，各个存储结构层120位于开口122处的区域可以作为字线WL的引出区域，便于各层中的多条字线WL连接至控制电路层110中的控制电路，从而简化了布线设计和制造工艺。另外，字线WL的引出区域占用面积较小，进一步地提高了存储器10的集成度。
在一些实施例中，如图3所示，位于不同所述存储结构层120中的所述开口122的宽度由所述衬底100向上的方向依次减小。
在本公开实施例中，在Z方向上，各存储结构层120中的开口122的宽度由衬底100向上的方向逐层减小，这里开口122的宽度指的是在X方向或在Y方向上相邻两个存储块121之间的距离。如此，各存储结构层120在开口122处的边缘呈阶梯状，且各存储结构层120中的字线WL在开口122处的长度从下至上逐层增加，以便于字线WL可以直接从所在存储结构层120的下表面引出并连接至控制电路层110，简化了存储器10的制造工艺，并减小字线WL引出区域在水平方向上的占用面积。
在一些实施例中，如图3所示，所述存储器10还包括：多个连接结构130，所述连接结构130沿垂直于所述衬底100表面的方向连接所述字线WL和所述控制电路层110。
在本公开实施例中，存储器10中还包括多个连接结构130，连接结构130的材料包括但不限于铜、钨、掺杂多晶硅等导电材料。连接结构130中具有沿Z方向延伸的部分，并用于沿Z方向将各存储结构层120中的字线WL与控制电路层110连接，从而使得控制电路层110可以通过字线WL控制多个存储单元中选择晶体管的导通和截止，以实现数据的读取和写入操作。
在一些实施例中，所述存储器还包括：与每个所述连接结构对应连接的多个补偿电阻，所述补偿电阻的阻值与所述连接结构的长度成反比。
在本公开实施例中，每个连接结构还可以连接补偿电阻。可以理解的是，位于不同存储结构层中的字线，可以通过不同长度的连接结构连接至控制电路层，这就使得控制电路层对各个存储结构层中的字线的驱动能力不同。由此，可以设置连接每个连接结构的补偿电阻，且补偿电阻的阻值与连接结构的长度成反比。也就是说，连接结构越短，补偿电阻的阻值越大，从而使得各个存储结构层中字线所连接的连接结构与补偿电阻的总阻值基本一致，以实现控制电路层对每条字线的驱动能力基本相同。可以理解的是，补偿电阻的阻值还可以由连接结构的长度和字线的长度共同决定，进一步确保控制电路层对各存储结构层中字线的驱动能力一致。
在一些实施例中，如图3所示，所述开口122位于在第一方向上相邻的存储块121之间，所述连接结构130包括：第一连接结构131，所述第一连接结构131在垂直于所述衬底100表面的方向上贯穿至少一个所述开口122；位于最底层的所述存储结构层120上方的所述存储结构层120中的所述字线WL通过所述第一连接结构131连接至所述控制电路层110；第二连接结构132，位于最底层的所述存储结构层120与所述控制电路层110之间；最底层的所述存储结构层120中的所述字线WL通过所述第二连接结构132连接至所述控制电路层110。
在本公开实施例中，开口122可以位于在X方向上相邻的两个存储块121之间。连接结构130包括第一连接结构131和第二连接结构132。其中，第一连接结构131沿Z方向贯穿至少一个开口122，即第一连接结构131中沿Z方向延伸的部分位于贯通的多个开口122内。如此，位于最底层的存储结构层120上方的各存储结构层120中的字线WL可以由第一连接结构131，通过贯通的多个开口122连接至控制电路层110。也就是说，最底层以上的存储结构层120中的字线WL可以在阶梯状的字线引出区域连接至第一连接结构131，这种连接方式较为简单，有利于简化制造工艺。
第二连接结构132则位于最底层的存储结构层120与控制电路层110之间，并将最底层的存储结构层120中的字线WL直接连接至控制电路层110。也就是说，第二连接结构132可以不位于开口122内，最底层的存储结构层120中的字线WL可以直接通过第二连接结构132，从最底层的存储结构层120靠近控制电路层110一侧的表面引出，并连接至控制电路层110。可以理解的是，由于第二连接结构132不经过开口122，故长度较短，有利于简化制造工艺和节省成本。
在一些实施例中，所述第一连接结构131由所述字线WL下通过所述开口122沿垂直所述衬底100的方向连接至所述控制电路层110；或者，所述第一连接结构131由所述字线WL靠近所述开口122的一端沿所述第一方向延伸至所述开口122，并通过所述开口122沿垂直所述衬底100的方向 连接至所述控制电路层110。
在本公开实施例中，如图3所示，第一连接结构131可以沿Z方向与字线WL连接；第一连接结构131也可以沿X方向与字线WL靠近开口122的一端连接。示例性地，如图3所示，在Z方向上，多个存储块121可以错位堆叠，此时，第一连接结构131可以直接连接在字线WL的下方，并通过该字线WL下方的多个开口122连接至控制电路层110。如图1所示，在Z方向上堆叠的多个存储块121在衬底100上的投影可以重合，即多个存储块121没有错位堆叠。此时，第一连接结构可以连接字线WL靠近开口122的一端，即第一连接结构可以先沿X方向延伸至开口122内，然后弯折并通过多个贯通的开口122垂直连接至控制电路层110。值得注意的是，第一连接结构的延伸方向和弯折方式不限于附图中所示出的情况。
在一些实施例中，如图3所示，所述第一连接结构131包括：第一导线133，所述第一导线133平行于所述衬底100的表面；所述第一导线133的第一端133a连接所述存储结构层120中的所述字线WL，所述第一导线133的第二端133b位于所述第一端133a所在的存储结构层120的所述开口122内；第二导线134，所述第二导线134贯穿至少一个所述开口122，所述第二导线134连接所述第一导线133的所述第二端133b和所述控制电路层110。
在本公开实施例中，第一连接结构131包括第一导线133和第二导线134。其中，第一导线133可以平行于衬底100的表面，且第一导线133的第一端133a与字线WL连接，第二端133b则位于同一存储结构层120的开口122内，第一导线133的第二端133b连接第二导线134，字线WL经由第一导线133和第二导线134连接至控制电路层110。可以理解的是，这里的第一导线133用于在水平方向上将字线WL延伸至开口122内，以便于字线WL通过贯穿至少一个开口122的第二导线134连接至控制电路层110。
在一些实施例中，第一连接结构131可以不具有第一导线133。示例性地，字线WL可以直接通过所在存储结构层120靠近衬底100一侧的表面连接至第二导线134，即字线WL不经过字线WL所在存储结构层120中的开口122，从而进一步地简化存储器10的布线设计。
在一些实施例中，如图3所示，所述第二导线134包括：第一部分135，位于至少一个所述开口122内，所述第一部分135垂直于所述衬底100的表面；所述第一部分135连接所述第一导线133的所述第二端133b；第二部分136，位于最底层的所述存储结构层120下方；所述第二部分136平行于所述衬底100的表面，所述第二部分136连接所述第一部分135和所述控制电路层110。
在本公开实施例中，第二导线134包括第一部分135和第二部分136。其中，第一部分135位于开口122内且沿Z方向延伸，可以理解的是，第 一部分135可以连接第一导线133的第二端133b，也可以直接在存储结构层120中靠近衬底100一侧的表面连接字线WL。第二部分136则位于最底层的存储结构层120的下方，并连接第一部分135和控制电路层110，也就是说，第二部分136可以在水平方向上延伸，从而改变第二导线134与控制电路层110的接触位置，实现字线WL与控制电路层110的灵活连接。
在一些实施例中，如图4所示，所述控制电路层110包括：与每个所述存储块121对应连接的多个控制块111。
在本公开实施例中，存储块121可以连接至控制电路层110中的控制块111。控制块111可以通过字线、位线及其他连接结构，对存储块121中的多个存储单元进行写入和读取等操作。可以理解的是，控制块111与存储块121的连接关系可以为一一对应的关系，也可以是一对多、多对一或者多对多等关系。
在一些实施例中，如图4所示，所述控制块111所在的区域与所述控制块111所连接的存储块121在所述控制电路层110上的投影区域至少部分重合。也就是说，每个控制块111的至少部分区域是位于其所连接的存储块121的下方，从而便于规划布线，提高各个连接结构的空间利用率。
在一些实施例中，如图4所示，所述存储块121包括：多个阵列排布的存储单元123，每条所述字线WL连接多个沿所述第一方向排布的所述存储单元123；至少一个所述存储结构层120中的所述存储单元123通过所述字线WL经由贯通的所述开口122连接至所述控制块111。
在本公开实施例中，存储块121中的每条字线WL连接沿第一方向，即X方向排布的多个存储单元123。至少一个存储结构层120中的存储单元123可以通过字线WL，以及上述实施例中的连接结构，经由贯通的开口122，连接至控制块111，从而使得一个控制块111可以通过一条字线WL控制多个存储单元123中选择晶体管的导通或者截止。在一些实施例中，每个存储块121可以单独与控制块111连接，并由该控制块111单独控制。
在一些实施例中，一个存储块121的字线WL可以是独立的，不与其他存储块121中的字线WL连接。在另一实施例中，并列排布的多个存储块121可以共用字线WL。
在一些实施例中，如图5所示为存储器10在YZ方向上的示意图，所述存储器10还包括：位线结构层140，位于所述控制电路层110与至少两个所述存储结构层120之间；所述位线结构层140中包括多条沿第二方向延伸的位线BL；所述第二方向与所述第一方向之间具有夹角，所述第二方向平行于所述衬底100的表面；每条所述位线BL连接沿第二方向排布的多组存储单元123，其中，每组存储单元123是通过第一连接线连接的沿垂直于所述衬底100表面的方向上堆叠设置的多个存储单元123。
在本公开实施例中，位线结构层140位于最底层的存储结构层120与控制电路层110之间，且位线结构层140中具有多条沿第二方向延伸的位 线BL。这里的第二方向可以为Y方向，也可以是与X方向呈一定夹角的其他方向。
至少两个存储结构层120中具有沿Y方向排布的多组存储单元123，这里的一组存储单元123指的是由第一连接线141连接的沿Z方向堆叠设置的多个存储单元123，也就是说，每组存储单元中的多个存储单元123位于不同的存储结构层120中，且由沿Z方向延伸的第一连接线141连接在一起。
在一些实施例中，同一存储结构层120中在Y方向上相邻的两个存储单元123中的选择晶体管连接至同一第一连接线141，而在Z方向上位于同一直线的多条第一连接线141连接在同一条位线BL上；位线BL则通过第二连接线142与控制电路层110连接。
可以理解的是，贯穿于存储结构层120的多条第一连接线141可以连接在同一条位线BL上。
同一条位线BL可以向沿Y方向排布的多组存储单元123提供电连接。这里，每组存储单元123即上述同一条第一连接线141所连接的多个存储单元123。
由于存储结构层120包括至少两层，因此，本公开实施例中的存储单元123是在衬底100以及控制电路层110上以三维的结构阵列排布的。也就是说，位线BL所连接的存储单元123包括一个面上的多个存储单元123。
相对于同一条位线BL连接的存储单元123，可以通过对每个存储单元123的选择晶体管进行单独选通，实现对每个存储单元123的单独控制。
控制电路层110中可以包括连接位线BL并通过位线BL对各存储单元123进行读写操作的电路及器件。由于位线BL沿平行于衬底100表面的第一方向延伸，故这里还需要垂直于衬底的第二连接线142连接在位线BL与控制电路层110之间。
在一些实施例中，如图6和图7所示，所述控制块111包括：与所述字线WL连接的第一控制块；与所述位线BL连接的第二控制块。
如图6所示，控制块111可以包括与字线WL连接的第一控制块，这里的第一控制块包括但不限于图6中的SWD，SWD可以用于驱动每个存储块121的本地字线WL，即用于提供对各存储单元123的选通信号。这里，SWD连接的子字线是针对存储块121的本地字线的概念，即上述字线WL。相对地，对于多个存储块121还可以有全局字线(Global Word Line)连接多条本地字线。
可以理解的是，一个SWD可以连接一条字线WL，并用于导通该字线WL连接的每个存储单元123的选择晶体管。
对于要进行读写的存储单元123，即目标存储单元，只需通过该目标存储单元对应的SWD提供驱动信号，通过其连接的字线WL导通该目标存储单元所在的字线WL连接的多个存储单元123。同时，对于该目标存储单元 连接的位线则提供相应的数据信号，从而达到对目标存储单元进行独立的读写操作的目的。
如图7所示，控制块111可以包括与位线BL连接的第二控制块，这里的第二控制块包括但不限于图7中的SA，SA又称为灵敏放大器，用于在对存储单元123进行读写的过程中将目标位线与参考位线上的小的电位差进行放大。这里，目标位线可以是当前进行读写的存储单元123的选择晶体管所连接的位线BL，参考位线则可以为与目标位线连接在同一SA上的其他任意一条位线BL。参考位线所连接的存储单元123此时不参与数据的读写。在本公开实施例中，可以每两条位线BL连接在同一个SA上，在对第一条位线BL连接的存储单元123进行数据读写时，这条位线则为目标位线，另一条位线BL则可以作为参考位线。
示例性地，在对存储单元123进行数据读取时，打开该存储单元123的选择晶体管，这时，存储单元123存储的电荷会对其连接的目标位线电位产生影响，进而使得该条目标位线与参考位线之间产生一个小的电位差。SA则将该电位差放大，并体现在目标位线与参考位线上。如此，通过检测目标位线与参考位线上的电压差就可以实现数据的读取。
这里，位线BL可以通过上述第二连接线142与控制块111中的SA连接。
在一些实施例中，在第二方向上相邻的两个所述存储块121连接的所述位线BL连接至同一个所述第二控制块。
示例性的，位于同一存储结构层120中且在Y方向上相邻的两个存储块121连接的两条位线BL可以连接同一个SA。其中一个存储块121处于工作状态时，另一个存储块121连接的位线BL则作为参考位线，而处于工作状态的存储块121连接的位线则作为SA的目标位线。如此，可以使这两个存储块交替进行读写等操作，提升SA的使用效率，减少SA的占用面积。
此外，还可以使不同存储结构层120中相邻的两个存储块121连接同一个SA，但是，这种情况下这两个存储块121连接的位线不能共用，而是使用两组位线，并在操作过程中分别作为目标位线和参考位线。
在一些实施例中，所述存储器还包括：数据输入输出(I/O)模块，连接所述第二控制块，所述数据输入输出模块配置为通过所述第二控制块对存储单元进行数据的写入或读取。
数据输入输出模块可以配置为与存储器以外的组件进行数据交换。示例性地，数据输入输出模块可以连接SA，并通过SA对存储单元进行数据的读取和写入等操作。
在一些实施例中，所述存储器还包括：电源模块，连接多个所述控制块，用于提供电源信号；所述电源模块位于所述衬底中，且所述电源模块与所述控制电路层位于同一结构层内。
电源模块可以产生不同的电压，以在写入、读取等操作时满足存储器 中各个器件的需求。示例性地，电源模块和控制电路层在衬底中所在的深度基本相同，以优化存储器的器件及线路布局。
在一些实施例中，如图8所示，所述控制电路层110还包括：全局控制电路112；所述全局控制电路112与多个所述控制块111连接；所述全局控制电路112至少用于向多个所述控制块111提供控制信号。
全局控制电路112可以通过多个控制块111连接部分存储块121，或者存储器10的全部存储块121，并用于向多个存储块121提供控制信号。
在一些实施例中，所述全局控制电路112包括：全局字线驱动模块，连接多个所述第一控制块，用于提供多个所述第一控制块连接的所述存储块121中多条字线的控制信号。
在本公开实施例中，全局字线驱动模块连接多个第一控制块，并通过多个第一控制块连接多个存储块121中的多条字线WL，全局字线驱动模块还可以连接至行解码器，以控制多个存储块121中的选择晶体管的导通和截止。
在一些实施例中，全局控制电路112还可以包括全局感测放大电路(Global Sense Amplifier)，全局感测放大电路可以连接多个第二控制块，并通过多个第二控制块连接多条位线BL，以控制多个存储块121中的存储单元123进行读取、写入等操作。可以理解的是，全局控制电路112还可以包括行/列解码器、熔丝修复电路、缓冲器等。
在一些实施例中，如图8所示，所述全局控制电路112所在的区域位于任意的所述存储块121在所述控制电路层110上的投影区域以外。
示例性地，全局控制电路112可以位于控制电路层110***的区域，即存储结构层120投影区域以外。全局控制电路112可以连接多个控制块111，从而为多个控制块111提供控制信号。全局控制电路112也可以位于一些控制块111之间，例如，位于多个并列的控制块111中间的两个控制块111之间的间隙内。
全局控制电路112连接的多个控制块111可以分时控制，也可以同步控制，这取决于全局控制电路与对应控制块111的功能及连接关系，这里不做限制。
如图9所示，本公开实施例还提供了一种存储***20，包括：上述实施例中任一所述的存储器10；存储控制器21。该存储***20可以为任意一种存储芯片。存储控制器21可以根据主机发出的信号，控制存储器10进行各项操作。可以理解的是，由于采用了堆叠设置的存储结构层与控制电路层，故存储***20的集成度较高；此外，存储器10中贯通的开口便于各存储结构层中的字线引出并连接至控制电路层，简化了布线设计和制造工艺。
需要说明的是，本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实 施例。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个***，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本公开各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
在本公开实施例提供的存储器中，至少两个存储结构层依次堆叠在控 制电路层上，至少一个存储结构层中的各字线通过贯通的开口连接至控制电路层。如此，一方面，堆叠设置的存储结构层与控制电路层的占用面积较小，提高了存储器的集成度；另一方面，贯通的开口便于各存储结构层中的字线引出并连接至控制电路层，简化了存储器的布线设计和制造工艺。

Claims (17)

  1. 一种存储器，包括：
    衬底；
    位于所述衬底内的控制电路层；所述控制电路层中包括所述存储器的至少部分控制电路；
    至少两个存储结构层；所述至少两个存储结构层依次堆叠在所述控制电路层上；所述存储结构层包括多个阵列排布的存储块；所述存储块包括沿第一方向延伸的多条平行的字线；所述第一方向平行于所述衬底的表面；
    其中，位于同一存储结构层中相邻的存储块之间具有开口；位于不同存储结构层中的所述开口相互贯通；至少一个所述存储结构层中的各字线通过贯通的所述开口连接至所述控制电路层。
  2. 根据权利要求1所述的存储器，其中，位于不同所述存储结构层中的所述开口的宽度由所述衬底向上的方向依次减小。
  3. 根据权利要求1所述的存储器，其中，还包括：
    多个连接结构，所述连接结构沿垂直于所述衬底表面的方向连接所述字线和所述控制电路层。
  4. 根据权利要求3所述的存储器，其中，还包括：
    与每个所述连接结构对应连接的补偿电阻，所述补偿电阻的阻值与所述连接结构的长度成反比。
  5. 根据权利要求3所述的存储器，其中，所述开口位于在第一方向上相邻的存储块之间，所述连接结构包括：
    第一连接结构，所述第一连接结构在垂直于所述衬底表面的方向上贯穿至少一个所述开口；位于最底层的所述存储结构层上方的所述存储结构层中的所述字线通过所述第一连接结构连接至所述控制电路层；
    第二连接结构，位于最底层的所述存储结构层与所述控制电路层之间；最底层的所述存储结构层中的所述字线通过所述第二连接结构连接至所述控制电路层。
  6. 根据权利要求5所述的存储器，其中，所述第一连接结构由所述字线下通过所述开口沿垂直所述衬底的方向连接至所述控制电路层；
    或者，所述第一连接结构由所述字线靠近所述开口的一端沿所述第一方向延伸至所述开口，并通过所述开口沿垂直所述衬底的方向连接至所述控制电路层。
  7. 根据权利要求1所述的存储器，其中，所述控制电路层包括：与每个所述存储块对应连接的多个控制块。
  8. 根据权利要求7所述的存储器，其中，所述存储块包括：
    多个阵列排布的存储单元，每条所述字线连接多个沿所述第一方向排 布的所述存储单元；
    至少一个所述存储结构层中的所述存储单元通过所述字线经由贯通的所述开口连接至所述控制块。
  9. 根据权利要求8所述的存储器，其中，还包括：
    位线结构层，位于所述控制电路层与至少两个所述存储结构层之间；所述位线结构层中包括多条沿第二方向延伸的位线；所述第二方向与所述第一方向之间具有夹角，所述第二方向平行于所述衬底的表面；
    每条所述位线连接沿第二方向排布的多组存储单元，其中，每组存储单元是通过第一连接线连接的沿垂直于所述衬底表面的方向上堆叠设置的多个存储单元。
  10. 根据权利要求9所述的存储器，其中，所述控制块包括：
    与所述字线连接的第一控制块；
    与所述位线连接的第二控制块。
  11. 根据权利要求10所述的存储器，其中，在第二方向上相邻的两个所述存储块连接的所述位线连接至同一个所述第二控制块。
  12. 根据权利要求10所述的存储器，其中，还包括：
    数据输入输出模块，连接所述第二控制块，所述数据输入输出模块配置为通过所述第二控制块对存储单元进行数据的写入或读取。
  13. 根据权利要求7所述的存储器，其中，还包括：
    电源模块，连接多个所述控制块，用于提供电源信号；
    所述电源模块位于所述衬底中，且所述电源模块与所述控制电路层位于同一结构层内。
  14. 根据权利要求7至13任一所述的存储器，其中，所述控制电路层还包括：全局控制电路；
    所述全局控制电路与多个所述控制块连接；
    所述全局控制电路至少用于向多个所述控制块提供控制信号。
  15. 根据权利要求14所述的存储器，其中，所述全局控制电路包括：
    全局字线驱动模块，连接多个所述第一控制块，用于提供多个所述第一控制块连接的所述存储块中多条字线的控制信号。
  16. 根据权利要求15所述的存储器，其中，所述全局控制电路所在的区域位于任意的所述存储块在所述控制电路层上的投影区域以外。
  17. 一种存储***，包括：
    如权利要求1至16任一所述的存储器；
    存储控制器。
PCT/CN2022/130570 2022-09-19 2022-11-08 存储器和存储*** WO2024060367A1 (zh)

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