WO2024060220A1 - Nitride-based semiconductor device and method for manufacturing thereof - Google Patents

Nitride-based semiconductor device and method for manufacturing thereof Download PDF

Info

Publication number
WO2024060220A1
WO2024060220A1 PCT/CN2022/120960 CN2022120960W WO2024060220A1 WO 2024060220 A1 WO2024060220 A1 WO 2024060220A1 CN 2022120960 W CN2022120960 W CN 2022120960W WO 2024060220 A1 WO2024060220 A1 WO 2024060220A1
Authority
WO
WIPO (PCT)
Prior art keywords
nitride
based semiconductor
gate electrode
semiconductor layer
semiconductor device
Prior art date
Application number
PCT/CN2022/120960
Other languages
French (fr)
Inventor
Ming-Hong Chang
Original Assignee
Innoscience (Zhuhai) Technology Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innoscience (Zhuhai) Technology Co., Ltd. filed Critical Innoscience (Zhuhai) Technology Co., Ltd.
Priority to PCT/CN2022/120960 priority Critical patent/WO2024060220A1/en
Publication of WO2024060220A1 publication Critical patent/WO2024060220A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3228—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of AIIIBV compounds, e.g. to make them semi-insulating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device including a gate electrode with a profile modified.
  • III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
  • devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
  • a nitride-based semiconductor device includes a nitride-based semiconductor structure, a doped nitride-based semiconductor layer, and a gate electrode.
  • the nitride-based semiconductor structure has an active region and an isolation region enclosing the active region.
  • the doped nitride-based semiconductor layer is disposed over the nitride-based semiconductor structure and extends across the active region along an extending direction.
  • the gate electrode is disposed over the doped nitride-based semiconductor layer and narrower than the doped nitride-based semiconductor layer. The gate electrode extends along the extending direction and is shorter than the doped nitride-based semiconductor layer along the extending direction.
  • a method for manufacturing a nitride-based semiconductor device has steps as follows: forming a nitride-based semiconductor structure; forming a doped nitride-based semiconductor layer over the nitride-based semiconductor structure; forming a gate electrode over the doped nitride-based semiconductor layer, wherein the gate electrode is narrow than the doped nitride-based semiconductor layer; forming a mask layer over the gate electrode, wherein the mask layer is shorter than the gate electrode such that at least one portion of the gate electrode is exposed; and patterning the gate electrode by using the mask layer.
  • a nitride-based semiconductor device includes a nitride-based semiconductor structure, a doped nitride-based semiconductor layer, and a gate electrode.
  • the nitride-based semiconductor structure has an active region and an isolation region enclosing the active region.
  • the doped nitride-based semiconductor layer is disposed over the nitride-based semiconductor structure and extends across the active region along an extending direction.
  • the gate electrode is disposed over the doped nitride-based semiconductor layer, in which an entirety of the gate electrode is spaced apart from edges of the doped nitride-based semiconductor layer.
  • two ends of the doped nitride-based semiconductor layer are free from coverage of the gate electrode which includes metal.
  • FIG. 1 is a three-dimensional schematic diagram of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 2A is a three-dimensional schematic diagram of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 2B is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 2C is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 3A, FIG. 3B, FIG. 3C, and FIG 3D show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure
  • FIG. 4 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 5 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 6 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 7 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 8 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 9 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 10 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 1 is a three-dimensional schematic diagram of a nitride-based semiconductor device 100 according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 100 includes an epitaxy substrate 101, a dope nitride-based semiconductor layer 103, and a gate electrode 104.
  • the epitaxy substrate 101 may include epitaxy layers with different bandgaps so a two-dimensional electron gas (2DEG) region can be generated in the epitaxy substrate 101.
  • the epitaxy substrate 101 has an active region 102 which is called device region as well to operate device function, such as switch.
  • the active region 102 can be defined by an isolation region enclosing the active region 102.
  • the isolation region can be formed by block ion implantation.
  • the dope nitride-based semiconductor layer 103 is disposed on the epitaxy substrate 101.
  • the gate electrode 104 is disposed on the dope nitride-based semiconductor layer 103.
  • At least one current laterally flows beneath the dope nitride-based semiconductor layer 103 and the gate electrode 104.
  • the edge of the active region 102 cannot have resistance enough to resist leakage current.
  • at least one leakage current 105 flows beneath ends of the dope nitride-based semiconductor layer 103 and the gate electrode 104, which reduces reliability and stability of the nitride-based semiconductor device 100.
  • the present disclosure provides a novel structure to reduce the leakage current as such.
  • FIG. 2A is a three-dimensional schematic diagram of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure
  • FIG. 2B is a top view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure
  • FIG. 2C is a side view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1A includes a nitride-based semiconductor structure 10, a doped nitride-based semiconductor layer 20, and gate electrode 22.
  • the illustration of the present embodiment is exemplary for a configuration of a gate stack and the present disclosure is not limited thereto.
  • electrodes can be formed adjacent to the gate stack to act as source or drain.
  • the nitride-based semiconductor structure 10 may include a substrate.
  • the substrate may be a semiconductor substrate.
  • the exemplary materials of the substrate can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials.
  • the substrate can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the nitride-based semiconductor structure 10 may include a nucleation layer and a buffer layer disposed on the nucleation layer.
  • the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference.
  • the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
  • the buffer layer can be configured to reduce lattice and thermal mismatches, thereby curing defects due to the mismatches/difference.
  • the buffer layer may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the nitride-based semiconductor structure 10 may include two stacked nitride-based semiconductor layers.
  • the two nitride-based semiconductor layers can serve as a channel layer and a barrier layer, in which the barrier layer has a bandgap greater than that of the channel layer.
  • the exemplary materials of the channel layer can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al x Ga (1–x) N where x ⁇ 1.
  • the exemplary materials of the barrier layer can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the channel layer and the barrier layer are selected such that a two-dimensional electron gas (2DEG) region adjacent to heterojunction between the channel layer and the barrier layer is generated.
  • the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
  • HEMT high-electron-mobility transistor
  • the nitride-based semiconductor structure 10 has an active region 12 and an isolation region 14.
  • the isolation region 14 encloses the active region 12.
  • the active region 12 can serve as a device region to allow current to flow therein.
  • the isolation region 14 can serve as a device boundary to distinguish than other devices/transistors.
  • the isolation region 14 can be doped with ions to achieve an electrically isolating purpose.
  • the isolation region 14 is formed by ion implantation into the nitride-based semiconductor layers of the nitride-based semiconductor structure 10.
  • the ions can include, for example but are not limited to, nitrogen ion, fluorine ion, oxygen ion, argon atom, aluminum atom, or combinations thereof. These dopants can make the isolation region 14 have a high resistivity and thus act as an electrically isolating region.
  • the doped nitride-based semiconductor layer 20 is disposed over the nitride-based semiconductor structure 10.
  • the doped nitride-based semiconductor layer 20 extends across the active region 12 along an extending direction ED.
  • the doped nitride-based semiconductor layer 20 may be p-type.
  • the doped nitride-based semiconductor layer 20 can be a p-type doped III-V semiconductor layer.
  • the doped nitride-based semiconductor layer 20 is configured to bring the device into enhancement mode.
  • the exemplary materials of the doped nitride-based semiconductor layer 20 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.
  • the gate electrode 22 is disposed over the doped nitride-based semiconductor layer 20.
  • the gate electrode 22 is narrower than the doped nitride-based semiconductor layer 20.
  • the gate electrode 22 can extend along the extending direction ED. To improve the issue as afore-mentioned, the gate electrode 22 is shorter than the doped nitride-based semiconductor layer 20 along the extending direction ED.
  • the gate electrode 22 is shorter than the doped nitride-based semiconductor layer 20, two ends of the doped nitride-based semiconductor layer 20 are free from coverage of the gate electrode 22 which includes metal. As such, there is no metal layer on the two ends of the doped nitride-based semiconductor layer 20 to block ion implantation at the formation of the isolation region 14, so the isolation region 14 can be formed to comply with the device design, which can reduce leakage current flowing beneath the two ends of the doped nitride-based semiconductor layer 20.
  • An entirety of the gate electrode 22 is spaced apart from edges of the doped nitride-based semiconductor layer 20. More specifically, the doped nitride-based semiconductor layer 20 is longer than the active region 12 and has the edges out of the active region 12. Along the extending direction, the gate electrode 22 has the same length as that of the active region 12. Accordingly, the gate electrode 22 has opposite end sidewalls vertically extending from the doped nitride-based semiconductor layer 20 and aligning with the border of the active region 12. Such the configuration is effective, which means leakage current can be reduced significantly.
  • the exemplary materials of the gate electrode 2 may include metals or metal compounds.
  • the gate electrode 22 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • a nitride-based semiconductor structure 10 is provided.
  • the nitride-based semiconductor structure 10 can be provided by forming two nitride-based semiconductor layers with different bandgaps to serve as a channel layer and a barrier layer in the nitride-based semiconductor structure 10. The channel layer and the barrier layer are free from being performed by an isolation process so no isolation region is formed in the channel layer and the barrier layer.
  • a doped nitride-based semiconductor layer 20 is formed over the nitride-based semiconductor structure 10.
  • a gate electrode 22 is formed over the doped nitride-based semiconductor layer 20. The gate electrode 22 is narrower than the doped nitride-based semiconductor layer 20.
  • the narrower gate electrode 22 can be achieved by a patterning process.
  • An oxide layer 30 can be formed on/over/above the gate electrode 22 to serve as a hard mask in an etching process to be performed. In some embodiments, the oxide layer 30 and the gate electrode 22 have the same width.
  • a photoresist layer 32 is formed over the oxide layer 30, in which portions of the oxide layer 30 are exposed from the photoresist layer 32.
  • the pattern of the photoresist layer 32 is transferred to the oxide layer 30.
  • a patterning process is performed to the exposed portions of the oxide layer 30 for removal. After the patterning process, the mask layer 30 becomes shorter. The mask layer 30 can get shorter than the gate electrode 22 such that at least one portion of the gate electrode 22 is exposed from the mask layer 30. After the patterning process, the photoresist layer 32 is removed.
  • the pattern of the mask layer 30 is transferred to the gate electrode 22.
  • a patterning process is performed to the exposed portions of the gate electrode 22 by using the mask layer 30 for removal. After the patterning process, the gate electrode 22 becomes shorter. The gate electrode 22 can get shorter than the doped nitride-based semiconductor layer 20. After the patterning process, mask layer 30 is removed.
  • an isolation region 14 is formed.
  • the isolation region 14 can be formed by ion implantation into the nitride-based semiconductor structure 10. Since the gate electrode 22 has been further patterned, the border between the active region 12 and the isolation region 14 can comply with the device design, thereby reducing leakage current.
  • FIG. 4 is a side view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22B.
  • the gate electrode 22B has a sidewall obliquely extending from the doped nitride-based semiconductor layer 20.
  • the gate electrode 22B has a thickness gradually varying at the sidewall. For some device operating cases, a share profile may cause electric field distribution changes suddenly, which may cause unexpected results. The gradually varying thickness of the gate electrode 22B is made to avoid such the cases.
  • FIG. 5 is a side view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22C.
  • the gate electrode 22C has a sidewall vertically extending from the doped nitride-based semiconductor layer 20 and has a thickness gradually varying from the sidewall.
  • the edge of the gate electrode 22C is in taper shape. The taper shape can make a layer to be formed on the gate electrode 22C fit to the profile of the gate electrode 22C, in order to avoid peeling.
  • FIG. 6 is a side view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1D is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22D.
  • the gate electrode 22D has a sidewall obliquely extending from the doped nitride-based semiconductor layer 20.
  • the gate electrode 22D has a thickness gradually varying at the sidewall.
  • a vertical projection of the gate electrode 22D on the nitride-based semiconductor structure 10 is out of the active region 12.
  • FIG. 7 is a side view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1E is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22E.
  • the gate electrode 22E has a sidewall vertically extending from the doped nitride-based semiconductor layer 20 and has a thickness gradually varying from the sidewall.
  • the edge of the gate electrode 22C is in taper shape. A vertical projection of the taper shape on the nitride-based semiconductor structure 10 is out of the active region 12.
  • FIG. 8 is a side view of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1F is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22F.
  • the gate electrode 22F has a plurality of projections arranged along a horizontal direction. The projections of the gate electrode 22F extend toward an edge of the doped nitride-based semiconductor layer 20.
  • the pattern of the gate electrode 22F can adjust the border of the active region.
  • the projections of the gate electrode 22F can make a leakage current path discontinuous, so resistivity of the leakage current path get raised.
  • FIG. 9 is a side view of a nitride-based semiconductor device 1G according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1G is similar to the semiconductor device 1F as described and illustrated with reference to FIG. 8, except that the gate electrode 22F of the semiconductor device 1F is replaced by a gate electrode 22G.
  • the projections of the gate electrode 22F are spaced apart from the edges oof the doped nitride-based semiconductor layer 20.
  • the projections of the gate electrode 22G can make a leakage current path discontinuous, so resistivity of the leakage current path get raised.
  • FIG. 10 is a top view of a nitride-based semiconductor device 1H according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1H applies the structures as embodiments above to expand.
  • the nitride-based semiconductor device 1H includes a nitride-based semiconductor structure 40, in which the nitride-based semiconductor structure 40 has an active region 42.
  • the nitride-based semiconductor device 1H further includes electrodes 44, 46, 48, doped nitride-based semiconductor layer 50, 52, gate electrodes 54, 56.
  • the electrodes 44, 46, 48 are disposed over the nitride-based semiconductor structure 40.
  • the electrodes 44, 46, 48 are located within the active region 42.
  • Each of the electrodes 44, 46, 48 can serve as a source electrode or a drain electrode.
  • the electrodes 44 and 48 can serve as drain electrodes and the electrode 46 can serve as a source electrode.
  • the doped nitride-based semiconductor layers 50 and 52 are disposed over the nitride-based semiconductor structure 40.
  • the doped nitride-based semiconductor layers 50 and 52 extend across the active region 42.
  • the doped nitride-based semiconductor layer 50 is located between the electrodes 44 and 46.
  • the doped nitride-based semiconductor layer 52 is located between the electrodes 46 and 48.
  • the doped nitride-based semiconductor layers 50 and 52 are longer than the electrodes 44, 46, 48.
  • the gate electrodes 54 and 56 are disposed over the nitride-based semiconductor structure 40.
  • the gate electrodes 54 and 56 are located within the active region 42.
  • the gate electrodes 54 and 56 are located over the doped nitride-based semiconductor layers 50 and 52, respectively.
  • the gate electrodes 54 and 56 are within boundaries of the doped nitride-based semiconductor layers 50 and 52, respectively.
  • the gate electrode 54 is located between the electrodes 44 and 46.
  • the gate electrode 54 is located between the electrodes 46 and 48.
  • the gate electrodes 54 and 56 are shorter than the doped nitride-based semiconductor layers 50 and 52.
  • the gate electrodes 54 and 56 have the same length as those of the electrodes 44, 46, 48.
  • such the configuration can reduce leakage current.
  • the configuration provided by the present disclosure can applied to a dual gate device.
  • the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
  • the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
  • a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A nitride-based semiconductor device includes a nitride-based semiconductor structure, a doped nitride-based semiconductor layer, and a gate electrode. The nitride-based semiconductor structure has an active region and an isolation region enclosing the active region. The doped nitride-based semiconductor layer is disposed over the nitride-based semiconductor structure and extends across the active region along an extending direction. The gate electrode is disposed over the doped nitride-based semiconductor layer and narrower than the doped nitride-based semiconductor layer. The gate electrode extends along the extending direction and is shorter than the doped nitride-based semiconductor layer along the extending direction.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Inventors: Ming-Hong CHANG
Field of the Disclosure:
The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device including a gate electrode with a profile modified.
Background of the Disclosure:
In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
Summary of the Disclosure:
In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a nitride-based semiconductor structure, a doped nitride-based semiconductor layer, and a gate electrode. The nitride-based semiconductor structure has an active region and an isolation region enclosing the active region. The doped nitride-based semiconductor layer is disposed over the nitride-based semiconductor structure and extends across the active region along an extending direction. The gate electrode is disposed over the doped nitride-based semiconductor layer and narrower than the doped nitride-based semiconductor layer. The gate electrode extends along the extending direction and is shorter than the doped nitride-based semiconductor layer along the extending direction.
In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method has steps as follows: forming a nitride-based semiconductor structure; forming a doped nitride-based semiconductor layer over the nitride-based semiconductor structure; forming a gate electrode over the doped nitride-based semiconductor layer, wherein the gate electrode is narrow than the doped nitride-based semiconductor layer; forming a mask layer over the gate electrode, wherein the mask layer is shorter than the gate electrode such that at least one portion of the gate electrode is exposed; and patterning the gate electrode by using the mask layer.
In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a nitride-based semiconductor structure, a doped nitride-based semiconductor layer, and a gate electrode. The nitride-based semiconductor structure has an active region and an isolation region enclosing the active region. The doped nitride-based semiconductor layer is disposed over the nitride-based semiconductor structure and extends across the active region along an extending direction. The gate electrode is disposed over the doped nitride-based semiconductor layer, in which an entirety of the gate electrode is spaced apart from edges of the doped nitride-based semiconductor layer.
By the above configuration, two ends of the doped nitride-based semiconductor layer are free from coverage of the gate electrode which includes metal. As such, there is no metal layer on the two ends of the doped nitride-based semiconductor layer to block ion implantation at the formation of the isolation region, so the isolation region can be formed to comply with the device design, which can reduce leakage current flowing beneath the two ends of the doped nitride-based semiconductor layer.
Brief Description of the Drawings:
Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:
FIG. 1 is a three-dimensional schematic diagram of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 2A is a three-dimensional schematic diagram of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 2B is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 2C is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 3A, FIG. 3B, FIG. 3C, and FIG 3D show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
FIG. 4 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 5 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 6 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 7 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 8 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 9 is a side view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and
FIG. 10 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
Detailed Description:
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.
Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.
In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
FIG. 1 is a three-dimensional schematic diagram of a nitride-based semiconductor device 100 according to some embodiments of the present disclosure. The nitride-based semiconductor device 100 includes an epitaxy substrate 101, a dope nitride-based semiconductor layer 103, and a gate electrode 104.
The epitaxy substrate 101 may include epitaxy layers with different bandgaps so a two-dimensional electron gas (2DEG) region can be generated in the epitaxy substrate 101. The epitaxy substrate 101 has an active region 102 which is called device region as well to operate device function, such as switch. The active region 102 can be defined by an isolation region enclosing the active region 102. The isolation region can be formed by block ion implantation. The dope nitride-based semiconductor layer 103 is disposed on the epitaxy substrate 101. The gate electrode 104 is disposed on the dope nitride-based semiconductor layer 103.
During the switch-on operation, at least one current laterally flows beneath the dope nitride-based semiconductor layer 103 and the gate electrode 104. However, once two ends of the gate electrode 104 block ion implantation at the formation of the isolation region, the edge of the active region 102 cannot have resistance enough to resist leakage current. As a result, at least one leakage current 105 flows beneath ends of the dope nitride-based semiconductor layer 103 and the gate electrode 104, which reduces reliability and stability of the nitride-based semiconductor device 100.
Therefore, there is a leakage current issue to be improved. The present disclosure provides a novel structure to reduce the leakage current as such.
FIG. 2A is a three-dimensional schematic diagram of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure; FIG. 2B is a top view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure; FIG. 2C is a side view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
The nitride-based semiconductor device 1A includes a nitride-based semiconductor structure 10, a doped nitride-based semiconductor layer 20, and gate electrode 22. The illustration of the present embodiment is exemplary for a configuration of a gate stack and the present disclosure is not limited thereto. For example, although there is no source electrode or drain electrode, electrodes can be formed adjacent to the gate stack to act as source or drain.
The nitride-based semiconductor structure 10 may include a substrate. The substrate may be a semiconductor substrate. The exemplary materials of the substrate can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate can include, for example, but is not limited to, group III  elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
In some embodiments, the nitride-based semiconductor structure 10 may include a nucleation layer and a buffer layer disposed on the nucleation layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys. The buffer layer can be configured to reduce lattice and thermal mismatches, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
In some embodiments, the nitride-based semiconductor structure 10 may include two stacked nitride-based semiconductor layers. The two nitride-based semiconductor layers can serve as a channel layer and a barrier layer, in which the barrier layer has a bandgap greater than that of the channel layer. The exemplary materials of the channel layer can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In xAl yGa  (1–x–y) N where x+y ≤ 1, Al xGa  (1–x) N where x ≤ 1. The exemplary materials of the barrier layer can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In xAl yGa  (1–x–y) N where x+y ≤ 1, Al yGa  (1–y) N where y ≤ 1.
The exemplary materials of the channel layer and the barrier layer are selected such that a two-dimensional electron gas (2DEG) region adjacent to heterojunction between the channel layer and the barrier layer is generated. Accordingly, the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
The nitride-based semiconductor structure 10 has an active region 12 and an isolation region 14. The isolation region 14 encloses the active region 12. The active region 12 can serve as a device region to allow current to flow therein. The isolation region 14 can serve as a device boundary to distinguish than other devices/transistors. In some embodiments, the isolation region 14 can be doped with ions to achieve an electrically isolating purpose. In some embodiments, the isolation region 14 is formed by ion implantation into the nitride-based semiconductor layers of the nitride-based semiconductor structure 10.
The ions can include, for example but are not limited to, nitrogen ion, fluorine ion, oxygen ion, argon atom, aluminum atom, or combinations thereof. These dopants can make the isolation region 14 have a high resistivity and thus act as an electrically isolating region.
The doped nitride-based semiconductor layer 20 is disposed over the nitride-based semiconductor structure 10. The doped nitride-based semiconductor layer 20 extends across the active region 12 along an extending direction ED. The doped nitride-based semiconductor layer 20 may be p-type. The doped nitride-based semiconductor layer 20 can be a p-type doped III-V semiconductor layer. The doped nitride-based semiconductor layer 20 is configured to bring the device into enhancement mode. The exemplary materials of the doped nitride-based semiconductor layer 20 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.
The gate electrode 22 is disposed over the doped nitride-based semiconductor layer 20. The gate electrode 22 is narrower than the doped nitride-based semiconductor layer 20. The gate electrode 22 can extend along the extending direction ED. To improve the issue as afore-mentioned, the gate electrode 22 is shorter than the doped nitride-based semiconductor layer 20 along the extending direction ED.
Since the gate electrode 22 is shorter than the doped nitride-based semiconductor layer 20, two ends of the doped nitride-based semiconductor layer 20 are free from coverage of the gate electrode 22 which includes metal. As such, there is no metal layer on the two ends of the doped nitride-based semiconductor layer 20 to block ion implantation at the formation of the isolation region 14, so the isolation region 14 can be formed to comply with the device design, which can reduce leakage current flowing beneath the two ends of the doped nitride-based semiconductor layer 20.
An entirety of the gate electrode 22 is spaced apart from edges of the doped nitride-based semiconductor layer 20. More specifically, the doped nitride-based semiconductor layer 20 is longer than the active region 12 and has the edges out of the active region 12. Along the extending direction, the gate electrode 22 has the same length as that of the active region 12. Accordingly, the gate electrode 22 has opposite end sidewalls vertically extending from the doped nitride-based semiconductor layer 20 and aligning with the border of the active region 12. Such the configuration is effective, which means leakage current can be reduced significantly.
The exemplary materials of the gate electrode 2 may include metals or metal compounds. The gate electrode 22 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 3A, FIG. 3B, FIG. 3C, and FIG 3D, described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
Referring to FIG. 3A, a nitride-based semiconductor structure 10 is provided. The nitride-based semiconductor structure 10 can be provided by forming two nitride-based semiconductor layers with different bandgaps to serve as a channel layer and a barrier layer in the nitride-based semiconductor structure 10. The channel layer and the barrier layer are free from being performed by an isolation process so no isolation region is formed in the channel layer and the barrier layer. A doped nitride-based semiconductor layer 20 is formed over the nitride-based semiconductor structure 10. A gate electrode 22 is formed over the doped nitride-based semiconductor layer 20. The gate electrode 22 is narrower than the doped nitride-based semiconductor layer 20. The narrower gate electrode 22 can be achieved by a patterning process. An oxide layer 30 can be formed on/over/above the gate electrode 22 to serve as a hard mask in an etching process to be performed. In some embodiments, the oxide layer 30 and the gate electrode 22 have the same width. A photoresist layer 32 is formed over the oxide layer 30, in which portions of the oxide layer 30 are exposed from the photoresist layer 32.
Referring to FIG. 3B, the pattern of the photoresist layer 32 is transferred to the oxide layer 30. In some embodiments, a patterning process is performed to the exposed portions of the oxide layer 30 for removal. After the patterning process, the mask layer 30 becomes shorter. The mask layer 30 can get shorter than the gate electrode 22 such that at least one portion of the gate electrode 22 is exposed from the mask layer 30. After the patterning process, the photoresist layer 32 is removed.
Referring to FIG. 3C, the pattern of the mask layer 30 is transferred to the gate electrode 22. In some embodiments, a patterning process is performed to the exposed portions of the gate electrode 22 by using the mask layer 30 for removal. After the patterning process, the gate electrode 22 becomes shorter. The gate electrode 22 can get shorter than the doped nitride-based semiconductor layer 20. After the patterning process, mask layer 30 is removed.
Referring to FIG. 3D, an isolation region 14 is formed. The isolation region 14 can be formed by ion implantation into the nitride-based semiconductor structure 10. Since the gate electrode 22 has been further patterned, the border between the active region 12 and the isolation region 14 can comply with the device design, thereby reducing leakage current.
FIG. 4 is a side view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22B. The gate electrode 22B has a sidewall obliquely extending from the doped nitride-based semiconductor layer 20. The gate electrode 22B has a thickness gradually varying at the sidewall. For some device operating cases, a share profile may cause electric field distribution changes suddenly, which may cause unexpected results. The gradually varying thickness of the gate electrode 22B is made to avoid such the cases.
FIG. 5 is a side view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22C. The gate electrode 22C has a sidewall vertically extending from the doped nitride-based semiconductor layer 20 and has a thickness gradually varying from the sidewall. The edge of the gate electrode 22C is in taper shape. The taper shape can make a layer to be formed on the gate electrode 22C fit to the profile of the gate electrode 22C, in order to avoid peeling.
FIG. 6 is a side view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22D. The gate electrode 22D has a sidewall obliquely extending from the doped nitride-based semiconductor layer 20. The gate electrode 22D has a thickness gradually varying at the sidewall. A vertical projection of the gate electrode 22D on the nitride-based semiconductor structure 10 is out of the active region 12.
FIG. 7 is a side view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22E. The gate electrode 22E has a sidewall vertically extending from the doped nitride-based semiconductor layer 20 and has a thickness gradually varying from the sidewall. The edge of the gate electrode 22C is in taper shape. A vertical projection of the taper shape on the nitride-based semiconductor structure 10 is out of the active region 12.
FIG. 8 is a side view of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure. The nitride-based semiconductor device 1F is similar to  the semiconductor device 1A as described and illustrated with reference to FIGS. 2A-2C, except that the gate electrode 22 of the semiconductor device 1A is replaced by a gate electrode 22F. The gate electrode 22F has a plurality of projections arranged along a horizontal direction. The projections of the gate electrode 22F extend toward an edge of the doped nitride-based semiconductor layer 20. The pattern of the gate electrode 22F can adjust the border of the active region. The projections of the gate electrode 22F can make a leakage current path discontinuous, so resistivity of the leakage current path get raised.
FIG. 9 is a side view of a nitride-based semiconductor device 1G according to some embodiments of the present disclosure. The nitride-based semiconductor device 1G is similar to the semiconductor device 1F as described and illustrated with reference to FIG. 8, except that the gate electrode 22F of the semiconductor device 1F is replaced by a gate electrode 22G. The projections of the gate electrode 22F are spaced apart from the edges oof the doped nitride-based semiconductor layer 20. The projections of the gate electrode 22G can make a leakage current path discontinuous, so resistivity of the leakage current path get raised.
FIG. 10 is a top view of a nitride-based semiconductor device 1H according to some embodiments of the present disclosure. The nitride-based semiconductor device 1H applies the structures as embodiments above to expand. The nitride-based semiconductor device 1H includes a nitride-based semiconductor structure 40, in which the nitride-based semiconductor structure 40 has an active region 42. The nitride-based semiconductor device 1H further includes  electrodes  44, 46, 48, doped nitride-based  semiconductor layer  50, 52,  gate electrodes  54, 56.
The  electrodes  44, 46, 48 are disposed over the nitride-based semiconductor structure 40. The  electrodes  44, 46, 48 are located within the active region 42. Each of the  electrodes  44, 46, 48 can serve as a source electrode or a drain electrode. For example, the  electrodes  44 and 48 can serve as drain electrodes and the electrode 46 can serve as a source electrode.
The doped nitride-based semiconductor layers 50 and 52 are disposed over the nitride-based semiconductor structure 40. The doped nitride-based semiconductor layers 50 and 52 extend across the active region 42. The doped nitride-based semiconductor layer 50 is located between the  electrodes  44 and 46. The doped nitride-based semiconductor layer 52 is located between the  electrodes  46 and 48. The doped nitride-based semiconductor layers 50 and 52 are longer than the  electrodes  44, 46, 48.
The  gate electrodes  54 and 56 are disposed over the nitride-based semiconductor structure 40. The  gate electrodes  54 and 56 are located within the active region 42. The  gate electrodes  54 and 56 are located over the doped nitride-based semiconductor layers 50 and 52, respectively. The  gate electrodes  54 and 56 are within boundaries of the doped nitride-based semiconductor layers 50 and 52, respectively. The gate electrode 54 is located between the  electrodes  44 and 46. The gate electrode 54 is located between the  electrodes  46 and 48. The  gate electrodes  54 and 56 are shorter than the doped nitride-based semiconductor layers 50 and 52. The  gate electrodes  54 and 56 have the same length as those of the  electrodes  44, 46, 48.
As afore described, such the configuration can reduce leakage current. The configuration provided by the present disclosure can applied to a dual gate device.
The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.
As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition,  etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims (25)

  1. A nitride-based semiconductor device, comprising:
    a nitride-based semiconductor structure having an active region and an isolation region enclosing the active region; and
    a doped nitride-based semiconductor layer disposed over the nitride-based semiconductor structure and extending across the active region along an extending direction; and
    a gate electrode disposed over the doped nitride-based semiconductor layer and narrower than the doped nitride-based semiconductor layer, wherein the gate electrode extends along the extending direction and is shorter than the doped nitride-based semiconductor layer along the extending direction.
  2. The nitride-based semiconductor device of the any one of preceding claims, wherein an entirety of the gate electrode is spaced apart from edges of the doped nitride-based semiconductor layer.
  3. The nitride-based semiconductor device of the any one of preceding claims, wherein the active region has the same length as the gate electrode along the extending direction.
  4. The nitride-based semiconductor device of the any one of preceding claims, wherein the gate electrode has a sidewall vertically extending from the doped nitride-based semiconductor layer.
  5. The nitride-based semiconductor device of the any one of preceding claims, wherein the gate electrode has a sidewall obliquely extending from the doped nitride-based semiconductor layer.
  6. The nitride-based semiconductor device of the any one of preceding claims, wherein the sidewall of the gate electrode is out of the active region.
  7. The nitride-based semiconductor device of the any one of preceding claims, wherein the gate electrode has a thickness gradually varying at the sidewall.
  8. The nitride-based semiconductor device of the any one of preceding claims, herein the gate electrode has a sidewall vertically extending from the doped nitride-based semiconductor layer and has a thickness gradually varying from the sidewall.
  9. The nitride-based semiconductor device of the any one of preceding claims, wherein the gate electrode has a plurality of projections arranged along a direction and extending toward an edge of the doped nitride-based semiconductor layer.
  10. The nitride-based semiconductor device of the any one of preceding claims, wherein the nitride-based semiconductor structure comprises:
    a first nitride-based semiconductor layer; and
    a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer.
  11. The nitride-based semiconductor device of the any one of preceding claims, wherein the isolation region is formed by ion implantation into the first and second nitride-based semiconductor layers.
  12. The nitride-based semiconductor device of the any one of preceding claims, wherein the first nitride-based semiconductor layer comprises GaN, and the second nitride-based semiconductor layer comprises AlGaN.
  13. The nitride-based semiconductor device of the any one of preceding claims, wherein the gate electrode comprises metal.
  14. The nitride-based semiconductor device of the any one of preceding claims, further comprising a source electrode and a drain electrode disposed over the nitride-based semiconductor structure , wherein the gate electrode is located between the source electrode and the drain electrode.
  15. The nitride-based semiconductor device of the any one of preceding claims, wherein the source electrode and the drain electrode have the same length as that of the gate electrode.
  16. A manufacturing method of a semiconductor device, comprising:
    forming a nitride-based semiconductor structure;
    forming a doped nitride-based semiconductor layer over the nitride-based semiconductor structure;
    forming a gate electrode over the doped nitride-based semiconductor layer, wherein the gate electrode is narrow than the doped nitride-based semiconductor layer;
    forming a mask layer over the gate electrode, wherein the mask layer is shorter than the gate electrode such that at least one portion of the gate electrode is exposed; and
    patterning the gate electrode by using the mask layer.
  17. The manufacturing method of any one of preceding claims, wherein the mask layer and the gate electrode have the same width.
  18. The manufacturing method of any one of preceding claims, further comprising:
    forming an isolation region after patterning the gate electrode.
  19. The manufacturing method of any one of preceding claims, wherein the isolation region is formed by ion implantation into the nitride-based semiconductor structure.
  20. The manufacturing method of any one of preceding claims, wherein the forming the nitride-based semiconductor structure comprises:
    forming a first nitride-based semiconductor layer; and
    forming a second nitride-based semiconductor layer over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer.
  21. A nitride-based semiconductor device, comprising:
    a nitride-based semiconductor structure having an active region and an isolation region enclosing the active region; and
    a doped nitride-based semiconductor layer disposed over the nitride-based semiconductor structure and extending across the active region along an extending direction; and
    a gate electrode disposed over the doped nitride-based semiconductor layer, wherein an entirety of the gate electrode is spaced apart from edges of the doped nitride-based semiconductor layer.
  22. The nitride-based semiconductor device of the any one of preceding claims, wherein the nitride-based semiconductor structure comprises:
    a first nitride-based semiconductor layer; and
    a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer.
  23. The nitride-based semiconductor device of the any one of preceding claims, wherein the isolation region is formed by ion implantation into the first and second nitride-based semiconductor layers.
  24. The nitride-based semiconductor device of the any one of preceding claims, wherein the first nitride-based semiconductor layer comprises GaN, and the second nitride-based semiconductor layer comprises AlGaN.
  25. The nitride-based semiconductor device of the any one of preceding claims, wherein the gate electrode comprises metal.
PCT/CN2022/120960 2022-09-23 2022-09-23 Nitride-based semiconductor device and method for manufacturing thereof WO2024060220A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/120960 WO2024060220A1 (en) 2022-09-23 2022-09-23 Nitride-based semiconductor device and method for manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/120960 WO2024060220A1 (en) 2022-09-23 2022-09-23 Nitride-based semiconductor device and method for manufacturing thereof

Publications (1)

Publication Number Publication Date
WO2024060220A1 true WO2024060220A1 (en) 2024-03-28

Family

ID=90453714

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/120960 WO2024060220A1 (en) 2022-09-23 2022-09-23 Nitride-based semiconductor device and method for manufacturing thereof

Country Status (1)

Country Link
WO (1) WO2024060220A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010015446A1 (en) * 1999-12-08 2001-08-23 Kaoru Inoue Semiconductor device
JP2006269586A (en) * 2005-03-23 2006-10-05 Toshiba Corp Semiconductor element
KR20150065005A (en) * 2013-12-04 2015-06-12 삼성전자주식회사 Normally off high electron mobility transistor
US20160336437A1 (en) * 2014-02-21 2016-11-17 Panasonic Corporation Field effect transistor
CN112768505A (en) * 2020-12-31 2021-05-07 西安电子科技大学 Heterojunction power device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010015446A1 (en) * 1999-12-08 2001-08-23 Kaoru Inoue Semiconductor device
JP2006269586A (en) * 2005-03-23 2006-10-05 Toshiba Corp Semiconductor element
KR20150065005A (en) * 2013-12-04 2015-06-12 삼성전자주식회사 Normally off high electron mobility transistor
US20160336437A1 (en) * 2014-02-21 2016-11-17 Panasonic Corporation Field effect transistor
CN112768505A (en) * 2020-12-31 2021-05-07 西安电子科技大学 Heterojunction power device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
WO2022174562A1 (en) Semiconductor device and method for manufacturing thereof
WO2023039746A1 (en) Nitride-based semiconductor device and method for manufacturing thereof
WO2023082202A1 (en) Semiconductor device and method for manufacturing thereof
US20220376074A1 (en) Nitride-based semiconductor device and method for manufacturing the same
US20230095367A1 (en) Semiconductor device and method for manufacturing the same
WO2022178773A1 (en) Semiconductor device and method for manufacturing thereof
US20240038886A1 (en) Semiconductor device and method for manufacturing the same
US20240038887A1 (en) Semiconductor device and method for manufacturing the same
CN114402442B (en) Nitride-based semiconductor device and method for manufacturing the same
WO2023019436A1 (en) Semiconductor device and method for manufacturing the same
WO2023141749A1 (en) GaN-BASED SEMICONDUCTOR DEVICE WITH REDUCED LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME
WO2023082058A1 (en) Nitride-based semiconductor device and method for manufacturing thereof
WO2023015493A1 (en) Semiconductor device and manufacturing method thereof
US20240030331A1 (en) Semiconductor device and method for manufacturing the same
WO2024060220A1 (en) Nitride-based semiconductor device and method for manufacturing thereof
WO2024108422A1 (en) Nitride-based semiconductor device and method for manufacturing thereof
US20230215912A1 (en) Semiconductor device and method for manufacturing the same
WO2024103199A1 (en) Nitride-based semiconductor device and method for manufacturing the same
WO2024108489A1 (en) Nitride-based semiconductor device and method for manufacturing the same
WO2024108488A1 (en) Nitride-based semiconductor device and method for manufacturing the same
WO2024092720A1 (en) Semiconductor device and method for manufacturing the same
WO2024065149A1 (en) Nitride-based semiconductor device and method for manufacturing thereof
WO2024092543A1 (en) Nitride-based semiconductor device and method for manufacturing the same
WO2024065148A1 (en) Nitride-based semiconductor device and method for manufacturing thereof
WO2024026738A1 (en) Nitride-based semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22959225

Country of ref document: EP

Kind code of ref document: A1