WO2024051041A1 - 一种数据存取方法、装置、设备和非易失性可读存储介质 - Google Patents
一种数据存取方法、装置、设备和非易失性可读存储介质 Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Definitions
- the present application relates to the field of computer technology, and in particular to a data access method, device, equipment and non-volatile readable storage medium.
- the file system is used to manage data blocks on the disk.
- the file system When the disk is formatted, the file system writes and reads data on the disk in a fixed format. Since the access bandwidth of memory is much greater than that of disk, based on the locality principle of data access by CPU (Central Processing Unit/Processor, central processing unit), the file system will cache the disk data blocks recently accessed by the CPU in memory, which is called file cache. When the CPU accesses the file block at the same location again, it no longer reads from the disk, but directly returns the data in the file cache to the CPU, thus improving the overall performance of the system.
- CPU Central Processing Unit/Processor
- GPU Graphics Processing Unit
- FPGA Field-Programmable Gate Array
- ASCI Application Specific Integrated Circuit
- Figure 1 is a schematic structural diagram of a heterogeneous computing platform provided by the prior art.
- the data is read from the disk to the file cache, and then sent to the accelerator card for calculation, and finally the calculated results are obtained from The accelerator card is read into the system memory. Since the computing power of the accelerator card for specific data far exceeds the computing power of the CPU, the overall performance of the system can be significantly improved through heterogeneous computing methods.
- the heterogeneous computing method requires transferring the data in the file cache to the accelerator card, and then retrieving the calculated data from the accelerator card, which introduces the overhead of data transfer back and forth and reduces the performance benefits that can be obtained by using heterogeneous computing.
- the traditional file system cache manages memory according to 4KB page size, and the file is divided into multiple 4KB data blocks and then cached.
- DMA Direct Memory Access
- a descriptor can only describe a size of 4KB, and the accelerator card can only obtain 4KB data at a time, which limits the DMA transmission bandwidth. Since data blocks are randomly distributed in memory, a DMA descriptor needs to be constructed for each page in units of 4K. Creating too many descriptors will take a long time.
- FIG. 2 is a schematic structural diagram of a heterogeneous computing platform based on continuous memory provided by the existing technology.
- the operation process for file pages includes 1
- the data read from the disk on the host side is cached in the file cache of the operating system.
- 2 The CPU copies the data blocks in the file cache to consecutive anonymous pages.
- step 3 uses continuous memory, which greatly improves the efficiency of DMA data transmission, the copy operation in step 2 still introduces a large delay.
- the method of pre-applying for large blocks of continuous memory reduces the DMA descriptor creation time and improves the accelerator card DMA bandwidth.
- this implementation method is only suitable for anonymous page scenarios, and there is copy overhead for file pages, which affects the overall performance.
- the current file system cache management mechanism does not manage the data in the accelerator card. Since the data in the accelerator card does not correspond to the file, even if the accelerator card has cached the file data block in the last calculation, the file data required for the next calculation still needs to be transferred from the host side to the accelerator card, causing Repeated transmissions waste a lot of transmission bandwidth.
- the purpose of the embodiments of this application is to provide a data access method, device, equipment and non-volatile readable storage medium, which can improve bandwidth utilization and reduce data transmission delay.
- a data access method which includes: creating a cache pool on the host side that matches the memory capacity of the accelerator card; wherein the cache pool contains cache blocks divided according to set capacity units. ;
- the target cache block matching the capacity of the target data is called from the cache pool, and the target data is stored in the target cache block;
- the meta information of the target cache block is recorded, and the target cache block is The cache block is write-protected;
- the meta-information includes the file number to which the target data belongs, the length of the target data, the address information of the target data, and status information used to characterize the data synchronization status of the target cache block and the accelerator card; according to each cache The status information corresponding to the block, performs the data access operation, and adjusts the status information of the cache block after the data access operation is performed; among which, the status information includes an identifier used to represent the uncached data of the cache block, a identifier used to represent only the cache
- the accelerator card after creating a cache pool matching the memory capacity of the accelerator card on the host side, it also includes: creating a free linked list and a cache linked list; the free linked list is used to store unused cache blocks, and the cache linked list is used to store used cache blocks;
- calling the target cache block matching the capacity of the target data from the cache pool, and storing the target data to the target cache block includes: obtaining the read instruction of the target data.
- the target cache block matching the capacity of the target data is selected from the free linked list and the cache linked list, and the target data is stored in the target cache block; wherein, the target cache block is stored in the cache linked list.
- selecting a target cache block that matches the capacity of the target data from the free linked list and the cache linked list, and storing the target data into the target cache block includes: when the free linked list is not empty, storing a block in the free linked list
- the free cache block is stored in the cache linked list; when a page fault occurs when accessing the target data, the first data block matching the set capacity unit is read from the disk, and the first data block is stored in the free cache block; established The mapping relationship between the physical address and the virtual address of the first data block; when the free linked list is empty, an available cache block is released from the cache linked list, and when a page fault exception occurs when accessing the target data, it is read from the disk
- the second data block that matches the set capacity unit is stored in the available cache block; a mapping relationship between the physical address and the virtual address of the second data block is established; until all data blocks divided by the target data are stored in target cache block, the operation ends.
- releasing an available cache block from the cache link list includes: selecting an available cache block from the cache link list according to the replacement algorithm of the cache link list; and writing back the original data in the available cache block to the disk.
- the meta-information for recording the target cache block includes: the file number recording the target data, the length of the target data, the offset of the target data in the file, the source address of the target cache block used to indicate where the target data is located, and the source address of the target cache block.
- the destination address of the accelerator card corresponding to the address and the status information used to characterize the data synchronization status of the target cache block and the accelerator card.
- adjusting the status information of the cache block after performing the data access operation includes: after transmitting the target data to the accelerator card, adjusting the status information to represent that both the accelerator card and the target cache block store data and the data is consistent. logo.
- performing a data access operation based on the status information corresponding to each cache block, and adjusting the status information of the cache block after performing the data access operation includes: modifying the target cache block when receiving a target data modification instruction.
- the target data stored in the accelerator card and the target cache block are adjusted to an identifier used to indicate that both the accelerator card and the target cache block store data and the data is inconsistent.
- the accelerator card after creating a cache pool matching the memory capacity of the accelerator card on the host side, it also includes: memory locking the cache blocks of the cache pool.
- the method further includes: upon receiving an acceleration processing instruction for the first data, determining whether the first data is cached by the cache pool; If cached by the cache pool, load the first data from the disk into the cache pool; add the first data in the cache pool to the DMA sending linked list; generate a DMA description based on the meta information corresponding to the cache block storing the first data descriptor; transmit the DMA descriptor to the accelerator card so that the accelerator card can obtain the first data contained in the DMA transmission list based on the DMA descriptor.
- determining whether the first data is cached by the cache pool includes: when an accelerated processing instruction for the first data is received, based on the file number of the first data and data amount, construct a file information linked list; divide the first data into file blocks according to the set capacity unit; traverse the file blocks of the file information linked list, and determine whether the current file information linked list is empty; if the current file information linked list is not empty In this case, it is determined whether the current file block is cached by the cache pool; accordingly, if the first data is not cached by the cache pool, the first data is loaded from the disk into the cache pool; the first data in the cache pool is added to
- the DMA sending linked list includes: when the current file block is not cached in the cache pool, load the current file block from the disk into the cache pool; add the current file block in the cache pool to the DMA sending linked list; until the current file information linked list is empty In the case of , perform the step of generating a DMA descriptor
- it also includes: when the current file block is cached by the cache pool, determining whether the status information corresponding to the current cache block that caches the current file block is used to represent that both the accelerator card and the current cache block store data and the data is consistent.
- the identifier when the status information corresponding to the current cache block is an identifier used to indicate that both the accelerator card and the current cache block store data and the data is inconsistent, add the current file block in the cache pool to the DMA sending linked list; in the current cache If the status information corresponding to the block is an identifier used to indicate that both the accelerator card and the current cache block store data and the data is consistent, the current file block is skipped.
- the accelerator card after transmitting the DMA descriptor to the accelerator card so that the accelerator card obtains the first data contained in the DMA sending linked list according to the DMA descriptor, it also includes: adjusting the status information corresponding to the first data in the buffer pool to use It is an identifier that indicates that the first data is stored in the accelerator card and the cache pool and that the data is consistent; write protection is set for the cache block where the first data is located.
- the embodiment of the present application also provides a data access device, including a creation unit, a storage unit, a recording unit, a write protection setting unit and an adjustment unit; the creation unit is used to create a cache pool on the host side that matches the memory capacity of the accelerator card ; Among them, the cache pool contains cache blocks divided according to set capacity units; the storage unit is used to call the target cache that matches the capacity of the target data from the cache pool when the read instruction of the target data is obtained.
- the recording unit is used to record the meta-information of the target cache block; where the meta-information includes the file number to which the target data belongs, the length of the target data, the address information of the target data, and the Status information representing the data synchronization status of the target cache block and the accelerator card; a write protection setting unit used to set write protection on the target cache block; an adjustment unit used to perform data access operations based on the status information corresponding to each cache block, And adjust the status information of the cache block after performing the data access operation; among which, the status information includes an identifier used to characterize the uncached data of the cache block, an identifier used to characterize only the cached data of the cache block, and an identifier used to characterize the cache block and the accelerator card. Both store data and the data is consistent, and the cache block and the accelerator card both store data and the data is inconsistent.
- a linked list creation unit is also included; a linked list creation unit is used to create a free linked list and a cache linked list; the free linked list is used to store unused cache blocks, and the cache linked list is used to store used cache blocks; correspondingly, a storage unit Used to select the target cache block that matches the capacity of the target data from the free linked list and the cache linked list when the read instruction of the target data is obtained, and store the target data in the target cache block; where, the target cache block stores to the cache linked list.
- the storage unit includes a storage sub-unit, a first reading sub-unit, a first storage sub-unit, a first establishing sub-unit, a releasing sub-unit, a second reading sub-unit, a second storing sub-unit, a second establishing sub-unit Subunit; storage subunit, used to store a free cache block in the free linked list to the cache linked list when the free linked list is not empty; the first read subunit, used to store a page fault exception when accessing the target data
- the first data block matching the set capacity unit from the disk the first storage subunit is used to store the first data block to the free cache block;
- the first creation subunit is used to create The mapping relationship between the physical address and the virtual address of the first data block;
- the release subunit is used to release an available cache block from the cache list when the free list is empty;
- the second read subunit is used to access the When a page fault exception occurs in the target data, read the second data block matching the set capacity unit from the disk; the second storage subunit
- the release subunit selects an available cache block from the cache link list according to the replacement algorithm of the cache link list; and writes back the original data in the available cache block to the disk.
- the recording unit is used to record the file number of the target data, the length of the target data, the offset of the target data in the file, the source address used to indicate the target cache block where the target data is located, and the acceleration corresponding to the source address.
- the destination address of the card and status information used to characterize the data synchronization status of the target cache block and the accelerator card.
- the adjustment unit is configured to adjust the status information to an identifier used to represent that both the accelerator card and the target cache block store data and that the data is consistent after transmitting the target data to the accelerator card.
- the adjustment unit is configured to modify the target data stored in the target cache block when receiving a target data modification instruction; adjust the status information of the target cache block to represent that both the accelerator card and the target cache block store Data and data inconsistency identification.
- a locking unit is also included; a locking unit is used for memory locking the cache blocks of the cache pool.
- it also includes a data caching judgment unit, a loading unit, an adding unit, a generating unit and a sending unit; a data caching judging unit, configured to judge whether the first data is Cached by the cache pool; the loading unit is used to load the first data from the disk into the cache pool when the first data is not cached by the cache pool; the adding unit is used to add the first data in the cache pool to DMA sending linked list; the generating unit is used to generate a DMA descriptor based on the meta-information corresponding to the cache block storing the first data; the sending unit is used to transmit the DMA descriptor to the accelerator card so that the accelerator card can obtain it based on the DMA descriptor DMA sends the first data contained in the linked list.
- a data caching judgment unit configured to judge whether the first data is Cached by the cache pool
- the loading unit is used to load the first data from the disk into the cache pool when the first data is not cached by the cache pool
- the adding unit is used to add the first data in
- the data cache judgment unit includes a construction subunit, a division subunit, a first judgment subunit, and a second judgment subunit; the construction subunit is configured to, upon receiving an accelerated processing instruction for the first data, perform the processing according to The file number and data amount of the first data are used to construct a file information linked list; the dividing subunit is used to divide the first data into file blocks according to the set capacity unit; the first judgment subunit is used to traverse the files in the file information linked list block, to determine whether the current file information list is empty; the second judgment subunit is used to determine whether the current file block is cached by the cache pool when the current file information list is not empty; correspondingly, the loading unit is used to When the current file block is not cached by the cache pool, load the current file block from the disk into the cache pool; add the current file block in the cache pool to the DMA sending linked list; until the current file information linked list is empty, trigger
- the generating unit performs the step of generating a DMA descriptor based on meta-information
- an identification judgment unit and a skip unit are also included; an identification judgment unit is used to judge whether the status information corresponding to the current cache block that caches the current file block is used when the current file block is cached by the cache pool.
- skip unit used when the status information corresponding to the current cache block is an identifier used to indicate that both the accelerator card and the current cache block store data and the data is consistent , skip the current file block.
- the adjustment unit is also configured to transfer the DMA descriptor to the accelerator card so that the accelerator card obtains the first data contained in the DMA transmission list according to the DMA descriptor, and then transfers the status information corresponding to the first data in the buffer pool to the accelerator card. It is adjusted to be an identifier used to represent that the accelerator card and the cache pool both store data and that the data is consistent; the write protection setting unit is also used to set write protection on the cache block where the first data is located.
- An embodiment of the present application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the above data access method.
- Embodiments of the present application also provide a non-volatile readable storage medium.
- a computer program is stored on the non-volatile readable storage medium.
- the computer program is executed by a processor, the steps of the above data access method are implemented.
- a cache pool matching the memory capacity of the accelerator card is created on the host side; the cache pool contains cache blocks divided according to set capacity units; the cache blocks can cache data, and the cache blocks Corresponding to the accelerator card, the data of the cache block can be transferred to the accelerator card.
- the capacity of the cache pool matches the memory capacity of the accelerator card, which can cache a large amount of data. Setting the capacity unit based on the single data transmission requirement can effectively solve the problem of wasting transmission bandwidth caused by too small a single transmission of data.
- the data in the cache pool can be transferred to the accelerator card, and the host side can record the meta information of the target cache block and set write protection on the target cache block; the meta information can include the file number to which the target data belongs, the length of the target data, and the target data.
- the accelerator card both stores data and the data is consistent, and the cache block and the accelerator card both store data and the data is inconsistent.
- a cache pool is created on the host side that matches the memory capacity of the accelerator card, and the cache pool is divided into multiple cache blocks according to the set capacity unit.
- the cache blocks are continuous large blocks of memory. The required With fewer transmission descriptors, a large amount of data can be continuously transmitted at one time, which improves bandwidth utilization and data transmission efficiency.
- the data read from the disk can be directly put into the cache pool, and the data in the cache pool can be directly transferred to the accelerator card.
- the target data is directly cached in the pre-allocated cache pool, and there is no need to transfer it to the accelerator card. Additional memory copy operations effectively reduce data transmission delays.
- Data that has been cached by the accelerator card and has consistent content does not need to be transmitted repeatedly, saving transmission time and improving execution efficiency. And by setting write protection on the target cache block where data is written, when the data in the target cache block changes, the status information can be dynamically adjusted, so that the host side can clearly understand the data in the cache pool and accelerate based on the status information. Whether the data in the card is synchronized to avoid repeated transmission of the same data.
- Figure 1 is a schematic structural diagram of a heterogeneous computing platform provided by the prior art
- Figure 2 is a schematic structural diagram of a heterogeneous computing platform based on continuous memory provided by the prior art
- Figure 3 is a flow chart of a data access method provided by an embodiment of the present application.
- Figure 4 is a file system cache architecture diagram provided by an embodiment of the present application.
- Figure 5 is a schematic diagram of meta-information provided by an embodiment of the present application.
- Figure 6 is a schematic diagram of cached data in a host-side buffer pool provided by an embodiment of the present application.
- Figure 7 is a flow chart of a method for selecting a target cache block from a free linked list and a cache linked list to store target data according to an embodiment of the present application:
- Figure 8 is a schematic diagram of a free cache block storing data provided by an embodiment of the present application.
- Figure 9 is a schematic diagram of a usable cache block for storing data provided by an embodiment of the present application.
- Figure 10 is a schematic diagram of modifying cache block data provided by an embodiment of the present application.
- Figure 11 is a schematic flow chart of a method of transmitting data to an accelerator card provided by an embodiment of the present application.
- Figure 12 is a schematic diagram for querying the total salary expenditure provided by the embodiment of the present application.
- Figure 13 is a schematic diagram of querying the number of company positions provided by the embodiment of the present application.
- Figure 14 is a schematic diagram of modifying the salary schedule provided by the embodiment of the present application.
- Figure 15 is a schematic diagram of querying a doctorate degree or above provided by the embodiment of the present application.
- Figure 16 is a schematic structural diagram of a data access device provided by an embodiment of the present application.
- Figure 17 is a structural diagram of an electronic device provided by an embodiment of the present application.
- Figure 3 is a flow chart of a data access method provided by an embodiment of the present application. The method includes:
- S301 Create a cache pool on the host side that matches the memory capacity of the accelerator card.
- the memory space on the host side can be divided into a memory space that matches the memory capacity of the accelerator card, and the divided memory space can be used as a cache pool.
- the cache pool implementation Data transfer to and from the accelerator card.
- a cache pool with the same memory capacity as the accelerator card can be created on the host side. For example, if the memory of the accelerator card is 8GB, 8GB of memory can be divided into the host-side memory as a cache pool.
- the capacity unit can be set. Divide the cache pool into multiple cache blocks according to set capacity units.
- different capacity units can be set for different cache blocks, or all cache blocks can be divided into the same capacity unit.
- the capacity unit can be set to 8MB.
- Figure 4 is a file system cache architecture diagram provided by an embodiment of the present application.
- Figure 4 includes three parts: a disk, a host side, and an accelerator card.
- Figure 4 takes 4 cache blocks as an example, and the arrows indicate the direction of data transmission.
- data transmission between the host side and the accelerator card can be divided into the following four situations: (1) The host side does not cache the data block. (2) The data block is cached on the host side, but there is no cache in the accelerator card. (3) Both the host side and the accelerator card cache the data block, but the data on the host side is modified, causing the data cached on the host side and the accelerator card to be inconsistent. (4) Both the host side and the accelerator card are cached and consistent.
- the data can be read from the disk into the cache block of the cache pool, the cached data can be sent to the accelerator card memory, and the status of the cache block can be modified.
- the information is: Both the host and the accelerator card are cached and consistent.
- the data of the cache block can be sent to the accelerator card, and the status information of the cache block can be modified to: both the host and the accelerator card are cached and consistent.
- the data of the cache block can be sent to the accelerator card, and the status information of the cache block can be modified to: both the host and the accelerator card are cached and consistent.
- the data on the host side and the accelerator card are consistent, so there is no need to transmit the cache block, which avoids repeated data transmission and reduces bandwidth usage.
- the cache pool does not store data, and the data is all located on the disk.
- the target data needs to be read from the disk.
- the target cache block that matches the capacity of the target data.
- each cache block As an example and assuming that the target data size is 15MB, two cache blocks are needed to accommodate the target data.
- the cache block used to cache target data is called a target cache block.
- S303 Store the target data in the target cache block, record meta information of the target cache block, and set write protection on the target cache block.
- Meta information can be set for each target cache block.
- Meta information can include information used to characterize the target cache block and the accelerator card. The status information of the data synchronization status, the file number to which the target data belongs, the length of the target data, and the address information of the target data.
- the address information of the target data may include the offset of the target data in the file, the source address of the target data in the cache pool, the destination address of the accelerator card corresponding to the source address, etc.
- a complete file may require multiple cache blocks to accommodate it.
- the file can be divided into multiple target data according to the capacity of each cache block, and each target data is stored in a cache block of corresponding capacity.
- the block number can be added to the meta information.
- a timestamp can be added to the metainformation, and the time when the cache block writes the target data is used as the timestamp.
- Figure 5 is a schematic diagram of meta information provided by an embodiment of the present application.
- the capacity of each cache block is 8MB.
- Each cache block has its corresponding meta information.
- the meta information can include block number, synchronization
- Each element has its corresponding storage space. For example, 4 bytes or 4B can be used to record the block number, and 8 bytes can be used to record the source address, etc.
- the elements contained in the meta-information can also be added or deleted according to requirements.
- the elements contained in the meta-information in Figure 5 are only examples and do not limit the elements contained in the meta-information.
- each cache block As an example, assuming that the accelerator card has 8GB of memory, the host side applies for 1024 cache blocks, and the physical memory addresses of each cache block are consecutive. Lock all cache blocks in memory and mark all pages as non-swapable by modifying the page flag bit.
- the accelerator card memory can be divided into 1024 memory blocks in units of 8MB. The source address in the host-side cache block is written to the address of the data area, and the destination address is written to the acceleration Card memory block offset.
- S304 Perform a data access operation according to the status information corresponding to each cache block, and adjust the status information of the cache block after the data access operation is performed.
- the data synchronization status between the cache pool and the accelerator card on the host side can include four situations.
- the first situation is that neither the cache pool nor the accelerator card caches data;
- the second situation is that the cache pool caches data.
- the accelerator card does not cache data;
- the third case is that the cache pool and the accelerator card both store data and the data is consistent;
- the fourth case is that the cache pool and the accelerator card both store data and the data is inconsistent.
- the cache pool can be divided into multiple cache blocks according to the set capacity unit. Each cache block is a continuous large block of memory. Data transmission uses the cache block as the basic transmission unit. For each cache block, its corresponding status will be set. information. Combined with the four situations included in the data synchronization status between the cache pool and the accelerator card on the host side, the status information can include an identifier used to characterize the uncached data of the cache block, an identifier used to characterize only the cached data of the cache block, and an identifier used to characterize the cache. An identifier indicating that both the block and the accelerator card store data and the data is consistent, and an identifier used to indicate that both the cache block and the accelerator card store data and the data is inconsistent.
- FIG. 6 is a schematic diagram of cached data in a host-side buffer pool provided by an embodiment of the present application.
- the accelerator card memory is divided into 1024 accelerator card memory blocks in units of 8MB.
- the corresponding divisions on the host side are 1024 Cache block, the data area of each cache block is 8MB in size, and the physical memory address is continuous.
- Put the cache block into the free list. Lock all cache blocks in memory, and mark all pages as non-swapable by modifying the page flag bit.
- the source address in the host-side cache block is written into the address of the data area, and the destination address is written into the accelerator card memory block offset.
- the cache pool contains multiple cache blocks. After some cache blocks in the cache pool store data, when new data needs to be cached, free cache blocks need to be selected from the cache pool to store new data.
- an idle linked list and a cache linked list can be created; the idle linked list is used to store unused cache blocks, and the cache The linked list is used to store used cache blocks.
- the target cache block matching the capacity of the target data can be selected from the free linked list and the cache linked list; the selected target cache block is used to store the target data, so The target cache block can be stored in the cache linked list.
- the cache blocks in the cache linked list all store data.
- the cache blocks in the free linked list are unused free cache blocks. In practical applications, there will be a problem of insufficient space for the free cache blocks in the free linked list. In this case, it is necessary to obtain the data from the cache linked list. Release some cache blocks to ensure smooth caching of data.
- a cache pool matching the memory capacity of the accelerator card is created on the host side; the cache pool contains cache blocks divided according to set capacity units; the cache blocks can cache data, and the cache blocks Corresponding to the accelerator card, the data of the cache block can be transferred to the accelerator card.
- the capacity of the cache pool matches the memory capacity of the accelerator card, which can cache a large amount of data. Setting the capacity unit based on the single data transmission requirement can effectively solve the problem of wasting transmission bandwidth caused by too small a single transmission of data.
- the data in the cache pool can be transferred to the accelerator card, and the host side can record the meta information of the target cache block and set write protection on the target cache block; the meta information can include the file number to which the target data belongs, the length of the target data, and the target data.
- the accelerator card both stores data and the data is consistent, and the cache block and the accelerator card both store data and the data is inconsistent.
- a cache pool is created on the host side that matches the memory capacity of the accelerator card, and the cache pool is divided into multiple cache blocks according to the set capacity unit.
- the cache blocks are continuous large blocks of memory. The required With fewer transmission descriptors, a large amount of data can be continuously transmitted at one time, which improves bandwidth utilization and data transmission efficiency.
- the data read from the disk can be directly put into the cache pool, and the data in the cache pool can be directly transferred to the accelerator card.
- the target data is directly cached in the pre-allocated cache pool, and there is no need to transfer it to the accelerator card. Additional memory copy operations effectively reduce data transmission delays.
- Data that has been cached by the accelerator card and has consistent content does not need to be transmitted repeatedly, saving transmission time and improving execution efficiency. And by setting write protection on the target cache block where data is written, when the data in the target cache block changes, the status information can be dynamically adjusted, so that the host side can clearly understand the data in the cache pool and accelerate based on the status information. Whether the data in the card is synchronized to avoid repeated transmission of the same data.
- the operating system divides physical memory into fixed-size pages (usually 4KB) and manages them according to page size. Each page has a flag indicating whether the memory can be cached to disk. For memory pages that can be temporarily saved to disk, when the operating system runs out of memory, the data in the page will be written to the disk, thereby freeing up free pages for other processes to use. This operation is called page swapping out.
- page swapping out In heterogeneous computing scenarios, in order to ensure that the page will not be accidentally swapped out to the disk during the process of transmitting data from the host side to the accelerator card, the flag bit of the corresponding page needs to be modified to not be swapped out. This operation is called page locking. .
- the cache blocks in the cache pool can be Perform memory locking to prevent other processes from occupying or swapping memory pages to disk.
- Figure 7 is a flow chart of a method for selecting a target cache block from a free linked list and a cache linked list to store target data provided by an embodiment of the present application.
- the method includes:
- the free linked list contains unused free cache blocks.
- free cache blocks for caching data are first selected from the free linked list.
- S702 Store a free cache block in the free linked list to the cache linked list.
- the selected free cache block needs to store the target data.
- the selected space cache block can be stored in the cache link list, so that the target data can be stored in the free cache block of the cache link list.
- Each file in the file system has a unique file number, which is an index number.
- the operating system can find the data blocks of the file on the disk based on the index number.
- the operating system will cause a page fault exception.
- the CPU hardware will mark the cause of the page missing exception as: there is no corresponding physical address.
- the operating system will call the general cache application interface of the file system, apply for memory in 4KB units as file cache blocks, store disk data, and then establish a mapping relationship between the cache block physical address and the file virtual address.
- a page fault exception without a physical address will not occur.
- the data when obtaining the target data, the data will be read according to the size of 4KB.
- the data corresponding to the current data can be read according to the set capacity unit. block, this data block may be called the first data block.
- the first data block may be part or all of the target data.
- the target data is 7MB and the currently read data belongs to data between 0 and 7MB
- the target data between 0 and 7MB can be used as the first data block.
- the target data is 15MB
- the currently read data is between 0 and 8MB (excluding the 8th MB).
- the data between 0 and 8MB in the target data can be used as the first data block.
- the currently read data belongs to data between 8MB and 15MB (including the 8th MB).
- the data between 8MB and 15MB in the target data can be used as the first data block.
- the host side When a page fault occurs when accessing target data, the host side reads the first data block from the disk and stores the first data block into a free cache block.
- S704 Establish a mapping relationship between the physical address and the virtual address of the first data block.
- the file number of the first data block, the length of the first data block, the offset of the first data block in the file, and the information used to indicate the free cache where the first data block is located can be recorded.
- S705 Release an available cache block from the cache link list. When a page fault occurs when accessing the target data, read the second data block matching the set capacity unit from the disk and store the second data block in the available cache block. cache block.
- releasing an available cache block from the cache link list may be to select a cache block with the longest data storage time from the cache link list, and write the data of the cache block back to the disk.
- the cache block is Empty, for ease of distinction, this cache block can be called an available cache block.
- an available cache block can be selected from the cache link list based on the cache link list replacement algorithm (Least Recently Used, LRU); the original data in the available cache block can be written back to the disk.
- LRU cache link list replacement algorithm
- the capacity of the target data is 15MB
- the capacity of each cache block is 8MB
- the free linked list contains a free cache block
- all cache blocks in the cache linked list store data.
- you can The free cache block in the free linked list is stored in the cache linked list.
- This free cache block can store 8MB of data.
- an available cache block needs to be released from the cache linked list, so that the released available cache block can be used for storage.
- the remaining 7MB of data is stored, thereby achieving smooth storage of the target data.
- S706 Establish a mapping relationship between the physical address and the virtual address of the second data block.
- the file number of the second data block, the length of the second data block, the offset of the second data block in the file, and the available cache used to indicate where the second data block is located can be recorded.
- S707 Determine whether all data blocks divided by the target data are stored in the target cache block.
- Figure 8 is a schematic diagram of a free cache block storing data provided by an embodiment of the present application.
- the first data block reading process is shown in Figure 8, including: 1 Take out an free cache block from the free linked list, and cache the free cache block. The block is put into the cache linked list; the dotted line with an arrow in Figure 8 indicates that the free cache block is put into the cache linked list. 2Read 8MB data from the disk and store it in the free cache block.
- 3 Set the virtual address to physical address mapping relationship 4Set the length of the free cache block to 8MB, the file number to the corresponding index number, and the file offset to 0. 5 Mark the status of the free cache block as 1, indicating that the data stored in the free cache block has not been cached in the accelerator card memory. 6Set the 8MB data area page table attribute to write protection. 7Update timestamp.
- Figure 9 is a schematic diagram of a usable cache block to store data provided by the embodiment of the present application.
- the second data block reading process is shown in Figure 9, including: 1 According to the LRU algorithm, select a replacement from the cache linked list cache block. 2Write the data of the cache block back to the disk. At this time, there is no data in the cache block, and the cache block can be called an available cache block. 3Read 7MB data from the disk into the replaced cache block. 4Set the mapping relationship between virtual address and physical address. 5Set the cache block length to 7MB, the file number to the corresponding index number, and the file offset to 8MB. 6 Mark the cache block status as 1, which means that the data stored in the cache block has not been cached in the accelerator card memory. 7Set the 8MB data area page table attribute to write protection. 8Update timestamp.
- the timestamp can be the time the data was written to the cache block.
- the metainformation corresponding to each cache block can be mounted separately, and a pointer can be set to point to the corresponding cache block. Metainformation and cache blocks can also be placed together.
- a cache pool can be constructed based on the storage space occupied by each metainformation and the memory capacity of the accelerator card.
- the status information is adjusted to an identifier used to represent that both the accelerator card and the target cache block store data and the data is consistent. For example, the status information may use the number "0", indicating that the accelerator card and target cache block data are consistent.
- the behavior of data manipulation in the cache block can be detected, so that the synchronization status can be updated in a timely manner.
- the operating system will set the flag bit of the page to a dirty page in the write-protected page fault exception handling function, indicating that the data in the memory is inconsistent with the data in the disk.
- the operating system background thread writes a page marked as a dirty page to the disk, it will cancel the dirty page mark of the page and reset the page attribute to write protection.
- the host-side cache block is inconsistent with the disk and accelerator card memory.
- the operating system background thread writes the dirty pages to the disk, the host-side cache block is consistent with the disk data, but is still inconsistent with the accelerator card memory.
- the management of the accelerator card cache block will be added to the write-protected page fault exception, and the status information used to represent the data synchronization status of the cache block and the accelerator card memory will be added to the meta-information corresponding to the cache block. , using status information to mark whether the contents of the host-side cache block and the accelerator card memory block are consistent.
- the status information can be adjusted to represent that both the accelerator card and the target cache block are stored Data and data inconsistency identification. For example, the status information may use the number "2", indicating that the accelerator card and target cache block data are inconsistent.
- Figure 10 is a schematic diagram of modifying cache block data provided by an embodiment of the present application. Assume that a 15MB file has been cached by the cache pool. The first cache block stores 8MB data, and the second cache block stores 7MB data. Since the data page is set to be write-protected, a write operation on any 15MB data page will trigger a page missing exception. The system will mark the reason in the page missing exception as: a write operation occurred on a write-protected page. In the embodiment of this application, in the corresponding page fault exception processing logic, the status information corresponding to the cache block is modified to 2, indicating that the accelerator card and cache block data are inconsistent.
- disk data can be directly cached in a large block of continuous memory.
- status information about the synchronization status of the cache block and the accelerator card memory data it is possible to know in a timely manner whether the data in the accelerator card memory and the cache block are Consistent, for example, when the cache block data has been stored in the accelerator card, the status information is 0 at this time, indicating that the accelerator card and cache block data are consistent.
- the accelerator card needs to be used to perform operations on the data, there is no need to transmit the data from the cache block to the accelerator card, reducing unnecessary data transmission.
- Figure 11 is a schematic flowchart of a method of transmitting data to an accelerator card provided by an embodiment of the present application. The method includes:
- S1001 Upon receiving an accelerated processing instruction for the first data, determine whether the first data is cached by the cache pool.
- the data currently required to be transmitted to the accelerator card may be called first data.
- the first data In the case where the first data is not cached by the cache pool, the first data needs to be read from the disk, that is, S1002 is executed.
- S1002 Load the first data from the disk into the buffer pool; add the first data in the buffer pool to the DMA sending linked list.
- the first data When the first data is not cached by the cache pool, the first data needs to be read from the disk first.
- the data When transmitting data from the cache pool to the accelerator card, the data needs to be converted into a format that can be recognized by the accelerator card.
- a DMA (Direct Memory Access) sending linked list can be constructed.
- the data from the cache pool needs to be transferred to When accelerating the card, first add the first data in the buffer pool to the DMA sending chain list.
- S1003 Determine whether the status information corresponding to the first data is an identifier used to indicate that data is stored in both the accelerator card and the cache pool and is consistent.
- S1004 is executed.
- the status information corresponding to the first data is an identifier used to indicate that both the accelerator card and the cache pool store data and the data are consistent, it means that the first data has been stored in the accelerator card, and there is no need to transmit the third data to the accelerator card at this time. Once you have the data, you can end the operation directly.
- S1005 Generate a DMA descriptor according to meta-information corresponding to the cache block storing the first data.
- the DMA descriptor is used to indicate the source address, destination address and data length of the data in the cache block.
- the DMA descriptor belongs to the data format recognized by the accelerator card.
- S1006 Transmit the DMA descriptor to the accelerator card, so that the accelerator card obtains the first data contained in the DMA transmission list based on the DMA descriptor.
- the host transmits the DMA descriptor to the accelerator card, and the accelerator card can obtain the first data based on the DMA descriptor.
- the accelerator card after transmitting the DMA descriptor to the accelerator card, the accelerator card can obtain the first data contained in the DMA transmission list based on the DMA descriptor. At this time, the accelerator card and the cache pool data are consistent. Therefore, after transmitting the DMA descriptor to the accelerator card, the status information corresponding to the first data in the cache pool can be adjusted to an identifier used to represent that both the accelerator card and the cache pool store data and the data is consistent; The cache block is write-protected.
- disk data is directly cached in a large block of continuous memory.
- cache blocks and accelerator card memory synchronization marks that is, status information, unnecessary data transmission is reduced.
- the file information can be constructed based on the file number and data volume of the first data after receiving the accelerated processing instruction of the first data.
- Linked list divide the first data into file blocks according to the set capacity unit; traverse the file blocks of the file information linked list, and determine whether the current file information linked list is empty; when the current file information linked list is not empty, determine the current file block Whether it is cached by the cache pool.
- the cache pool When the current file block is cached by the cache pool, it is necessary to determine whether the status information corresponding to the current cache block that caches the current file block is an identifier used to indicate that both the accelerator card and the current cache block store data and the data is consistent.
- the status information corresponding to the current cache block is an identifier used to indicate that both the accelerator card and the current cache block store data and the data is inconsistent, it means that the current file block needs to be transferred to the accelerator card.
- the current file in the cache pool can be The block is added to the DMA transmit list.
- the status information corresponding to the current cache block is an identifier used to indicate that both the accelerator card and the current cache block store data and the data is consistent, it means that the current file block has been stored in the accelerator card, and the current file block can be skipped at this time.
- the current file information list is empty, it means that all the data to be transmitted to the accelerator card has been added to the DMA transmission list.
- a DMA descriptor can be generated based on the meta-information corresponding to the cache block storing the first data; to the accelerator card The DMA descriptor is transmitted so that the accelerator card obtains the first data contained in the DMA transmission list based on the DMA descriptor.
- Salary table file size 32MB, including fields: employee ID, monthly performance, salary, bonus
- Position information table file size 1MB, including fields : Position ID, position name, job content
- Employee information table file size 16MB, including fields: employee ID, name, position ID, phone number, education.
- the salary table needs to be modified.
- the CPU modifies the relevant data blocks and modifies the cache block to mark it as inconsistent with the accelerator card memory.
- the data block cache operation is as shown in Figure 14. Since only part of the data is modified, a page missing exception will be triggered when the CPU modifies the corresponding page. In the page missing exception: 1 Modify the corresponding cache block mark to 2, indicating that the host side cache and the cache block data in the accelerator card are inconsistent.
- a storage system includes: NVME hard disks, mechanical disks, and network storage.
- the capacity increases in sequence, but the performance decreases in sequence. Repeated transmissions can also be reduced by adding tags to data blocks.
- Figure 16 is a schematic structural diagram of a data access device provided by an embodiment of the present application, including a creation unit 151, a storage unit 152, a recording unit 153, a write protection setting unit 154 and an adjustment unit 155;
- the creation unit 151 is used to create a cache pool on the host side that matches the memory capacity of the accelerator card; wherein the cache pool contains cache blocks divided according to set capacity units; the storage unit 152 is used to read the target data after obtaining the target data. In the case of fetching instructions, the target cache block matching the capacity of the target data is called from the cache pool, and the target data is stored in the target cache block; the recording unit 153 is used to record meta-information of the target cache block; wherein the meta-information includes The file number to which the target data belongs, the length of the target data, the address information of the target data, and status information used to represent the data synchronization status of the target cache block and the accelerator card; the write protection setting unit 154 is used to set write settings on the target cache block.
- adjustment unit 155 used to perform data access operations based on the status information corresponding to each cache block, and adjust the status information of the cache block after performing the data access operation; wherein, the status information includes a cache block used to indicate that the cache block is not cached
- the identifier of the data, the identifier used to represent that only the cache block caches the data, the identifier used to represent that both the cache block and the accelerator card store data and the data is consistent, and the identifier used to represent that the cache block and the accelerator card both store data and the data is inconsistent.
- a linked list creation unit is also included; a linked list creation unit is used to create a free linked list and a cache linked list; the free linked list is used to store unused cache blocks, and the cache linked list is used to store used cache blocks; correspondingly, a storage unit Used to select the target cache block that matches the capacity of the target data from the free linked list and the cache linked list when the read instruction of the target data is obtained, and store the target data in the target cache block; where, the target cache block stores to the cache linked list.
- the storage unit includes a storage sub-unit, a first reading sub-unit, a first storage sub-unit, a first establishing sub-unit, a releasing sub-unit, a second reading sub-unit, a second storing sub-unit, a second establishing sub-unit Subunit; storage subunit, used to store a free cache block in the free linked list to the cache linked list when the free linked list is not empty; the first read subunit, used to store a page fault exception when accessing the target data
- the first data block matching the set capacity unit from the disk the first storage subunit is used to store the first data block to the free cache block;
- the first creation subunit is used to create The mapping relationship between the physical address and the virtual address of the first data block;
- the release subunit is used to release an available cache block from the cache list when the free list is empty;
- the second read subunit is used to access the When a page fault exception occurs in the target data, read the second data block matching the set capacity unit from the disk; the second storage subunit
- the release subunit selects an available cache block from the cache link list according to the replacement algorithm of the cache link list; and writes back the original data in the available cache block to the disk.
- the recording unit is used to record the file number of the target data, the length of the target data, the offset of the target data in the file, the source address used to indicate the target cache block where the target data is located, and the acceleration corresponding to the source address.
- the destination address of the card and status information used to characterize the data synchronization status of the target cache block and the accelerator card.
- the adjustment unit is configured to adjust the status information to an identifier used to represent that both the accelerator card and the target cache block store data and that the data is consistent after transmitting the target data to the accelerator card.
- the adjustment unit is configured to modify the target data stored in the target cache block when receiving a target data modification instruction; adjust the status information of the target cache block to represent that both the accelerator card and the target cache block store Data and data inconsistency identification.
- a locking unit is also included; a locking unit is used for memory locking the cache blocks of the cache pool.
- it also includes a data caching judgment unit, a loading unit, an adding unit, a generating unit and a sending unit; a data caching judging unit, configured to judge whether the first data is Cached by the cache pool; the loading unit is used to load the first data from the disk into the cache pool when the first data is not cached by the cache pool; the adding unit is used to add the first data in the cache pool to DMA sending linked list; the generating unit is used to generate a DMA descriptor based on the meta-information corresponding to the cache block storing the first data; the sending unit is used to transmit the DMA descriptor to the accelerator card so that the accelerator card can obtain it based on the DMA descriptor DMA sends the first data contained in the linked list.
- a data caching judgment unit configured to judge whether the first data is Cached by the cache pool
- the loading unit is used to load the first data from the disk into the cache pool when the first data is not cached by the cache pool
- the adding unit is used to add the first data in
- the data cache judgment unit includes a construction subunit, a division subunit, a first judgment subunit, and a second judgment subunit; the construction subunit is configured to, upon receiving an accelerated processing instruction for the first data, perform the processing according to The file number and data amount of the first data are used to construct a file information linked list; the dividing subunit is used to divide the first data into file blocks according to the set capacity unit; the first judgment subunit is used to traverse the files in the file information linked list block, to determine whether the current file information list is empty; the second judgment subunit is used to determine whether the current file block is cached by the cache pool when the current file information list is not empty; correspondingly, the loading unit is used to When the current file block is not cached by the cache pool, load the current file block from the disk into the cache pool; add the current file block in the cache pool to the DMA sending linked list; until the current file information linked list is empty, trigger
- the generating unit performs the step of generating a DMA descriptor based on meta-information
- an identification judgment unit and a skip unit are also included; an identification judgment unit is used to judge whether the status information corresponding to the current cache block that caches the current file block is used when the current file block is cached by the cache pool.
- skip unit used when the status information corresponding to the current cache block is an identifier used to indicate that both the accelerator card and the current cache block store data and the data is consistent , skip the current file block.
- the adjustment unit is also configured to transfer the DMA descriptor to the accelerator card so that the accelerator card obtains the first data contained in the DMA transmission list according to the DMA descriptor, and then transfers the status information corresponding to the first data in the buffer pool to the accelerator card. Adjusted to be an identifier used to represent that the accelerator card and the first cache pool both store data and the data is consistent; the write protection setting unit is also used to set write protection on the cache block where the first data is located.
- a cache pool matching the memory capacity of the accelerator card is created on the host side; the cache pool contains cache blocks divided according to set capacity units; the cache blocks can cache data, and the cache blocks Corresponding to the accelerator card, the data of the cache block can be transferred to the accelerator card.
- the capacity of the cache pool matches the memory capacity of the accelerator card, which can cache a large amount of data. Setting the capacity unit based on the single data transmission requirement can effectively solve the problem of wasting transmission bandwidth caused by too small a single transmission of data.
- the data in the cache pool can be transferred to the accelerator card, and the host side can record the meta information of the target cache block and set write protection on the target cache block; the meta information can include the file number to which the target data belongs, the length of the target data, and the target data.
- the accelerator card both stores data and the data is consistent, and the cache block and the accelerator card both store data and the data is inconsistent.
- a cache pool is created on the host side that matches the memory capacity of the accelerator card, and the cache pool is divided into multiple cache blocks according to the set capacity unit.
- the cache blocks are continuous large blocks of memory. The required With fewer transmission descriptors, a large amount of data can be continuously transmitted at one time, which improves bandwidth utilization and data transmission efficiency.
- the data read from the disk can be directly put into the cache pool, and the data in the cache pool can be directly transferred to the accelerator card.
- the target data is directly cached in the pre-allocated cache pool, and there is no need to transfer it to the accelerator card. Additional memory copy operations effectively reduce data transmission delays.
- Data that has been cached by the accelerator card and has consistent content does not need to be transmitted repeatedly, saving transmission time and improving execution efficiency. And by setting write protection on the target cache block where data is written, when the data in the target cache block changes, the status information can be dynamically adjusted, so that the host side can clearly understand the data in the cache pool and accelerate based on the status information. Whether the data in the card is synchronized to avoid repeated transmission of the same data.
- Figure 17 is a structural diagram of an electronic device provided by an embodiment of the present application. As shown in Figure 17, the electronic device includes: a memory 20, used to store a computer program; a processor 21, used to implement the above implementation when executing the computer program. Example data access method steps.
- Electronic devices provided in this embodiment may include, but are not limited to, smartphones, tablets, laptops, or desktop computers.
- the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc.
- the processor 21 can adopt at least one hardware form among DSP (Digital Signal Processing, digital signal processing), FPGA (Field-Programmable Gate Array, field programmable gate array), and PLA (Programmable Logic Array, programmable logic array).
- the processor 21 may also include a main processor and a co-processor.
- the main processor is a processor used to process data in the wake-up state, also called CPU (Central Processing Unit, central processing unit); the co-processor is A low-power processor used to process data in standby mode.
- the processor 21 may be integrated with a GPU (Graphics Processing Unit, image processor), and the GPU is responsible for rendering and drawing content that needs to be displayed on the display screen.
- the processor 21 may also include an AI (Artificial Intelligence, artificial intelligence) processor, which is used to process computing operations related to machine learning.
- AI Artificial Intelligence, artificial intelligence
- Memory 20 may include one or more non-volatile readable storage media, which may be non-transitory.
- the memory 20 may also include high-speed random access memory, and non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices.
- the memory 20 is at least used to store the following computer program 201. After the computer program is loaded and executed by the processor 21, the relevant steps of the data access method disclosed in any of the foregoing embodiments can be implemented.
- the resources stored in the memory 20 may also include the operating system 202, data 203, etc., and the storage method may be short-term storage or permanent storage.
- the operating system 202 may include Windows, Unix, Linux, etc.
- Data 203 may include, but is not limited to, meta information and the like.
- the electronic device may also include a display screen 22 , an input-output interface 23 , a communication interface 24 , a power supply 25 and a communication bus 26 .
- FIG. 17 does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure.
- the data access method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
- the technical solution of the present application is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , execute all or part of the steps of the methods of various embodiments of this application.
- the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (Random Access Memory, RAM), electrically erasable programmable ROM, register, hard disk, removable memory.
- Various media that can store program code such as removable disks, CD-ROMs, magnetic disks or optical disks.
- embodiments of the present application also provide a non-volatile readable storage medium.
- a computer program is stored on the non-volatile readable storage medium.
- the above data access method is implemented. step.
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Abstract
一种数据存取方法、装置、设备和计算机可读存储介质,在主机侧创建与加速卡内存容量匹配的缓存池;缓存池中包含按照设定的容量单位划分的缓存块。在获取到目标数据的读取指令的情况下,从缓存池中调用与目标数据的容量匹配的目标缓存块,将目标数据存储至目标缓存块。记录目标缓存块的元信息,并对目标缓存块设置写保护。依据各缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息,可以避免主机侧与加速卡之间相同数据的重复传输。缓存块为连续的大块内存,所需的传输描述符少,可一次性连续传输大量数据,提升了带宽利用率,提高了数据传输效率。
Description
相关申请的交叉引用
本申请要求于2022年9月6日提交中国专利局,申请号为202211081605.9,申请名称为″一种数据存取方法、装置、设备和计算机可读存储介质″的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本申请涉及计算机技术领域,特别是涉及一种数据存取方法、装置、设备和非易失性可读存储介质。
文件***用于管理磁盘上的数据块,当磁盘进行格式化后,文件***便按照固定的格式将数据在磁盘上进行写入和读出。由于内存的访问带宽远大于磁盘,根据CPU(Central Processing Unit/Processor,中央处理器)访问数据的局部性原理,文件***会将CPU最近访问的磁盘数据块,在内存进行缓存称为文件缓存。当CPU再次访问相同位置的文件块,便不再从磁盘中读取,而是直接将文件缓存中的数据返回给CPU,从而提高***的整体性能。
随着人工智能、大数据的发展,传统架构下依赖CPU进行运算的模式难以满足新业务对计算机算力的需求。为了解决传统架构下算力不足的问题,近年来业界普遍采用GPU(Graphics Processing Unit,图形处理器)、FPGA(Field-Programmable Gate Array,现场可编程门阵列)、ASCI(Application Specific Integrated Circuit,集成电路)等加速卡,以异构计算的方式实现***整体性能的提升。
图1为现有技术提供的一种异构计算平台的结构示意图,异构计算方式中将数据从磁盘中读取到文件缓存后,再发送到加速卡进行计算,最后将计算完的结果从加速卡中读取到***内存。由于加速卡对特定数据的算力远远超过CPU算力,因此通过异构计算方式能够显著的提高***的整体性能。
但是异构计算方式需要将文件缓存中的数据传输到加速卡中,再从加速卡中取出计算完成的数据,引入了数据来回搬运的开销,降低了使用异构计算所能获得的性能收益。传统的文件***缓存,按照4KB大小页面管理内存,文件分割为多个4KB大小的数据块再进行缓存。DMA(Direct Memory Access,直接存储访问)传输前,需要以4KB为单位,逐个遍历所有页面进行内存锁定,耗时较长。同时一个描述符只能描述4KB大小,加速卡一次只能获取4KB数据,限制了DMA的传输带宽。由于数据块在内存中是不连续的随机分布,因此需要以4K为单位,给每一个页面都构建一个DMA描述符,过多的描述符创建导致耗时较长。
针对缓存块小且不连续所导致的DMA传输效率低的问题,提出了预先申请大块连续内存的方式,图2为现有技术提供的一种基于连续内存的异构计算平台的结构示意图,对于文件页面的操作过程包括①主机侧从磁盘读取的数据在操作***的文件缓存中缓存。②CPU将文件缓存中的数据块拷贝到连续的匿名页中。③将匿名页中的数据发送至加速卡。由于匿名页面是连续的大块内存,因此DMA描述符的构建很快,加速卡一次获取大块内存DMA带宽也相应提高。④加速卡计算完成后,主机侧从加速卡中获取计算的结果。测试发现,虽然步骤③使用连续内存,大幅提高了DMA数据发送效率,但步骤②中的拷贝操作仍会引入较大的延迟。
预先申请大块连续内存的方式虽然减少了DMA描述符创建时间,提高了加速卡DMA带宽。但是该实现方式仅适用于匿名页的场景,对文件页面存在拷贝开销,影响了整体性能。并且目前的文件***缓存管理机制中,并不管理加速卡内的数据。由于加速卡内的数据并不与文件存在对应关系,因此即使加速卡在上次计算中已经缓存了文件数据块,下一次计算需要的文件数据,仍需要从主机侧传输到加速卡中,造成 了重复传输,浪费了大量传输带宽。
可见,如何提升带宽利用率,降低数据传输延迟,是本领域技术人员需要解决的问题。
发明内容
本申请实施例的目的是提供一种数据存取方法、装置、设备和非易失性可读存储介质,可以提升带宽利用率,降低数据传输延迟。
为解决上述技术问题,本申请实施例提供一种数据存取方法,包括:在主机侧创建与加速卡内存容量匹配的缓存池;其中,缓存池中包含按照设定的容量单位划分的缓存块;在获取到目标数据的读取指令的情况下,从缓存池中调用与目标数据的容量匹配的目标缓存块,将目标数据存储至目标缓存块;记录目标缓存块的元信息,并对目标缓存块设置写保护;其中,元信息包括目标数据所属的文件号、目标数据的长度、目标数据的地址信息,以及用于表征目标缓存块与加速卡的数据同步状态的状态信息;依据各缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息;其中,状态信息包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均存储数据且数据不一致的标识。
可选地,在主机侧创建与加速卡内存容量匹配的缓存池之后还包括:创建空闲链表和缓存链表;空闲链表用于存放未使用的缓存块,缓存链表用于存放已使用的缓存块;相应的,在获取到目标数据的读取指令的情况下,从缓存池中调用与目标数据的容量匹配的目标缓存块,将目标数据存储至目标缓存块包括:在获取到目标数据的读取指令的情况下,从空闲链表和缓存链表中选取与目标数据的容量相匹配的目标缓存块,将目标数据存储至目标缓存块;其中,目标缓存块存放至缓存链表中。
可选地,从空闲链表和缓存链表中选取与目标数据的容量相匹配的目标缓存块,将目标数据存储至目标缓存块包括:在空闲链表不为空的情况下,将空闲链表中的一个空闲缓存块存放至缓存链表;在访问目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第一数据块,将第一数据块存储至空闲缓存块;建立第一数据块的物理地址和虚拟地址的映射关系;在空闲链表为空的情况下,从缓存链表中释放一个可用缓存块,在访问目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第二数据块,将第二数据块存储至可用缓存块;建立第二数据块的物理地址和虚拟地址的映射关系;直至目标数据划分的所有数据块均存储至目标缓存块,则结束操作。
可选地,从缓存链表中释放一个可用缓存块包括:依据缓存链表的替换算法,从缓存链表中选出一个可用缓存块;将可用缓存块中的原有数据回写到磁盘。
可选地,记录目标缓存块的元信息包括:记录目标数据的文件号、目标数据的长度、目标数据在文件中的偏移量、用于指示目标数据所在目标缓存块的源地址、与源地址相对应的加速卡的目的地址以及用于表征目标缓存块与加速卡的数据同步状态的状态信息。
可选地,调整执行数据存取操作后的缓存块的状态信息包括:在将目标数据传输至加速卡之后,将状态信息调整为用于表征加速卡和目标缓存块均存储数据且数据一致的标识。
可选地,依据各缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息包括:在接收到目标数据修改指令的情况下,修改目标缓存块中存储的目标数据,并将状态信息调整为用于表征加速卡和目标缓存块均存储数据且数据不一致的标识。
可选地,在主机侧创建与加速卡内存容量匹配的缓存池之后还包括:对缓存池的缓存块进行内存锁定。
可选地,在主机侧创建与加速卡内存容量匹配的缓存池之后还包括:在接收到第一数据的加速处理指令的情况下,判断第一数据是否被缓存池缓存;在第一数据未被缓存池缓存的情况下,将第一数据从磁盘载入缓存池;将缓存池中的第一数据添加至DMA发送链表;依据存储第一数据的缓存块所对应的元信息,生成DMA描述符;向加速卡传输DMA描述符,以便于加速卡依据DMA描述符获取DMA发送链表中包含 的第一数据。
可选地,在接收到第一数据的加速处理指令的情况下,判断第一数据是否被缓存池缓存包括:在接收到第一数据的加速处理指令的情况下,依据第一数据的文件号和数据量,构建文件信息链表;将第一数据按照设定的容量单位划分为文件块;遍历文件信息链表的文件块,判断当前文件信息链表是否为空;在当前文件信息链表不为空的情况下,判断当前文件块是否被缓存池缓存;相应的,在第一数据未被缓存池缓存的情况下,将第一数据从磁盘载入缓存池;将缓存池中的第一数据添加至DMA发送链表包括:在当前文件块未被缓存池缓存的情况下,将当前文件块从磁盘载入缓存池;将缓存池中的当前文件块添加至DMA发送链表;直至当前文件信息链表为空的情况下,执行依据存储第一数据的缓存块所对应的元信息,生成DMA描述符的步骤。
可选地,还包括:在当前文件块被缓存池缓存的情况下,判断缓存当前文件块的当前缓存块所对应的状态信息是否为用于表征加速卡和当前缓存块均存储数据且数据一致的标识;在当前缓存块对应的状态信息为用于表征加速卡和当前缓存块均存储数据且数据不一致的标识的情况下,将缓存池中的当前文件块添加至DMA发送链表;在当前缓存块对应的状态信息为用于表征加速卡和当前缓存块均存储数据且数据一致的标识的情况下,跳过当前文件块。
可选地,在向加速卡传输DMA描述符,以便于加速卡依据DMA描述符获取DMA发送链表中包含的第一数据之后还包括:将缓存池中的第一数据对应的状态信息调整为用于表征加速卡和缓存池中第一均存储数据且数据一致的标识;对第一数据所在的缓存块设置写保护。
本申请实施例还提供了一种数据存取装置,包括创建单元、存储单元、记录单元、写保护设置单元和调整单元;创建单元,用于在主机侧创建与加速卡内存容量匹配的缓存池;其中,缓存池中包含按照设定的容量单位划分的缓存块;存储单元,用于在获取到目标数据的读取指令的情况下,从缓存池中调用与目标数据的容量匹配的目标缓存块,将目标数据存储至目标缓存块;记录单元,用于记录目标缓存块的元信息;其中,元信息包括目标数据所属的文件号、目标数据的长度、目标数据的地址信息,以及用于表征目标缓存块与加速卡的数据同步状态的状态信息;写保护设置单元,用于对目标缓存块设置写保护;调整单元,用于依据各缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息;其中,状态信息包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均存储数据且数据不一致的标识。
可选地,还包括链表创建单元;链表创建单元,用于创建空闲链表和缓存链表;空闲链表用于存放未使用的缓存块,缓存链表用于存放已使用的缓存块;相应的,存储单元用于在获取到目标数据的读取指令的情况下,从空闲链表和缓存链表中选取与目标数据的容量相匹配的目标缓存块,将目标数据存储至目标缓存块;其中,目标缓存块存放至缓存链表中。
可选地,存储单元包括存放子单元、第一读取子单元、第一存储子单元、第一建立子单元、释放子单元、第二读取子单元、第二存储子单元、第二建立子单元;存放子单元,用于在空闲链表不为空的情况下,将空闲链表中的一个空闲缓存块存放至缓存链表;第一读取子单元,用于在访问目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第一数据块;第一存储子单元,用于将第一数据块存储至空闲缓存块;第一建立子单元,用于建立第一数据块的物理地址和虚拟地址的映射关系;释放子单元,用于在空闲链表为空的情况下,从缓存链表中释放一个可用缓存块;第二读取子单元,用于在访问目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第二数据块;第二存储子单元,用于将第二数据块存储至可用缓存块;第二建立子单元,用于建立第二数据块的物理地址和虚拟地址的映射关系;直至目标数据划分的所有数据块均存储至目标缓存块,则结束操作。
可选地,从释放子单元依据缓存链表的替换算法,从缓存链表中选出一个可用缓存块;将可用缓存块中的原有数据回写到磁盘。
可选地,记录单元用于记录目标数据的文件号、目标数据的长度、目标数据在文件中的偏移量、用于指示目标数据所在目标缓存块的源地址、与源地址相对应的加速卡的目的地址以及用于表征目标缓存块与加速卡的数据同步状态的状态信息。
可选地,调整单元,用于在将目标数据传输至加速卡之后,将状态信息调整为用于表征加速卡和目标缓存块均存储数据且数据一致的标识。
可选地,调整单元,用于在接收到目标数据修改指令的情况下,修改目标缓存块中存储的目标数据;将目标缓存块的状态信息调整为用于表征加速卡和目标缓存块均存储数据且数据不一致的标识。
可选地,还包括锁定单元;锁定单元,用于对缓存池的缓存块进行内存锁定。
可选地,还包括数据缓存判断单元、载入单元、添加单元、生成单元和发送单元;数据缓存判断单元,用于在接收到第一数据的加速处理指令的情况下,判断第一数据是否被缓存池缓存;载入单元,用于在第一数据未被缓存池缓存的情况下,将第一数据从磁盘载入缓存池;添加单元,用于将缓存池中的第一数据添加至DMA发送链表;生成单元,用于依据存储第一数据的缓存块所对应的元信息,生成DMA描述符;发送单元,用于向加速卡传输DMA描述符,以便于加速卡依据DMA描述符获取DMA发送链表中包含的第一数据。
可选地,数据缓存判断单元包括构建子单元、划分子单元、第一判断子单元、第二判断子单元;构建子单元,用于在接收到第一数据的加速处理指令的情况下,依据第一数据的文件号和数据量,构建文件信息链表;划分子单元,用于将第一数据按照设定的容量单位划分为文件块;第一判断子单元,用于遍历文件信息链表的文件块,判断当前文件信息链表是否为空;第二判断子单元,用于在当前文件信息链表不为空的情况下,判断当前文件块是否被缓存池缓存;相应的,载入单元,用于在当前文件块未被缓存池缓存的情况下,将当前文件块从磁盘载入缓存池;将缓存池中的当前文件块添加至DMA发送链表;直至当前文件信息链表为空的情况下,触发生成单元执行依据存储第一数据的缓存块所对应的元信息,生成DMA描述符的步骤。
可选地,还包括标识判断单元和跳过单元;标识判断单元,用于在当前文件块被缓存池缓存的情况下,判断缓存当前文件块的当前缓存块所对应的状态信息是否为用于表征加速卡和当前缓存块均存储数据且数据一致的标识;添加单元,用于在当前缓存块对应的状态信息为用于表征加速卡和当前缓存块均存储数据且数据不一致的标识的情况下,将缓存池中的当前文件块添加至DMA发送链表;跳过单元,用于在当前缓存块对应的状态信息为用于表征加速卡和当前缓存块均存储数据且数据一致的标识的情况下,跳过当前文件块。
可选地,调整单元还用于在向加速卡传输DMA描述符,以便于加速卡依据DMA描述符获取DMA发送链表中包含的第一数据之后,将缓存池中的第一数据对应的状态信息调整为用于表征加速卡和缓存池中第一均存储数据且数据一致的标识;写保护设置单元还用于对第一数据所在的缓存块设置写保护。
本申请实施例还提供了一种电子设备,包括:存储器,用于存储计算机程序;处理器,用于执行计算机程序以实现如上述数据存取方法的步骤。
本申请实施例还提供了一种非易失性可读存储介质,非易失性可读存储介质上存储有计算机程序,计算机程序被处理器执行时实现如上述数据存取方法的步骤。
由上述技术方案可以看出,在主机侧创建与加速卡内存容量匹配的缓存池;其中,缓存池中包含按照设定的容量单位划分的缓存块;缓存块可以实现对数据的缓存,缓存块与加速卡相对应,缓存块的数据可以传输至加速卡。缓存池的容量和加速卡内存容量相匹配,可以实现对大量数据的缓存,基于单次数据的传输需求设定容量单位,可以有效的解决单次传输数据量过小造成传输带宽浪费的问题。在获取到目标数据的读取指令的情况下,可以从缓存池中调用与目标数据的容量匹配的目标缓存块,将目标数据存储至目标缓存块。缓存池的数据可以传输至加速卡,主机侧可以记录目标缓存块的元信息,并对目标缓存块设置写保护;其中,元信息可以包括目标数据所属的文件号、目标数据的长度、目标数据的地址信息,以及用 于表征目标缓存块与加速卡的数据同步状态的状态信息。依据各缓存块中数据所执行的操作,调整各缓存块的状态信息;状态信息包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均均存储数据且数据不一致的标识。在该技术方案中,通过在主机侧创建与加速卡内存容量匹配的缓存池,并且将缓存池按照设定的容量单位划分成多个缓存块,缓存块为连续的大块内存,所需的传输描述符少,可一次性连续传输大量数据,提升了带宽利用率,提高了数据传输效率。从磁盘读取的数据可以直接放入缓存池中,缓存池的数据可以直接传输至加速卡中,对于主机侧而言,目标数据直接缓存到预分配的缓存池中,向加速卡传输时无需额外的内存拷贝操作,有效的降低了数据的传输延迟。对于加速卡已缓存且内容一致的数据,无需重复传输,节省了传输时间并提高了执行效率。并且通过对写入数据的目标缓存块设置写保护,可以在目标缓存块中的数据发生变化时,实现对状态信息的动态调整,使得主机侧依据状态信息可以清楚的获知缓存池中数据和加速卡中数据是否同步,从而避免相同数据的重复传输。
为了更清楚地说明本申请实施例,下面将对实施例中所需要使用的附图做简单的介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种异构计算平台的结构示意图;
图2为现有技术提供的一种基于连续内存的异构计算平台的结构示意图;
图3为本申请实施例提供的一种数据存取方法的流程图;
图4为本申请实施例提供的一种文件***缓存架构图;
图5为本申请实施例提供的一种元信息的示意图;
图6为本申请实施例提供的一种主机侧缓冲池缓存数据的示意图;
图7为本申请实施例提供的一种从空闲链表和缓存链表中选取目标缓存块以存储目标数据的方法的流程图:
图8为本申请实施例提供的一种空闲缓存块存储数据的示意图;
图9为本申请实施例提供的一种可用缓存块存储数据的示意图;
图10为本申请实施例提供的一种修改缓存块数据的示意图;
图11为本申请实施例提供的一种向加速卡传输数据的方法的流程示意图;
图12为本申请实施例提供的一种查询薪资总支出的示意图;
图13为本申请实施例提供的一种查询公司职位数量的示意图;
图14为本申请实施例提供的一种修改薪资表的示意图;
图15为本申请实施例提供的一种查询博士以上学历的示意图
图16为本申请实施例提供的一种数据存取装置的结构示意图;
图17为本申请实施例提供的一种电子设备的结构图。
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下,所获得的所有其他实施例,都属于本申请保护范围。
本申请的说明书和权利要求书及上述附图中的术语″包括″和″具有″以及他们任何变形,意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元,而是可包括没有列出的步骤或单元。
为了使本技术领域的人员更好地理解本申请方案,下面结合附图和具体实施方式对本申请作进一步的详细说明。
接下来,详细介绍本申请实施例所提供的一种数据存取方法。图3为本申请实施例提供的一种数据存取方法的流程图,该方法包括:
S301:在主机侧创建与加速卡内存容量匹配的缓存池。
在本申请实施例中,为了降低主机侧内部数据拷贝花费的时间,可以在主机侧的内存中划分出与加速卡内存容量匹配的内存空间,将划分出的内存空间作为缓存池,缓存池实现与加速卡之间的数据传输。
在具体实现中,可以在主机侧创建与加速卡内存容量相同的缓存池。例如,加速卡内存为8GB,则可以在主机侧内存中划分出8GB内存作为缓存池。
在实际应用中,为了提升缓存池的空间利用率,便于数据的单次传输,可以设置容量单位。将缓存池按照设定的容量单位划分为多个缓存块。
在本申请实施例中,可以针对于不同的缓存块设置不同的容量单位,也可以将所有缓存块按照相同的容量单位划分。对于容量单位的取值不做限定,例如,容量单位可以均设置为8MB。
以所有缓存块按照相同的容量单位划分为例,假设加速卡内存为8GB,容量单位为8MB,8GB/8MB=1024,则可以在主机侧设置1024个缓存块。
图4为本申请实施例提供的一种文件***缓存架构图,图4中包括磁盘、主机侧和加速卡三部分。为了便于展示,图4中以4个缓存块为例,箭头表示了数据的传输方向。以一个数据块为例,主机侧与加速卡之间数据传输可以分为如下4种情况:(1)主机侧未缓存该数据块。(2)主机侧缓存了该数据块,但加速卡内没有缓存。(3)主机侧与加速卡均缓存了该数据块,但主机侧数据被修改,导致主机侧与加速卡缓存的数据不一致。(4)主机侧与加速卡均缓存,且一致。
针对于第一种情况,为了实现主机侧和加速卡数据的一致,可以从磁盘中读取数据到缓存池的缓存块中,将缓存的数据发送至加速卡内存中,并修改缓存块的状态信息为:主机与加速卡均缓存,且一致。
针对于第二种情况,为了实现主机侧和加速卡数据的一致,可以将缓存块的数据发送至加速卡内,并修改缓存块的状态信息为:主机与加速卡均缓存,且一致。
针对于第三种情况,为了实现主机侧和加速卡数据的一致,可以将缓存块的数据发送至加速卡内,并修改缓存块的状态信息为:主机与加速卡均缓存,且一致。
针对于第四种情况,主机侧和加速卡数据一致,因此无需对该缓存块进行传输操作,避免了重复数据的传输,减少了对带宽的占用。
S302:在获取到目标数据的读取指令的情况下,从缓存池中调用与目标数据的容量匹配的目标缓存块。
初始状态下,缓存池未存储数据,数据均位于磁盘中,在获取到目标数据的读取指令的情况下,需要从磁盘中读取目标数据,为了实现对目标数据的缓存,需要从缓存池中调用与目标数据的容量匹配的目标缓存块。
以每个缓存块容量为8MB为例,假设目标数据的数据量为15MB,此时需要两个缓存块才可以容纳目标数据。为了便于区分,为了将用于缓存目标数据的缓存块称作目标缓存块。
S303:将目标数据存储至目标缓存块,记录目标缓存块的元信息,并对目标缓存块设置写保护。
为了使得主机侧可以准确的获取缓存池中存储的数据与加速卡中存储的数据的同步状态,可以针对于每个目标缓存块设置元信息,元信息可以包括用于表征目标缓存块与加速卡的数据同步状态的状态信息,目标数据所属的文件号、目标数据的长度、目标数据的地址信息。
目标数据的地址信息可以包括目标数据在文件中的偏移量、目标数据在缓存池的源地址、与源地址对应的加速卡的目的地址等。
在实际应用中,一个完整的文件可能需要多个缓存块才能容纳,此时可以将文件按照每个缓存块的容 量,划分为多个目标数据,将每个目标数据存储至对应容量的缓存块中,为了便于区分各目标数据的前后顺序,可以在元信息中添加块编号。
此外,为了了解数据在缓存块中存储时间的长短,以支持缓存链表的替换算法(Least Recently Used,LRU),可以在元信息中添加时间戳,以缓存块写入目标数据的时间作为时间戳。
图5为本申请实施例提供的一种元信息的示意图,图5中以每个缓存块容量为8MB为例,每个缓存块有其对应的一个元信息,元信息可以包括块编号、同步状态、源地址、目的地址、文件号、长度、偏移和时间戳这8个元素。每个元素有其对应的存储空间,如可以采用4字节即4B记录块编号,采用8字节记录源地址等。在实际应用中,也可以根据需求,对元信息中包含的元素进行增加或删减,图5中关于元信息中包含的元素仅为举例说明,并不对元信息中包含的元素造成限定。
以每个缓存块的容量为8MB为例,假设加速卡内有8GB内存,则主机侧申请1024个缓存块,每个缓存块的物理内存地址连续。将所有的缓存块在内存中锁定,可以通过修改页面标志位,标记所有页面不可换出到磁盘。为了实现缓存池中缓存块与加速卡内存的对应,可以将加速卡内存以8MB为单位,划分为1024个内存块,主机侧缓存块中源地址写入数据区域的地址,目的地址写入加速卡内存块偏移。
S304:依据各缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息。
考虑到实际应用中,主机侧的缓存池与加速卡之间数据同步状态可以包含4种情况,第一种情况是缓存池和加速卡均未缓存数据;第二种情况是缓存池缓存了数据,加速卡未缓存数据;第三种情况是缓存池和加速卡均存储数据且数据一致;第四种情况是缓存池和加速卡均存储数据且数据不一致。
缓存池按照设定的容量单位可以划分成多个缓存块,每个缓存块为一个连续的大块内存,数据传输以缓存块为基本传输单元,针对于每个缓存块会设置其对应的状态信息。结合主机侧的缓存池与加速卡之间数据同步状态包含的4种情况,状态信息可以包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均存储数据且数据不一致的标识。
图6为本申请实施例提供的一种主机侧缓冲池缓存数据的示意图,图6中加速卡内存是以8MB为单位,划分为1024个加速卡内存块,主机侧相对应的划分有1024个缓存块,每个缓存块的数据区域8MB大小,物理内存地址连续。将缓存块放入空闲链表中。将所有的缓存块在内存中锁定,通过修改页面标志位,标记所有页面不可换出到磁盘。主机侧缓存块中源地址写入数据区域的地址,目的地址写入加速卡内存块偏移。
缓存池中包含有多个缓存块,缓存池中的一些缓存块存储有数据后,当有新的数据需要缓存时,需要从缓存池选取空闲缓存块,用于存储新的数据。为了方便对缓存块的调用,在本申请实施例中,在主机侧创建与加速卡内存容量匹配的缓存池之后,可以创建空闲链表和缓存链表;空闲链表用于存放未使用的缓存块,缓存链表用于存放已使用的缓存块。
相应的,在获取到目标数据的读取指令的情况下,可以从空闲链表和缓存链表中选取与目标数据的容量相匹配的目标缓存块;选取出的目标缓存块用于存储目标数据,因此可以将目标缓存块存放至缓存链表中。
缓存链表中的缓存块均存储有数据,空闲链表中缓存块属于未被使用的空闲缓存块,在实际应用中,会存在空闲链表中空闲缓存块容纳空间不足的问题,此时需要从缓存链表中释放部分缓存块,以保证数据的顺利缓存。
由上述技术方案可以看出,在主机侧创建与加速卡内存容量匹配的缓存池;其中,缓存池中包含按照设定的容量单位划分的缓存块;缓存块可以实现对数据的缓存,缓存块与加速卡相对应,缓存块的数据可以传输至加速卡。缓存池的容量和加速卡内存容量相匹配,可以实现对大量数据的缓存,基于单次数据的传输需求设定容量单位,可以有效的解决单次传输数据量过小造成传输带宽浪费的问题。在获取到目标数 据的读取指令的情况下,可以从缓存池中调用与目标数据的容量匹配的目标缓存块,将目标数据存储至目标缓存块。缓存池的数据可以传输至加速卡,主机侧可以记录目标缓存块的元信息,并对目标缓存块设置写保护;其中,元信息可以包括目标数据所属的文件号、目标数据的长度、目标数据的地址信息,以及用于表征目标缓存块与加速卡的数据同步状态的状态信息。依据各缓存块中数据所执行的操作,调整各缓存块的状态信息;状态信息包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均均存储数据且数据不一致的标识。在该技术方案中,通过在主机侧创建与加速卡内存容量匹配的缓存池,并且将缓存池按照设定的容量单位划分成多个缓存块,缓存块为连续的大块内存,所需的传输描述符少,可一次性连续传输大量数据,提升了带宽利用率,提高了数据传输效率。从磁盘读取的数据可以直接放入缓存池中,缓存池的数据可以直接传输至加速卡中,对于主机侧而言,目标数据直接缓存到预分配的缓存池中,向加速卡传输时无需额外的内存拷贝操作,有效的降低了数据的传输延迟。对于加速卡已缓存且内容一致的数据,无需重复传输,节省了传输时间并提高了执行效率。并且通过对写入数据的目标缓存块设置写保护,可以在目标缓存块中的数据发生变化时,实现对状态信息的动态调整,使得主机侧依据状态信息可以清楚的获知缓存池中数据和加速卡中数据是否同步,从而避免相同数据的重复传输。
传统方式中,操作***会将物理内存划分为固定大小的页面(通常为4KB),按页面大小进行管理。每个页面都有一个标志位,表示该内存是否可以暂存到磁盘中。对于可以暂存到磁盘的内存页面,在操作***内存不足时,会将页面中的数据写入磁盘中,从而腾出空闲页面给其它进程使用,该操作称为页面换出。在异构计算场景中,为了保障将数据从主机侧传输到加速卡过程中,页面不会被意外的换出到磁盘,需要修改相应页面的标志位为不可换出,该操作称为页面锁定。
为了避免缓存池被其它应用占用,或者缓存池中的数据被无故释放回磁盘,在本申请实施例中,可以在主机侧创建与加速卡内存容量匹配的缓存池之后,对缓存池的缓存块进行内存锁定,防止其它进程占用或内存页面交换到磁盘中。
图7为本申请实施例提供的一种从空闲链表和缓存链表中选取目标缓存块以存储目标数据的方法的流程图,该方法包括:
S701:判断空闲链表是否为空。
在本申请实施例中,空闲链表中包含的是未被使用的空闲缓存块。在需要缓存数据时,优先从空闲链表中选取用于缓存数据的空闲缓存块。
在执行目标数据的缓存时,需要判断空闲链表是否为空。
在空闲链表不为空的情况下,说明可以从空闲链表中选取空闲缓存块存储数据,此时可以执行S702;在空闲链表为空的情况下,需要从缓存链表中释放可用缓存块以用于存储数据,即执行S705。
S702:将空闲链表中的一个空闲缓存块存放至缓存链表。
选取出的空闲缓存块需要存储目标数据,为了便于缓存块的管理,可以将选取出的空间缓存块存放至缓存链表,以便于将目标数据存储至缓存链表的空闲缓存块中。
S703:在访问目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第一数据块,将第一数据块存储至空闲缓存块。
文件***中每个文件都有唯一的文件号即索引号。操作***根据索引号,可以找到文件在磁盘中的数据块。在CPU访问磁盘文件数据时,如果数据不在内存中,操作***会发生缺页异常。在缺页异常中,CPU硬件会标记导致缺页异常的原因为:没有对应的物理地址。传统方式中操作***会调用文件***的通用缓存申请接口,以4KB为单位申请内存作为文件缓存块,存放磁盘数据,之后建立缓存块物理地址与文件虚拟地址的映射关系。当CPU再次访问文件数据时,便不会发生没有物理地址的缺页异常。
在本申请实施例中,在获取目标数据时,会按照4KB的大小读取数据,在当前读取的数据发生缺页异常的情况,可以按照设定的容量单位读取当前数据所对应的数据块,可以将该数据块称作第一数据块。
第一数据块可以是目标数据中的部分或全部数据。例如,目标数据为7MB,当前读取的数据属于0~7MB之间的数据,此时可以将0~7MB的目标数据作为第一数据块。又例如,目标数据为15MB,当前读取的数据属于0~8MB(不包括第8MB)之间的数据,此时可以将目标数据中0~8MB的数据作为第一数据块。又或者当前读取的数据属于8~15MB(包括第8MB)之间的数据,此时可以将目标数据中8~15MB的数据作为第一数据块。
在访问目标数据发生缺页异常的情况下,主机侧会从磁盘中读取第一数据块,将第一数据块存储至空闲缓存块。
S704:建立第一数据块的物理地址和虚拟地址的映射关系。
在将第一数据块存储至空闲缓存块后,可以建立物理地址和虚拟地址的映射关系。
在空闲缓存块存储第一数据块后,可以记录第一数据块的文件号、第一数据块的长度、第一数据块在文件中的偏移量、用于指示第一数据块所在空闲缓存块的源地址、与源地址相对应的加速卡的目的地址以及用于表征空闲缓存块与加速卡的数据同步状态的状态信息。
S705:从缓存链表中释放一个可用缓存块,在访问目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第二数据块,将第二数据块存储至可用缓存块。
在空闲链表为空情况下,说明需要从缓存链表中释放部分缓存块,以保证目标数据的顺利缓存。
在本申请实施例中,从缓存链表中释放一个可用缓存块可以是从缓存链表中选取数据存储时间最久的一个缓存块,将该缓存块的数据回写到磁盘,此时该缓存块为空,为了便于区分,可以将该缓存块称作可用缓存块。
在具体实现中,可以依据缓存链表的替换算法(Least Recently Used,LRU)从缓存链表中选出一个可用缓存块;将可用缓存块中的原有数据回写到磁盘。
举例说明,假设目标数据的容量为15MB,每个缓存块的容量为8MB,空闲链表中包含有一个空闲缓存块,缓存链表中所有缓存块均存储有数据,此时为了存储目标数据,可以将空闲链表中的空闲缓存块存放至缓存链表中,该空闲缓存块可以存储8MB数据,对于剩余的7MB数据,则需要从缓存链表中释放一个可用缓存块,从而利用释放得到的一个可用缓存块存储剩余的7MB数据,从而实现目标数据的顺利存储。
S706:建立第二数据块的物理地址和虚拟地址的映射关系。
在将第二数据块存储至可用缓存块后,可以建立第二数据块的物理地址和虚拟地址的映射关系。
在可用缓存块存储第二数据块后,可以记录第二数据块的文件号、第二数据块的长度、第二数据块在文件中的偏移量、用于指示第二数据块所在可用缓存块的源地址、与源地址相对应的加速卡的目的地址以及用于表征可用缓存块与加速卡的数据同步状态的状态信息。
S707:判断目标数据划分的所有数据块是否均存储至目标缓存块。
在目标数据中仍有部分数据块未存储至目标缓存块的情况下,则返回S701,直至目标数据划分的所有数据块均存储至目标缓存块的情况下,则结束操作。
以每个缓存块容量为8MB为例,假设一个文件大小为15MB,文件没有被缓存,缓存池内空闲链表剩余一个空闲缓存块,文件会按照8MB分割为2个数据块。图8为本申请实施例提供的一种空闲缓存块存储数据的示意图,第一个数据块读取过程如图8所示,包括:①从空闲链表中取出一个空闲缓存块,将该空闲缓存块放入缓存链表中;图8中带箭头的虚线表示将该空闲缓存块放入缓存链表。②从磁盘中读取8MB数据存储到该空闲缓存块内。③设置虚拟地址到物理地址映射关系④设置该空闲缓存块中长度为8MB,文件号为对应的索引号,文件偏移为0。⑤标记该空闲缓存块状态为1,表示加速卡内存中尚未缓存该空闲缓存块中存储的数据。⑥将8MB数据区域页表属性设置为写保护。⑦更新时间戳。
图9为本申请实施例提供的一种可用缓存块存储数据的示意图,对于第二个数据块读取过程如图9所示,包括:①根据LRU算法,从缓存链表中选择出一个被替换的缓存块。②将该缓存块的数据回写到磁盘中,此时该缓存块不存在数据,可以将该缓存块称作可用缓存块。③从磁盘中读取7MB数据到该被替换的 缓存块中。④设置虚拟地址到物理地址映射关系。⑤设置缓存块中长度为7MB,文件号为对应的索引号,文件偏移为8MB。⑥标记缓存块状态为1,表示加速卡内存中尚未缓存该缓存块中存储的数据。⑦将8MB数据区域页表属性设置为写保护。⑧更新时间戳。
时间戳可以是缓存块写入数据的时间。
需要说明的是,在本申请实施例中,对于每个缓存块对应的元信息可以单独挂载,通过设置指针可以指向对应的缓存块。也可以将元信息与缓存块放置在一块,相应的,可以基于每个元信息占用的存储空间以及加速卡内存容量构建缓存池。
在本申请实施例中,在将目标数据存储至目标缓存块,记录目标缓存块的元信息,并对目标缓存块设置写保护之后,如果涉及到将目标数据向加速卡传输的操作,此时加速卡中的数据和缓存块中的数据变为一致,为了便于操作人员了解加速卡和缓存块的数据同步状态,此时需要对缓存块对应的同步状态进行调整。因此在将目标数据传输至加速卡之后,将状态信息调整为用于表征加速卡和目标缓存块均存储数据且数据一致的标识。例如,状态信息可以采用数字″0″,表示加速卡和目标缓存块数据一致。
通过对缓存块设置写保护,可以检测缓存块中数据***作的行为,从而可以及时更新同步状态。
在实际应用中,会涉及到缓存块中数据进行修改的情况。在内存中的页面数据回写到磁盘后,页面的属性会设置为写保护状态。当CPU对页面数据进行修改时,操作***会发生缺页异常,硬件会在缺页异常中标记导致缺页异常的原因为:对写保护区域执行了写入操作。
传统方式中,操作***在写保护的缺页异常的处理函数内,会设置页面的标志位为脏页,表示内存中的数据与磁盘中的数据不一致。当操作***后台线程将标记为脏页的页面写入磁盘后,会将取消页面的脏页标记,并重新设置页面属性为写保护。
在异构加速场景中,主机侧内存修改后,主机侧缓存块与磁盘、加速卡内存都不一致。操作***后台线程将脏页写入磁盘后,主机侧缓存块与磁盘数据一致,但仍与加速卡内存不一致。
因此在本申请实施例中,会在写保护缺页异常中添加对加速卡缓存块的管理,在缓存块对应的元信息中添加用于表征缓存块与加速卡内存的数据同步状态的状态信息,通过状态信息标记主机侧缓存块与加速卡内存块内容是否一致。
在实际应用中,在主机侧接收到目标数据修改指令的情况下,会修改目标缓存块中存储的目标数据,此时可以一并将状态信息调整为用于表征加速卡和目标缓存块均存储数据且数据不一致的标识。例如,状态信息可以采用数字″2″,表示加速卡和目标缓存块数据不一致。
图10为本申请实施例提供的一种修改缓存块数据的示意图,假设一个15MB的文件,已被缓存池缓存,第一个缓存块存储8MB数据,第二个缓存块存储7MB数据。由于数据页面设置为写保护,对任意15MB数据页面内,发生写操作均会触发缺页异常,***会在缺页异常中标记原因为:对写保护页面发生写操作。本申请实施例中,会在相应的缺页异常处理逻辑中,将缓存块对应的状态信息修改为2,表示加速卡和缓存块数据不一致。
在本申请实施例中,可以将磁盘的数据直接缓存在大块的连续的内存中,通过添加缓存块与加速卡内存数据同步状态的状态信息,可以及时了解加速卡内存与缓存块中数据是否一致,例如,在加速卡内已经存储了缓存块的数据的情况下,此时状态信息为0,表示加速卡和缓存块数据一致。当需要利用加速卡对该数据执行操作时,无需再从缓存块向加速卡传输该数据,减少了不必要的数据传输。
图11为本申请实施例提供的一种向加速卡传输数据的方法的流程示意图,该方法包括:
S1001:在接收到第一数据的加速处理指令的情况下,判断第一数据是否被缓存池缓存。
在本申请实施例中,为了便于和其它数据相区分,可以将当前所需向加速卡传输的数据称作第一数据。
在第一数据未被缓存池缓存的情况下,此时需要从磁盘中读取第一数据,即执行S1002。
在第一数据被缓存池缓存的情况下,需要进一步判断加速卡中是否已经存储了第一数据,即执行 S1003。
S1002:将第一数据从磁盘载入缓存池;将缓存池中的第一数据添加至DMA发送链表。
在第一数据未被缓存池缓存的情况下,需要先从磁盘中读取第一数据。
由缓存池向加速卡传输数据时,需要将数据转换为加速卡可识别的格式,在实际应用中可以构建DMA(Direct Memory Access,直接存储访问)发送链表,在需要将缓存池的数据传输至加速卡时,先将缓存池中的第一数据添加至DMA发送链表。
S1003:判断第一数据对应的状态信息是否为用于表征加速卡和缓存池中均存储数据且数据一致的标识。
在第一数据对应的状态信息为用于表征加速卡和缓存池中第一均存储数据且数据不一致的标识的情况下,执行S1004。
在第一数据对应的状态信息为用于表征加速卡和缓存池中均存储数据且数据一致的标识的情况下,说明加速卡中已经存储了第一数据,此时无需再向加速卡传输第一数据,直接结束操作即可。
S1004:将缓存池中的第一数据添加至DMA发送链表。
S1005:依据存储第一数据的缓存块所对应的元信息,生成DMA描述符。
DMA描述符用于指示缓存块中数据的源地址、目的地址和数据长度。DMA描述符属于加速卡可识别的数据格式。
S1006:向加速卡传输DMA描述符,以便于加速卡依据DMA描述符获取DMA发送链表中包含的第一数据。
主机侧向加速卡传输DMA描述符,加速卡可以基于DMA描述符获取到第一数据。
在实际应用中,在向加速卡传输DMA描述符之后,加速卡可以依据DMA描述符获取DMA发送链表中包含的第一数据,此时加速卡和缓存池数据一致。因此在向加速卡传输DMA描述符之后,可以将缓存池中的第一数据对应的状态信息调整为用于表征加速卡和缓存池中均存储数据且数据一致的标识;对第一数据所在的缓存块设置写保护。
在本申请实施例中,磁盘的数据直接缓存在大块的连续的内存中,通过添加缓存块与加速卡内存同步标记即状态信息,减少不必要的数据传输。
考虑到实际应用中,第一数据的数据量往往大于单个缓存块的容量,因此可以在接收到第一数据的加速处理指令的情况下,依据第一数据的文件号和数据量,构建文件信息链表;将第一数据按照设定的容量单位划分为文件块;遍历文件信息链表的文件块,判断当前文件信息链表是否为空;在当前文件信息链表不为空的情况下,判断当前文件块是否被缓存池缓存。
相应的,在当前文件块未被缓存池缓存的情况下,将当前文件块从磁盘载入缓存池;将缓存池中的当前文件块添加至DMA发送链表;直至当前文件信息链表为空的情况下,执行依据存储第一数据的缓存块所对应的元信息,生成DMA描述符的步骤。
在当前文件块被缓存池缓存的情况下,需要判断缓存当前文件块的当前缓存块所对应的状态信息是否为用于表征加速卡和当前缓存块均存储数据且数据一致的标识。
在当前缓存块对应的状态信息为用于表征加速卡和当前缓存块均存储数据且数据不一致的标识的情况下,说明需要向加速卡传输当前文件块,此时可以将缓存池中的当前文件块添加至DMA发送链表。
在当前缓存块对应的状态信息为用于表征加速卡和当前缓存块均存储数据且数据一致的标识的情况下,说明加速卡中已经存储了当前文件块,此时可以跳过当前文件块。直至当前文件信息链表为空,说明所需向加速卡传输的数据已全部添加至DMA发送链表,此时可以依据存储第一数据的缓存块所对应的元信息,生成DMA描述符;向加速卡传输DMA描述符,以便于加速卡依据DMA描述符获取DMA发送链表中包含的第一数据。
通过将第一数据按照单个缓存块的容量划分为多个文件块,可以实现第一数据的快速传输。并且通过 设置文件信息链表,保证了所有文件块的传输,避免了遗漏部分数据的情况发生。
举例说明,以数据库访问为例,设数据库中有三个表格:1.薪资表,文件大小32MB,包含字段:员工ID,月度绩效,薪资,奖金;2.职位信息表,文件大小1MB,包含字段:职位ID,职位名称,工作内容;3.员工信息表,文件大小16MB,包含字段:员工ID,姓名,职位ID,电话,学历。
设用户执行如下操作:1.查询薪资总支出,需要访问薪资表。数据块缓存操作,如图12所示。①从空闲链表中分配4个8MB缓存块,载入磁盘数据;②将缓存块加入的缓存链表中;③根据缓存块中的目的地址,源地址,长度信息构建DMA描述符,将缓存块缓存的数据发送到加速卡内存中,标记同步状态为0,在发送完成后重新设置页面为写保护状态。
2.查询公司职位数量,需要访问职位信息表。由于职位信息表较少,单独查询该表,假设CPU选择不使用异构计算方式,数据块缓存操作,如图13所示。①从空闲链表中分配一个8MB缓存块,从磁盘中读取1MB数据到缓存块内;②将缓存块放入到缓存链表中;③由于该数据表只有1MB,数据较小,假设CPU不选择进行异构计算,设置缓存块的同步标记为1。
3.修改部分员工薪资,需要修改薪资表,CPU修改相关数据块,并修改缓存块标记为与加速卡内存不一致,数据块缓存操作,如图14所示。由于只是修改部分数据,当CPU修改相应页面是会触发缺页异常,在缺页异常中:①修改相应的缓存块标记为2,表示主机侧缓存与加速卡内缓存块数据不一致。
4.查询博士以上学历,从事研发职位的员工平均薪资,需要同时访问员工信息表,职位信息表,薪资表。CPU选择异构计算方式,对于加速卡中已经缓存且与主机侧缓存一致的数据块,不再进行重复发送数据块的操作,如图15所示。①空闲链表中分配2个8MB缓存块,从磁盘中读取数据到缓存块中;②将缓存块加入缓存链表;③构建DMA描述符,将加速卡内未缓存的缓存块,与加速卡数据不一致的缓存块发送至加速卡内,跳过加速卡已经缓存且与主机侧一致的缓存块,修改缓存块同步状态为0,并设置页面为写保护状态。
需要说明的是,本申请实施例提供的数据存取方案同样适用于与存储体系中存在性能差异的场景,例如:一个存储体系中包含:NVME硬盘、机械磁盘、网络存储。容量上依次增加,但性能依次降低,同样可以对数据块添加标记的方式降低重复传输。
图16为本申请实施例提供的一种数据存取装置的结构示意图,包括创建单元151、存储单元152、记录单元153、写保护设置单元154和调整单元155;
创建单元151,用于在主机侧创建与加速卡内存容量匹配的缓存池;其中,缓存池中包含按照设定的容量单位划分的缓存块;存储单元152,用于在获取到目标数据的读取指令的情况下,从缓存池中调用与目标数据的容量匹配的目标缓存块,将目标数据存储至目标缓存块;记录单元153,用于记录目标缓存块的元信息;其中,元信息包括目标数据所属的文件号、目标数据的长度、目标数据的地址信息,以及用于表征目标缓存块与加速卡的数据同步状态的状态信息;写保护设置单元154,用于对目标缓存块设置写保护;调整单元155,用于依据各缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息;其中,状态信息包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均存储数据且数据不一致的标识。
可选地,还包括链表创建单元;链表创建单元,用于创建空闲链表和缓存链表;空闲链表用于存放未使用的缓存块,缓存链表用于存放已使用的缓存块;相应的,存储单元用于在获取到目标数据的读取指令的情况下,从空闲链表和缓存链表中选取与目标数据的容量相匹配的目标缓存块,将目标数据存储至目标缓存块;其中,目标缓存块存放至缓存链表中。
可选地,存储单元包括存放子单元、第一读取子单元、第一存储子单元、第一建立子单元、释放子单元、第二读取子单元、第二存储子单元、第二建立子单元;存放子单元,用于在空闲链表不为空的情况下,将空闲链表中的一个空闲缓存块存放至缓存链表;第一读取子单元,用于在访问目标数据发生缺页异 常的情况下,从磁盘中读取与设定的容量单位匹配的第一数据块;第一存储子单元,用于将第一数据块存储至空闲缓存块;第一建立子单元,用于建立第一数据块的物理地址和虚拟地址的映射关系;释放子单元,用于在空闲链表为空的情况下,从缓存链表中释放一个可用缓存块;第二读取子单元,用于在访问目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第二数据块;第二存储子单元,用于将第二数据块存储至可用缓存块;第二建立子单元,用于建立第二数据块的物理地址和虚拟地址的映射关系;直至目标数据划分的所有数据块均存储至目标缓存块,则结束操作。
可选地,从释放子单元依据缓存链表的替换算法,从缓存链表中选出一个可用缓存块;将可用缓存块中的原有数据回写到磁盘。
可选地,记录单元用于记录目标数据的文件号、目标数据的长度、目标数据在文件中的偏移量、用于指示目标数据所在目标缓存块的源地址、与源地址相对应的加速卡的目的地址以及用于表征目标缓存块与加速卡的数据同步状态的状态信息。
可选地,调整单元,用于在将目标数据传输至加速卡之后,将状态信息调整为用于表征加速卡和目标缓存块均存储数据且数据一致的标识。
可选地,调整单元,用于在接收到目标数据修改指令的情况下,修改目标缓存块中存储的目标数据;将目标缓存块的状态信息调整为用于表征加速卡和目标缓存块均存储数据且数据不一致的标识。
可选地,还包括锁定单元;锁定单元,用于对缓存池的缓存块进行内存锁定。
可选地,还包括数据缓存判断单元、载入单元、添加单元、生成单元和发送单元;数据缓存判断单元,用于在接收到第一数据的加速处理指令的情况下,判断第一数据是否被缓存池缓存;载入单元,用于在第一数据未被缓存池缓存的情况下,将第一数据从磁盘载入缓存池;添加单元,用于将缓存池中的第一数据添加至DMA发送链表;生成单元,用于依据存储第一数据的缓存块所对应的元信息,生成DMA描述符;发送单元,用于向加速卡传输DMA描述符,以便于加速卡依据DMA描述符获取DMA发送链表中包含的第一数据。
可选地,数据缓存判断单元包括构建子单元、划分子单元、第一判断子单元、第二判断子单元;构建子单元,用于在接收到第一数据的加速处理指令的情况下,依据第一数据的文件号和数据量,构建文件信息链表;划分子单元,用于将第一数据按照设定的容量单位划分为文件块;第一判断子单元,用于遍历文件信息链表的文件块,判断当前文件信息链表是否为空;第二判断子单元,用于在当前文件信息链表不为空的情况下,判断当前文件块是否被缓存池缓存;相应的,载入单元,用于在当前文件块未被缓存池缓存的情况下,将当前文件块从磁盘载入缓存池;将缓存池中的当前文件块添加至DMA发送链表;直至当前文件信息链表为空的情况下,触发生成单元执行依据存储第一数据的缓存块所对应的元信息,生成DMA描述符的步骤。
可选地,还包括标识判断单元和跳过单元;标识判断单元,用于在当前文件块被缓存池缓存的情况下,判断缓存当前文件块的当前缓存块所对应的状态信息是否为用于表征加速卡和当前缓存块均存储数据且数据一致的标识;添加单元,用于在当前缓存块对应的状态信息为用于表征加速卡和当前缓存块均存储数据且数据不一致的标识的情况下,将缓存池中的当前文件块添加至DMA发送链表;跳过单元,用于在当前缓存块对应的状态信息为用于表征加速卡和当前缓存块均存储数据且数据一致的标识的情况下,跳过当前文件块。
可选地,调整单元还用于在向加速卡传输DMA描述符,以便于加速卡依据DMA描述符获取DMA发送链表中包含的第一数据之后,将缓存池中的第一数据对应的状态信息调整为用于表征加速卡和缓存池中第一均存储数据且数据一致的标识;写保护设置单元还用于对第一数据所在的缓存块设置写保护。
图16所对应实施例中特征的说明可以参见图3、图7和图11所对应实施例的相关说明,这里不再一一赘述。
由上述技术方案可以看出,在主机侧创建与加速卡内存容量匹配的缓存池;其中,缓存池中包含按照 设定的容量单位划分的缓存块;缓存块可以实现对数据的缓存,缓存块与加速卡相对应,缓存块的数据可以传输至加速卡。缓存池的容量和加速卡内存容量相匹配,可以实现对大量数据的缓存,基于单次数据的传输需求设定容量单位,可以有效的解决单次传输数据量过小造成传输带宽浪费的问题。在获取到目标数据的读取指令的情况下,可以从缓存池中调用与目标数据的容量匹配的目标缓存块,将目标数据存储至目标缓存块。缓存池的数据可以传输至加速卡,主机侧可以记录目标缓存块的元信息,并对目标缓存块设置写保护;其中,元信息可以包括目标数据所属的文件号、目标数据的长度、目标数据的地址信息,以及用于表征目标缓存块与加速卡的数据同步状态的状态信息。依据各缓存块中数据所执行的操作,调整各缓存块的状态信息;状态信息包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均均存储数据且数据不一致的标识。在该技术方案中,通过在主机侧创建与加速卡内存容量匹配的缓存池,并且将缓存池按照设定的容量单位划分成多个缓存块,缓存块为连续的大块内存,所需的传输描述符少,可一次性连续传输大量数据,提升了带宽利用率,提高了数据传输效率。从磁盘读取的数据可以直接放入缓存池中,缓存池的数据可以直接传输至加速卡中,对于主机侧而言,目标数据直接缓存到预分配的缓存池中,向加速卡传输时无需额外的内存拷贝操作,有效的降低了数据的传输延迟。对于加速卡已缓存且内容一致的数据,无需重复传输,节省了传输时间并提高了执行效率。并且通过对写入数据的目标缓存块设置写保护,可以在目标缓存块中的数据发生变化时,实现对状态信息的动态调整,使得主机侧依据状态信息可以清楚的获知缓存池中数据和加速卡中数据是否同步,从而避免相同数据的重复传输。
图17为本申请实施例提供的一种电子设备的结构图,如图17所示,电子设备包括:存储器20,用于存储计算机程序;处理器21,用于执行计算机程序时实现如上述实施例数据存取方法的步骤。
本实施例提供的电子设备可以包括但不限于智能手机、平板电脑、笔记本电脑或台式电脑等。
其中,处理器21可以包括一个或多个处理核心,比如4核心处理器、8核心处理器等。处理器21可以采用DSP(Digital Signal Processing,数字信号处理)、FPGA(Field-Programmable Gate Array,现场可编程门阵列)、PLA(Programmable Logic Array,可编程逻辑阵列)中的至少一种硬件形式来实现。处理器21也可以包括主处理器和协处理器,主处理器是用于对在唤醒状态下的数据进行处理的处理器,也称CPU(Central Processing Unit,中央处理器);协处理器是用于对在待机状态下的数据进行处理的低功耗处理器。在一些实施例中,处理器21可以在集成有GPU(Graphics Processing Unit,图像处理器),GPU用于负责显示屏所需要显示的内容的渲染和绘制。一些实施例中,处理器21还可以包括AI(Artificial Intelligence,人工智能)处理器,该AI处理器用于处理有关机器学习的计算操作。
存储器20可以包括一个或多个非易失性可读存储介质,该非易失性可读存储介质可以是非暂态的。存储器20还可包括高速随机存取存储器,以及非易失性存储器,比如一个或多个磁盘存储设备、闪存存储设备。本实施例中,存储器20至少用于存储以下计算机程序201,其中,该计算机程序被处理器21加载并执行之后,能够实现前述任一实施例公开的数据存取方法的相关步骤。另外,存储器20所存储的资源还可以包括操作***202和数据203等,存储方式可以是短暂存储或者永久存储。其中,操作***202可以包括Windows、Unix、Linux等。数据203可以包括但不限于元信息等。
在一些实施例中,电子设备还可包括有显示屏22、输入输出接口23、通信接口24、电源25以及通信总线26。
本领域技术人员可以理解,图17中示出的结构并不构成对电子设备的限定,可以包括比图示更多或更少的组件。
可以理解的是,如果上述实施例中的数据存取方法以软件功能单元的形式实现并作为独立的产品销售或使用时,可以存储在一个计算机可读取存储介质中。基于这样的理解,本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储介质中,执行本申请各个实施例方法的全部或部分步骤。而前述的存储介质包括:U 盘、移动硬盘、只读存储器(Read-Only Memory,ROM)、随机存取存储器(Random Access Memory,RAM)、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、磁碟或者光盘等各种可以存储程序代码的介质。
基于此,本申请实施例还提供了一种非易失性可读存储介质,非易失性可读存储介质上存储有计算机程序,计算机程序被处理器执行时实现如上述数据存取方法的步骤。
以上对本申请实施例所提供的一种数据存取方法、装置、设备和非易失性可读存储介质进行了详细介绍。说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言,由于其与实施例公开的方法相对应,所以描述的比较简单,相关之处参见方法部分说明即可。
专业人员还可以进一步意识到,结合本文中所公开的实施例描述的各示例的单元及算法步骤,能够以电子硬件、计算机软件或者二者的结合来实现,为了清楚地说明硬件和软件的可互换性,在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行,取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能,但是这种实现不应认为超出本申请的范围。
以上对本申请所提供的一种数据存取方法、装置、设备和非易失性可读存储介质进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的方法及其核心思想。应当指出,对于本技术领域的普通技术人员来说,在不脱离本申请原理的前提下,还可以对本申请进行若干改进和修饰,这些改进和修饰也落入本申请权利要求的保护范围内。
Claims (20)
- 一种数据存取方法,其特征在于,包括:在主机侧创建与加速卡内存容量匹配的缓存池;其中,所述缓存池中包含按照设定的容量单位划分的缓存块;在获取到目标数据的读取指令的情况下,从所述缓存池中调用与所述目标数据的容量匹配的目标缓存块,将所述目标数据存储至所述目标缓存块;记录所述目标缓存块的元信息,并对所述目标缓存块设置写保护;其中,所述元信息包括目标数据所属的文件号、目标数据的长度、目标数据的地址信息,以及用于表征所述目标缓存块与所述加速卡的数据同步状态的状态信息;依据各所述缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息;其中,所述状态信息包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均存储数据且数据不一致的标识。
- 根据权利要求1所述的数据存取方法,其特征在于,在主机侧创建与加速卡内存容量匹配的缓存池之后还包括:创建空闲链表和缓存链表;所述空闲链表用于存放未使用的缓存块,所述缓存链表用于存放已使用的缓存块;相应的,所述在获取到目标数据的读取指令的情况下,从所述缓存池中调用与所述目标数据的容量匹配的目标缓存块,将所述目标数据存储至所述目标缓存块包括:在获取到目标数据的读取指令的情况下,从所述空闲链表和所述缓存链表中选取与所述目标数据的容量相匹配的目标缓存块,将所述目标数据存储至所述目标缓存块;其中,所述目标缓存块存放至所述缓存链表中。
- 根据权利要求2所述的数据存取方法,其特征在于,所述从所述空闲链表和所述缓存链表中选取与所述目标数据的容量相匹配的目标缓存块,将所述目标数据存储至所述目标缓存块包括:在所述空闲链表不为空的情况下,将所述空闲链表中的一个空闲缓存块存放至所述缓存链表;在访问所述目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第一数据块,将所述第一数据块存储至所述空闲缓存块;建立所述第一数据块的物理地址和虚拟地址的映射关系;在所述空闲链表为空的情况下,从所述缓存链表中释放一个可用缓存块,在访问所述目标数据发生缺页异常的情况下,从磁盘中读取与设定的容量单位匹配的第二数据块,将所述第二数据块存储至所述可用缓存块;建立所述第二数据块的物理地址和虚拟地址的映射关系;直至所述目标数据划分的所有数据块均存储至目标缓存块,则结束操作。
- 根据权利要求3所述的数据存取方法,其特征在于,所述从所述缓存链表中释放一个可用缓存块包括:依据缓存链表的替换算法,从所述缓存链表中选出一个可用缓存块;将所述可用缓存块中的原有数据回写到磁盘。
- 根据权利要求1所述的数据存取方法,其特征在于,所述记录所述目标缓存块的元信息包括:记录目标数据的文件号、所述目标数据的长度、目标数据在文件中的偏移量、用于指示所述目标数据所在目标缓存块的源地址、与所述源地址相对应的加速卡的目的地址以及用于表征所述目标缓存块与所述加速卡的数据同步状态的状态信息。
- 根据权利要求1所述的数据存取方法,其特征在于,所述调整执行数据存取操作后的缓存块的状态信息包括:在将所述目标数据传输至所述加速卡之后,将所述状态信息调整为用于表征所述加速卡和所述目标缓 存块均存储数据且数据一致的标识。
- 根据权利要求1所述的数据存取方法,其特征在于,所述依据各所述缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息包括:在接收到目标数据修改指令的情况下,修改所述目标缓存块中存储的目标数据,并将所述状态信息调整为用于表征所述加速卡和所述目标缓存块均存储数据且数据不一致的标识。
- 根据权利要求1所述的数据存取方法,其特征在于,在主机侧创建与加速卡内存容量匹配的缓存池之后还包括:对所述缓存池的缓存块进行内存锁定。
- 根据权利要求1所述的数据存取方法,其特征在于,在主机侧创建与加速卡内存容量匹配的缓存池之后还包括:在接收到第一数据的加速处理指令的情况下,判断所述第一数据是否被所述缓存池缓存;在所述第一数据未被所述缓存池缓存的情况下,将所述第一数据从磁盘载入所述缓存池;将所述缓存池中的第一数据添加至DMA发送链表;依据存储所述第一数据的缓存块所对应的元信息,生成DMA描述符;向所述加速卡传输所述DMA描述符,以便于所述加速卡依据所述DMA描述符获取所述DMA发送链表中包含的第一数据。
- 根据权利要求9所述的数据存取方法,其特征在于,所述在接收到第一数据的加速处理指令的情况下,判断所述第一数据是否被所述缓存池缓存包括:在接收到第一数据的加速处理指令的情况下,依据所述第一数据的文件号和数据量,构建文件信息链表;将所述第一数据按照设定的容量单位划分为文件块;遍历所述文件信息链表的文件块,判断当前文件信息链表是否为空;在所述当前文件信息链表不为空的情况下,判断当前文件块是否被所述缓存池缓存;相应的,所述在所述第一数据未被所述缓存池缓存的情况下,将所述第一数据从磁盘载入所述缓存池;将所述缓存池中的第一数据添加至DMA发送链表包括:在所述当前文件块未被所述缓存池缓存的情况下,将所述当前文件块从磁盘载入所述缓存池;将所述缓存池中的当前文件块添加至DMA发送链表;直至所述当前文件信息链表为空的情况下,执行所述依据存储所述第一数据的缓存块所对应的元信息,生成DMA描述符的步骤。
- 根据权利要求10所述的数据存取方法,其特征在于,还包括:在当前文件块被所述缓存池缓存的情况下,判断缓存所述当前文件块的当前缓存块所对应的状态信息是否为用于表征所述加速卡和所述当前缓存块均存储数据且数据一致的标识;在所述当前缓存块对应的状态信息为用于表征所述加速卡和所述当前缓存块均存储数据且数据不一致的标识的情况下,将所述缓存池中的当前文件块添加至DMA发送链表;在所述当前缓存块对应的状态信息为用于表征所述加速卡和所述当前缓存块均存储数据且数据一致的标识的情况下,跳过所述当前文件块。
- 根据权利要求9所述的数据存取方法,其特征在于,在所述向所述加速卡传输所述DMA描述符,以便于所述加速卡依据所述DMA描述符获取所述DMA发送链表中包含的第一数据之后还包括:将所述缓存池中的第一数据对应的状态信息调整为用于表征所述加速卡和所述缓存池中均存储数据且数据一致的标识;对所述第一数据所在的缓存块设置写保护。
- 根据权利要求1所述的数据存取方法,其特征在于,所述目标数据的地址信息至少包括所述目标 数据在文件中的偏移量、所述目标数据在所述缓存池的源地址、与所述源地址对应的加速卡的目的地址。
- 根据权利要求1所述的数据存取方法,其特征在于,在所述主机侧未缓存预设数据块的情况下,从所述磁盘中读取所述预设数据到所述缓存池的缓存块中,将所述缓存块的数据发送至所述加速卡内,并修改所述缓存块的状态信息为:所述主机侧与所述加速卡均缓存,且一致。
- 根据权利要求1所述的数据存取方法,其特征在于,在所述主机侧缓存了预设数据块,但所述加速卡内没有缓存所述预设数据块的情况下,将缓存块中存储的所述预设数据块发送至所述加速卡内,并修改所述缓存块的状态信息为:所述主机侧与所述加速卡均缓存,且一致。
- 根据权利要求1所述的数据存取方法,其特征在于,在所述主机侧与所述加速卡均缓存了预设数据块,但所述主机侧的所述预设数据块的数据被修改的情况下,将缓存块中存储的所述预设数据块数据发送至所述加速卡内,并修改所述缓存块的状态信息为:所述主机侧与所述加速卡均缓存,且一致。
- 根据权利要求1所述的数据存取方法,其特征在于,在所述主机侧与所述加速卡均缓存数据,且缓存的数据一致的情况下,无需对所述缓存池中的缓存块进行传输操作。
- 一种数据存取装置,其特征在于,包括创建单元、存储单元、记录单元、写保护设置单元和调整单元;所述创建单元,用于在主机侧创建与加速卡内存容量匹配的缓存池;其中,所述缓存池中包含按照设定的容量单位划分的缓存块;所述存储单元,用于在获取到目标数据的读取指令的情况下,从所述缓存池中调用与所述目标数据的容量匹配的目标缓存块,将所述目标数据存储至所述目标缓存块;所述记录单元,用于记录所述目标缓存块的元信息;其中,所述元信息包括目标数据所属的文件号、目标数据的长度、目标数据的地址信息,以及用于表征所述目标缓存块与所述加速卡的数据同步状态的状态信息;所述写保护设置单元,用于对所述目标缓存块设置写保护;所述调整单元,用于依据各所述缓存块对应的状态信息,执行数据存取操作,并调整执行数据存取操作后的缓存块的状态信息;其中,所述状态信息包括用于表征缓存块未缓存数据的标识、用于表征仅缓存块缓存数据的标识、用于表征缓存块与加速卡均存储数据且数据一致的标识以及用于表征缓存块与加速卡均存储数据且数据不一致的标识。
- 一种电子设备,其特征在于,包括:存储器,用于存储计算机程序;处理器,用于执行所述计算机程序以实现如权利要求1至17任意一项所述数据存取方法的步骤。
- 一种非易失性可读存储介质,其特征在于,所述非易失性可读存储介质上存储有计算机程序,所述计算机程序被处理器执行时实现如权利要求1至17任意一项所述数据存取方法的步骤。
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