WO2024040698A1 - Semiconductor structure manufacturing method and semiconductor structure - Google Patents

Semiconductor structure manufacturing method and semiconductor structure Download PDF

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WO2024040698A1
WO2024040698A1 PCT/CN2022/124144 CN2022124144W WO2024040698A1 WO 2024040698 A1 WO2024040698 A1 WO 2024040698A1 CN 2022124144 W CN2022124144 W CN 2022124144W WO 2024040698 A1 WO2024040698 A1 WO 2024040698A1
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layer
gate
conductive
substrate
forming
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PCT/CN2022/124144
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Chinese (zh)
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黄文华
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure and its structure.
  • Memory is a common semiconductor structure, and the memory includes an array area and a peripheral circuit active area.
  • the array area has a memory array
  • the peripheral circuit active area has a circuit structure that controls the memory array
  • the array area and the peripheral circuit active area Isolation structures are provided in the substrates. Since different transistors in the active area of the peripheral circuit need to be configured with different functions, different structures need to be formed, such as the PMOS area, and usually a channel layer needs to be formed on the top of the substrate in the PMOS area to improve the efficiency of forming PMOS transistors in the PMOS area. Reading speed.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including a PMOS region; forming a channel layer, the channel layer being located on the PMOS The surface of the substrate in the area; forming a gate structure and a protective layer, the gate structure is located on the surface of the channel layer, the protective layer covers the surface of the gate structure and the channel layer Part of the surface; after forming the gate structure and the protective layer, a hydrogen ion casting process is used to passivate the surface of the channel layer.
  • the passivation treatment includes: passing a hydrogen-containing passivation gas into the channel layer, where the hydrogen-containing passivation gas includes: hydrogen or a mixed gas of hydrogen and an inert gas.
  • the passivation treatment temperature is 310 ⁇ 530°C.
  • the gas flow rate of the hydrogen-containing passivation gas introduced into the passivation process is 3.5L/min to 6.5L/min.
  • the duration of the passivation treatment is 21 minutes to 39 minutes.
  • the method before performing the passivation treatment, further includes: forming an insulating layer, the insulating layer is located on the surface of the substrate, and the insulating layer covers the sidewall of the protective layer; forming a first conductive layer Pillar, the first conductive pillar penetrates the insulating layer to connect with the substrate of the PMOS region or the first conductive pillar penetrates the insulating layer and the protective layer to connect with the gate structure .
  • the method of forming the first conductive pillar includes etching the insulating layer to form a groove penetrating the insulating layer to expose the PMOS region of the substrate.
  • the surface or the groove penetrates the insulating layer and the protective layer to expose the top surface of the gate; a conductive contact layer is formed, and the conductive contact layer is located on the bottom surface of the groove; a diffusion barrier layer is formed, so The diffusion barrier layer is located on the inner wall of the groove and on the surface of the conductive contact layer; a conductive plug layer is formed, and the conductive plug layer fills the groove.
  • the method of forming the conductive contact layer includes: forming a contact material layer located on the substrate surface or the gate top surface exposed by the bottom surface of the groove; using A rapid thermal annealing process causes the substrate or the gate electrode to react with the contact material layer to form the conductive contact layer.
  • the passivation treatment before performing the passivation treatment, it further includes: forming a first conductive layer, the first conductive layer is located on the surface of the insulating layer, and the first conductive layer is in contact with the first conductive layer. The top surface of the column contacts the connection.
  • the passivation process further includes: performing the passivation process on sidewalls of the first conductive line layer and the first conductive pillar facing the insulating layer.
  • the step of forming the gate structure includes: forming an initial gate dielectric layer covering the surface of the channel layer; forming an initial gate electrode covering the surface of the channel layer; The surface of the initial gate dielectric layer; etching the initial gate electrode and the initial gate dielectric layer, leaving the initial gate electrode as a gate electrode, and the remaining initial gate dielectric layer as a gate dielectric layer, the gate electrode and the gate dielectric layer
  • the dielectric layer serves as the gate structure.
  • the steps of forming the gate structure and the protective layer include: forming the gate structure, which is located on the surface of the channel layer; forming the protective layer, The protective layer covers part of the surface of the channel layer and the sidewalls and top surface of the gate structure.
  • the steps of forming the gate structure and the protective layer include: forming an initial protective layer covering the surface of the channel layer; etching the initial protective layer to form trench, the trench exposes the surface of the channel layer; forming the gate structure, the gate structure is located in the trench; forming a cover layer, the cover layer and the remaining initial protective layer constitute the protective layer.
  • another aspect of the present disclosure further provides a semiconductor structure, including: a substrate including a PMOS region; and a channel layer located at all parts of the PMOS region.
  • the surface of the substrate, hydrogen bonds are formed on the surface of the channel layer; a gate structure, the gate structure is located on the surface of the channel layer; a protective layer, the protective layer covers the gate structure
  • the protective layer also covers at least part of the surface of the channel layer.
  • an insulating layer the insulating layer is located on the surface of the substrate, and the insulating layer covers the sidewall of the protective layer; a first conductive pillar, the first conductive pillar penetrates the insulating layer Connected to the substrate of the PMOS region or the first conductive pillar penetrates the insulating layer and the protective layer to connect to the gate structure.
  • the first conductive pillar includes: a conductive contact layer located within the substrate of the PMOS region or on the top surface of the gate structure; a diffusion barrier layer, the diffusion The bottom surface of the barrier layer is in contact with the top surface of the conductive contact layer.
  • the diffusion barrier layer also includes side surfaces surrounding the bottom surface of the diffusion barrier layer. The bottom surface and side surfaces of the diffusion barrier layer form an accommodation space; a conductive plug layer , the conductive plug layer is located on the surface of the diffusion barrier layer and fills the accommodation space.
  • At least a portion of the conductive plug layer is located within the substrate of the PMOS region.
  • hydrogen bonds are formed on a surface of the first conductive pillar facing the insulating layer.
  • the thickness of the channel layer is 2-10 nm.
  • the technical solution provided by the embodiments of the present disclosure at least has the following advantages: by forming a channel layer in the PMOS region to meet the performance requirements required by the PMOS region, and by setting the channel layer as a channel in the PMOS region, the current carrying capacity of the semiconductor structure can be improved. By using hydrogen ions to passivate the channel layer, the interface state on the surface of the channel layer can be improved, thereby reducing the leakage of the semiconductor structure.
  • FIG. 1 and 2 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • the present disclosure provides a method for manufacturing a semiconductor structure.
  • By passivating the channel layer after forming the channel layer, the gate electrode and the protective layer, using hydrogen ions to passivate the channel layer can reduce the cost of the semiconductor structure.
  • the interface state on the surface of the channel layer can thereby reduce the leakage between the source and drain of the transistor structure formed in the PMOS region.
  • FIGS. 1 and 2 are structural schematic diagrams corresponding to each step of a semiconductor structure provided by embodiments of the present disclosure.
  • a substrate 100 is provided that includes a PMOS region 101 .
  • the substrate 100 is a semiconductor material, including but not limited to any one of a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon carbide substrate.
  • the substrate 100 can also be an ion-doped substrate.
  • the doped ions are N-type ions or P-type ions.
  • the N-type ions can be phosphorus ions, arsenic ions or antimony ions, and the P-type ions can be boron ions or indium ions. Or boron fluoride ion.
  • the substrate 100 may be divided into a peripheral region, a core region, and an array region.
  • the peripheral area can be used to form peripheral circuit structures, for example, it can include a peripheral NMOS area and a peripheral PMOS area, where the peripheral NMOS area is the area where peripheral NMOS transistors are to be formed, and the peripheral PMOS area is the area where peripheral PMOS transistors are to be formed.
  • the core area can be used to form a core circuit structure, and the core area can include a core NMOS area and a core PMOS area, where the core NMOS area is the area where the core NMOS transistor is to be formed, and the core PMOS area is the area where the core PMOS transistor is to be formed.
  • the array area may be an area used to form a memory array, and the memory array may include word lines, bit lines, storage capacitors, and the like.
  • the substrate also includes an NMOS region 103 for forming NMOS transistors.
  • the channel layer 110 is formed, and the channel layer 110 is located on the surface of the substrate 100 in the PMOS region 101. It can be understood that by forming the channel layer 110 on the surface of the substrate 100 in the PMOS region 101, the channel layer 110 can be used as a PMOS The channel of the region 101 , that is to say, by forming the channel layer 110 and using the channel layer 110 as a channel, the mobility of channel carriers in the PMOS region 101 can be improved, so that the required performance of the PMOS region 101 can be achieved.
  • the method of forming the channel layer 110 may be to form an initial channel layer on the surfaces of the PMOS region 101 and the NMOS region 103, and by etching the initial channel layer on the surface of the NMOS region 103, leaving the The initial channel layer serves as channel layer 110 .
  • the material of the channel layer 110 may be silicon germanium or the like.
  • a gate dielectric layer 120 is formed, and the gate dielectric layer 120 is located on the surface of the channel layer 110 .
  • the gate dielectric layer 120 is also located on the surface of the substrate 100 in the NMOS region 103 .
  • part of the channel layer 110 and the substrate 103 of the NMOS region 103 can be converted into the gate dielectric layer 120 by means of in-situ steam generation (ISSG In-Situ Steam Generation).
  • the gate dielectric layer 120 can also be formed on the surface of the substrate 100 of the channel layer 110 and the NMOS region 103 by atomic deposition. The density of the gate dielectric layer 120 can be improved by in-situ water vapor generation. The deposition method can improve the uniformity of the gate dielectric layer 120 .
  • the gate dielectric layer 120 of the NMOS region 103 and the PMOS region 101 may be formed in the same step.
  • Figure 2 is a schematic structural diagram of the PMOS region 101.
  • An isolation layer 130 is formed.
  • the isolation layer 130 includes: a first isolation layer 131; a second isolation layer 132.
  • the second isolation layer 132 is located at the bottom of the first isolation layer 131 and Sidewall; third isolation layer 133.
  • the third isolation layer 133 is located at the bottom and sidewall of the second isolation layer 132.
  • the first isolation layer 131 can be used to isolate the memory cells in the array area to prevent the memory cells from being too close to each other and causing adjacent memory cells to conduct each other, thereby causing the performance of the semiconductor structure to decrease;
  • the second isolation layer The layer 132 is used to isolate the mutual influence between the circuit structures in the circuit area to avoid the interconnection between the circuit structures, thereby preventing the data disorder after the circuit structures are connected from affecting the performance of the semiconductor structure;
  • the third isolation layer 133 can It is used to fill the semiconductor structure so that the morphology of the semiconductor structure is better, and the third isolation layer 133 can isolate adjacent active areas to form separate active areas.
  • the material of the first isolation layer 131 may be the same as the material of the third isolation layer 133, which may be silicon oxide; the material of the second isolation layer 132 may be silicon nitride, silicon oxynitride, or the like.
  • an ONO (Oxide-Nitride-Oxide) structure can be formed, that is, an oxide layer-nitride layer-oxide layer structure.
  • the manufacturing method of the semiconductor structure further includes: forming a gate structure 200 , the gate structure 200 is located on the surface of the channel layer 110 .
  • the gate structure 200 includes a gate electrode 140 and a gate dielectric layer 120 .
  • the steps of forming the gate structure 200 include: forming an initial gate dielectric layer covering the surface of the initial channel layer; forming an initial gate electrode covering the surface of the initial gate dielectric layer; etching The initial gate electrode and the initial gate dielectric layer are etched, and the remaining initial gate electrode is used as the gate electrode 140 , the remaining initial gate dielectric layer is used as the gate dielectric layer 120 , and the gate electrode 140 and the gate dielectric layer 120 are used as the gate electrode structure 200 .
  • the channel layer 110 covers the entire top surface of the substrate 100 , and the length of the channel layer 110 is greater than the length of the gate structure 200 .
  • the step of forming the gate structure 200 may also include forming an initial gate electrode, an initial gate dielectric layer, and an initial channel layer.
  • the initial gate dielectric layer covers the surface of the initial channel layer, and the initial gate electrode covers the initial gate layer.
  • the gate 140 and the gate dielectric layer 120 serve as the gate structure 200
  • the remaining initial channel layer serves as the channel layer 110 , that is to say, the channel layer 110 does not cover the entire top surface of the substrate 100 in the PMOS region 101 , and the length of the channel layer 110 is equal to the length of the gate electrode 140 .
  • the gate 140 may have a three-layer structure, including a first gate conductive layer 141, a first diffusion barrier layer 142, and a second gate conductive layer 143.
  • the first gate conductive layer 141 is located in the gate dielectric layer. 120
  • the first diffusion barrier layer 142 is located on the top surface of the first gate conductive layer 141
  • the second gate conductive layer 143 is located on the surface of the first diffusion barrier layer 142.
  • the gate 140 may also be a single-layer structure. The embodiment of the present disclosure does not limit the specific structure of the gate 140 and can be adjusted according to actual conditions.
  • the material of the first gate conductive layer 141 may be a semiconductor material, such as polysilicon, and the material of the first diffusion barrier layer 142 may be a mixture of metal and non-metal materials, such as titanium nitride.
  • the material of the extremely conductive layer 143 can be a metal material, such as metal tungsten, etc.
  • metal ions in the second gate conductive layer 143 can be prevented from diffusing into the first gate conductive layer 141, thereby preventing the first gate conductive layer 141 from being contaminated, thereby improving the performance of the first gate conductive layer 141. Reliability of Semiconductor Structures.
  • parts of the substrate 100 on both sides of the projection of the gate structure 200 on the surface of the substrate 100 may serve as the first doping region 105 and the second doping region 106 to serve as the source and drain.
  • the gate structure 200 is used to control whether the first doped region 105 and the second doped region 106 are conductive. Theoretically, when the gate structure 200 has no voltage, the first doped region 105 and the second doped region 106 are conductive. No current will flow between the second doped regions 106, that is, the semiconductor structure is in a cut-off state.
  • the gate dielectric layer 120 assuming that the material of the channel layer 110 is silicon germanium, for example, A large number of germanium-oxygen bonds and interface states are formed on the surface of the channel layer 110 , resulting in a large number of leakage paths in the channel layer 110 and increasing the leakage between the first doped region 105 and the second doped region 106 . Therefore, passivation treatment is performed in subsequent steps to reduce the germanium-oxygen bonds and interface states formed on the surface of the channel layer 110, thereby reducing leakage between the first doped region 105 and the second doped region 106.
  • a protective layer 150 covers the surface of the gate structure 200 and part of the surface of the channel layer 110.
  • the gate structure 200 can be isolated from external structures by forming the protective layer 150. Therefore, the gate structure 200 can be prevented from contacting the outside world, the gate structure 200 can be prevented from being in contact with air, the gate structure 200 can be prevented from being oxidized, the reliability of the semiconductor structure can be improved, and the protective layer 150 can also be formed in the semiconductor.
  • the protective layer 150 absorbs part of the stress, thereby reducing the stress on the gate structure 200 and improving the reliability of the semiconductor structure.
  • the protective layer 150 may include a first protective layer 151; a second protective layer 152 located on the sidewall of the first protective layer; and a third protective layer 153 located on the sidewall of the first protective layer.
  • the materials of the first protective layer 151 and the third protective layer 153 may be the same.
  • the material of the first protective layer 151 and the third protective layer 153 may be silicon nitride, and the material of the second protective layer 152 may be silicon oxide, so that the protective layer 150 forms NON (Nitride- Oxide-Nitride) structure, that is, nitride layer-oxide layer-nitride layer structure, by providing the second protective layer 152, the insulation performance between the first protective layer 151 and the third protective layer 153 can be improved. Since the second protective layer 152 The material is soft and the morphology is poor. Therefore, the first protective layer 151 and the third protective layer 153 made of nitride layers are formed to improve the morphology of the second protective layer 152 .
  • the channel layer 110 is passivated using hydrogen ions.
  • the gap between the channel layer 110 and the gate electrode 140 It also includes a gate dielectric layer 120.
  • the germanium oxide chemical bond formed between the gate dielectric layer 120 and the channel layer 110 will cause a large number of leakage paths in the channel layer 110, resulting in the source of the PMOS tube formed on the PMOS region 101.
  • Leakage occurs between the gate dielectric layer 120 and the channel layer 110 through passivation treatment to destroy the germanium oxide chemical bond formed between the gate dielectric layer 120 and the channel layer 110, thereby reducing the source and drain resistance of the PMOS tube formed on the PMOS region 101. Leakage in the room.
  • the channel layer 110 in the PMOS region 101 By forming the channel layer 110 in the PMOS region 101 to meet the required performance requirements of the PMOS region 101, and by providing the channel layer 110 as the channel layer 110 of the PMOS region 101, the carrier mobility of the semiconductor structure can be improved, The passivation treatment can improve the interface state on the surface of the channel layer 110, thereby reducing the leakage of the semiconductor structure.
  • the steps of forming the gate structure 200 and the protective layer 150 include: forming the gate structure 200, which is located on the surface of the channel layer 110; forming the protective layer 150, which covers the channel layer 110 surface and the sidewalls and top surface of the gate structure 200.
  • the gate structure 200 is formed first, and then the protective layer 150 is formed. This is also a gate-first process.
  • the gate structure 200 is formed first, and then the protective layer 150 is formed.
  • Layer 150 can reduce the process difficulty of the manufacturing method of the semiconductor structure.
  • the steps of forming the gate structure 200 and the protective layer 150 include: forming an initial protective layer to cover the surface of the channel layer 110; etching the initial protective layer to form a trench, and the trench exposes the trench. on the surface of the channel layer 110; a gate structure 200 is formed, and the gate structure 200 is located in the trench; a cover layer is formed, and the cover layer and the remaining initial protective layer constitute the protective layer 150.
  • a part of the protective layer is formed first. 150, and then the gate structure 200 is formed, which is a gate-last process.
  • the passivation process before performing the passivation process, it further includes: forming an insulating layer 160 , the insulating layer 160 is located on the surface of the substrate 100 , and the insulating layer 160 covers the sidewalls of the protective layer 150 .
  • the formation of the insulating layer 160 provides support for the subsequent formation of the first conductive layer 190 .
  • forming the insulating layer 160 further includes: forming a support layer 170 , the support layer 170 is located on the top surface of the insulating layer 160 , and the support layer 170 is located on the top surface of the protective layer 150 .
  • the material of the insulating layer 160 can be silicon oxide
  • the material of the supporting layer 170 can be silicon nitride.
  • the material of silicon nitride is relatively hard, so it can have a better supporting effect, and can avoid the problem of insulating the supporting layer.
  • the first conductor layer 190 formed on the surface of 170 is deformed.
  • it may also include: forming a first conductive pillar 180 penetrating the insulating layer 160 to connect with the substrate 100 of the PMOS region 101 or the first conductive pillar 180 penetrating the insulating layer 160 and the protective layer 150 to connect with the gate structure 200 .
  • a first conductive pillar 180 electrical signals from the first doped region 105 and the second doped region 106 can be derived, or signals from the gate structure 200 can be derived, or electrical signals can be provided to the gate structure 200 .
  • the method of forming the first conductive pillar 180 may be: etching the insulating layer 160 and the support layer 170 through mask etching to form a groove, and the groove penetrates the insulating layer 160 to expose the PMOS region 101 lining.
  • the surface or groove of the bottom 100 penetrates the insulating layer 160 and the protective layer 150 to expose the top surface of the gate structure 200; a conductive contact layer 181 is formed, and the conductive contact layer 181 is located on the bottom surface of the groove; a diffusion barrier layer 182 is formed, the diffusion barrier layer 182 is located on the inner wall of the groove and the surface of the conductive contact layer 181; a conductive plug layer 183 is formed, and the conductive plug layer 183 fills the groove.
  • the conductive contact layer 181 can be used to avoid a too large gap between the material properties of the first conductive pillar 180 and the material properties of the substrate 100 when the first conductive pillar 180 contacts the substrate 100, thereby avoiding the first An abnormality occurs during signal transmission between the conductive pillar 180 and the substrate 100; the diffusion barrier layer 182 can be used to isolate the conductive contact layer 181 from the conductive plug layer 183, thereby preventing the metal ions of the conductive plug layer 183 from diffusing to The conductive contact layer 181 affects the transmission of the conductive contact layer 181; the conductive plug layer 183 is used to increase the transmission speed of the first conductive pillar 180, reduce the response time of the semiconductor structure, and improve the performance of the semiconductor structure.
  • the method of forming the conductive contact layer 181 includes: forming a contact material layer (not shown in the figure), the contact material layer is located on the surface of the substrate 100 exposed by the bottom surface of the groove or the top surface of the gate structure 200 ; Use a rapid thermal annealing process to react the substrate 100 or the gate structure 200 with the contact material layer to form the conductive contact layer 181.
  • the conductive contact layer 181 can be formed using a metal oxide process.
  • the contact resistance between the formed conductive contact layer 181 and the substrate 100 is relatively low, which can improve the performance of the semiconductor structure.
  • the groove is located in the substrate 100, and the formed conductive contact layer 181, part of the diffusion barrier layer 182 and part of the conductive plug layer 183 is located in the substrate 100; in other embodiments, the groove is located in the substrate 100.
  • the conductive contact layer 181 formed is located in the substrate 100 , and the diffusion barrier layer 182 and the conductive plug layer 183 are located on the surface of the substrate 100 .
  • the passivation treatment before performing the passivation treatment, it further includes: forming a first conductive layer 190 , the first conductive layer 190 is located on the surface of the insulating layer 160 , and the first conductive layer 190 is in contact with the top surface of the first conductive pillar 180 connect.
  • the first conductor layer 190 can be used for wiring of the semiconductor structure. That is to say, the structure inside the semiconductor structure can be connected to external electrical signals through the first conductor layer 190 , for example, the first doped region 105 and the first conductor layer can be connected. 190 is connected, and then the electrical signal required by the first doping region 105 is input to the first conductor layer 190, so that the required electrical signal can be input to the first doping region 105.
  • the passivation treatment includes: passing a hydrogen-containing passivation gas into the channel layer 110, the hydrogen-containing passivation gas includes: hydrogen or a mixed gas of hydrogen and an inert gas, passivating the channel layer 110 through hydrogen bonding.
  • the germanium-oxygen bond on the surface reduces the interface state on the surface of the channel layer 110, and after the surface of the channel layer 110 is passivated by hydrogen gas, a film layer with hydrogen bonds will be formed on the surface of the channel layer 110.
  • the bonding film layer can also improve the tightness of the connection between the channel layer 110 and the substrate 100 .
  • the semiconductor structure may be passivated after the protective layer 150 is formed and before the insulating layer 160 is formed. Passivating the semiconductor structure after the protective layer 150 is formed may prevent the gate structure 200 from being passivated. , thereby avoiding affecting the performance of the gate structure 200 .
  • the passivation process can also be performed after the first conductive layer 190 is formed. At this time, the hydrogen-containing passivation gas introduced in the passivation process can pass through the first conductive pillar 180, the insulating layer 160 and the support.
  • connection gap between the layers 170 flows to the surface of the channel layer 110, thereby reacting with the germanium-oxygen bonds on the surface of the channel layer 110, thereby destroying the germanium-oxygen bonds on the surface of the channel layer 110, and reducing the surface area of the channel layer 110. interface state, thereby reducing the leakage path in the channel layer 110 and reducing the possibility of leakage of the semiconductor structure.
  • the passivation process also includes: passivating the sidewalls of the first conductive layer 190 and the first conductive pillar 180 facing the insulating layer 160 , and the surface of the first conductive pillar 180 can also be repaired through the passivation process. , to improve the connection effect between the first conductive layer 190 and the first conductive pillar 180 and the insulating layer 160, so that the first conductive layer 190 and the first conductive pillar 180 and the insulating layer 160 can be connected more closely.
  • the gas flow rate of the hydrogen-containing passivation gas introduced into the passivation process is 3.5L/min to 6.5L/min, such as 4L/min or 5L/min. It can be understood that the passivation process The smaller the gas flow rate of the hydrogen-containing passivation gas introduced, the worse the ability to destroy germanium-oxygen bonds. That is to say, when the gas flow rate of the hydrogen-containing passivation gas introduced during the passivation process is less than 3.5L/min At this time, the passivation effect of the passivation treatment is not good, and the effect of improving the leakage of the semiconductor structure is not good.
  • the phenomenon of passivation that is to say, when the gas flow rate of the hydrogen-containing passivation gas introduced in the passivation process is greater than 6.5L/min, it may cause the parts that do not need to be passivated to be passivated, such as the gate structure 200 being passivated. ation, causing the performance of the gate structure 200 to degrade.
  • the duration of the passivation treatment is 21 minutes to 39 minutes, such as 25 minutes or 30 minutes.
  • the shorter the duration of the passivation treatment the correspondingly poorer the ability to destroy germanium-oxygen bonds. That is to say, When the passivation treatment time is less than 21 minutes, the passivation effect of the passivation treatment is not good, and the effect of improving the leakage of the semiconductor structure is not good.
  • the passivation phenomenon that is, when the passivation treatment lasts longer than 39 minutes, may cause parts that do not need to be passivated to be passivated, such as the gate structure 200 being passivated, resulting in a decrease in the performance of the gate structure 200 .
  • the temperature of the passivation treatment is 310-530°C, such as 350°C, 400°C, or 450°C.
  • the temperature of the passivation treatment is less than 310°C, the reaction between the hydrogen gas and the channel layer 110 is incomplete and thus As a result, the passivation effect of the passivation treatment is poor.
  • the temperature of the passivation treatment is greater than 530° C., it may affect other formed structures, such as the gate structure 200 , which may cause the performance of the gate structure 200 to decrease.
  • the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. After forming the channel layer 110 on the surface of the substrate 100 in the PMOS region 101, and then forming the gate structure 200 and the protective layer 150 on the surface of the channel layer 110, hydrogen is used.
  • the channel layer 110 is passivated by ions to reduce the interface state on the surface of the channel layer 110, thereby reducing the leakage path of the channel layer 110 and improving the reliability of the semiconductor structure.
  • Another embodiment of the present disclosure also provides a semiconductor structure, which can be formed by using all or part of the steps of the above-mentioned manufacturing method of the semiconductor structure.
  • the semiconductor structure will be described below with reference to the accompanying drawings. The same or corresponding parts can refer to the above-mentioned embodiments. No further details will be given below.
  • the semiconductor structure includes: a substrate 100, which includes a PMOS region 101; a channel layer 110, which is located on the surface of the substrate 100 in the PMOS region 101, and is formed on the surface of the channel layer 110. Hydrogen bonding; gate structure 200, the gate structure 200 is located on the surface of the channel layer 110; protective layer 150, the protective layer 150 covers the top surface and side walls of the gate structure 200, and the protective layer 150 also covers the channel layer 110 At least part of the surface. Through the hydrogen bonding on the surface of the channel layer 110, the interface state on the surface of the channel layer 110 can be reduced, thereby reducing the leakage of the channel layer 110.
  • the substrate 100 further includes: an NMOS region 103, and the NMOS region 103 is used to form an NMOS tube.
  • the thickness of the channel layer 110 may be 2 to 10 nm, such as 5 nm, 6 nm, 7 nm, or 8 nm.
  • the thickness of the channel layer 110 is greater than 10 nm, the probability of lattice dislocation may increase, resulting in The performance of the semiconductor structure decreases.
  • the thickness of the channel layer 110 is less than 2 nm, the number of carriers in the channel layer 110 is small, and the width of the channel as a semiconductor structure is narrow, which affects the carriers of the semiconductor structure.
  • the transmission rate affects the performance of semiconductor structures.
  • the semiconductor structure further includes: an isolation layer 130.
  • the isolation layer 130 may include: a first isolation layer 131; a second isolation layer 132 located on the bottom and sidewalls of the first isolation layer 131;
  • the third isolation layer 133 is located at the bottom and side walls of the second isolation layer.
  • the first isolation layer 131 can be used to isolate the memory cells in the array area to prevent the memory cells from being too close to each other and affecting each other.
  • the second isolation layer 132 is used to isolate the mutual influence between the circuit structures in the circuit area, to avoid the interconnection between the circuit structures, thereby Prevent data disorder after the circuit structure is connected from affecting the performance of the semiconductor structure;
  • the third isolation layer 133 can be used to fill the semiconductor structure, thereby making the morphology of the semiconductor structure better, and the third isolation layer 133 can separate adjacent active The areas are isolated to form separate active areas.
  • the gate structure 200 includes: a gate electrode 140 and a gate dielectric layer 120.
  • the gate electrode 140 is used to control the conduction of the channel layer 110.
  • the gate dielectric layer 120 is used to prevent the gate electrode 140 from contacting the channel layer 110. direct contact.
  • the gate 140 may have a three-layer structure, including a first gate conductive layer 141, a first diffusion barrier layer 142, and a second gate conductive layer 143.
  • the first gate conductive layer 141 is located in the gate dielectric layer. 120
  • the first diffusion barrier layer 142 is located on the top surface of the first gate conductive layer 141
  • the second gate conductive layer 143 is located on the surface of the first diffusion barrier layer 142.
  • the gate 140 may also be a single-layer structure. The embodiment of the present disclosure does not limit the specific structure of the gate 140 and can be adjusted according to actual conditions.
  • parts of the substrate 100 on both sides of the projection of the gate structure 200 on the surface of the substrate 100 may serve as the first doping region 105 and the second doping region 106 to serve as the source and drain.
  • the protective layer 150 may include a first protective layer 151; a second protective layer 152 located on the sidewall of the first protective layer; and a third protective layer 153 located on the sidewall of the first protective layer.
  • the first protective layer 151 and the third protective layer 153 can be made of the same material.
  • the second protective layer 150 can be made of the same material.
  • the protective layer 152 can improve the insulation performance between the first protective layer 151 and the third protective layer 153.
  • the second protective layer 152 is made of a nitride layer.
  • a protective layer 151 and a third protective layer 153 are used to improve the topography of the second protective layer 152.
  • it also includes: an insulating layer 160 located on the surface of the substrate 100 and covering the sidewalls of the protective layer 150; a first conductive pillar 180 penetrating the insulating layer 160 and The substrate 100 of the PMOS region 101 is connected or the first conductive pillar 180 penetrates the insulating layer 160 and the protective layer 150 to connect with the gate structure 200 .
  • the insulating layer 160 can support the sidewalls of the first conductive pillar 180 and can also support the first conductive line layer 190.
  • the first conductive pillar 180 When the first conductive pillar 180 is connected to the substrate 100 of the PMOS region 101, the first conductive pillar 180 can Electrical signals are extracted from the first doped region 105 and the second doped region 106 of the semiconductor structure, or electrical signals are provided to the first doped region 105 and the second doped region 106; when the first conductive pillar 180 and the gate structure 200 is connected, the electrical signal of the gate structure 200 can be extracted through the first conductive pillar 180 or the electrical signal can be provided to the gate structure 200 .
  • the first conductive pillar 180 includes: a conductive contact layer 181 located in the substrate 100 of the PMOS region 101 or on the top surface of the gate structure 200; a diffusion barrier layer 182 on the bottom surface of the diffusion barrier layer 182 In contact with the top surface of the conductive contact layer 181, the diffusion barrier layer 182 also includes side surfaces surrounding the bottom surface of the diffusion barrier layer 182. The bottom surface and side surfaces of the diffusion barrier layer 182 form an accommodation space; a conductive plug layer 183, which is located The surface of the diffusion barrier layer 182 is filled with the accommodation space. That is to say, when the first conductive pillar 180 is connected to the substrate 100, the conductive contact layer 181 is located in the substrate 100 of the PMOS region 101.
  • the conductive contact layer 181 When the first conductive pillar 180 is connected to the gate structure 200, the conductive contact layer 181 is located in the substrate 100. On the top surface of the gate structure 200, the conductive contact layer 181 can be used to avoid the gap between the material of the first conductive pillar 180 and the material of the substrate 100 being too large when the first conductive pillar 180 is in contact with the substrate 100, thereby preventing the second conductive pillar 180 from being in contact with the substrate 100.
  • An abnormality occurs during signal transmission between a conductive pillar 180 and the substrate 100; the diffusion barrier layer 182 can be used to isolate the conductive contact layer 181 from the conductive plug layer 183, thereby avoiding the diffusion of metal ions in the conductive plug layer 183. into the conductive contact layer 181 to affect the transmission of the conductive contact layer 181; the conductive plug layer 183 is used to increase the transmission speed of the first conductive pillar 180, reduce the response time of the semiconductor structure, and improve the performance of the semiconductor structure.
  • the conductive plug layer 183 may also be located within the substrate 100 of the PMOS region 101 , that is, the bottom surface of the conductive plug layer 183 is lower than the top surface of the substrate 100 .
  • the layer 183 located in the substrate 100 of the PMOS region 101 can improve the reliability of the connection between the first conductive pillar 180 and the substrate 100 , and can also increase the contact area between the first conductive pillar 180 and the substrate 100 and reduce the Contact resistance to substrate 100.
  • a support layer 170 is also included, the support layer 170 is located on the top surface of the insulating layer 160 , and the support layer 170 is located on the top surface of the protective layer 150 .
  • the support layer 170 may provide support for the first conductor layer 190 .
  • the first conductive layer 190 is located on the surface of the insulating layer 160 , and the first conductive layer 190 is in contact with the top surface of the first conductive pillar 180 .
  • the first conductor layer 190 can be used for wiring of the semiconductor structure. That is to say, the structure inside the semiconductor structure can be connected to external electrical signals through the first conductor layer 190 , for example, the first doped region 105 and the first conductor layer can be connected. 190 is connected, and then the electrical signal required by the first doping region 105 is input to the first conductor layer 190, so that the required electrical signal can be input to the first doping region 105.
  • a hydrogen bond is formed on the surface of the first conductive pillar 180 facing the insulating layer 160 .
  • the hydrogen bond disposed between the first conductive pillar 180 and the insulating layer 160 can improve the relationship between the first conductive pillar 180 and the insulating layer 160 . tightness of connection.
  • the embodiment of the present disclosure provides a semiconductor structure, including a substrate 100, a channel layer 110 located on the surface of the substrate 100 in the PMOS region 101, and hydrogen bonds are formed on the surface of the channel layer 110, and a channel layer 110 located on the surface of the channel layer 110.

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate, the substrate comprising a PMOS region; forming a channel layer, the channel layer being located on the surface of the substrate in the PMOS region; forming a gate structure and a protective layer, the gate structure being located on the surface of the channel layer, and the protective layer covering the surface of the gate structure and part of the surface of the channel layer; and after the gate structure and the protective layer are formed, passivating the surface of the channel layer by using a hydrogen ion casting process. Therefore, electric leakage of the semiconductor structure can be reduced.

Description

一种半导体结构的制作方法及其结构A method for manufacturing a semiconductor structure and its structure
交叉引用cross reference
本公开要求于2022年08月25日递交的名称为“一种半导体结构的制作方法及其结构”、申请号为202211027230.8的中国专利申请的优先权，其通过引用被全部并入本公开。This disclosure claims priority to the Chinese patent application titled "A manufacturing method and structure of a semiconductor structure" and application number 202211027230.8, which was submitted on August 25, 2022, which is fully incorporated into this disclosure by reference.
技术领域Technical field
本公开实施例涉及半导体领域，特别涉及一种半导体结构的制作方法及其结构。Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure and its structure.
背景技术Background technique
存储器是一种常见半导体结构，且存储器包括阵列区和***电路有源区，其中，阵列区具有存储阵列，***电路有源区具有控制存储阵列的电路结构，且阵列区以及***电路有源区的衬底内均设置有隔离结构。由于***电路有源区中不同的晶体管需要配置不同的功能，从而需要形成不同的结构，如PMOS区，且通常PMOS区的衬底顶部需要形成沟道层，以提高PMOS区中形成PMOS晶体管的读取速度。Memory is a common semiconductor structure, and the memory includes an array area and a peripheral circuit active area. The array area has a memory array, the peripheral circuit active area has a circuit structure that controls the memory array, and the array area and the peripheral circuit active area Isolation structures are provided in the substrates. Since different transistors in the active area of the peripheral circuit need to be configured with different functions, different structures need to be formed, such as the PMOS area, and usually a channel layer needs to be formed on the top of the substrate in the PMOS area to improve the efficiency of forming PMOS transistors in the PMOS area. Reading speed.
然而形成沟道层之后会增加存储器的漏电现象。However, forming the channel layer will increase the leakage of the memory.
发明内容Contents of the invention
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制作方法，包括：提供衬底，所述衬底包括PMOS区；形成沟道层，所述沟道层位于所述PMOS区的所述衬底的表面；形成栅极结构和保护层，所述栅极结构位于所述沟道层的表面，所述保护层覆盖所述栅极结构的表面以及所述沟道层的部分表面；在形成所述栅极结构及所述保护层之后，采用氢离子铸合工艺对所述沟道层的表面进行钝化处理。According to some embodiments of the present disclosure, on the one hand, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including a PMOS region; forming a channel layer, the channel layer being located on the PMOS The surface of the substrate in the area; forming a gate structure and a protective layer, the gate structure is located on the surface of the channel layer, the protective layer covers the surface of the gate structure and the channel layer Part of the surface; after forming the gate structure and the protective layer, a hydrogen ion casting process is used to passivate the surface of the channel layer.
在一些实施例中所述钝化处理包括：向所述沟道层通入含氢钝化气体，所述含氢钝化气体包括：氢气或者氢气与惰性气体的混合气体。In some embodiments, the passivation treatment includes: passing a hydrogen-containing passivation gas into the channel layer, where the hydrogen-containing passivation gas includes: hydrogen or a mixed gas of hydrogen and an inert gas.
在一些实施例中，所述钝化处理的温度为310～530℃。In some embodiments, the passivation treatment temperature is 310˜530°C.
在一些实施例中，所述钝化处理通入的含氢钝化气体的气流量为3.5L/min～6.5L/min。In some embodiments, the gas flow rate of the hydrogen-containing passivation gas introduced into the passivation process is 3.5L/min to 6.5L/min.
在一些实施例中，所述钝化处理的时长为21min～39min。In some embodiments, the duration of the passivation treatment is 21 minutes to 39 minutes.
在一些实施例中，进行所述钝化处理之前，还包括：形成绝缘层，所述绝缘层位于所述衬底表面，且所述绝缘层覆盖所述保护层的侧壁；形成第一导电柱，所述第一导电柱贯穿 所述绝缘层以与所述PMOS区的所述衬底连接或所述第一导电柱贯穿所述绝缘层以及所述保护层以与所述栅极结构连接。In some embodiments, before performing the passivation treatment, the method further includes: forming an insulating layer, the insulating layer is located on the surface of the substrate, and the insulating layer covers the sidewall of the protective layer; forming a first conductive layer Pillar, the first conductive pillar penetrates the insulating layer to connect with the substrate of the PMOS region or the first conductive pillar penetrates the insulating layer and the protective layer to connect with the gate structure .
在一些实施例中，形成所述第一导电柱的方法包括：刻蚀所述绝缘层，以形成凹槽，所述凹槽贯穿所述绝缘层以暴露所述PMOS区的所述衬底的表面或所述凹槽贯穿所述绝缘层以及所述保护层以暴露所述栅极的顶面；形成导电接触层，所述导电接触层位于所述凹槽的底面；形成扩散阻挡层，所述扩散阻挡层位于所述凹槽的内壁和所述导电接触层的表面；形成导电插塞层，所述导电插塞层填充满所述凹槽。In some embodiments, the method of forming the first conductive pillar includes etching the insulating layer to form a groove penetrating the insulating layer to expose the PMOS region of the substrate. The surface or the groove penetrates the insulating layer and the protective layer to expose the top surface of the gate; a conductive contact layer is formed, and the conductive contact layer is located on the bottom surface of the groove; a diffusion barrier layer is formed, so The diffusion barrier layer is located on the inner wall of the groove and on the surface of the conductive contact layer; a conductive plug layer is formed, and the conductive plug layer fills the groove.
在一些实施例中，形成所述导电接触层的方法包括：形成接触材料层，所述接触材料层位于所述凹槽的底面所暴露出的所述衬底表面或所述栅极顶面；采用快速热退火工艺使所述衬底或所述栅极与所述接触材料层反应形成所述导电接触层。In some embodiments, the method of forming the conductive contact layer includes: forming a contact material layer located on the substrate surface or the gate top surface exposed by the bottom surface of the groove; using A rapid thermal annealing process causes the substrate or the gate electrode to react with the contact material layer to form the conductive contact layer.
在一些实施例中，进行所述钝化处理之前，还包括：形成第一导线层，所述第一导线层位于所述绝缘层的表面，且所述第一导线层与所述第一导电柱的顶面接触连接。In some embodiments, before performing the passivation treatment, it further includes: forming a first conductive layer, the first conductive layer is located on the surface of the insulating layer, and the first conductive layer is in contact with the first conductive layer. The top surface of the column contacts the connection.
在一些实施例中，所述钝化处理还包括：对所述第一导线层及所述第一导电柱朝向所述绝缘层的侧壁进行所述钝化处理。In some embodiments, the passivation process further includes: performing the passivation process on sidewalls of the first conductive line layer and the first conductive pillar facing the insulating layer.
在一些实施例中，形成所述栅极结构的步骤包括：形成初始栅介质层，所述初始栅介质层覆盖所述沟道层的表面；形成初始栅极，所述初始栅极覆盖所述初始栅介质层的表面；刻蚀所述初始栅极和初始栅介质层，剩余所述初始栅极作为栅极，剩余所述初始栅介质层作为栅介质层，所述栅极及所述栅介质层作为所述栅极结构。In some embodiments, the step of forming the gate structure includes: forming an initial gate dielectric layer covering the surface of the channel layer; forming an initial gate electrode covering the surface of the channel layer; The surface of the initial gate dielectric layer; etching the initial gate electrode and the initial gate dielectric layer, leaving the initial gate electrode as a gate electrode, and the remaining initial gate dielectric layer as a gate dielectric layer, the gate electrode and the gate dielectric layer The dielectric layer serves as the gate structure.
在一些实施例中，形成所述栅极结构和所述保护层的步骤包括：形成所述栅极结构，所述栅极结构位于所述沟道层的表面；形成所述保护层，所述保护层覆盖所述沟道层的部分表面及所述栅极结构的侧壁及顶面。In some embodiments, the steps of forming the gate structure and the protective layer include: forming the gate structure, which is located on the surface of the channel layer; forming the protective layer, The protective layer covers part of the surface of the channel layer and the sidewalls and top surface of the gate structure.
在一些实施例中，形成所述栅极结构和所述保护层的步骤包括：形成初始保护层，所述初始保护层覆盖所述沟道层的表面；刻蚀所述初始保护层，以形成沟槽，所述沟槽暴露所述沟道层的表面；形成所述栅极结构，所述栅极结构位于所述沟槽内；形成盖层，所述盖层与剩余所述初始保护层构成所述保护层。In some embodiments, the steps of forming the gate structure and the protective layer include: forming an initial protective layer covering the surface of the channel layer; etching the initial protective layer to form trench, the trench exposes the surface of the channel layer; forming the gate structure, the gate structure is located in the trench; forming a cover layer, the cover layer and the remaining initial protective layer constitute the protective layer.
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：衬底，所述衬底包括PMOS区；沟道层，所述沟道层位于所述PMOS区的所述衬底的表面，所述沟道层的表面形成有氢键；栅极结构，所述栅极结构位于所述沟道层的表面；保护层，所述保护层覆盖所述栅极结构的顶面及侧壁，且所述保护层还覆盖所述沟道层的至少部分表面。According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor structure, including: a substrate including a PMOS region; and a channel layer located at all parts of the PMOS region. The surface of the substrate, hydrogen bonds are formed on the surface of the channel layer; a gate structure, the gate structure is located on the surface of the channel layer; a protective layer, the protective layer covers the gate structure The protective layer also covers at least part of the surface of the channel layer.
在一些实施例中，绝缘层，所述绝缘层位于所述衬底表面，且所述绝缘层覆盖所述保护层的侧壁；第一导电柱，所述第一导电柱贯穿所述绝缘层与所述PMOS区的所述衬底连接或所述第一导电柱贯穿所述绝缘层以及所述保护层以与所述栅极结构连接。In some embodiments, an insulating layer, the insulating layer is located on the surface of the substrate, and the insulating layer covers the sidewall of the protective layer; a first conductive pillar, the first conductive pillar penetrates the insulating layer Connected to the substrate of the PMOS region or the first conductive pillar penetrates the insulating layer and the protective layer to connect to the gate structure.
在一些实施例中，所述第一导电柱包括：导电接触层，所述导电接触层位于所述PMOS区的所述衬底内或所述栅极结构顶面；扩散阻挡层，所述扩散阻挡层的底面与所述导电接触层的顶面接触，所述扩散阻挡层还包括环绕所述扩散阻挡层底面的侧面，所述扩散阻挡层的底面与侧面围成容纳空间；导电插塞层，所述导电插塞层位于所述扩散阻挡层的表面，且填充满所述容纳空间。In some embodiments, the first conductive pillar includes: a conductive contact layer located within the substrate of the PMOS region or on the top surface of the gate structure; a diffusion barrier layer, the diffusion The bottom surface of the barrier layer is in contact with the top surface of the conductive contact layer. The diffusion barrier layer also includes side surfaces surrounding the bottom surface of the diffusion barrier layer. The bottom surface and side surfaces of the diffusion barrier layer form an accommodation space; a conductive plug layer , the conductive plug layer is located on the surface of the diffusion barrier layer and fills the accommodation space.
在一些实施例中，至少部分所述导电插塞层位于所述PMOS区的所述衬底内。In some embodiments, at least a portion of the conductive plug layer is located within the substrate of the PMOS region.
在一些实施例中，所述第一导电柱朝向所述绝缘层的表面形成有氢键。In some embodiments, hydrogen bonds are formed on a surface of the first conductive pillar facing the insulating layer.
在一些实施例中，所述沟道层的厚度为2～10nm。In some embodiments, the thickness of the channel layer is 2-10 nm.
本公开实施例提供的技术方案至少具有以下优点：通过在PMOS区形成沟道层以满足PMOS区所需的性能要求，通过设置沟道层作为PMOS区的沟道，可以提高半导体结构的载流子的迁移率，通过采用氢离子对沟道层进行钝化处理可以改善沟道层表面的界面态，从而可以降低半导体结构的漏电。The technical solution provided by the embodiments of the present disclosure at least has the following advantages: by forming a channel layer in the PMOS region to meet the performance requirements required by the PMOS region, and by setting the channel layer as a channel in the PMOS region, the current carrying capacity of the semiconductor structure can be improved. By using hydrogen ions to passivate the channel layer, the interface state on the surface of the channel layer can be improved, thereby reducing the leakage of the semiconductor structure.
附图说明Description of drawings
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。One or more embodiments are exemplified by the pictures in the corresponding drawings. These illustrative illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a limitation on proportions; in order to To more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.
图1及图2为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。1 and 2 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
具体实施方式Detailed ways
本公开实施提供一种半导体结构的制作方法，通过在形成沟道层、栅极及保护层之后对沟道层进行钝化处理，采用氢离子的方式对沟道层进行对钝化处理可以减低沟道层表面的界面态，从而可以降低PMOS区内形成的晶体管结构的源漏之间漏电。The present disclosure provides a method for manufacturing a semiconductor structure. By passivating the channel layer after forming the channel layer, the gate electrode and the protective layer, using hydrogen ions to passivate the channel layer can reduce the cost of the semiconductor structure. The interface state on the surface of the channel layer can thereby reduce the leakage between the source and drain of the transistor structure formed in the PMOS region.
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但 是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to allow the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present disclosure can also be implemented.
参考图1及图2，图1及图2为本公开实施例提供的一种半导体结构各步骤对应的结构示意图。Referring to FIGS. 1 and 2 , FIGS. 1 and 2 are structural schematic diagrams corresponding to each step of a semiconductor structure provided by embodiments of the present disclosure.
在一些实施例中，参考图1，提供衬底100，衬底100包括PMOS区101。In some embodiments, referring to FIG. 1 , a substrate 100 is provided that includes a PMOS region 101 .
在一些实施例中，衬底100为半导体材料，半导体材料包括但不限于硅衬底、锗衬底、锗硅衬底或碳化硅衬底的任一种。衬底100还可以是离子掺杂衬底，掺杂离子为N型离子或者P型离子，N型离子具体可以为磷离子、砷离子或者锑离子，P型离子具体可以为硼离子、铟离子或者氟化硼离子。In some embodiments, the substrate 100 is a semiconductor material, including but not limited to any one of a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon carbide substrate. The substrate 100 can also be an ion-doped substrate. The doped ions are N-type ions or P-type ions. The N-type ions can be phosphorus ions, arsenic ions or antimony ions, and the P-type ions can be boron ions or indium ions. Or boron fluoride ion.
在一些实施例中，可以将衬底100分为***区、核心区和阵列区。In some embodiments, the substrate 100 may be divided into a peripheral region, a core region, and an array region.
***区可以用于形成***电路结构，例如可以包括***NMOS区及***PMOS区，其中***NMOS区为待形成***NMOS晶体管的区域，***PMOS区为待形成***PMOS晶体管的区域。The peripheral area can be used to form peripheral circuit structures, for example, it can include a peripheral NMOS area and a peripheral PMOS area, where the peripheral NMOS area is the area where peripheral NMOS transistors are to be formed, and the peripheral PMOS area is the area where peripheral PMOS transistors are to be formed.
核心区可以用于形成核心电路结构，核心区可以包括核心NMOS区及核心PMOS区，其中，核心NMOS区为待形成核心NMOS晶体管的区域，核心PMOS区为待形成核心PMOS晶体管的区域。The core area can be used to form a core circuit structure, and the core area can include a core NMOS area and a core PMOS area, where the core NMOS area is the area where the core NMOS transistor is to be formed, and the core PMOS area is the area where the core PMOS transistor is to be formed.
阵列区可以是用于形成存储阵列的区域，存储阵列可以包括字线、位线以及存储电容等。The array area may be an area used to form a memory array, and the memory array may include word lines, bit lines, storage capacitors, and the like.
在一些实施例中，衬底还包括NMOS区103，NMOS区103用于形成NMOS晶体管。In some embodiments, the substrate also includes an NMOS region 103 for forming NMOS transistors.
形成沟道层110，沟道层110位于PMOS区101的衬底100表面，可以理解的是，通过在PMOS区101的衬底100表面形成沟道层110，从而可以将沟道层110作为PMOS区101的沟道，也就是说通过形成沟道层110并将沟道层110作为沟道可以提高PMOS区101沟道载流子的迁移率，从而可以实现PMOS区101所需求的性能。The channel layer 110 is formed, and the channel layer 110 is located on the surface of the substrate 100 in the PMOS region 101. It can be understood that by forming the channel layer 110 on the surface of the substrate 100 in the PMOS region 101, the channel layer 110 can be used as a PMOS The channel of the region 101 , that is to say, by forming the channel layer 110 and using the channel layer 110 as a channel, the mobility of channel carriers in the PMOS region 101 can be improved, so that the required performance of the PMOS region 101 can be achieved.
在一些实施例中，形成沟道层110的方法可以是在PMOS区101和NMOS区103的表面形成初始沟道层，通过刻蚀NMOS区103表面的初始沟道层，保留位于PMOS区101的初始沟道层作为沟道层110。In some embodiments, the method of forming the channel layer 110 may be to form an initial channel layer on the surfaces of the PMOS region 101 and the NMOS region 103, and by etching the initial channel layer on the surface of the NMOS region 103, leaving the The initial channel layer serves as channel layer 110 .
在一些实施例中，沟道层110的材料可以是锗化硅等。In some embodiments, the material of the channel layer 110 may be silicon germanium or the like.
继续参考图1，形成栅介质层120，栅介质层120位于沟道层110的表面。Continuing to refer to FIG. 1 , a gate dielectric layer 120 is formed, and the gate dielectric layer 120 is located on the surface of the channel layer 110 .
在一些实施例中，栅介质层120还位于NMOS区103的衬底100表面。In some embodiments, the gate dielectric layer 120 is also located on the surface of the substrate 100 in the NMOS region 103 .
在一些实施例中，可以通过原位水气生成(ISSG In-Situ Steam Generation)的方式形成将部分沟道层110和NMOS区103的衬底100转化为栅介质层120，在另一些实施例中，还可以通过原子沉积的方式在沟道层110和NMOS区103的衬底100表面形成栅介质层120，通过原位水气生成的方式可以提高形成栅介质层120的致密性，通过原子沉积的方式可以提高栅介质层120的均匀性。在一些实施例中，可以在同一步中形成NMOS区103和PMOS区101的栅介质层120。In some embodiments, part of the channel layer 110 and the substrate 103 of the NMOS region 103 can be converted into the gate dielectric layer 120 by means of in-situ steam generation (ISSG In-Situ Steam Generation). In other embodiments, In addition, the gate dielectric layer 120 can also be formed on the surface of the substrate 100 of the channel layer 110 and the NMOS region 103 by atomic deposition. The density of the gate dielectric layer 120 can be improved by in-situ water vapor generation. The deposition method can improve the uniformity of the gate dielectric layer 120 . In some embodiments, the gate dielectric layer 120 of the NMOS region 103 and the PMOS region 101 may be formed in the same step.
参考图2，图2为PMOS区101的结构示意图，形成隔离层130，隔离层130包括：第一隔离层131；第二隔离层132，第二隔离层132位于第一隔离层131的底部和侧壁；第三隔离层133，第三隔离层133位于第二隔离层132的底部和侧壁。Referring to Figure 2, Figure 2 is a schematic structural diagram of the PMOS region 101. An isolation layer 130 is formed. The isolation layer 130 includes: a first isolation layer 131; a second isolation layer 132. The second isolation layer 132 is located at the bottom of the first isolation layer 131 and Sidewall; third isolation layer 133. The third isolation layer 133 is located at the bottom and sidewall of the second isolation layer 132.
第一隔离层131可以用于隔离阵列区内的存储单元，避免存储单元之间的距离过近而相互影响，导致相邻的存储单元相互导通，从而导致半导体结构的性能下降；第二隔离层132用于隔离电路区内电路结构之间的相互影响，避免出现电路结构之间相互连通的情况，从而防止因电路结构连通后的数据紊乱对半导体结构性能造成影响；第三隔离层133可以用于填充半导体结构，从而使得半导体结构的形貌较好，且第三隔离层133可以将相邻有源区之间进行隔离，从而形成一个个分立的有源区。The first isolation layer 131 can be used to isolate the memory cells in the array area to prevent the memory cells from being too close to each other and causing adjacent memory cells to conduct each other, thereby causing the performance of the semiconductor structure to decrease; the second isolation layer The layer 132 is used to isolate the mutual influence between the circuit structures in the circuit area to avoid the interconnection between the circuit structures, thereby preventing the data disorder after the circuit structures are connected from affecting the performance of the semiconductor structure; the third isolation layer 133 can It is used to fill the semiconductor structure so that the morphology of the semiconductor structure is better, and the third isolation layer 133 can isolate adjacent active areas to form separate active areas.
在一些实施例中，第一隔离层131的材料可以与第三隔离层133的材料相同，可以为氧化硅；第二隔离层132的材料可以是氮化硅或者氮氧化硅等。通过形成第一隔离层131、第二隔离层132及第一隔离层131可以形成ONO(Oxide-Nitride-Oxide)结构，即氧化层-氮化层-氧化层结构，通过形成ONO结构可以提供较高的相对介电常数、高的击穿电场及低的漏电特征等。In some embodiments, the material of the first isolation layer 131 may be the same as the material of the third isolation layer 133, which may be silicon oxide; the material of the second isolation layer 132 may be silicon nitride, silicon oxynitride, or the like. By forming the first isolation layer 131, the second isolation layer 132 and the first isolation layer 131, an ONO (Oxide-Nitride-Oxide) structure can be formed, that is, an oxide layer-nitride layer-oxide layer structure. By forming the ONO structure, a better High relative dielectric constant, high breakdown electric field and low leakage characteristics, etc.
继续参考图2，半导体结构的制作方法还包括：形成栅极结构200，栅极结构200位于沟道层110的表面。在一些实施例中，栅极结构200包括栅极140和栅介质层120。Continuing to refer to FIG. 2 , the manufacturing method of the semiconductor structure further includes: forming a gate structure 200 , the gate structure 200 is located on the surface of the channel layer 110 . In some embodiments, the gate structure 200 includes a gate electrode 140 and a gate dielectric layer 120 .
在一些实施例中，形成栅极结构200的步骤包括：形成初始栅介质层，初始栅介质层覆盖初始沟道层的表面；形成初始栅极，初始栅极覆盖初始栅介质层的表面；刻蚀初始栅极、初始栅介质层，剩余所述初始栅极作为栅极140，剩余初始栅介质层作为栅介质层120，栅极140及栅介质层120作为栅极结构200。换句话说，沟道层110覆盖衬底100的整个顶面，沟道层110的长度大于栅极结构200的长度。In some embodiments, the steps of forming the gate structure 200 include: forming an initial gate dielectric layer covering the surface of the initial channel layer; forming an initial gate electrode covering the surface of the initial gate dielectric layer; etching The initial gate electrode and the initial gate dielectric layer are etched, and the remaining initial gate electrode is used as the gate electrode 140 , the remaining initial gate dielectric layer is used as the gate dielectric layer 120 , and the gate electrode 140 and the gate dielectric layer 120 are used as the gate electrode structure 200 . In other words, the channel layer 110 covers the entire top surface of the substrate 100 , and the length of the channel layer 110 is greater than the length of the gate structure 200 .
在一些实施例中，形成栅极结构200的步骤也可以是，形成初始栅极及初始栅介质层 及初始沟道层，初始栅介质层覆盖初始沟道层的表面，初始栅极覆盖初始栅介质层的表面；刻蚀初始栅极、初始栅介质层及初始沟道层，以形成栅极140、栅介质层120及沟道层110，栅极140及栅介质层120作为栅极结构200，剩余初始沟道层作为沟道层110，也就是说沟道层110并未覆盖PMOS区101的衬底100的整个顶面，沟道层110的长度与栅极140的长度相等。In some embodiments, the step of forming the gate structure 200 may also include forming an initial gate electrode, an initial gate dielectric layer, and an initial channel layer. The initial gate dielectric layer covers the surface of the initial channel layer, and the initial gate electrode covers the initial gate layer. The surface of the dielectric layer; etching the initial gate, the initial gate dielectric layer and the initial channel layer to form the gate 140, the gate dielectric layer 120 and the channel layer 110. The gate 140 and the gate dielectric layer 120 serve as the gate structure 200 , the remaining initial channel layer serves as the channel layer 110 , that is to say, the channel layer 110 does not cover the entire top surface of the substrate 100 in the PMOS region 101 , and the length of the channel layer 110 is equal to the length of the gate electrode 140 .
在一些实施例中，栅极140可以是三层结构，包括第一栅极导电层141、第一扩散阻挡层142及第二栅极导电层143，第一栅极导电层141位于栅介质层120的顶面，第一扩散阻挡层142位于第一栅极导电层141的顶面，第二栅极导电层143位于第一扩散阻挡层142的表面。在另一些实施例中，栅极140还可以是单层结构。本公开实施例不对栅极140的具体结构进行限制，可以根据实际情况进行调整。In some embodiments, the gate 140 may have a three-layer structure, including a first gate conductive layer 141, a first diffusion barrier layer 142, and a second gate conductive layer 143. The first gate conductive layer 141 is located in the gate dielectric layer. 120, the first diffusion barrier layer 142 is located on the top surface of the first gate conductive layer 141, and the second gate conductive layer 143 is located on the surface of the first diffusion barrier layer 142. In other embodiments, the gate 140 may also be a single-layer structure. The embodiment of the present disclosure does not limit the specific structure of the gate 140 and can be adjusted according to actual conditions.
在一些实施例中，第一栅极导电层141的材料可以是半导体材料，例如多晶硅等，第一扩散阻挡层142的材料可以是金属与非金属材料的混合物，例如氮化钛，第二栅极导电层143的材料可以是金属材料，例如金属钨等，通过设置第一栅极导电层141可以避免栅极结构200与衬底100之间的材料属性差距太大，避免在信号传递的过程中出现异常，通过设置第一扩散阻挡层142可以避免第二栅极导电层143的金属离子扩散到第一栅极导电层141中，从而避免第一栅极导电层141被污染，从而可以提高半导体结构的可靠性。In some embodiments, the material of the first gate conductive layer 141 may be a semiconductor material, such as polysilicon, and the material of the first diffusion barrier layer 142 may be a mixture of metal and non-metal materials, such as titanium nitride. The material of the extremely conductive layer 143 can be a metal material, such as metal tungsten, etc. By providing the first gate conductive layer 141, it can be avoided that the material property gap between the gate structure 200 and the substrate 100 is too large, and the signal transmission process can be avoided. When an abnormality occurs, by providing the first diffusion barrier layer 142, metal ions in the second gate conductive layer 143 can be prevented from diffusing into the first gate conductive layer 141, thereby preventing the first gate conductive layer 141 from being contaminated, thereby improving the performance of the first gate conductive layer 141. Reliability of Semiconductor Structures.
在一些实施例中在栅极结构200在衬底100表面投影的两侧的部分衬底100可以作为第一掺杂区105及第二掺杂区106，以作为源极及漏极。In some embodiments, parts of the substrate 100 on both sides of the projection of the gate structure 200 on the surface of the substrate 100 may serve as the first doping region 105 and the second doping region 106 to serve as the source and drain.
在一些实施例中，栅极结构200用于控制第一掺杂区105及第二掺杂区106是否导通，理论上来说，当栅极结构200没有电压时，第一掺杂区105及第二掺杂区106之间不会有电流流过，也就是半导体结构处于截止状态，然而在形成栅介质层120的过程中，以沟道层110的材料为锗化硅为例，会在沟道层110表面形成大量的锗-氧键及界面态，导致沟道层110存在大量的漏电路径，增加第一掺杂区105及第二掺杂区106之间的漏电。因此在后续的步骤中通过钝化处理以减少沟道层110表面形成的锗-氧键及界面态，从而降低第一掺杂区105及第二掺杂区106之间的漏电。In some embodiments, the gate structure 200 is used to control whether the first doped region 105 and the second doped region 106 are conductive. Theoretically, when the gate structure 200 has no voltage, the first doped region 105 and the second doped region 106 are conductive. No current will flow between the second doped regions 106, that is, the semiconductor structure is in a cut-off state. However, during the process of forming the gate dielectric layer 120, assuming that the material of the channel layer 110 is silicon germanium, for example, A large number of germanium-oxygen bonds and interface states are formed on the surface of the channel layer 110 , resulting in a large number of leakage paths in the channel layer 110 and increasing the leakage between the first doped region 105 and the second doped region 106 . Therefore, passivation treatment is performed in subsequent steps to reduce the germanium-oxygen bonds and interface states formed on the surface of the channel layer 110, thereby reducing leakage between the first doped region 105 and the second doped region 106.
在一些实施例中，还包括：形成保护层150，保护层150覆盖栅极结构200的表面以及沟道层110的部分表面，通过形成保护层150可以将栅极结构200与外界结构进行隔离，从而可以避免栅极结构200与外界进行接触，从而可以避免栅极结构200与空气接触，可以避免栅极结构200被氧化，可以提高半导体结构的可靠性，且通过形成保护层150还可以在 半导体结构受到外界的应力作用时通过保护层150吸收部分应力作用，从而可以降低栅极结构200上受到的应力大小，可以提高半导体结构的可靠性。In some embodiments, it also includes: forming a protective layer 150. The protective layer 150 covers the surface of the gate structure 200 and part of the surface of the channel layer 110. The gate structure 200 can be isolated from external structures by forming the protective layer 150. Therefore, the gate structure 200 can be prevented from contacting the outside world, the gate structure 200 can be prevented from being in contact with air, the gate structure 200 can be prevented from being oxidized, the reliability of the semiconductor structure can be improved, and the protective layer 150 can also be formed in the semiconductor. When the structure is subjected to external stress, the protective layer 150 absorbs part of the stress, thereby reducing the stress on the gate structure 200 and improving the reliability of the semiconductor structure.
在一些实施例中，保护层150可以包括第一保护层151；第二保护层152，第二保护层152位于第一保护层的侧壁；第三保护层153，第三保护层153位于第二保护层152的侧壁。第一保护层151和第三保护层153的材料可以相同。In some embodiments, the protective layer 150 may include a first protective layer 151; a second protective layer 152 located on the sidewall of the first protective layer; and a third protective layer 153 located on the sidewall of the first protective layer. The side walls of the second protective layer 152. The materials of the first protective layer 151 and the third protective layer 153 may be the same.
在一些实施例中，第一保护层151的材料可以与第三保护层153的材料可以是氮化硅，第二保护层152的材料可以是氧化硅，以使保护层150形成NON(Nitride-Oxide-Nitride)结构即氮化层-氧化层-氮化层结构，通过设置第二保护层152可以提高第一保护层151与第三保护层153之间的绝缘性能，由于第二保护层152的材质较软，形成的形貌较差，故通过形成材质为氮化层的第一保护层151与第三保护层153以提高形成第二保护层152的形貌。In some embodiments, the material of the first protective layer 151 and the third protective layer 153 may be silicon nitride, and the material of the second protective layer 152 may be silicon oxide, so that the protective layer 150 forms NON (Nitride- Oxide-Nitride) structure, that is, nitride layer-oxide layer-nitride layer structure, by providing the second protective layer 152, the insulation performance between the first protective layer 151 and the third protective layer 153 can be improved. Since the second protective layer 152 The material is soft and the morphology is poor. Therefore, the first protective layer 151 and the third protective layer 153 made of nitride layers are formed to improve the morphology of the second protective layer 152 .
在一些实施例中，在形成保护层150之后，采用氢离子对沟道层110进行钝化处理，以沟道层110的材料为锗化硅为例，沟道层110与栅极140之间还会包括栅介质层120，栅介质层120与沟道层110之间形成的锗氧化学键会造成沟道层110内存在大量的漏电路径，导致在PMOS区101上形成的PMOS管的源极和漏极之间出现漏电，通过钝化处理将栅介质层120与沟道层110之间形成的锗氧化学键进行破坏，从而可以降低PMOS区101上形成的PMOS管的源极和漏极之间漏电。In some embodiments, after the protective layer 150 is formed, the channel layer 110 is passivated using hydrogen ions. Taking the material of the channel layer 110 as silicon germanium as an example, the gap between the channel layer 110 and the gate electrode 140 It also includes a gate dielectric layer 120. The germanium oxide chemical bond formed between the gate dielectric layer 120 and the channel layer 110 will cause a large number of leakage paths in the channel layer 110, resulting in the source of the PMOS tube formed on the PMOS region 101. Leakage occurs between the gate dielectric layer 120 and the channel layer 110 through passivation treatment to destroy the germanium oxide chemical bond formed between the gate dielectric layer 120 and the channel layer 110, thereby reducing the source and drain resistance of the PMOS tube formed on the PMOS region 101. Leakage in the room.
通过在PMOS区101形成沟道层110以满足PMOS区101所需的性能要求，通过设置沟道层110作为PMOS区101的沟道层110，从而可以提高半导体结构的载流子的迁移率，通过钝化处理可以改善沟道层110表面的界面态，从而可以降低半导体结构的漏电。By forming the channel layer 110 in the PMOS region 101 to meet the required performance requirements of the PMOS region 101, and by providing the channel layer 110 as the channel layer 110 of the PMOS region 101, the carrier mobility of the semiconductor structure can be improved, The passivation treatment can improve the interface state on the surface of the channel layer 110, thereby reducing the leakage of the semiconductor structure.
在一些实施例中，形成栅极结构200和保护层150的步骤包括：形成栅极结构200，栅极结构200位于沟道层110的表面；形成保护层150，保护层150覆盖沟道层110的表面及栅极结构200的侧壁及顶面，换句话说，也就是先形成栅极结构200，后形成保护层150，也就是先栅工艺，通过先形成栅极结构200，后形成保护层150可以降低半导体结构的制作方法的工艺难度。In some embodiments, the steps of forming the gate structure 200 and the protective layer 150 include: forming the gate structure 200, which is located on the surface of the channel layer 110; forming the protective layer 150, which covers the channel layer 110 surface and the sidewalls and top surface of the gate structure 200. In other words, the gate structure 200 is formed first, and then the protective layer 150 is formed. This is also a gate-first process. The gate structure 200 is formed first, and then the protective layer 150 is formed. Layer 150 can reduce the process difficulty of the manufacturing method of the semiconductor structure.
在一些实施例中，形成栅极结构200和保护层150的步骤包括：形成初始保护层，初始保护层覆盖沟道层110的表面；刻蚀初始保护层，以形成沟槽，沟槽暴露沟道层110的表面；形成栅极结构200，栅极结构200位于所述沟槽内；形成盖层，盖层与剩余初始保护层构成保护层150，换句话说，也就是先形成部分保护层150，后形成栅极结构200，也就是后栅工艺，通过先形成部分保护层150后形成栅极结构200可以提高形成的栅极结构的性能。In some embodiments, the steps of forming the gate structure 200 and the protective layer 150 include: forming an initial protective layer to cover the surface of the channel layer 110; etching the initial protective layer to form a trench, and the trench exposes the trench. on the surface of the channel layer 110; a gate structure 200 is formed, and the gate structure 200 is located in the trench; a cover layer is formed, and the cover layer and the remaining initial protective layer constitute the protective layer 150. In other words, a part of the protective layer is formed first. 150, and then the gate structure 200 is formed, which is a gate-last process. By first forming part of the protective layer 150 and then forming the gate structure 200, the performance of the formed gate structure can be improved.
在一些实施例中，进行所述钝化处理之前，还包括：形成绝缘层160，绝缘层160位于衬底100表面，且绝缘层160覆盖保护层150的侧壁。通过形成绝缘层160为后续形成第一导线层190提供支撑。In some embodiments, before performing the passivation process, it further includes: forming an insulating layer 160 , the insulating layer 160 is located on the surface of the substrate 100 , and the insulating layer 160 covers the sidewalls of the protective layer 150 . The formation of the insulating layer 160 provides support for the subsequent formation of the first conductive layer 190 .
在一些实施例中，形成绝缘层160之后还包括：形成支撑层170，支撑层170位于绝缘层160的顶面，且支撑层170位于保护层150的顶面。In some embodiments, forming the insulating layer 160 further includes: forming a support layer 170 , the support layer 170 is located on the top surface of the insulating layer 160 , and the support layer 170 is located on the top surface of the protective layer 150 .
在一些实施例中，绝缘层160的材料可以是氧化硅，支撑层170的材料可以是氮化硅，氮化硅的材料较硬，从而可以起到较好的支撑效果，可以避免在支撑层170表面形成的第一导线层190出现变形。In some embodiments, the material of the insulating layer 160 can be silicon oxide, and the material of the supporting layer 170 can be silicon nitride. The material of silicon nitride is relatively hard, so it can have a better supporting effect, and can avoid the problem of insulating the supporting layer. The first conductor layer 190 formed on the surface of 170 is deformed.
在一些实施例中，还可以包括：形成第一导电柱180，第一导电柱180贯穿绝缘层160以与PMOS区101的衬底100连接或第一导电柱180贯穿绝缘层160以及保护层150以与栅极结构200连接。通过形成第一导电柱180可以将第一掺杂区105及第二掺杂区106的电信号导出，或者可以将栅极结构200的信号引出，或者向栅极结构200提供电信号。In some embodiments, it may also include: forming a first conductive pillar 180 penetrating the insulating layer 160 to connect with the substrate 100 of the PMOS region 101 or the first conductive pillar 180 penetrating the insulating layer 160 and the protective layer 150 to connect with the gate structure 200 . By forming the first conductive pillar 180 , electrical signals from the first doped region 105 and the second doped region 106 can be derived, or signals from the gate structure 200 can be derived, or electrical signals can be provided to the gate structure 200 .
在一些实施例中，形成第一导电柱180的方法可以是：通过掩膜刻蚀的方式刻蚀绝缘层160及支撑层170以形成凹槽，凹槽贯穿绝缘层160以暴露PMOS区101衬底100的表面或凹槽贯穿绝缘层160以及保护层150以暴露栅极结构200的顶面；形成导电接触层181，导电接触层181位于凹槽的底面；形成扩散阻挡层182，扩散阻挡层182位于凹槽的内壁和导电接触层181的表面；形成导电插塞层183，导电插塞层183填充满凹槽。In some embodiments, the method of forming the first conductive pillar 180 may be: etching the insulating layer 160 and the support layer 170 through mask etching to form a groove, and the groove penetrates the insulating layer 160 to expose the PMOS region 101 lining. The surface or groove of the bottom 100 penetrates the insulating layer 160 and the protective layer 150 to expose the top surface of the gate structure 200; a conductive contact layer 181 is formed, and the conductive contact layer 181 is located on the bottom surface of the groove; a diffusion barrier layer 182 is formed, the diffusion barrier layer 182 is located on the inner wall of the groove and the surface of the conductive contact layer 181; a conductive plug layer 183 is formed, and the conductive plug layer 183 fills the groove.
在一些实施例中，导电接触层181可以用于第一导电柱180与衬底100接触的时候避免第一导电柱180的材料属性与衬底100的材料属性之间差距太大，避免第一导电柱180与衬底100之间进行信号传递的时候出现异常；扩散阻挡层182可以用于将导电接触层181与导电插塞层183进行隔离，从而避免导电插塞层183的金属离子扩散至导电接触层181内，影响导电接触层181的传输；导电插塞层183用于提高第一导电柱180的传输速度，减低半导体结构的响应时间，提高半导体结构的性能。In some embodiments, the conductive contact layer 181 can be used to avoid a too large gap between the material properties of the first conductive pillar 180 and the material properties of the substrate 100 when the first conductive pillar 180 contacts the substrate 100, thereby avoiding the first An abnormality occurs during signal transmission between the conductive pillar 180 and the substrate 100; the diffusion barrier layer 182 can be used to isolate the conductive contact layer 181 from the conductive plug layer 183, thereby preventing the metal ions of the conductive plug layer 183 from diffusing to The conductive contact layer 181 affects the transmission of the conductive contact layer 181; the conductive plug layer 183 is used to increase the transmission speed of the first conductive pillar 180, reduce the response time of the semiconductor structure, and improve the performance of the semiconductor structure.
在一些实施例中，形成导电接触层181的方法包括：形成接触材料层(图中未示出)，接触材料层位于凹槽的底面所暴露出的衬底100表面或栅极结构200顶面；采用快速热退火的方式工艺使衬底100或栅极结构200与接触材料层反应形成导电接触层181。换句话说，可以采用金属氧化物工艺形成导电接触层181，形成的导电接触层181与衬底100之间的接触电阻比较低，可以提高半导体结构的性能，形成导电接触层181之后还包括：去除接触材料层。In some embodiments, the method of forming the conductive contact layer 181 includes: forming a contact material layer (not shown in the figure), the contact material layer is located on the surface of the substrate 100 exposed by the bottom surface of the groove or the top surface of the gate structure 200 ; Use a rapid thermal annealing process to react the substrate 100 or the gate structure 200 with the contact material layer to form the conductive contact layer 181. In other words, the conductive contact layer 181 can be formed using a metal oxide process. The contact resistance between the formed conductive contact layer 181 and the substrate 100 is relatively low, which can improve the performance of the semiconductor structure. After forming the conductive contact layer 181, it also includes: Remove the layer of contact material.
在一些实施例中，凹槽位于衬底100内，形成的导电接触层181、部分扩散阻挡层182及部分导电插塞层183位于衬底100内；在另一些实施例中，凹槽位于衬底100的表面，形成的导电接触层181位于衬底100内，扩散阻挡层182及导电插塞层183位于衬底100表面。In some embodiments, the groove is located in the substrate 100, and the formed conductive contact layer 181, part of the diffusion barrier layer 182 and part of the conductive plug layer 183 is located in the substrate 100; in other embodiments, the groove is located in the substrate 100. On the surface of the bottom 100 , the conductive contact layer 181 formed is located in the substrate 100 , and the diffusion barrier layer 182 and the conductive plug layer 183 are located on the surface of the substrate 100 .
在一些实施例中，进行钝化处理之前，还包括：形成第一导线层190，第一导线层190位于绝缘层160的表面，且第一导线层190与第一导电柱180的顶面接触连接。第一导线层190可以用于半导体结构的布线，也就是说，可以通过第一导线层190将半导体结构内部的结构与外界的电信号连通，例如将第一掺杂区105与第一导线层190连通，再向第一导线层190输入第一掺杂区105所需的电信号，从而可以实现向第一掺杂区105输入所需的电信号。In some embodiments, before performing the passivation treatment, it further includes: forming a first conductive layer 190 , the first conductive layer 190 is located on the surface of the insulating layer 160 , and the first conductive layer 190 is in contact with the top surface of the first conductive pillar 180 connect. The first conductor layer 190 can be used for wiring of the semiconductor structure. That is to say, the structure inside the semiconductor structure can be connected to external electrical signals through the first conductor layer 190 , for example, the first doped region 105 and the first conductor layer can be connected. 190 is connected, and then the electrical signal required by the first doping region 105 is input to the first conductor layer 190, so that the required electrical signal can be input to the first doping region 105.
在一些实施例中，钝化处理包括：向沟道层110通入含氢钝化气体，含氢钝化气体包括：氢气或者氢气与惰性气体的混合气体，通过氢键钝化沟道层110表面的锗-氧键，从而降低沟道层110表面的界面态，且通过氢气钝化沟道层110表面后还会在沟道层110表面形成带有氢键的膜层，通过形成含有氢键的膜层还可以提高沟道层110与衬底100的连接的紧密性。In some embodiments, the passivation treatment includes: passing a hydrogen-containing passivation gas into the channel layer 110, the hydrogen-containing passivation gas includes: hydrogen or a mixed gas of hydrogen and an inert gas, passivating the channel layer 110 through hydrogen bonding. The germanium-oxygen bond on the surface reduces the interface state on the surface of the channel layer 110, and after the surface of the channel layer 110 is passivated by hydrogen gas, a film layer with hydrogen bonds will be formed on the surface of the channel layer 110. By forming a hydrogen-containing film layer, The bonding film layer can also improve the tightness of the connection between the channel layer 110 and the substrate 100 .
在一些实施例中，可以在形成保护层150之后，形成绝缘层160之前对半导体结构进行钝化处理，在形成保护层150之后再对半导体结构进行钝化处理可以避免栅极结构200被钝化，从而可以避免影响栅极结构200性能。在另一些实施例中，还可以在形成第一导线层190之后再进行钝化处理，此时，钝化处理通入的含氢钝化气体可以通过第一导电柱180与绝缘层160及支撑层170之间的连接缝隙流向沟道层110的表面，从而与沟道层110表面的锗-氧键发生反应，进而破坏沟道层110表面的锗-氧键，减小沟道层110表面的界面态，从而减少沟道层110内的漏电路径，减低半导体结构的漏电的可能性。In some embodiments, the semiconductor structure may be passivated after the protective layer 150 is formed and before the insulating layer 160 is formed. Passivating the semiconductor structure after the protective layer 150 is formed may prevent the gate structure 200 from being passivated. , thereby avoiding affecting the performance of the gate structure 200 . In other embodiments, the passivation process can also be performed after the first conductive layer 190 is formed. At this time, the hydrogen-containing passivation gas introduced in the passivation process can pass through the first conductive pillar 180, the insulating layer 160 and the support. The connection gap between the layers 170 flows to the surface of the channel layer 110, thereby reacting with the germanium-oxygen bonds on the surface of the channel layer 110, thereby destroying the germanium-oxygen bonds on the surface of the channel layer 110, and reducing the surface area of the channel layer 110. interface state, thereby reducing the leakage path in the channel layer 110 and reducing the possibility of leakage of the semiconductor structure.
在一些实施例中，钝化处理还包括：对第一导线层190及第一导电柱180朝向绝缘层160的侧壁进行钝化处理，通过钝化处理还可以修复第一导电柱180的表面，改善第一导线层190及第一导电柱180与绝缘层160的连接效果，从而还可以使第一导线层190及第一导电柱180与绝缘层160连接的更紧密。In some embodiments, the passivation process also includes: passivating the sidewalls of the first conductive layer 190 and the first conductive pillar 180 facing the insulating layer 160 , and the surface of the first conductive pillar 180 can also be repaired through the passivation process. , to improve the connection effect between the first conductive layer 190 and the first conductive pillar 180 and the insulating layer 160, so that the first conductive layer 190 and the first conductive pillar 180 and the insulating layer 160 can be connected more closely.
在一些实施例中，钝化处理通入的含氢钝化气体的气流量为3.5L/min～6.5L/min，例如是4L/min或者5L/min等，可以理解的是，钝化处理通入的含氢钝化气体的气流量越小，破坏锗-氧键的能力也就越差，也就是说，当钝化处理通入的含氢钝化气体的气流量小于3.5L/min时，钝化处理的钝化效果不好，改善半导体结构的漏电的效果不佳，钝化处理通入的含氢钝化气体的气流量越大，钝化效果较好但是可能会出现过钝化的现象，也就是说，当 钝化处理通入的含氢钝化气体的气流量大于6.5L/min时，可能导致不需要被钝化的部分被钝化，例如栅极结构200被钝化，导致栅极结构200的性能下降。In some embodiments, the gas flow rate of the hydrogen-containing passivation gas introduced into the passivation process is 3.5L/min to 6.5L/min, such as 4L/min or 5L/min. It can be understood that the passivation process The smaller the gas flow rate of the hydrogen-containing passivation gas introduced, the worse the ability to destroy germanium-oxygen bonds. That is to say, when the gas flow rate of the hydrogen-containing passivation gas introduced during the passivation process is less than 3.5L/min At this time, the passivation effect of the passivation treatment is not good, and the effect of improving the leakage of the semiconductor structure is not good. The greater the gas flow rate of the hydrogen-containing passivation gas introduced into the passivation treatment, the better the passivation effect, but over-passivation may occur. The phenomenon of passivation, that is to say, when the gas flow rate of the hydrogen-containing passivation gas introduced in the passivation process is greater than 6.5L/min, it may cause the parts that do not need to be passivated to be passivated, such as the gate structure 200 being passivated. ation, causing the performance of the gate structure 200 to degrade.
在一些实施例中，钝化处理的时长为21min～39min，例如是25min或者30min等，钝化处理的时长越短，相应的，破坏锗-氧键的能力也就越差，也就是说，当钝化处理的时长小于21min时，钝化处理的钝化效果不好，改善半导体结构的漏电的效果不佳，钝化处理的时长越长，虽然钝化效果更好了但是可能会出现过钝化的现象，也就是说，当钝化处理的时长大于39min，可能导致不需要被钝化的部分被钝化，例如栅极结构200被钝化，导致栅极结构200的性能下降。In some embodiments, the duration of the passivation treatment is 21 minutes to 39 minutes, such as 25 minutes or 30 minutes. The shorter the duration of the passivation treatment, the correspondingly poorer the ability to destroy germanium-oxygen bonds. That is to say, When the passivation treatment time is less than 21 minutes, the passivation effect of the passivation treatment is not good, and the effect of improving the leakage of the semiconductor structure is not good. The longer the passivation treatment time, although the passivation effect is better, there may be excessive The passivation phenomenon, that is, when the passivation treatment lasts longer than 39 minutes, may cause parts that do not need to be passivated to be passivated, such as the gate structure 200 being passivated, resulting in a decrease in the performance of the gate structure 200 .
在一些实施例中，钝化处理的温度为310～530℃，例如是350℃、400℃或者450℃等，当钝化处理的温度小于310℃时，氢气和沟道层110反应不彻底从而导致钝化处理的钝化效果不佳，当钝化处理的温度大于530℃时，可能会影响其他已经形成好的结构，例如影响栅极结构200，从而可能导致栅极结构200的性能下降。In some embodiments, the temperature of the passivation treatment is 310-530°C, such as 350°C, 400°C, or 450°C. When the temperature of the passivation treatment is less than 310°C, the reaction between the hydrogen gas and the channel layer 110 is incomplete and thus As a result, the passivation effect of the passivation treatment is poor. When the temperature of the passivation treatment is greater than 530° C., it may affect other formed structures, such as the gate structure 200 , which may cause the performance of the gate structure 200 to decrease.
本公开实施例通过提供一种半导体结构的制作方法，通过在PMOS区101的衬底100表面形成沟道层110之后，在沟道层110表面形成栅极结构200及保护层150之后，采用氢离子对沟道层110进行钝化处理，以减小沟道层110表面的界面态，从而减少沟道层110的漏电路径，提高半导体结构的可靠性。The embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. After forming the channel layer 110 on the surface of the substrate 100 in the PMOS region 101, and then forming the gate structure 200 and the protective layer 150 on the surface of the channel layer 110, hydrogen is used. The channel layer 110 is passivated by ions to reduce the interface state on the surface of the channel layer 110, thereby reducing the leakage path of the channel layer 110 and improving the reliability of the semiconductor structure.
本公开另一实施例还提供一种半导体结构，可以采用上述半导体结构的制作方法的全部或者部分步骤形成，以下将结合附图对半导体结构进行说明，相同或者相应的部分可以参考上述实施例，以下将不再赘述。Another embodiment of the present disclosure also provides a semiconductor structure, which can be formed by using all or part of the steps of the above-mentioned manufacturing method of the semiconductor structure. The semiconductor structure will be described below with reference to the accompanying drawings. The same or corresponding parts can refer to the above-mentioned embodiments. No further details will be given below.
参考图1及图2，半导体结构包括：衬底100，衬底100包括PMOS区101；沟道层110，沟道层110位于PMOS区101的衬底100表面，沟道层110的表面形成有氢键；栅极结构200，栅极结构200位于沟道层110的表面；保护层150，保护层150覆盖栅极结构200的顶面及侧壁，且保护层150还覆盖沟道层110的至少部分表面。通过在沟道层110表面的氢键从而可以减少沟道层110表面的界面态，从而减少沟道层110的漏电。Referring to Figures 1 and 2, the semiconductor structure includes: a substrate 100, which includes a PMOS region 101; a channel layer 110, which is located on the surface of the substrate 100 in the PMOS region 101, and is formed on the surface of the channel layer 110. Hydrogen bonding; gate structure 200, the gate structure 200 is located on the surface of the channel layer 110; protective layer 150, the protective layer 150 covers the top surface and side walls of the gate structure 200, and the protective layer 150 also covers the channel layer 110 At least part of the surface. Through the hydrogen bonding on the surface of the channel layer 110, the interface state on the surface of the channel layer 110 can be reduced, thereby reducing the leakage of the channel layer 110.
在一些实施例中，衬底100还包括：NMOS区103，NMOS区103用于形成NMOS管。In some embodiments, the substrate 100 further includes: an NMOS region 103, and the NMOS region 103 is used to form an NMOS tube.
在一些实施例中，沟道层110的厚度可以为2～10nm，例如是5nm、6nm、7nm或者8nm等，当沟道层110的厚度大于10nm时，可能导致晶格错位的几率增加，导致半导体结构的性能下降，当沟道层110的厚度小于2nm时，沟道层110内的载流子的数量较少，且作 为半导体结构的沟道的宽度较窄，影响半导体结构载流子的传输速率，影响半导体结构的性能。In some embodiments, the thickness of the channel layer 110 may be 2 to 10 nm, such as 5 nm, 6 nm, 7 nm, or 8 nm. When the thickness of the channel layer 110 is greater than 10 nm, the probability of lattice dislocation may increase, resulting in The performance of the semiconductor structure decreases. When the thickness of the channel layer 110 is less than 2 nm, the number of carriers in the channel layer 110 is small, and the width of the channel as a semiconductor structure is narrow, which affects the carriers of the semiconductor structure. The transmission rate affects the performance of semiconductor structures.
在一些实施例中，半导体结构还包括：隔离层130，隔离层130可以包括：第一隔离层131；第二隔离层132，第二隔离层132位于第一隔离层131的底部和侧壁；第三隔离层133，第三隔离层133位于第二隔离层的底部和侧壁，第一隔离层131可以用于隔离阵列区内的存储单元，避免存储单元之间的距离过近而相互影响，导致相邻的存储单元相互导通，从而导致半导体结构的性能下降；第二隔离层132用于隔离电路区内电路结构之间的相互影响，避免出现电路结构之间相互连通的情况，从而防止因电路结构连通后的数据紊乱对半导体结构性能造成影响；第三隔离层133可以用于填充半导体结构，从而使得半导体结构的形貌较好，且第三隔离层133可以将相邻有源区之间进行隔离，从而形成一个个分立的有源区。In some embodiments, the semiconductor structure further includes: an isolation layer 130. The isolation layer 130 may include: a first isolation layer 131; a second isolation layer 132 located on the bottom and sidewalls of the first isolation layer 131; The third isolation layer 133 is located at the bottom and side walls of the second isolation layer. The first isolation layer 131 can be used to isolate the memory cells in the array area to prevent the memory cells from being too close to each other and affecting each other. , causing adjacent memory cells to be connected to each other, resulting in a decrease in the performance of the semiconductor structure; the second isolation layer 132 is used to isolate the mutual influence between the circuit structures in the circuit area, to avoid the interconnection between the circuit structures, thereby Prevent data disorder after the circuit structure is connected from affecting the performance of the semiconductor structure; the third isolation layer 133 can be used to fill the semiconductor structure, thereby making the morphology of the semiconductor structure better, and the third isolation layer 133 can separate adjacent active The areas are isolated to form separate active areas.
在一些实施例中，栅极结构200包括：栅极140及栅介质层120，栅极140用于控制沟道层110的导通，栅介质层120用于避免栅极140与沟道层110直接接触。In some embodiments, the gate structure 200 includes: a gate electrode 140 and a gate dielectric layer 120. The gate electrode 140 is used to control the conduction of the channel layer 110. The gate dielectric layer 120 is used to prevent the gate electrode 140 from contacting the channel layer 110. direct contact.
在一些实施例中，栅极140可以是三层结构，包括第一栅极导电层141、第一扩散阻挡层142及第二栅极导电层143，第一栅极导电层141位于栅介质层120的顶面，第一扩散阻挡层142位于第一栅极导电层141的顶面，第二栅极导电层143位于第一扩散阻挡层142的表面。在另一些实施例中，栅极140还可以是单层结构。本公开实施例不对栅极140的具体结构进行限制，可以根据实际情况进行调整。In some embodiments, the gate 140 may have a three-layer structure, including a first gate conductive layer 141, a first diffusion barrier layer 142, and a second gate conductive layer 143. The first gate conductive layer 141 is located in the gate dielectric layer. 120, the first diffusion barrier layer 142 is located on the top surface of the first gate conductive layer 141, and the second gate conductive layer 143 is located on the surface of the first diffusion barrier layer 142. In other embodiments, the gate 140 may also be a single-layer structure. The embodiment of the present disclosure does not limit the specific structure of the gate 140 and can be adjusted according to actual conditions.
在一些实施例中，在栅极结构200在衬底100表面投影的两侧的部分衬底100可以作为第一掺杂区105及第二掺杂区106，以作为源极及漏极。In some embodiments, parts of the substrate 100 on both sides of the projection of the gate structure 200 on the surface of the substrate 100 may serve as the first doping region 105 and the second doping region 106 to serve as the source and drain.
在一些实施例中，保护层150可以包括第一保护层151；第二保护层152，第二保护层152位于第一保护层的侧壁；第三保护层153，第三保护层153位于第二保护层152的侧壁。第一保护层151和第三保护层153的材料可以相同，通过设置保护层150的结构为NON(Nitride-Oxide-Nitride)结构即氮化层-氧化层-氮化层结构，通过设置第二保护层152可以提高第一保护层151与第三保护层153之间的绝缘性能，由于第二保护层152的材质较软，形成的形貌较差，故通过形成材质为氮化层的第一保护层151与第三保护层153以提高形成第二保护层152的形貌。In some embodiments, the protective layer 150 may include a first protective layer 151; a second protective layer 152 located on the sidewall of the first protective layer; and a third protective layer 153 located on the sidewall of the first protective layer. The side walls of the second protective layer 152. The first protective layer 151 and the third protective layer 153 can be made of the same material. By setting the structure of the protective layer 150 to a NON (Nitride-Oxide-Nitride) structure, that is, a nitride layer-oxide layer-nitride layer structure, the second protective layer 150 can be made of the same material. The protective layer 152 can improve the insulation performance between the first protective layer 151 and the third protective layer 153. Since the material of the second protective layer 152 is softer and has a poor morphology, the second protective layer 152 is made of a nitride layer. A protective layer 151 and a third protective layer 153 are used to improve the topography of the second protective layer 152.
在一些实施例中，还包括：绝缘层160，绝缘层160位于衬底100表面，且绝缘层160覆盖保护层150的侧壁；第一导电柱180，第一导电柱180贯穿绝缘层160与PMOS区101的衬底100连接或第一导电柱180贯穿绝缘层160以及保护层150以与栅极结构200连接。 通过绝缘层160可以支撑第一导电柱180的侧壁，且还可以支撑第一导线层190，当第一导电柱180与PMOS区101的衬底100连接时，通过第一导电柱180可以将半导体结构的第一掺杂区105及第二掺杂区106的电信号引出，或者向第一掺杂区105及第二掺杂区106提供电信号；当第一导电柱180与栅极结构200连接时，通过第一导电柱180可以将栅极结构200的电信号引出或者想栅极结构200提供电信号。In some embodiments, it also includes: an insulating layer 160 located on the surface of the substrate 100 and covering the sidewalls of the protective layer 150; a first conductive pillar 180 penetrating the insulating layer 160 and The substrate 100 of the PMOS region 101 is connected or the first conductive pillar 180 penetrates the insulating layer 160 and the protective layer 150 to connect with the gate structure 200 . The insulating layer 160 can support the sidewalls of the first conductive pillar 180 and can also support the first conductive line layer 190. When the first conductive pillar 180 is connected to the substrate 100 of the PMOS region 101, the first conductive pillar 180 can Electrical signals are extracted from the first doped region 105 and the second doped region 106 of the semiconductor structure, or electrical signals are provided to the first doped region 105 and the second doped region 106; when the first conductive pillar 180 and the gate structure 200 is connected, the electrical signal of the gate structure 200 can be extracted through the first conductive pillar 180 or the electrical signal can be provided to the gate structure 200 .
在一些实施例中，第一导电柱180包括：导电接触层181，导电接触层181位于PMOS区101的衬底100内或栅极结构200顶面；扩散阻挡层182，扩散阻挡层182的底面与导电接触层181的顶面接触，扩散阻挡层182还包括环绕扩散阻挡层182底面的侧面，扩散阻挡层182的底面与侧面围成容纳空间；导电插塞层183，导电插塞层183位于扩散阻挡层182的表面，且填充满容纳空间。也就是说，当第一导电柱180与衬底100连接时，导电接触层181位于PMOS区101的衬底100内，当第一导电柱180与栅极结构200连接时，导电接触层181位于栅极结构200的顶面，导电接触层181可以用于避免第一导电柱180与衬底100接触的时候避免第一导电柱180的材料与衬底100的材料之间差距太大，避免第一导电柱180与衬底100之间进行信号传递的时候出现异常；扩散阻挡层182可以用于将导电接触层181与导电插塞层183进行隔离，从而避免导电插塞层183的金属离子扩散至导电接触层181内，影响导电接触层181的传输；导电插塞层183用于提高第一导电柱180的传输速度，减低半导体结构的响应时间，提高半导体结构的性能。In some embodiments, the first conductive pillar 180 includes: a conductive contact layer 181 located in the substrate 100 of the PMOS region 101 or on the top surface of the gate structure 200; a diffusion barrier layer 182 on the bottom surface of the diffusion barrier layer 182 In contact with the top surface of the conductive contact layer 181, the diffusion barrier layer 182 also includes side surfaces surrounding the bottom surface of the diffusion barrier layer 182. The bottom surface and side surfaces of the diffusion barrier layer 182 form an accommodation space; a conductive plug layer 183, which is located The surface of the diffusion barrier layer 182 is filled with the accommodation space. That is to say, when the first conductive pillar 180 is connected to the substrate 100, the conductive contact layer 181 is located in the substrate 100 of the PMOS region 101. When the first conductive pillar 180 is connected to the gate structure 200, the conductive contact layer 181 is located in the substrate 100. On the top surface of the gate structure 200, the conductive contact layer 181 can be used to avoid the gap between the material of the first conductive pillar 180 and the material of the substrate 100 being too large when the first conductive pillar 180 is in contact with the substrate 100, thereby preventing the second conductive pillar 180 from being in contact with the substrate 100. An abnormality occurs during signal transmission between a conductive pillar 180 and the substrate 100; the diffusion barrier layer 182 can be used to isolate the conductive contact layer 181 from the conductive plug layer 183, thereby avoiding the diffusion of metal ions in the conductive plug layer 183. into the conductive contact layer 181 to affect the transmission of the conductive contact layer 181; the conductive plug layer 183 is used to increase the transmission speed of the first conductive pillar 180, reduce the response time of the semiconductor structure, and improve the performance of the semiconductor structure.
在一些实施例中，至少部分导电插塞层183还可以位于PMOS区101的衬底100内，也就是说，导电插塞层183的底面低于衬底100的顶面，通过设置导电插塞层183位于PMOS区101的衬底100内可以提高第一导电柱180与衬底100连接的可靠性，且还可以提高第一导电柱180与衬底100的接触面积，降低第一导电柱180与衬底100的接触电阻。In some embodiments, at least part of the conductive plug layer 183 may also be located within the substrate 100 of the PMOS region 101 , that is, the bottom surface of the conductive plug layer 183 is lower than the top surface of the substrate 100 . By providing the conductive plug The layer 183 located in the substrate 100 of the PMOS region 101 can improve the reliability of the connection between the first conductive pillar 180 and the substrate 100 , and can also increase the contact area between the first conductive pillar 180 and the substrate 100 and reduce the Contact resistance to substrate 100.
在一些实施例中，还包括：支撑层170，支撑层170位于绝缘层160的顶面，且支撑层170位于保护层150的顶面。支撑层170可以为第一导线层190提供支撑。In some embodiments, a support layer 170 is also included, the support layer 170 is located on the top surface of the insulating layer 160 , and the support layer 170 is located on the top surface of the protective layer 150 . The support layer 170 may provide support for the first conductor layer 190 .
在一些实施例中，第一导线层190位于绝缘层160的表面，且第一导线层190与第一导电柱180的顶面接触连接。第一导线层190可以用于半导体结构的布线，也就是说，可以通过第一导线层190将半导体结构内部的结构与外界的电信号连通，例如将第一掺杂区105与第一导线层190连通，再向第一导线层190输入第一掺杂区105所需的电信号，从而可以实现向第一掺杂区105输入所需的电信号。In some embodiments, the first conductive layer 190 is located on the surface of the insulating layer 160 , and the first conductive layer 190 is in contact with the top surface of the first conductive pillar 180 . The first conductor layer 190 can be used for wiring of the semiconductor structure. That is to say, the structure inside the semiconductor structure can be connected to external electrical signals through the first conductor layer 190 , for example, the first doped region 105 and the first conductor layer can be connected. 190 is connected, and then the electrical signal required by the first doping region 105 is input to the first conductor layer 190, so that the required electrical signal can be input to the first doping region 105.
在一些实施例中，第一导电柱180朝向绝缘层160表面形成有氢键，通过设置在第一 导电柱180与绝缘层160之间的氢键可以提高第一导电柱180与绝缘层160之间连接的紧密性。In some embodiments, a hydrogen bond is formed on the surface of the first conductive pillar 180 facing the insulating layer 160 . The hydrogen bond disposed between the first conductive pillar 180 and the insulating layer 160 can improve the relationship between the first conductive pillar 180 and the insulating layer 160 . tightness of connection.
本公开实施例通过提供一种半导体结构，包括，衬底100，位于PMOS区101的衬底100表面的沟道层110，且沟道层110表面形成有氢键，位于沟道层110表面的栅极结构200，位于栅极结构200顶面和侧壁的保护层150。通过在沟道层110的表面设置氢键从而可以改善沟道层110表面的界面态，从而可以降低沟道层110的漏电。The embodiment of the present disclosure provides a semiconductor structure, including a substrate 100, a channel layer 110 located on the surface of the substrate 100 in the PMOS region 101, and hydrogen bonds are formed on the surface of the channel layer 110, and a channel layer 110 located on the surface of the channel layer 110. Gate structure 200, protective layer 150 located on the top surface and sidewalls of gate structure 200. By arranging hydrogen bonds on the surface of the channel layer 110, the interface state on the surface of the channel layer 110 can be improved, thereby reducing leakage of the channel layer 110.
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the scope of the embodiments of the present disclosure. spirit and scope. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the disclosed embodiments. Therefore, the protection scope of the disclosed embodiments should be subject to the scope defined by the claims.

Claims (19)

  1. 一种半导体结构的制作方法，包括：A method of manufacturing a semiconductor structure, including:
    提供衬底，所述衬底包括PMOS区；providing a substrate, the substrate including a PMOS region;
    形成沟道层，所述沟道层位于所述PMOS区的所述衬底的表面；Forming a channel layer located on the surface of the substrate in the PMOS region;
    形成栅极结构和保护层，所述栅极结构位于所述沟道层的表面，所述保护层覆盖所述栅极结构的表面以及所述沟道层的部分表面；Forming a gate structure and a protective layer, the gate structure is located on the surface of the channel layer, and the protective layer covers the surface of the gate structure and part of the surface of the channel layer;
    在形成所述栅极结构及所述保护层之后，采用氢离子铸合工艺对所述沟道层的表面进行钝化处理。After forming the gate structure and the protective layer, a hydrogen ion casting process is used to passivate the surface of the channel layer.
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述钝化处理包括：向所述沟道层通入含氢钝化气体，所述含氢钝化气体包括：氢气或者氢气与惰性气体的混合气体。The method of manufacturing a semiconductor structure according to claim 1, wherein the passivation treatment includes passing a hydrogen-containing passivation gas into the channel layer, the hydrogen-containing passivation gas including: hydrogen or hydrogen and inert gas. A mixture of gases.
  3. 根据权利要求2所述的半导体结构的制作方法，其中，所述钝化处理的温度为310～530℃。The method of manufacturing a semiconductor structure according to claim 2, wherein the temperature of the passivation treatment is 310˜530°C.
  4. 根据权利要求2所述的半导体结构的制作方法，其中，所述钝化处理通入的含氢钝化气体的气流量为3.5L/min～6.5L/min。The method for manufacturing a semiconductor structure according to claim 2, wherein the gas flow rate of the hydrogen-containing passivation gas introduced into the passivation process is 3.5L/min to 6.5L/min.
  5. 根据权利要求2所述的半导体结构的制作方法，其中，所述钝化处理的时长为21min～39min。The method of manufacturing a semiconductor structure according to claim 2, wherein the duration of the passivation treatment is 21 minutes to 39 minutes.
  6. 根据权利要求1所述的半导体结构的制作方法，其中，进行所述钝化处理之前，还包括：The method for manufacturing a semiconductor structure according to claim 1, wherein before performing the passivation treatment, it further includes:
    形成绝缘层，所述绝缘层位于所述衬底的表面，且所述绝缘层覆盖所述保护层的侧壁；Forming an insulating layer, the insulating layer is located on the surface of the substrate, and the insulating layer covers the sidewall of the protective layer;
    形成第一导电柱，所述第一导电柱贯穿所述绝缘层以与所述PMOS区的所述衬底连接或所述第一导电柱贯穿所述绝缘层以及所述保护层以与所述栅极结构连接。Forming a first conductive pillar, the first conductive pillar penetrating the insulating layer to connect with the substrate of the PMOS region or the first conductive pillar penetrating the insulating layer and the protective layer to connect with the Gate structure connection.
  7. 根据权利要求6所述的半导体结构的制作方法，其中，形成所述第一导电柱的方法包括：The method of manufacturing a semiconductor structure according to claim 6, wherein the method of forming the first conductive pillar includes:
    刻蚀所述绝缘层，以形成凹槽，所述凹槽贯穿所述绝缘层以暴露所述PMOS区的所述衬底的表面或所述凹槽贯穿所述绝缘层以及所述保护层以暴露所述栅极结构的顶面；The insulating layer is etched to form a groove that penetrates the insulating layer to expose the surface of the substrate of the PMOS region or the groove penetrates the insulating layer and the protective layer to exposing the top surface of the gate structure;
    形成导电接触层，所述导电接触层位于所述凹槽的底面；Forming a conductive contact layer located on the bottom surface of the groove;
    形成扩散阻挡层，所述扩散阻挡层位于所述凹槽的内壁和所述导电接触层的表面；Forming a diffusion barrier layer, the diffusion barrier layer is located on the inner wall of the groove and the surface of the conductive contact layer;
    形成导电插塞层，所述导电插塞层填充满所述凹槽。A conductive plug layer is formed, and the conductive plug layer fills the groove.
  8. 根据权利要求7所述的半导体结构的制作方法，其中，形成所述导电接触层的方法包括：The method of manufacturing a semiconductor structure according to claim 7, wherein the method of forming the conductive contact layer includes:
    形成接触材料层，所述接触材料层位于所述凹槽的底面所暴露出的所述衬底的表面或所述栅极结构的顶面；Forming a contact material layer, the contact material layer is located on the surface of the substrate exposed by the bottom surface of the groove or the top surface of the gate structure;
    采用快速热退火工艺使所述衬底或所述栅极结构与所述接触材料层反应形成所述导电接触层。A rapid thermal annealing process is used to react the substrate or the gate structure with the contact material layer to form the conductive contact layer.
  9. 根据权利要求6所述的半导体结构的制作方法，其中，进行所述钝化处理之前，还包括：The method for manufacturing a semiconductor structure according to claim 6, wherein before performing the passivation treatment, it further includes:
    形成第一导线层，所述第一导线层位于所述绝缘层的表面，且所述第一导线层与所述第一导电柱的顶面接触连接。A first conductive layer is formed, the first conductive layer is located on the surface of the insulating layer, and the first conductive layer is in contact with the top surface of the first conductive pillar.
  10. 根据权利要求9所述的半导体结构的制作方法，其中，所述钝化处理还包括：对所述第一导线层及所述第一导电柱朝向所述绝缘层的侧壁进行所述钝化处理。The method of manufacturing a semiconductor structure according to claim 9, wherein the passivation treatment further includes: passivating sidewalls of the first conductive layer and the first conductive pillar facing the insulating layer. deal with.
  11. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述栅极结构的步骤包括：The method of manufacturing a semiconductor structure according to claim 1, wherein the step of forming the gate structure includes:
    形成初始栅介质层，所述初始栅介质层覆盖所述沟道层的表面；Forming an initial gate dielectric layer covering the surface of the channel layer;
    形成初始栅极，所述初始栅极覆盖所述初始栅介质层的表面；Forming an initial gate covering the surface of the initial gate dielectric layer;
    刻蚀所述初始栅极和初始栅介质层，剩余所述初始栅极作为栅极，剩余所述初始栅介质层作为栅介质层，所述栅极及所述栅介质层作为所述栅极结构。Etching the initial gate electrode and the initial gate dielectric layer, leaving the initial gate electrode as a gate electrode, the remaining initial gate dielectric layer as a gate dielectric layer, and the gate electrode and the gate dielectric layer as the gate electrode structure.
  12. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述栅极结构和所述保护层的步骤包括：The method of manufacturing a semiconductor structure according to claim 1, wherein the step of forming the gate structure and the protective layer includes:
    形成所述栅极结构，所述栅极结构位于所述沟道层的表面；Forming the gate structure, the gate structure is located on the surface of the channel layer;
    形成所述保护层，所述保护层覆盖所述沟道层的部分表面及所述栅极结构的侧壁及顶面。The protective layer is formed, covering part of the surface of the channel layer and the sidewalls and top surface of the gate structure.
  13. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述栅极结构和所述保护层的步骤包括：The method of manufacturing a semiconductor structure according to claim 1, wherein the step of forming the gate structure and the protective layer includes:
    形成初始保护层，所述初始保护层覆盖所述沟道层的表面；Forming an initial protective layer covering the surface of the channel layer;
    刻蚀所述初始保护层，以形成沟槽，所述沟槽暴露所述沟道层的表面；Etching the initial protective layer to form trenches that expose the surface of the channel layer;
    形成所述栅极结构，所述栅极结构位于所述沟槽内；forming the gate structure, the gate structure being located within the trench;
    形成盖层，所述盖层与剩余所述初始保护层构成所述保护层。A capping layer is formed, and the capping layer and the remaining initial protective layer constitute the protective layer.
  14. 一种半导体结构，包括：A semiconductor structure including:
    衬底，所述衬底包括PMOS区；A substrate, the substrate including a PMOS region;
    沟道层，所述沟道层位于所述PMOS区的所述衬底的表面，所述沟道层的表面形成有氢键；A channel layer, the channel layer is located on the surface of the substrate in the PMOS region, and hydrogen bonds are formed on the surface of the channel layer;
    栅极结构，所述栅极结构位于所述沟道层的表面；A gate structure, the gate structure is located on the surface of the channel layer;
    保护层，所述保护层覆盖所述栅极结构的顶面及侧壁，且所述保护层还覆盖所述沟道层 的至少部分表面。A protective layer covering the top surface and sidewalls of the gate structure, and the protective layer also covers at least part of the surface of the channel layer.
  15. 根据权利要求14所述的半导体结构，其中，还包括：The semiconductor structure of claim 14, further comprising:
    绝缘层，所述绝缘层位于所述衬底的表面，且所述绝缘层覆盖所述保护层的侧壁；An insulating layer, the insulating layer is located on the surface of the substrate, and the insulating layer covers the sidewall of the protective layer;
    第一导电柱，所述第一导电柱贯穿所述绝缘层以与所述PMOS区的所述衬底连接或所述第一导电柱贯穿所述绝缘层以及所述保护层以与所述栅极结构连接。A first conductive pillar, the first conductive pillar penetrates the insulating layer to connect with the substrate of the PMOS region, or the first conductive pillar penetrates the insulating layer and the protective layer to connect with the gate pole structure connection.
  16. 根据权利要求15所述的半导体结构，其中，所述第一导电柱包括：The semiconductor structure of claim 15, wherein the first conductive pillar includes:
    导电接触层，所述导电接触层位于所述PMOS区的所述衬底内或所述栅极结构顶面；A conductive contact layer, the conductive contact layer is located in the substrate of the PMOS region or on the top surface of the gate structure;
    扩散阻挡层，所述扩散阻挡层的底面与所述导电接触层的顶面接触，所述扩散阻挡层还包括环绕所述扩散阻挡层底面的侧面，所述扩散阻挡层的底面与侧面围成容纳空间；Diffusion barrier layer, the bottom surface of the diffusion barrier layer is in contact with the top surface of the conductive contact layer, the diffusion barrier layer also includes side surfaces surrounding the bottom surface of the diffusion barrier layer, and the bottom surface and side surfaces of the diffusion barrier layer form a accommodation space;
    导电插塞层，所述导电插塞层位于所述扩散阻挡层的表面，且填充满所述容纳空间。A conductive plug layer is located on the surface of the diffusion barrier layer and fills the accommodation space.
  17. 根据权利要求16所述的半导体结构，其中，至少部分所述导电插塞层位于所述PMOS区的所述衬底内。16. The semiconductor structure of claim 16, wherein at least a portion of the conductive plug layer is located within the substrate of the PMOS region.
  18. 根据权利要求15所述的半导体结构，其中，所述第一导电柱朝向所述绝缘层的表面形成有氢键。The semiconductor structure of claim 15, wherein hydrogen bonds are formed on a surface of the first conductive pillar facing the insulating layer.
  19. 根据权利要求14所述的半导体结构，其中，所述沟道层的厚度为2～10nm。The semiconductor structure according to claim 14, wherein the thickness of the channel layer is 2˜10 nm.
PCT/CN2022/124144 2022-08-25 2022-10-09 Semiconductor structure manufacturing method and semiconductor structure WO2024040698A1 (en)

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JPH05102471A (en) * 1991-10-03 1993-04-23 Sharp Corp Manufacture of semiconductor device
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