WO2024037650A1 - 数据缓存 - Google Patents

数据缓存 Download PDF

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Publication number
WO2024037650A1
WO2024037650A1 PCT/CN2023/113941 CN2023113941W WO2024037650A1 WO 2024037650 A1 WO2024037650 A1 WO 2024037650A1 CN 2023113941 W CN2023113941 W CN 2023113941W WO 2024037650 A1 WO2024037650 A1 WO 2024037650A1
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WIPO (PCT)
Prior art keywords
data
video data
module
level cache
prefetched
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PCT/CN2023/113941
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English (en)
French (fr)
Inventor
卢子威
刘贤华
马凤翔
吴克寿
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摩尔线程智能科技(北京)有限责任公司
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Publication of WO2024037650A1 publication Critical patent/WO2024037650A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/231—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion
    • H04N21/23106—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion involving caching operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
    • H04N21/23406—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving management of server-side video buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/433—Content storage operation, e.g. storage operation in response to a pause request, caching operations
    • H04N21/4331—Caching operations, e.g. of an advertisement for later insertion during playback
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/44004—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer

Definitions

  • This application relates to the technical field of video data processing, and in particular to methods and chips for data caching.
  • the applied data is usually cached; on the other hand, in order to reduce the calculation waiting time and improve the video data calculation efficiency, it is usually from Prefetch part of the video data from the external memory for subsequent data processing.
  • One purpose of this application is to provide a data caching method that improves data caching efficiency, reduces data memory access, improves the computing efficiency of video data processing, and reduces power consumption. Another object of the present application is to provide a chip. Another object of this application is to provide a computer device. Another object of the present application is to provide a readable medium. Another object of the present application is to provide a computer program product.
  • the present application discloses a data caching method for use in a chip.
  • the chip includes multiple video data processing sub-modules and prefetch data units respectively used to cache video data of different data types.
  • the method includes: determining the target video data according to the identification information of the video data processing submodule of the video data to be cached; determining the data storage address of the target video data in the external memory; and the prefetching data unit from the data storage address according to the data storage address. Obtain the corresponding target video data from the external memory.
  • the method further includes: storing at least part of the target video data into a prefetch data unit corresponding to the video data processing sub-module.
  • the target video data includes video data to be cached and prefetched video data
  • the prefetched data unit includes a chip system level cache module and a video system level cache module.
  • the method further includes: converting the target video data into The video data to be cached is stored in the corresponding video data processing sub-module and/or video system level cache module, and the prefetched video data in the target video data is stored in the corresponding chip system level cache module and/or video system. level cache module.
  • determining the target video data according to the identification information of the video data processing sub-module of the video data to be cached includes: determining the data type according to the identification information of the video data processing sub-module of the video data to be cached; The data format and the amount of prefetched data are determined according to the data type; the target video data to be obtained is determined according to the data format and the amount of prefetched data.
  • the data type includes a three-dimensional space linear horizontal increment type
  • determining the data format and prefetched data amount according to the data type includes: determining the data format according to the data type; and determining the data format according to the data format and the three-dimensional
  • the specified horizontal step size and data amount of the spatial linear horizontal increment type determine the amount of prefetched data.
  • the target video data includes video data to be cached and prefetched video data
  • the prefetched data unit includes a chip system level cache module and a video system level cache module.
  • the method further includes: converting the target video data into The video data to be cached is stored in the corresponding video system level cache module; the prefetched video data in the target video data is stored in the corresponding video system level cache module.
  • the data type includes a three-dimensional space adjacent dependency type
  • determining the data format and prefetched data amount according to the data type includes: determining the data format according to the data type; and determining the data format according to the data format and the three-dimensional
  • the spatial adjacency depends on the specified adjacency orientation of the type to determine the amount of prefetched data.
  • the target video data includes video data to be cached and prefetched video data
  • the prefetched data unit includes a chip system level cache module and a video system level cache module.
  • the method further includes: converting the target video data into The video data to be cached is stored in the corresponding video system level cache module; the prefetched video data in the target video data is stored in the corresponding video system level cache module.
  • the data type includes a limited three-dimensional space mutation type
  • determining the data format and prefetched data amount according to the data type includes: determining the data format according to the data type; and determining the data format according to the data format and the limited three-dimensional space.
  • the mutation address of the spatial mutation type determines the amount of prefetched data.
  • the target video data includes video data to be cached and prefetched video data
  • the prefetched data unit includes a chip system level cache module and a video system level cache module.
  • the method further includes: converting the target video data into The video data to be cached is stored in the corresponding video system level cache module; the prefetched video data in the target video data is stored in the corresponding chip system level cache module.
  • obtaining the corresponding target video data from the external memory according to the data storage address includes: the video system level cache module forming a data acquisition request according to the data storage address, and sending the data acquisition request. to the chip system level cache module; the chip system level cache module obtains the video data in the data storage address from the external memory according to the data acquisition request to obtain the target video data.
  • the video data to be cached in the target video data is stored in the corresponding video data processing unit.
  • the sub-module and/or the video system level cache module, storing the prefetched video data in the target video data to the corresponding chip system level cache module and/or the video system level cache module includes: determining the corresponding chip according to the identification information.
  • Replacement algorithm According to the replacement algorithm, the video data to be cached in the target video data is stored in the corresponding video data processing sub-module and/or the video system level cache module, and the prefetched video data in the target video data is Store it in the corresponding chip system-level cache module and/or video system-level cache module.
  • the method further includes: determining the cache area in the prefetch data unit corresponding to the one video data processing sub-module according to the prefetch video data acquisition request transmitted by one video data processing sub-module;
  • the data acquisition request acquires the prefetched target video data in the cache area; and caches at least part of the target video data to the one video data processing sub-module.
  • This application also discloses a chip, which includes multiple video data processing sub-modules, a central control module and a prefetch data unit respectively used to cache video data of different data types; the central control module is configured to cache video data according to the The identification information of the video data processing sub-module determines the target video data; and determines the data storage address of the target video data in the external memory; the prefetch data unit is configured to obtain the target video data from the external memory according to the data storage address. Get the corresponding target video data.
  • This application also discloses a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the above method is implemented.
  • This application also discloses a computer-readable medium on which a computer program is stored. When the program is executed by a processor, the above method is implemented.
  • This application also discloses a computer program product, which includes a computer program that implements the above method when executed by a processor.
  • the chip according to the embodiment of the present application includes multiple video data processing sub-modules and prefetch data units respectively used to cache video data of different data types.
  • the target video data can be determined according to the identification information of the video data processing sub-module of the video data to be cached, and the data storage address of the target video data in the external memory can be determined.
  • the prefetch data unit obtains the corresponding target video data from the external memory according to the data storage address. Therefore, the chip of the present application is equipped with different video data processing sub-modules to store target video data of different data types.
  • the data type of the video data to be cached can be determined, thereby determining the data type to be obtained.
  • Target video data to obtain the target video data from external memory By using identification information corresponding to the data type to distinguish video data from chip system data, the solution of this application can effectively improve data caching efficiency and reduce data memory access. This further improves the computational efficiency of video data processing and reduces power consumption.
  • Figure 1 shows a flow chart of a specific embodiment of the data caching method of the present application.
  • Figure 2 shows a flow chart of target video data storage according to a specific embodiment of the data caching method of the present application.
  • Figure 3 shows a flow chart of step S400 in a specific embodiment of the data caching method of the present application.
  • Figure 4 shows a flow chart of step S100 in a specific embodiment of the data caching method of the present application.
  • Figure 5 shows a flow chart of step S300 in a specific embodiment of the data caching method of the present application.
  • Figure 6 shows a flow chart of step S410 in a specific embodiment of the data caching method of the present application.
  • Figure 7 shows a flow chart of step S500 in a specific embodiment of the data caching method of the present application.
  • Figure 8 shows a flow chart of step S120 when the data type is a three-dimensional space linear horizontal increment type according to a specific embodiment of the data caching method of the present application.
  • Figure 9 shows a flow chart of step S410 when the data type is a three-dimensional space linear horizontal increment type according to a specific embodiment of the data caching method of the present application.
  • Figure 10 shows a flow chart of step S120 when the data type is a three-dimensional space adjacent dependency type according to a specific embodiment of the data caching method of the present application.
  • Figure 11 shows a flow chart of step S410 when the data type is a three-dimensional space adjacent dependency type according to a specific embodiment of the data caching method of the present application.
  • Figure 12 shows a flow chart of step S120 when the data type is a limited three-dimensional space mutation type according to a specific embodiment of the data caching method of the present application.
  • Figure 13 shows a flow chart of step S410 when the data type is a limited three-dimensional space mutation type according to a specific embodiment of the data caching method of the present application.
  • Figure 14 shows a structural diagram of a chip applying the data caching method of the present application.
  • Figure 15 shows a schematic structural diagram of a computer device suitable for implementing embodiments of the present application.
  • the video data processing module in the existing chip can obtain the video data stored in the external memory and process the video data processing, and can cache or prefetch part of the video data for subsequent video data processing, thereby improving the computing efficiency of video data processing and reducing data memory access.
  • video data processing includes sequential processing or separate processing of video data through sub-modules with different functions in the video data processing module.
  • the video data processing module may include sub-modules for video display processing, video encoding and decoding, and the like.
  • the chip can also implement other chip system-level functions, whereby chip system data is also stored in the chip.
  • the video data read by the video data processing module may overlap in time and space. Caching the applied data can improve the retrieval speed of using the applied video data again, and to a certain extent, can reduce the loss of video data. Fetch.
  • the video data read by the video data processing module may have incremental characteristics in time and space. Prefetching part of the video data for subsequent video data processing can reduce the calculation waiting time for subsequent video data processing and improve calculation efficiency.
  • the chip Since the storage space of the chip is usually relatively small, the chip will replace the cached or prefetched video data with new video data or delete part of the cached data based on the replacement algorithm.
  • replacement algorithms There are three main types of commonly used replacement algorithms:
  • Random (RAND) algorithm Since there are more blocks of video data stored in the main memory than in the cache (Cache), when a block is transferred from the main memory to the Cache, the block mapped by the block will appear. A group (or a) Cache block has been fully occupied. At this time, one of the blocks needs to be randomly freed up to accommodate the newly transferred blocks.
  • LRU Least Recently Used
  • existing chips usually use a unified cache mechanism from the perspective of chip system versatility, and use a fixed replacement algorithm to process video data in the cache, without taking into account the different characteristics of chip system data and video data (compared with video data In comparison, chip system data occupies a large storage space, has no prefetch mechanism, and has long data delay). This results in low storage efficiency of the video data processing module, and the cache storage space of the chip cannot even be effectively utilized in different scenarios.
  • existing chips do not take into account the data arrangement characteristics required by the video data processing module, and the data storage methods of video data caching or prefetching are inflexible.
  • the video data processing module usually subdivides a variety of video data arrangement formats, such as line scan data arrangement, block data arrangement, code stream sequence arrangement, top and bottom data sequence arrangement, left and right data sequence arrangement and front and back data arrangement. Frames are arranged sequentially at the same position, etc.
  • Each format uses separate memory storage, allowing the amount of data that can be stored for each format of video data. It is related to the space occupied by this format and cannot be flexibly configured.
  • this application sets the chip as a multi-level storage structure including a prefetch data unit and a video data processing module, returns the video data to be cached to the video data processing module, and stores the prefetched video data in the prefetch data
  • the unit can provide larger storage space for caching or prefetching video data, making the storage method of video data more flexible.
  • This application can also determine the data type according to the identification information and determine the range of the target video data according to the data type, so as to distinguish the video data from the chip system data, thereby effectively improving the data caching efficiency and reducing data memory access.
  • this application can also effectively improve the storage and replacement efficiency of video data by determining the data type according to the identification information and setting different replacement algorithms for different data types.
  • This embodiment discloses a data caching method, which can be used in chips.
  • the chip can realize at least one data processing function such as 2D graphics processing, 3D graphics processing and video data processing.
  • the chip includes a prefetch data unit and multiple video data processing sub-modules respectively used to cache video data of different data types.
  • the method includes the following steps.
  • Step S100 Determine target video data according to the identification information of the video data processing sub-module of the video data to be cached.
  • Step S200 Determine the data storage address of the target video data in the external memory.
  • Step S300 The prefetch data unit obtains corresponding target video data from the external memory according to the data storage address.
  • the chip of the present application includes a prefetch data unit and multiple video data processing sub-modules respectively used to cache video data of different data types. Accordingly, the data caching method based on this chip according to the embodiment of the present application can determine the target video data based on the identification information of the video data processing sub-module of the video data to be cached, and determine the data storage address of the target video data in the external memory, The prefetch data unit may obtain corresponding target video data from the external memory according to the data storage address. Therefore, the chip of the present application is equipped with different video data processing sub-modules to store target video data of different data types.
  • the data type of the video data to be cached can be determined, thereby determining the data type to be obtained.
  • Target video data to obtain the target video data from external memory By using identification information corresponding to the data type to distinguish video data from chip system data, the solution of this application can effectively improve data caching efficiency and reduce data memory access, thereby further improving the computing efficiency of video data processing and reducing power consumption.
  • the method further includes step S400: converting the target At least part of the video data is stored in the prefetch data unit corresponding to the video data processing sub-module.
  • the chip is configured as a two-level storage structure including a video data processing sub-module and a prefetch data unit, so that at least part of the target video data can be stored in the prefetch data unit, which can be Cached or prefetched video data provides larger storage space, and the storage method of video data is more flexible.
  • the prefetch data unit which can be Cached or prefetched video data provides larger storage space, and the storage method of video data is more flexible.
  • all acquired target video data can also be returned to the corresponding video data processing sub-module.
  • Those skilled in the art can set it according to actual needs, and this application does not limit this.
  • the target video data includes video data to be cached and prefetched video data
  • the prefetched data unit includes a chip system level cache module and a video system level cache module, as shown in Figure 3.
  • Step S400 further includes:
  • Step S410 Store the video data to be cached in the target video data to the corresponding video data processing sub-module and/or video system-level cache module, and store the prefetched video data in the target video data to the corresponding chip.
  • System-level cache module and/or video system-level cache module are examples of System-level cache module and/or video system-level cache module.
  • the target video data may include video data to be cached and prefetched video data, where the video data to be cached is the video data that the video data processing sub-module of the video data to be cached currently needs to obtain, and the prefetched video data is based on the data type.
  • the determined video data processing sub-module may need to obtain video data later.
  • the chip is configured as a multi-level storage structure including a video data processing sub-module, a chip system-level cache module and a video system-level cache module to support the use of different caching strategies for video data of different data types.
  • Different caching strategies can be preset for different data types, so that when the data type is determined based on the identification information, the corresponding caching strategy can be determined at the same time.
  • the video data to be cached can be directly sent to the corresponding video data processing sub-module based on the corresponding caching strategy, or stored in the video system-level cache module of the prefetch data unit, and subsequently
  • the video data processing sub-module can directly request and obtain the video data to be cached from the video system-level cache module, or it can also store part of the video data to be cached in the corresponding video data processing sub-module, and the other part in the corresponding video system level cache module.
  • the prefetched video data can be stored in the video system-level cache module or chip system-level cache module of the prefetch data unit based on the corresponding caching strategy.
  • the subsequent video data processing sub-module can directly obtain the data from the video system-level cache module.
  • the chip system-level cache module requests and obtains the prefetched video data, or a part of the prefetched video data can be stored in the corresponding video system-level cache module, and the other part is stored in the corresponding chip system-level cache module.
  • chips with multi-level storage structures can provide larger storage space for cached or prefetched video data.
  • the storage method of video data More flexible.
  • the video data to be cached in the target video data can be stored in the chip system-level cache module, or the prefetched video data in the target video data can be directly stored in the corresponding video data processing sub-module.
  • the prefetched video data in the target video data can be directly stored in the corresponding video data processing sub-module.
  • step S100 may include:
  • Step S110 Determine the data type according to the identification information of the video data processing sub-module of the video data to be cached.
  • Step S120 Determine the data format and prefetch data amount according to the data type.
  • Step S130 Determine the target video data to be obtained according to the data format and the prefetched data amount.
  • corresponding identification information is preset for video data processing sub-modules of different data types. Therefore, for the video data processing sub-module that needs to cache video data, the identification information corresponding to the video data processing sub-module can be obtained, and the data type of the video data to be cached by the video data processing sub-module is determined based on the identification information.
  • the data type may include at least one of the three-dimensional space linear level increasing type, the three-dimensional space adjacent dependence type, and the limited three-dimensional space mutation type.
  • video data of different data types have different data formats.
  • the data format and prefetched data amount can be determined according to the determined data type of the video data processing sub-module, and then the video data to be cached and the prefetched video data can be determined according to the data type.
  • the range of target video data stored in the external memory, and then the target video data can be obtained from the external memory.
  • the identification information may include at least one of data type, prefetch data information, and prefetch address step size.
  • the data type the data format of the video data to be cached or the prefetched video data may be determined.
  • the data format may be determined.
  • the amount of prefetched data can be determined by fetching data information and the prefetch address step size.
  • One unit of video data corresponding to the data format is the video data to be cached.
  • the video data with the amount of prefetched data is the prefetched video data.
  • the video data to be cached and The prefetched video data is the target video data to be obtained from the external memory.
  • This application sets different video data caching and prefetching mechanisms through identification information according to the characteristics of the data types of video data cached in different video data processing sub-modules, that is, by setting identification information of the video data processing sub-module to set the to-be-processed video data.
  • the format and range of cached video data and prefetched video data It also uses the chip's prefetch data unit and the multi-level cache structure of the video data processing sub-module to achieve flexible storage of data in the chip, expand the storage space of video data, and reduce data access bandwidth to a greater extent. Delay, improve data usage efficiency, further improve computing efficiency, and reduce power consumption.
  • the prefetched data unit includes a chip system-level cache module and a video system-level cache module.
  • the step S300 may include:
  • Step S310 The video system level cache module forms a data acquisition request according to the data storage address, and sends the data acquisition request to the chip system level cache module.
  • Step S320 The chip system level cache module obtains the video data in the data storage address from the external memory according to the data acquisition request to obtain the target video data.
  • the prefetch data unit includes a chip system level cache module and a video system level cache module.
  • the chip system-level cache module can be used to store the chip system data of the entire chip, and can also be used to store the prefetched video data prefetched by each video data processing sub-module. It can also be connected with external devices (such as external memory) to realize the chip Data interaction with external devices.
  • the video system-level cache module can be used to store prefetched video data prefetched by each video data processing sub-module.
  • each video data processing sub-module can send a request to cache video data to the video system-level cache module.
  • the video system-level cache module receives a video data transmission from the video data processing sub-module. After the request for caching video data is obtained, the identification information of the video data processing sub-module is obtained to obtain the target video data.
  • the data stored at all addresses in the external memory is pre-stored in the chip, so that the data storage address of the target video data in the external memory can be determined based on the target video data and the pre-stored data in the external memory, and a data storage address is formed based on the data storage address.
  • the data acquisition request is transmitted to the chip system-level cache module, and the target video data stored in the external memory is obtained through data interaction between the chip system-level cache module and the external memory.
  • the data storage address of the target video data in the external memory can also be determined in other ways. Those skilled in the art can set the acquisition method of the data storage status of the external memory according to the actual situation. This application does not make a decision here. limited.
  • the external memory is preferably a non-volatile memory, including but not limited to DDR (Double Data Rate) type memory.
  • DDR Double Data Rate
  • the chip system-level cache module and the video system-level cache module realize bidirectional transmission of information through the bus. Then the data acquisition request formed by the video system-level cache module can be transmitted to the chip system-level cache module through the bus, and then the chip system The level cache module can access the external memory according to the data acquisition request to obtain the target video data.
  • step S410 may specifically include:
  • Step S4111 Determine the corresponding replacement algorithm according to the identification information.
  • Step S4112 Store the video data to be cached in the target video data to the corresponding video data processing sub-module and/or video system-level cache module according to the replacement algorithm, and store the prefetched video data in the target video data Store it in the corresponding chip system-level cache module and/or video system-level cache module.
  • the identification information may further include replacement algorithms set for different video data processing sub-modules, so that different cache data replacement strategies can be set for different data types by setting the replacement algorithm in the identification information, that is, by replacing The algorithm can subdivide the replacement methods of target video data for different types of video data, improving the flexibility of caching and prefetching video data storage.
  • step S500 which includes:
  • Step S510 Determine the cache area in the prefetch data unit corresponding to the one video data processing sub-module according to the pre-fetch video data acquisition request transmitted by the one video data processing sub-module.
  • Step S520 Obtain the prefetched target video data in the cache area according to the prefetched video data acquisition request.
  • Step S530 Cache at least part of the target video data to the one video data processing sub-module.
  • the target video data is stored in the cache area corresponding to the prefetch data unit and the video data processing sub-module.
  • the video data processing sub-module can Send a prefetch data acquisition request to the prefetch data unit.
  • the prefetch data unit can determine the corresponding cache area according to the prefetch data acquisition request and the video data processing submodule that sends the request.
  • the cache area is set in the prefetch data unit for storing data related to the video data processing submodule.
  • the storage space of the target video data corresponding to the type.
  • each video data processing sub-module can directly obtain the target video data from the prefetch data unit of the chip, which can improve the efficiency of video data acquisition and processing.
  • the target video data includes video data to be cached and prefetched video data
  • the prefetched data unit includes a chip system level cache module and a video system level cache module.
  • the video data processing sub-module needs to obtain the target video data stored in the video system-level cache module and/or the chip system-level cache module, it can At least part of the target video data stored in the cache area of the video system-level cache module and/or the chip system-level cache module is obtained by forming a prefetch video data acquisition request.
  • the data type includes a three-dimensional space linear horizontal increment type
  • the step S120 may include:
  • Step S1211 Determine the data format according to the data type.
  • Step S1212 Determine the prefetched data amount according to the data format and the specified horizontal step size and data quantity of the three-dimensional space linear horizontal increment type.
  • the data format of the video data to be cached is determined, for example, 8x8 pixel unit data, and the pixel unit can be an integer multiple of the pixel block in the video data. Further, according to the characteristics of the data type of linear horizontal increment in three-dimensional space, the specified horizontal step size and data quantity of the data type can be obtained, and the amount of prefetched data can be calculated.
  • the data type cached in the video data processing sub-module A is a horizontal incremental type in a linear three-dimensional space.
  • the video data processing sub-module A needs to cache one unit of data, such as 8x8 pixel unit data.
  • the identification information of sub-module A can determine that the specified horizontal step size is 16, and the data quantity is eight 8x8 pixel unit data, and then the prefetched data amount can be obtained.
  • the prefetched data unit includes a chip system-level cache module and a video system-level cache module.
  • the step S410 may include:
  • Step S3411 Store the video data to be cached in the target video data to the corresponding video system-level cache module.
  • Step S3412 Store the prefetched video data in the target video data to the corresponding video system-level cache module.
  • the prefetched data unit includes a multi-level structure such as a chip system-level cache module and a video system-level cache module
  • a caching strategy for prefetching video data can be defined, and the target can be set according to the characteristics of the prefetched video data.
  • the video data is stored in at least one of the video data processing sub-module, the chip system-level cache module and the video system-level cache module.
  • a caching strategy for target video data of linear horizontal increment type in three-dimensional space can be set, that is, both the to-be-cached video data and the prefetched video data of the target video data are stored in the corresponding video system-level cache. module.
  • the chip system-level cache module can be set to pass-through mode (by pass), from The target video data returned by the external memory can be directly stored in the video system-level cache module, and the chip system-level cache module no longer caches the prefetched video data.
  • the data type includes a three-dimensional space adjacent dependency type.
  • the step S120 may include:
  • Step S1221 Determine the data format according to the data type.
  • Step S1222 Determine the prefetched data amount according to the data format and the specified adjacent orientation of the three-dimensional space adjacent dependency type.
  • the data format of the video data to be cached is determined.
  • it can be a 16x16 pixel unit, and the pixel unit can be an integer multiple of the pixel block in the video data.
  • the specified adjacent orientation of the data type can be obtained, and the prefetched data amount can be calculated.
  • the data type cached in the video data processing sub-module B is the three-dimensional space adjacent dependency type.
  • the video data processing sub-module B needs to cache the current 16x16 pixel unit and the 16x16 adjacent pixel units left, right, upper and lower in the adjacent space.
  • data according to the identification information of the video data processing sub-module B, it can be determined that the designated adjacent directions are the left, right, upper and lower adjacent spaces, and the target video data is obtained as the current and left, right, upper and lower 5 16x16 pixel unit data, and the video data to be cached and prefetched are obtained The amount of data.
  • the prefetched data unit includes a chip system-level cache module and a video system-level cache module.
  • the step S410 may include:
  • Step S3421 Store the video data to be cached in the target video data to the corresponding video system-level cache module.
  • Step S3422 Store the prefetched video data in the target video data to the corresponding video system-level cache module.
  • the prefetched data unit includes a multi-level structure such as a chip system-level cache module and a video system-level cache module
  • a caching strategy for prefetching video data can be defined, and the target can be set according to the characteristics of the prefetched video data.
  • the video data is stored in at least one of the video data processing sub-module, the chip system-level cache module and the video system-level cache module.
  • a caching strategy for target video data of a three-dimensional space adjacent dependency type can be set, that is, the video data to be cached and the prefetched video data in the target video data can be stored in the corresponding view.
  • Frequency system level cache module the chip system-level cache module can be set to pass-through mode (by pass), so that the target video data returned by the external memory can be directly stored in the video system-level cache module, and the chip system-level cache module no longer caches the prefetched video data.
  • the data type includes a limited three-dimensional space mutation type, as shown in Figure 12, the step S120 may include:
  • Step S1231 Determine the data format according to the data type.
  • Step S1232 Determine the prefetched data amount according to the data format and the mutation address of the limited three-dimensional space mutation type.
  • the data format of the video data to be cached can be determined.
  • it can be a 16x16 pixel unit, and the pixel unit can be an integer multiple of the pixel block in the video data.
  • the mutation address of the data type can be obtained, and the prefetched data amount can be calculated.
  • the data type cached in the video data processing sub-module C is a limited three-dimensional space mutation type.
  • the video data processing sub-module C needs to cache data at a mutation address such as 16x16 pixel unit data.
  • the identification information of C can determine the mutation address of other data, and then the amount of prefetched data can be obtained.
  • the prefetched data unit includes a chip system-level cache module and a video system-level cache module.
  • the step S410 may include:
  • Step S3431 Store the video data to be cached in the target video data to the corresponding video system-level cache module.
  • Step S3432 Store the prefetched video data in the target video data to the corresponding chip system-level cache module.
  • the prefetched data unit includes a multi-level structure such as a chip system-level cache module and a video system-level cache module
  • a caching strategy for prefetching video data can be defined, and the target can be set according to the characteristics of the prefetched video data.
  • the video data is stored in at least one of the video data processing sub-module, the chip system-level cache module and the video system-level cache module.
  • a caching strategy for limited three-dimensional space mutation type target video data can be set, that is, the prefetched video data in the target video data is stored in the chip system-level cache module, and the target video data is stored in the system-level cache module of the chip.
  • the video data to be cached in the video data is stored in the video system-level cache module to facilitate the acquisition and processing of the video data processing sub-module.
  • Figure 14 is a schematic diagram of a specific embodiment of a chip applying the data caching method of the present application.
  • the chip includes a central control module, a video data processing module L3 and a prefetch data unit.
  • the video data processing module L3 includes three video data processing sub-modules (A, B, C) respectively used to cache different types of video data.
  • the prefetch data unit may include a chip system-level cache module L1 and a video system-level cache module L2.
  • the chip system-level cache module L1 can interface with the external memory 100 to realize data interaction with the external memory 100, and is used to store chip system data of the entire chip system, and can also be used to store prefetched video data.
  • the video system-level cache module L2 is mainly used to store prefetched video data.
  • chip system data and prefetched video data are stored in different modules respectively, and chip system data and prefetched video data with different data characteristics are stored separately to improve the utilization of chip storage space.
  • the central control module is used to determine the data storage address of the target video data according to the identification information of the video data processing sub-module of the video data to be cached.
  • the target video data includes the video data to be cached and the prefetched video data; according to the data
  • the storage address obtains the corresponding target video data from the external memory 100; stores the video data to be cached in the corresponding video data processing sub-module, and stores the prefetched video data in the corresponding prefetch data unit.
  • the central control module can be set up independently from the video data processing sub-module and prefetch data unit, or it can be integrated with the video data processing sub-module or prefetch data unit, or it can be divided into multiple central control sub-modules. Modules are respectively provided in the video data processing sub-module and the prefetch data unit.
  • the central control module includes multiple central control sub-modules respectively provided in the video data processing module L3, the chip system-level cache module L1 and the video system-level cache module L2. module, multiple central control sub-modules jointly realize the functions of the central control module.
  • those skilled in the art can set the central control module according to actual needs, and this application does not limit this.
  • the video data processing module L3 of the chip includes three video data processing sub-modules A, B, and C.
  • the data type cached by the video data processing sub-module A is the horizontal increment type in the three-dimensional linear space.
  • the video data The data type cached by the processing sub-module B is the three-dimensional space adjacent dependence type
  • the data type cached by the video data processing sub-module C is the limited three-dimensional space mutation type.
  • Video data processing sub-modules A, B and C can set different identification information to identify the caching strategies of different data types. Different caching strategies are used for different data types, which expands the cache space in a targeted manner and can also take into account The versatility of system and video internal caching improves video data caching efficiency.
  • the identification information may include data type, prefetch data information (such as Such as data quantity) and prefetch address step size and other information.
  • the video data processing sub-module A includes a video sub-module level cache unit a that caches video data of data type a (cache_type_a).
  • the video data processing sub-module B includes a video sub-module level cache unit b that caches video data of data type b (cache_type_b).
  • the video data processing sub-module C includes a video sub-module level cache unit c that caches video data of data type c (cache_type_c).
  • the chip video data cache is divided into three levels.
  • the first level is the chip system level cache module L1
  • the second level is the video system level cache module L2
  • the third level includes three video data processing sub-modules ( A, B, C) video data processing module L3.
  • L1 interfaces with the external memory 100, realizes data interaction with the external memory 100, and can cache the entire chip system data and prefetch video data.
  • L2 can be used to store prefetched video data.
  • L3 includes video data processing sub-modules A, B, and C, which can be used to process video data and cache video data.
  • L2 is provided with video system level cache area a, video system level cache area b and video system level cache area c, which are used to store prefetched video data of video data processing sub-modules A, B and C respectively.
  • L1 is provided with chip system-level cache area 0, chip system-level cache area 1, chip system-level cache area 2...chip system-level cache area n and other cache areas, which can also be used to store video data processing sub-modules A, B and C. Prefetch video data.
  • the data type stored by the video data processing sub-module A is a horizontal incremental type in a linear three-dimensional space.
  • the video data processing sub-module A needs to obtain a unit of video data to be cached, such as an 8x8 pixel unit (the unit size can be configured as an integer multiple of the pixel block) data.
  • L2 prefetches the specified horizontal step size such as 16 in advance according to the identification information of cache_type_a, and the specified unit is eight target video data of 8x8 pixel units (including video data to be cached and prefetched video data), and calculates the target video data in the external memory 100
  • a data acquisition request is sent to L1
  • the target video data is obtained from the external memory 100 through L1
  • the target video data is stored in the video system level cache area a corresponding to the video data processing sub-module A.
  • L1 can use bypass mode and no longer cache data.
  • the data type stored in the video data processing sub-module B is the three-dimensional space adjacent dependency type.
  • the video data processing sub-module B needs to obtain the data of the current 16x16 pixel unit and the 16x16 adjacent pixel units in the left, right, upper and lower adjacent spaces.
  • L2 prefetches five 16x16 pixel units of target video data (including video data to be cached and prefetched video data) in advance based on the identification information of cache_type_b. After calculating the storage address of the target video data in the external memory 100, L2 retrieves the target video data from the external memory 100. Prefetch the target video data in advance and store the target video data in the video sub-module level cache unit b and the video system level cache area b designated by L2.
  • the data of the unit is the video data to be cached, and the data of the 16x16 adjacent pixel units on the left, right, top and bottom of the adjacent space is the prefetched video data.
  • L1 can use the least recently used replacement algorithm. After the video data processing sub-module B obtains the video data to be cached, when applying for adjacent prefetched video data again, it can be obtained directly from the video system-level cache area b of L2.
  • the data type stored in the video data processing sub-module C is a limited three-dimensional space mutation type.
  • the L3 video data processing sub-module C needs to obtain in advance the video data to be cached at a mutation address with a mutation number of 4, such as 16x16 pixel unit data.
  • L2 determines the target video data according to the identification information of cache_type_c, and stores the data of a mutation address (video data to be cached) into the designated video system level cache area b.
  • L1 can use the least recently used replacement algorithm to cache the data of the other three mutation addresses (prefetch video data).
  • the data replacement algorithms of caches at all levels can be flexibly configured according to the method defined by cache_type_c.
  • the chip system's default replacement method can be used, and the target video data can be obtained based on the default identification information.
  • other sub-modules may directly send a data acquisition request to L1 through the bus 200 to obtain the target video data from the external memory 100 through L1.
  • Those skilled in the art can set the video data acquisition methods of other sub-modules according to actual conditions, which will not be described again here.
  • the chip of this embodiment uses L1, L2 and L3 three-level cache structures to hierarchically store different forms of video data with different caching strategies, which can greatly reduce access to the external memory 100, reduce memory access delays, and improve limited memory utilization space. , improve data utilization efficiency.
  • the chip can adopt a cache structure of three or more levels, and use identification information to define the target video data that each video data processing sub-module needs to obtain, as well as the caching strategy and replacement algorithm for each level of the cache structure of three or more levels. and other information to further improve the flexibility of the chip in caching video data, cache space utilization efficiency and data utilization efficiency.
  • Related technical solutions based on this inventive concept should also be within the scope of protection of this application.
  • this embodiment also discloses a chip.
  • the chip includes multiple video data processing sub-modules, a central control module and a prefetch data unit respectively used to cache video data of different data types.
  • the central control module is configured to determine the target video data according to the identification information of the video data processing sub-module of the video data to be cached; and determine the data storage address of the target video data in the external memory; the prefetch data unit determines the target video data according to the The data storage address obtains the corresponding target video data from the external memory.
  • the central control module is further configured to store at least part of the target video data into a prefetch data unit corresponding to the video data processing sub-module.
  • the target video data includes video data to be cached and prefetched video data.
  • the prefetched data unit includes a chip system level cache module and a video system level cache module.
  • the central control module is further configured to Store the video data to be cached in the target video data to the corresponding video data processing sub-module and/or video system-level cache module, and store the prefetched video data in the target video data to the corresponding chip system-level cache module and/or video system-level caching module.
  • the central control module is further configured to determine the data type according to the identification information of the video data processing sub-module of the video data to be cached; determine the data format and prefetch data amount according to the data type; according to the The data format and the amount of prefetched data determine the target video data to be obtained.
  • the data type includes a three-dimensional space linear horizontal increment type
  • the central control module is further configured to determine a data format according to the data type; according to the data format and the three-dimensional space linear horizontal increment type
  • the specified horizontal step size and data amount determine the amount of prefetched data.
  • the central control module is further configured to store the video data to be cached in the target video data to the corresponding video system-level cache module; store the prefetched video data in the target video data to the corresponding video system-level cache module.
  • the data type includes a three-dimensional space adjacent dependency type
  • the central control module is further configured to determine a data format according to the data type. According to the data format and the three-dimensional space adjacent dependency type The specified adjacent orientation determines the amount of prefetched data.
  • the central control module is further configured to store the video data to be cached in the target video data to the corresponding video system-level cache module; store the prefetched video data in the target video data to the corresponding video system-level cache module.
  • the data type includes a limited three-dimensional space mutation type
  • the central control module is further configured to determine a data format according to the data type; the mutation according to the data format and the limited three-dimensional space mutation type Address, determines the amount of prefetched data.
  • the central control module is further configured to store the video data to be cached in the target video data to the corresponding video system-level cache module; store the prefetched video data in the target video data to the corresponding chip system-level cache module.
  • the video system level cache module forms a data acquisition request according to the data storage address, and sends the data acquisition request to the chip system level cache module.
  • the chip system level cache module obtains the data from the external memory according to the data acquisition request. Store the video data in the address to obtain the target video data.
  • the central control module is further configured to determine a corresponding replacement algorithm according to the identification information; and store the video data to be cached in the target video data to the corresponding video data processing according to the replacement algorithm.
  • the sub-module and/or the video system level cache module stores the prefetched video data in the target video data to the corresponding chip system level cache module and/or video system level cache module.
  • the central control module is further configured to determine the cache area in the prefetch data unit corresponding to the one video data processing sub-module according to the pre-fetch video data acquisition request transmitted by one video data processing sub-module; Obtain the prefetched target video data in the cache area according to the prefetched video data acquisition request; cache at least part of the target video data to the one video data processing sub-module.
  • a typical implementation device is a computer device.
  • the computer device may be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, Game consoles, tablets, wearables, or a combination of any of these devices.
  • the computer device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor.
  • the processor executes the program, the method executed by the client as described above is implemented.
  • the processor executes the program, the method executed by the server as described above is implemented.
  • FIG. 15 a schematic structural diagram of a computer device 600 suitable for implementing embodiments of the present application is shown.
  • the computer device 600 includes a central processing unit (Central Processing Unit, CPU) 601, which can be loaded into a random accessory according to a program stored in a read-only memory (Read-Only Memory, ROM) 602 or from a storage portion 608. Access the program in the memory (Random-Access Memory, RAM) 603 to perform various appropriate tasks and processes. In RAM 603, various programs and data required for system operation are also stored.
  • CPU601, ROM602, and RAM603 are connected to each other through bus 604.
  • An input/output (I/O) interface 605 is also connected to bus 604.
  • the following components are connected to the I/O interface 605: an input portion 606 including a keyboard, mouse, etc.; including a cathode such as The output part 607 of a Cathode Ray Tube (CRT), a liquid crystal display (LCD), etc., and speakers; a storage part 608 including a hard disk, etc.; and a network interface card including a LAN card, a modem, etc. Communication section 609.
  • the communication section 609 performs communication processing via a network such as the Internet.
  • Driver 610 is also connected to I/O interface 605 as needed.
  • Removable media 611 such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 610 as needed, so that a computer program read therefrom is installed in the storage portion 608 as needed.
  • the process described above with reference to the flowchart may be implemented as a computer software program.
  • embodiments of the present application include a computer program product including a computer program tangibly embodied on a machine-readable medium, the computer program including program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via communication portion 609, and/or installed from removable media 611.
  • Computer-readable media includes both persistent and non-volatile, removable and non-removable media that can be implemented by any method or technology for storage of information.
  • Information may be computer-readable instructions, data structures, modules of programs, or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (Phase Change RAM, PRAM), static random access memory (Static Random-Access Memory, SRAM), dynamic random access memory (Dynamic Random Access Memory, DRAM) ), other types of random access memory (Random Access Memory, RAM), read-only memory (ROM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only memory, EEPROM), flash memory, or Other memory technologies, Compact disc read-only memory (CD-ROM), Digital Videodisk (DVD) or other optical storage, magnetic tape cassettes, tape and disk storage or other magnetic A storage device or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined in this article,
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.
  • embodiments of the present application may be provided as methods, systems or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • the application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer.
  • program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types.
  • the present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communications network.
  • program modules may be located in both local and remote computer storage media including storage devices.

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Abstract

本申请提供了一种数据缓存方法及芯片，所述芯片包括分别用于缓存不同数据类型视频数据的多个视频数据处理子模块，以及预取数据单元，所述方法包括：根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据；确定外部存储器中所述目标视频数据的数据存储地址；所述预取数据单元根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据，本申请可提高数据缓存效率，减少数据访存，提高视频数据处理的计算效率，降低功耗。

Description

数据缓存 技术领域
本申请涉及视频数据处理技术领域，尤其涉及用于数据缓存的方法及芯片。
背景技术
相关技术中，对于芯片中的视频数据处理模块，一方面，为了减少数据访存，通常会缓存已申请过的数据；另一方面，为了减少计算等待时间和提高视频数据计算效率，通常会从外部存储器中预取部分视频数据，以用于后续的数据处理。
发明内容
本申请的一个目的在于提供一种数据缓存方法，提高数据缓存效率，减少数据访存，提高视频数据处理的计算效率，降低功耗。本申请的另一个目的在于提供一种芯片。本申请再一个目的在于提供一种计算机设备。本申请的还一个目的在于提供一种可读介质。本申请的还一个目的在于提供一种计算机程序产品。
为了达到以上目的，本申请一方面公开了一种数据缓存方法，用于芯片，所述芯片包括分别用于缓存不同数据类型视频数据的多个视频数据处理子模块以及预取数据单元，所述方法包括：根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据；确定外部存储器中所述目标视频数据的数据存储地址；所述预取数据单元根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据。
优选的，所述方法进一步包括：将所述目标视频数据的至少部分存储至所述视频数据处理子模块对应的预取数据单元。
优选的，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述方法进一步包括：将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。
优选的，所述根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据包括：根据待缓存视频数据的视频数据处理子模块的标识信息确定数据类型；根 据所述数据类型确定数据格式和预取数据量；根据所述数据格式和预取数据量确定待获取的目标视频数据。
优选的，所述数据类型包括三维空间线性水平递增类型，所述根据所述数据类型确定数据格式和预取数据量包括：根据所述数据类型确定数据格式；根据所述数据格式和所述三维空间线性水平递增类型的指定水平步长和数据数量，确定所述预取数据量。
优选的，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述方法进一步包括：将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；将所述目标视频数据中的预取视频数据存储至对应的视频***级缓存模块。
优选的，所述数据类型包括三维空间相邻依赖类型，所述根据所述数据类型确定数据格式和预取数据量包括：根据所述数据类型确定数据格式；根据所述数据格式和所述三维空间相邻依赖类型的指定相邻方位，确定所述预取数据量。
优选的，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述方法进一步包括：将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；将所述目标视频数据中的预取视频数据存储至对应的视频***级缓存模块。
优选的，所述数据类型包括有限三维空间突变类型，所述根据所述数据类型确定数据格式和预取数据量包括：根据所述数据类型确定数据格式；根据所述数据格式和所述有限三维空间突变类型的突变地址，确定所述预取数据量。
优选的，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述方法进一步包括：将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块。
优选的，所述根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据包括：所述视频***级缓存模块根据所述数据存储地址形成数据获取请求，将所述数据获取请求发送至所述芯片***级缓存模块；所述芯片***级缓存模块根据所述数据获取请求从所述外部存储器获取所述数据存储地址中的视频数据，得到所述目标视频数据。
优选的，所述将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理 子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块包括：根据所述标识信息确定对应的替换算法；根据所述替换算法将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。
优选的，所述方法进一步包括：根据一个视频数据处理子模块传输的预取视频数据获取请求确定所述一个视频数据处理子模块对应的预取数据单元中的缓存区域；根据所述预取视频数据获取请求获取所述缓存区域中预取的目标视频数据；将所述目标视频数据的至少部分缓存至所述一个视频数据处理子模块。
本申请还公开了一种芯片，包括分别用于缓存不同数据类型视频数据的多个视频数据处理子模块、中控模块和预取数据单元；所述中控模块被配置为根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据；以及确定外部存储器中所述目标视频数据的数据存储地址；所述预取数据单元被配置为根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据。
本申请还公开了一种计算机设备，包括存储器、处理器以及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现如上所述方法。
本申请还公开了一种计算机可读介质，其上存储有计算机程序，该程序被处理器执行时实现如上所述方法。
本申请还公开了一种计算机程序产品，所述计算机程序产品包括计算机程序，所述计算机程序被处理器执行时实现如上所述方法。
根据本申请实施例的芯片，包括分别用于缓存不同数据类型视频数据的多个视频数据处理子模块和预取数据单元。相应地，根据本申请实施例的基于该芯片的数据缓存方法，可根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据，确定外部存储器中所述目标视频数据的数据存储地址，预取数据单元根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据。由此，本申请的芯片设置不同的视频数据处理子模块以存储不同数据类型的目标视频数据，根据视频数据处理子模块的标识信息可确定待缓存视频数据的数据类型，从而可确定待获取的目标视频数据，以从外部存储器获取到目标视频数据。通过利用与数据类型对应的标识信息将视频数据与芯片***数据区分，本申请的方案可以有效提高数据缓存效率，减少数据访存， 从而进一步提高视频数据处理的计算效率，降低功耗。
附图说明
图1示出本申请数据缓存方法具体实施例的流程图。
图2示出本申请数据缓存方法具体实施例目标视频数据存储的流程图。
图3示出本申请数据缓存方法具体实施例步骤S400的流程图。
图4示出本申请数据缓存方法具体实施例步骤S100的流程图。
图5示出本申请数据缓存方法具体实施例步骤S300的流程图。
图6示出本申请数据缓存方法具体实施例步骤S410的流程图。
图7示出本申请数据缓存方法具体实施例步骤S500的流程图。
图8示出本申请数据缓存方法具体实施例数据类型为三维空间线性水平递增类型时步骤S120的流程图。
图9示出本申请数据缓存方法具体实施例数据类型为三维空间线性水平递增类型时步骤S410的流程图。
图10示出本申请数据缓存方法具体实施例数据类型为三维空间相邻依赖类型时步骤S120的流程图。
图11示出本申请数据缓存方法具体实施例数据类型为三维空间相邻依赖类型时步骤S410的流程图。
图12示出本申请数据缓存方法具体实施例数据类型为有限三维空间突变类型时步骤S120的流程图。
图13示出本申请数据缓存方法具体实施例数据类型为有限三维空间突变类型时步骤S410的流程图。
图14示出应用本申请数据缓存方法的芯片的结构图。
图15示出适于用来实现本申请实施例的计算机设备的结构示意图。
具体实施方式
现有芯片中的视频数据处理模块可获取外部存储器存储的视频数据并进行视频数据 处理，并可缓存或预取部分视频数据以用于后续的视频数据处理，从而提高视频数据处理的计算效率，减少数据访存。其中，视频数据处理包括通过视频数据处理模块中的具有不同功能的子模块对视频数据进行顺序处理或单独处理。例如，视频数据处理模块可包括用于视频显示处理和用于视频编解码等的子模块。此外，芯片还可实现其他芯片***级功能，由此，芯片中还存储有芯片***数据。
相关技术中，视频数据处理模块读取的视频数据在时间和空间上可能存在重合，缓存已申请过的数据可提高再次使用申请过的视频数据的获取速度，在一定程度上可以减少视频数据的访存。视频数据处理模块读取的视频数据在时间和空间上可能存在递增特点，预取部分视频数据用于后续的视频数据处理，可减少后续视频数据处理的计算等待时间，提高计算效率。
由于芯片的存储空间通常比较小，芯片会基于替换算法将缓存或预取的视频数据替换为新的视频数据或删掉部分缓存数据。常用的替换算法主要有以下三种：
1.随机(Random，RAND)算法：由于主存中存储视频数据的块比缓存(Cache)中的块多，所以当要从主存中调一个块到Cache中时，会出现该块所映射到的一组(或一个)Cache块已全部被占用的情况。这时，需要随机腾出其中的某一块，以接纳新调入的块。
2.先进先出(First In First Out，FIFO)算法：遵循先入先出原则，若当前Cache被填满，则替换最早进入Cache的那个块。
3.近期最少使用算法(Least Recently Used，LRU)：最近最少被使用的块被替换，也就是替换最后一次访问时间最久的那个块。
但是，现有的芯片通常从芯片***通用性角度考虑采用统一的缓存机制，并采用固定的替换算法处理缓存中的视频数据，而没有考虑到芯片***数据与视频数据的不同特点(与视频数据相比，芯片***数据占用存储空间大，没有预取机制，数据延时长)。这导致视频数据处理模块的存储效率不高，不同场景下芯片的缓存存储空间甚至无法有效利用。此外，现有的芯片没有考虑到视频数据处理模块要求的数据排列特点，视频数据缓存或预取的数据存储方式不灵活。具言之，视频数据处理模块通常细分多种视频数据排列格式，例如，行扫描数据排列方式、块数据排列方式、码流顺序排列方式、上下数据顺序排列方式、左右数据顺序排列方式和前后帧同位置顺序排列方式等等。每种格式使用单独的内存存储，使得每种格式的视频数据可存储的数据量 与该格式占用空间相关，不能灵活配置。
有鉴于以上，本申请通过将芯片设置为包括预取数据单元和视频数据处理模块的多级存储结构，将待缓存视频数据返回至视频数据处理模块，并将预取视频数据存储至预取数据单元，可为缓存或预取视频数据提供更大的存储空间，使得视频数据的存储方式更灵活。
本申请还可通过根据标识信息确定数据类型，根据数据类型确定目标视频数据的范围，可将视频数据与芯片***数据区分，从而有效提高数据缓存效率，减少数据访存。
此外，本申请还可通过根据标识信息确定数据类型，为不同数据类型设置不同的替换算法，从而有效提高视频数据的存储和替换效率。
下面首先对本申请的基本原理进行具体说明。本实施例公开了一种数据缓存方法，可用于芯片。其中，该芯片能够实现2D图形处理、3D图形处理和视频数据处理等至少一种数据处理功能。所述芯片包括预取数据单元和分别用于缓存不同数据类型视频数据的多个视频数据处理子模块。如图1所示，本实施例中，所述方法包括以下步骤。
步骤S100：根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据。
步骤S200：确定外部存储器中所述目标视频数据的数据存储地址。
步骤S300：所述预取数据单元根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据。
本申请的芯片包括预取数据单元和分别用于缓存不同数据类型视频数据的多个视频数据处理子模块。相应地，根据本申请实施例的基于该芯片的数据缓存方法可根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据，确定外部存储器中所述目标视频数据的数据存储地址，预取数据单元可根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据。由此，本申请的芯片设置不同的视频数据处理子模块以存储不同数据类型的目标视频数据，根据视频数据处理子模块的标识信息可确定待缓存视频数据的数据类型，从而可确定待获取的目标视频数据，以从外部存储器获取到目标视频数据。通过利用与数据类型对应的标识信息将视频数据与芯片***数据区分，本申请的方案可以有效提高数据缓存效率，减少数据访存，从而进一步提高视频数据处理的计算效率，降低功耗。
在优选的实施方式中，如图2所示，所述方法进一步包括步骤S400：将所述目标 视频数据的至少部分存储至所述视频数据处理子模块对应的预取数据单元。
具体的，在该优选的实施方式中，将芯片设置为包括视频数据处理子模块和预取数据单元的两级存储结构，从而可将至少部分的目标视频数据存储至预取数据单元，可为缓存或预取的视频数据提供更大的存储空间，视频数据的存储方式更灵活。当然，在其他实施方式中，也可将获取的目标视频数据全部返回至对应的视频数据处理子模块，本领域技术人员可根据实际需求设置，本申请对此并不作限定。
在优选的实施方式中，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，如图3所示，所述步骤S400进一步包括：
步骤S410：将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。
具体的，目标视频数据可包括待缓存视频数据和预取视频数据，其中，待缓存视频数据为待缓存视频数据的视频数据处理子模块当前需要获取的视频数据，预取视频数据为根据数据类型确定的视频数据处理子模块后续可能需要获取的视频数据。
在该优选的实施方式中，将芯片设置为包括视频数据处理子模块、芯片***级缓存模块和视频***级缓存模块的多级存储结构，以支持对不同数据类型的视频数据采用不同的缓存策略。其中，可为不同数据类型预设不同的缓存策略，从而在根据标识信息确定数据类型时，可同时确定对应的缓存策略。
具体的，针对不同数据类型的待缓存视频数据，可基于对应的缓存策略将待缓存视频数据直接发送至对应的视频数据处理子模块，或者存储在预取数据单元的视频***级缓存模块，后续视频数据处理子模块可直接从视频***级缓存模块请求并获取该待缓存视频数据，或者还可以将待缓存视频数据的一部分存储至对应的视频数据处理子模块，另一部分存储至对应的视频***级缓存模块。对于预取视频数据，可基于对应的缓存策略将预取视频数据存储在预取数据单元的视频***级缓存模块或者芯片***级缓存模块，后续视频数据处理子模块可直接从视频***级缓存模块或芯片***级缓存模块请求并获取该预取视频数据，或者还可以将预取视频数据的一部分存储至对应的视频***级缓存模块，另一部分存储至对应的芯片***级缓存模块。由此，多级存储结构的芯片可为缓存或预取的视频数据提供更大的存储空间，视频数据的存储方式 更灵活。
当然，在其他实施方式中，可将目标视频数据中的待缓存视频数据存储至芯片***级缓存模块，也可将目标视频数据中的预取视频数据直接存储至对应的视频数据处理子模块，本领域技术人员可根据实际需求设置，本申请对此并不作限定。
在优选的实施方式中，如图4所示，所述步骤S100可包括：
步骤S110：根据待缓存视频数据的视频数据处理子模块的标识信息确定数据类型。
步骤S120：根据所述数据类型确定数据格式和预取数据量。
步骤S130：根据所述数据格式和预取数据量确定待获取的目标视频数据。
具体的，在该优选的实施方式中，为不同数据类型的视频数据处理子模块预设对应的标识信息。从而，对于待缓存视频数据的视频数据处理子模块，可获取该视频数据处理子模块对应的标识信息，根据标识信息确定该视频数据处理子模块待缓存的视频数据的数据类型。示例性的，数据类型可包括三维空间线性水平递增类型、三维空间相邻依赖类型和有限三维空间突变类型等数据类型的至少之一。
由此，不同的数据类型的视频数据的数据格式不同，根据确定的视频数据处理子模块的数据类型可确定数据格式和预取数据量，进而根据数据类型确定待缓存视频数据和预取视频数据的外部存储器中存储的目标视频数据的范围，进而可从外部存储器中获取目标视频数据。
在一个具体例子中，标识信息可包括数据类型、预取数据信息和预取地址步长等信息的至少之一，根据数据类型可确定待缓存视频数据或预取视频数据的数据格式，根据预取数据信息和预取地址步长可确定预取数据量，数据格式对应的一个单位的视频数据即为待缓存视频数据，预取数据量的视频数据为预取视频数据，待缓存视频数据和预取视频数据即为待从外部存储器获取的目标视频数据。
本申请针对不同的视频数据处理子模块中缓存的视频数据的数据类型的特点，通过标识信息设置不同的视频数据缓存和预取机制，即通过设置视频数据处理子模块的标识信息来设定待缓存视频数据和预取视频数据的格式和范围。并配合使用芯片的预取数据单元和视频数据处理子模块的多级缓存结构实现芯片中数据的灵活存储，扩大视频数据的存储空间，在更大程度上减少数据访存带宽，减少数据访存延时，提高数据使用效率，进一步提高计算效率，降低功耗。
在优选的实施方式中，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，如图5所示，所述步骤S300可包括：
步骤S310：所述视频***级缓存模块根据所述数据存储地址形成数据获取请求，将所述数据获取请求发送至所述芯片***级缓存模块。
步骤S320：所述芯片***级缓存模块根据所述数据获取请求从所述外部存储器获取所述数据存储地址中的视频数据，得到所述目标视频数据。
可以理解的是，在该优选的实施方式中，预取数据单元包括芯片***级缓存模块和视频***级缓存模块。其中，芯片***级缓存模块可用于存储整个芯片的芯片***数据，也可用于存储各视频数据处理子模块预取的预取视频数据，还可与外部设备(例如，外部存储器)对接，实现芯片与外部设备的数据交互。视频***级缓存模块可用于存储各视频数据处理子模块预取的预取视频数据。
从而，当视频数据处理子模块需要缓存视频数据时，各视频数据处理子模块可向视频***级缓存模块发送缓存视频数据的请求，视频***级缓存模块在接收到一个视频数据处理子模块传输的缓存视频数据的请求后，获取该视频数据处理子模块的标识信息得到目标视频数据。
通常情况下，芯片中预存了外部存储器中所有地址存储的数据，从而可根据目标视频数据和预存的外部存储器中存储的数据确定目标视频数据在外部存储器中的数据存储地址，根据数据存储地址形成数据获取请求并将该数据获取请求传输至芯片***级缓存模块，通过芯片***级缓存模块与外部存储器的数据交互获取外部存储器存储的目标视频数据。当然，在实际应用中，还可通过其他方式确定目标视频数据在外部存储器中的数据存储地址，本领域技术人员可根据实际情况设置外部存储器的数据存储情况的获取方式，本申请在此并不作限定。
其中，示例性的，外部存储器优选的为非易失性存储器，包括但不限于DDR(Double Data Rate)类型的存储器。
在一个具体例子中，芯片***级缓存模块和视频***级缓存模块通过总线实现信息的双向传输，则视频***级缓存模块形成的数据获取请求可通过总线传输至芯片***级缓存模块，进而芯片***级缓存模块可根据数据获取请求访问外部存储器以获取目标视频数据。
在优选的实施方式中，如图6所示，所述步骤S410具体可包括：
步骤S4111：根据所述标识信息确定对应的替换算法。
步骤S4112：根据所述替换算法将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。
具体的，标识信息中还可进一步包括针对不同视频数据处理子模块设置的替换算法，从而可通过设置标识信息中的替换算法的形式，针对不同数据类型设置不同的缓存数据替换策略，即通过替换算法可细分不同类型视频数据的目标视频数据的替换方式，提高缓存和预取视频数据存储的灵活性。
在优选的实施方式中，如图7所示，所述方法进一步包括步骤S500，其包括：
步骤S510：根据一个视频数据处理子模块传输的预取视频数据获取请求确定所述一个视频数据处理子模块对应的预取数据单元中的缓存区域。
步骤S520：根据所述预取视频数据获取请求获取所述缓存区域中预取的目标视频数据。
步骤S530：将所述目标视频数据的至少部分缓存至所述一个视频数据处理子模块。
可以理解的是，本申请中，目标视频数据存储在预取数据单元与视频数据处理子模块对应的缓存区域中，当各视频数据处理子模块需要获取目标视频数据时，视频数据处理子模块可向预取数据单元发送预取数据获取请求。预取数据单元可根据该预取数据获取请求和发送请求的视频数据处理子模块确定对应的缓存区域，该缓存区域为预取数据单元中设置的用于存储与该视频数据处理子模块的数据类型对应的目标视频数据的存储空间。进而可从缓存区域中获取预取数据获取请求对应的至少部分目标视频数据并返回至视频数据处理子模块。从而，各视频数据处理子模块可直接从芯片的预取数据单元中获取目标视频数据，可提高视频数据的获取和处理效率。
在一个具体例子中，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块。将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。从而，目标视频数据的待缓存视频数据和预取视频数据的至少部分存储在视频***级缓存模块和芯片***级缓存模块的至少之一。视频数据处理子模块在需要获取存储在视频***级缓存模块和/或芯片***级缓存模块的目标视频数据时，可通 过形成预取视频数据获取请求的形式获取视频***级缓存模块和/或芯片***级缓存模块的缓存区域中存储的至少部分目标视频数据。
在优选的实施方式中，如图8所示，所述数据类型包括三维空间线性水平递增类型，所述步骤S120可包括：
步骤S1211：根据所述数据类型确定数据格式。
步骤S1212：根据所述数据格式和所述三维空间线性水平递增类型的指定水平步长和数据数量，确定所述预取数据量。
具体的，当数据类型为三维空间线性水平递增类型时，确定待缓存视频数据的数据格式，例如，8x8像素单位的数据，像素单位可以为视频数据中像素块的整数倍。进一步的，可根据三维空间线性水平递增类型的数据类型的特点，得到该数据类型的指定水平步长和数据数量，计算得到预取数据量。
在一个具体例子中，视频数据处理子模块A中缓存的数据类型为三维空间线性中的水平递增类型，视频数据处理子模块A需要缓存一个单位的数据如8x8像素单位的数据，根据视频数据处理子模块A的标识信息可确定指定水平步长为16，数据数量为8个8x8像素单位的数据，进而可得到预取数据量。
在优选的实施方式中，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，如图9所示，所述步骤S410可包括：
步骤S3411：将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块。
步骤S3412：将所述目标视频数据中的预取视频数据存储至对应的视频***级缓存模块。
可以理解的是，当预取数据单元包括芯片***级缓存模块和视频***级缓存模块等多级结构时，可定义预取视频数据的缓存策略，即可根据预取视频数据的特性设置该目标视频数据存储在视频数据处理子模块、芯片***级缓存模块和视频***级缓存模块的至少之一。
由此，在该优选的实施方式中，可设置三维空间线性水平递增类型的目标视频数据的缓存策略，即将目标视频数据的待缓存视频数据和预取视频数据均存储至对应的视频***级缓存模块。可选的，芯片***级缓存模块可设置为直通模式(by pass)，从 而外部存储器返回的目标视频数据可直接存储至视频***级缓存模块，芯片***级缓存模块不再缓存该预取视频数据。
在优选的实施方式中，所述数据类型包括三维空间相邻依赖类型，如图10所示，所述步骤S120可包括：
步骤S1221：根据所述数据类型确定数据格式。
步骤S1222：根据所述数据格式和所述三维空间相邻依赖类型的指定相邻方位，确定所述预取数据量。
具体的，当数据类型为三维空间相邻依赖类型时，确定待缓存视频数据的数据格式，例如，可以为16x16像素单位，像素单位可以为视频数据中像素块的整数倍。进一步的，可根据三维空间相邻依赖类型的数据类型的特点，得到该数据类型的指定相邻方位，计算得到预取数据量。
在一个具体例子中，视频数据处理子模块B中缓存的数据类型为三维空间相邻依赖类型，视频数据处理子模块B需要缓存当前16x16像素单位与相邻空间左右上下各16x16相邻像素单位的数据，根据视频数据处理子模块B的标识信息可确定指定相邻方位为相邻空间左右上下，获取目标视频数据为当前和左右上下5个16x16像素单位的数据，得到待缓存视频数据和预取数据量。
在优选的实施方式中，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，如图11所示，所述步骤S410可包括：
步骤S3421：将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块。
步骤S3422：将所述目标视频数据中的预取视频数据存储至对应的视频***级缓存模块。
可以理解的是，当预取数据单元包括芯片***级缓存模块和视频***级缓存模块等多级结构时，可定义预取视频数据的缓存策略，即可根据预取视频数据的特性设置该目标视频数据存储在视频数据处理子模块、芯片***级缓存模块和视频***级缓存模块的至少之一。
由此，在该优选的实施方式中，可设置三维空间相邻依赖类型的目标视频数据的缓存策略，即可将目标视频数据中的待缓存视频数据和预取视频数据存储至对应的视 频***级缓存模块。可选的，芯片***级缓存模块可设置为直通模式(by pass)，从而外部存储器返回的目标视频数据可直接存储至视频***级缓存模块，芯片***级缓存模块不再缓存该预取视频数据。
在优选的实施方式中，所述数据类型包括有限三维空间突变类型，如图12所示，所述步骤S120可包括：
步骤S1231：根据所述数据类型确定数据格式。
步骤S1232：根据所述数据格式和所述有限三维空间突变类型的突变地址，确定所述预取数据量。
具体的，当数据类型为有限三维空间突变类型时，可确定待缓存视频数据的数据格式，例如，可以为16x16像素单位，像素单位可以为视频数据中像素块的整数倍。进一步的，可根据有限三维空间突变类型的数据类型的特点，得到该数据类型的突变地址，计算得到预取数据量。
在一个具体例子中，视频数据处理子模块C中缓存的数据类型为有限三维空间突变类型，视频数据处理子模块C需要缓存一个突变地址的数据如16x16像素单位的数据，根据视频数据处理子模块C的标识信息可确定其他数据的突变地址，进而可得到预取数据量。
在优选的实施方式中，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，如图13所示，所述步骤S410可包括：
步骤S3431：将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块。
步骤S3432：将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块。
可以理解的是，当预取数据单元包括芯片***级缓存模块和视频***级缓存模块等多级结构时，可定义预取视频数据的缓存策略，即可根据预取视频数据的特性设置该目标视频数据存储在视频数据处理子模块、芯片***级缓存模块和视频***级缓存模块的至少之一。
由此，在该优选的实施方式中，可设置有限三维空间突变类型的目标视频数据的缓存策略，即将目标视频数据中的预取视频数据存储至芯片***级缓存模块，将目标 视频数据中的待缓存视频数据存储至视频***级缓存模块，便于视频数据处理子模块的获取及处理。
下面通过一个具体例子来对本申请作进一步的说明。图14是应用本申请数据缓存方法的芯片的一个具体实施例的示意图。如图14所示，在该具体实施例中，芯片包括中控模块、视频数据处理模块L3和预取数据单元。
其中，视频数据处理模块L3包括分别用于缓存不同类型视频数据的三个视频数据处理子模块(A、B、C)。预取数据单元可包括芯片***级缓存模块L1和视频***级缓存模块L2。该芯片***级缓存模块L1可对接外部存储器100，实现与外部存储器100的数据交互，并用于存储整个芯片***的芯片***数据，还可用于存储预取视频数据。视频***级缓存模块L2，主要用于存储预取视频数据。在该具体实施例中，芯片***数据和预取视频数据分别存储在不同模块中，将具有不同数据特点的芯片***数据和预取视频数据分开存储，提高芯片存储空间的利用率。
中控模块用于根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据的数据存储地址，所述目标视频数据包括所述待缓存视频数据和预取视频数据；根据所述数据存储地址从外部存储器100中获取对应的目标视频数据；将所述待缓存视频数据存储至对应的视频数据处理子模块，将所述预取视频数据存储至对应的预取数据单元。
需要说明的是，中控模块可以独立于视频数据处理子模块和预取数据单元单独设置，也可以与视频数据处理子模块或预取数据单元集成在一起，还可以分为多个中控子模块，分别设置于视频数据处理子模块和预取数据单元，例如，中控模块包括分别设置于视频数据处理模块L3、芯片***级缓存模块L1和视频***级缓存模块L2的多个中控子模块，多个中控子模块共同实现中控模块的功能。在实际应用中，本领域技术人员可根据实际需求设置中控模块，本申请对此并不作限定。
本实施例中，芯片的视频数据处理模块L3包括三个视频数据处理子模块A、B、C，其中，视频数据处理子模块A缓存的数据类型为三维空间线性中的水平递增类型，视频数据处理子模块B缓存的数据类型为三维空间相邻依赖类型，视频数据处理子模块C缓存的数据类型为有限三维空间突变类型。视频数据处理子模块A、B和C可设置不同的标识信息，用以标识不同数据类型的缓存策略，对于不同数据类型使用不同的缓存策略，有针对性的扩大了缓存空间，同时也能够兼顾***和视频内部缓存的通用性，提高视频数据缓存效率。其中，标识信息可包括数据类型、预取数据信息(例 如数据数量)和预取地址步长等信息。
具体的，如图14所示，视频数据处理子模块A包括缓存a数据类型(cache_type_a)的视频数据的视频子模块级缓存单元a。视频数据处理子模块B包括缓存b数据类型(cache_type_b)的视频数据的视频子模块级缓存单元b。视频数据处理子模块C包括缓存c数据类型(cache_type_c)的视频数据的视频子模块级缓存单元c。
在该具体例子中，芯片视频数据缓存划分为三级，第一级为芯片***级缓存模块L1、第二级为视频***级缓存模块L2，第三级为包括三个视频数据处理子模块(A、B、C)的视频数据处理模块L3。其中，L1对接外部存储器100，与外部存储器100实现数据交互，并可缓存整个芯片***数据和预取视频数据。L2可用于存储预取视频数据。L3包括视频数据处理子模块A、B、C，可用于进行视频数据的处理以及缓存视频数据。其中，L2中设置有视频***级缓存区域a、视频***级缓存区域b和视频***级缓存区域c，分别用于存储视频数据处理子模块A、B和C的预取视频数据。L1中设置有芯片***级缓存区域0、芯片***级缓存区域1、芯片***级缓存区域2…芯片***级缓存区域n等缓存区域，也可用于存储视频数据处理子模块A、B和C的预取视频数据。
在缓存视频数据时，视频数据处理子模块A存储的数据类型为三维空间线性中的水平递增类型，视频数据处理子模块A需要获取一个单位的待缓存视频数据，如8x8像素单位(单位大小可以配置为像素块的整数倍)的数据。L2根据cache_type_a的标识信息提前预取指定水平步长如16，指定单位为8个8x8像素单位的目标视频数据(包括待缓存视频数据和预取视频数据)，计算出外部存储器100中目标视频数据的存储地址后，向L1发送数据获取请求，通过L1从外部存储器100获取目标视频数据，将目标视频数据存储至视频数据处理子模块A对应的视频***级缓存区域a中。其中，L1可以使用by pass模式，不再缓存数据。
视频数据处理子模块B存储的数据类型为三维空间相邻依赖类型，视频数据处理子模块B需要获取当前16x16像素单位与相邻空间左右上下各16x16相邻像素单位的数据。L2根据cache_type_b的标识信息，提前预取5个16x16像素单位的目标视频数据(包括待缓存视频数据和预取视频数据)，计算出外部存储器100中目标视频数据的存储地址后，从外部存储器100提前预取目标视频数据并将目标视频数据存储至视频子模块级缓存单元b和L2指定的视频***级缓存区域b中。其中，当前16x16像素 单位的数据为待缓存视频数据，相邻空间左右上下各16x16相邻像素单位的数据为预取视频数据。L1可以使用最近最少使用的替换算法。在视频数据处理子模块B获取待缓存视频数据后，再次申请相邻的预取视频数据时，可以直接从L2的视频***级缓存区域b中得到。
视频数据处理子模块C存储的数据类型为有限三维空间突变类型，L3的视频数据处理子模块C需要提前获取突变次数为4的一个突变地址的待缓存视频数据，如16x16像素单位的数据。L2根据cache_type_c的标识信息确定目标视频数据，存储一个突变地址的数据(待缓存视频数据)至指定的视频***级缓存区域b中。L1可采用最近最少使用的替换算法，缓存另外三次突变地址的数据(预取视频数据)。各级cache的数据替换算法可以根据cache_type_c定义的方式灵活配置。
此外，若存在其他子模块N(图中未示出)的数据类型没有对应的标识信息，可以使用芯片***默认的替换方法，并根据默认的标识信息，得到目标视频数据。例如，其他子模块可直接通过总线200向L1发送数据获取请求，以通过L1从外部存储器100获取目标视频数据。本领域技术人员可根据实际情况对其他子模块的视频数据获取方式进行设置，在此不再赘述。
本实施例的芯片使用L1、L2和L3三级缓存结构，分级存储不同缓存策略的不同形式的视频数据，可以大大减少对外部存储器100的访问，减少访存延时，提高有限的内存利用空间，提高数据利用效率。当然，在其他实施方式中，芯片可采用三级以上的缓存结构，通过标识信息定义各视频数据处理子模块需要获取的目标视频数据以及三级以上缓存结构中每一级的缓存策略和替换算法等信息，以进一步提升芯片缓存视频数据的灵活性、缓存空间利用效率和数据利用效率，基于该发明构思的相关技术方案也理应在本申请的保护范围内。
基于相同原理，本实施例还公开了一种芯片。所述芯片包括分别用于缓存不同数据类型视频数据的多个视频数据处理子模块、中控模块和预取数据单元。
所述中控模块被配置为根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据；以及确定外部存储器中所述目标视频数据的数据存储地址；所述预取数据单元根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据。
在优选的实施方式中，所述中控模块进一步用于将所述目标视频数据的至少部分存储至所述视频数据处理子模块对应的预取数据单元。
在优选的实施方式中，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述中控模块进一步用于将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。
在优选的实施方式中，所述中控模块进一步用于根据待缓存视频数据的视频数据处理子模块的标识信息确定数据类型；根据所述数据类型确定数据格式和预取数据量；根据所述数据格式和预取数据量确定待获取的目标视频数据。
在优选的实施方式中，所述数据类型包括三维空间线性水平递增类型，所述中控模块进一步用于根据所述数据类型确定数据格式；根据所述数据格式和所述三维空间线性水平递增类型的指定水平步长和数据数量，确定所述预取数据量。
在优选的实施方式中，所述中控模块进一步用于将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；将所述目标视频数据中的预取视频数据存储至对应的视频***级缓存模块。
在优选的实施方式中，所述数据类型包括三维空间相邻依赖类型，所述中控模块进一步用于根据所述数据类型确定数据格式，根据所述数据格式和所述三维空间相邻依赖类型的指定相邻方位，确定所述预取数据量。
在优选的实施方式中，所述中控模块进一步用于将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；将所述目标视频数据中的预取视频数据存储至对应的视频***级缓存模块。
在优选的实施方式中，所述数据类型包括有限三维空间突变类型，所述中控模块进一步用于根据所述数据类型确定数据格式；根据所述数据格式和所述有限三维空间突变类型的突变地址，确定所述预取数据量。
在优选的实施方式中，所述中控模块进一步用于将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块。
在优选的实施方式中，所述视频***级缓存模块根据所述数据存储地址形成数据获取请求，将所述数据获取请求发送至所述芯片***级缓存模块。
所述芯片***级缓存模块根据所述数据获取请求从所述外部存储器获取所述数据 存储地址中的视频数据，得到所述目标视频数据。
在优选的实施方式中，所述中控模块进一步用于根据所述标识信息确定对应的替换算法；根据所述替换算法将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。
在优选的实施方式中，所述中控模块进一步用于根据一个视频数据处理子模块传输的预取视频数据获取请求确定所述一个视频数据处理子模块对应的预取数据单元中的缓存区域；根据所述预取视频数据获取请求获取所述缓存区域中预取的目标视频数据；将所述目标视频数据的至少部分缓存至所述一个视频数据处理子模块。
由于该芯片解决问题的原理与以上方法类似，因此本芯片的实施可以参见方法的实施，在此不再赘述。
上述实施例阐明的***、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机设备，具体的，计算机设备例如可以为个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任何设备的组合。
在一个典型的实例中计算机设备具体包括存储器、处理器以及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现如上所述的由客户端执行的方法，或者，所述处理器执行所述程序时实现如上所述的由服务器执行的方法。
下面参考图15，其示出了适于用来实现本申请实施例的计算机设备600的结构示意图。
如图15所示，计算机设备600包括中央处理单元(Central Processing Unit，CPU)601，其可以根据存储在只读存储器(Read-Only Memory，ROM)602中的程序或者从存储部分608加载到随机访问存储器(Random-Access Memory，RAM)603中的程序而执行各种适当的工作和处理。在RAM603中，还存储有***操作所需的各种程序和数据。CPU601、ROM602、以及RAM603通过总线604彼此相连。输入/输出(I/O)接口605也连接至总线604。
以下部件连接至I/O接口605：包括键盘、鼠标等的输入部分606；包括诸如阴极 射线管(Cathode Ray Tube，CRT)、液晶反馈器(Liquid crystal display，LCD)等以及扬声器等的输出部分607；包括硬盘等的存储部分608；以及包括诸如LAN卡，调制解调器等的网络接口卡的通信部分609。通信部分609经由诸如因特网的网络执行通信处理。驱动器610也根据需要连接至I/O接口605。可拆卸介质611，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器610上，以便于从其上读出的计算机程序根据需要被安装在如存储部分608。
特别地，根据本申请的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本申请的实施例包括一种计算机程序产品，其包括有形地包含在机器可读介质上的计算机程序，所述计算机程序包括用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分609从网络上被下载和安装，和/或从可拆卸介质611被安装。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(Phase Change RAM，PRAM)、静态随机存取存储器((Static Random-Access Memory，SRAM)、动态随机存取存储器(Dynamic Random Access Memory，DRAM)、其他类型的随机存取存储器(Random Access Memory，RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(Electrically Erasable Programmable Read-Only memory，EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(Compact disc read-only memory，CD-ROM)、数字多功能光盘(Digital Videodisk，DVD)或其他光学存储、磁盒式磁带，磁带及磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
为了描述的方便，描述以上装置时以功能分为各种单元分别描述。当然，在实施本申请时可以把各单元的功能在同一个或多个软件和/或硬件中实现。
本申请是参照根据本申请实施例的方法、设备(***)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处 理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本领域技术人员应明白，本申请的实施例可提供为方法、***或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请可以在由计算机执行的计算机可执行指令的一般上下文中描述，例如程序模块。一般地，程序模块包括执行特定任务或实现特定抽象数据类型的例程、程序、对象、组件、数据结构等等。也可以在分布式计算环境中实践本申请，在这些分布式计算环境中，由通过通信网络而被连接的远程处理设备来执行任务。在分布式计算环境中，程序模块可以位于包括存储设备在内的本地和远程计算机存储介质中。
本申请中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于芯片实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (17)

  1. 一种数据缓存方法，其特征在于，用于芯片，所述芯片包括分别用于缓存不同数据类型视频数据的多个视频数据处理子模块以及预取数据单元，所述方法包括：
    根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据；
    确定外部存储器中所述目标视频数据的数据存储地址；
    所述预取数据单元根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据。
  2. 根据权利要求1所述的数据缓存方法，其特征在于，所述方法进一步包括：
    将所述目标视频数据的至少部分存储至所述视频数据处理子模块对应的预取数据单元。
  3. 根据权利要求2所述的数据缓存方法，其特征在于，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述方法进一步包括：
    将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。
  4. 根据权利要求1所述的数据缓存方法，其特征在于，所述根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据包括：
    根据待缓存视频数据的视频数据处理子模块的标识信息确定数据类型；
    根据所述数据类型确定数据格式和预取数据量；
    根据所述数据格式和预取数据量确定待获取的目标视频数据。
  5. 根据权利要求4所述的数据缓存方法，其特征在于，所述数据类型包括三维空间线性水平递增类型，所述根据所述数据类型确定数据格式和预取数据量包括：
    根据所述数据类型确定数据格式；
    根据所述数据格式和所述三维空间线性水平递增类型的指定水平步长和数据数量，确定所述预取数据量。
  6. 根据权利要求5所述的数据缓存方法，其特征在于，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述方法进一步包括：
    将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；
    将所述目标视频数据中的预取视频数据存储至对应的视频***级缓存模块。
  7. 根据权利要求4所述的数据缓存方法，其特征在于，所述数据类型包括三维空间相邻依赖类型，所述根据所述数据类型确定数据格式和预取数据量包括：
    根据所述数据类型确定数据格式；
    根据所述数据格式和所述三维空间相邻依赖类型的指定相邻方位，确定所述预取数据量。
  8. 根据权利要求7所述的数据缓存方法，其特征在于，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述方法进一步包括：
    将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；
    将所述目标视频数据中的预取视频数据存储至对应的视频***级缓存模块。
  9. 根据权利要求4所述的数据缓存方法，其特征在于，所述数据类型包括有限三维空间突变类型，所述根据所述数据类型确定数据格式和预取数据量包括：
    根据所述数据类型确定数据格式；
    根据所述数据格式和所述有限三维空间突变类型的突变地址，确定所述预取数据量。
  10. 根据权利要求9所述的数据缓存方法，其特征在于，所述目标视频数据包括待缓存视频数据和预取视频数据，所述预取数据单元包括芯片***级缓存模块和视频***级缓存模块，所述方法进一步包括：
    将所述目标视频数据中的待缓存视频数据存储至对应的视频***级缓存模块；
    将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块。
  11. 根据权利要求3所述的数据缓存方法，其特征在于，所述根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据包括：
    所述视频***级缓存模块根据所述数据存储地址形成数据获取请求，将所述数据获取请求发送至所述芯片***级缓存模块；
    所述芯片***级缓存模块根据所述数据获取请求从所述外部存储器获取所述数据存储地址中的视频数据，得到所述目标视频数据。
  12. 根据权利要求3所述的数据缓存方法，其特征在于，所述将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块包括：
    根据所述标识信息确定对应的替换算法；
    根据所述替换算法将所述目标视频数据中的待缓存视频数据存储至对应的视频数据处理子模块和/或视频***级缓存模块，将所述目标视频数据中的预取视频数据存储至对应的芯片***级缓存模块和/或视频***级缓存模块。
  13. 根据权利要求2所述的数据缓存方法，其特征在于，所述方法进一步包括：
    根据一个视频数据处理子模块传输的预取视频数据获取请求确定所述一个视频数据处理子模块对应的预取数据单元中的缓存区域；
    根据所述预取视频数据获取请求获取所述缓存区域中预取的目标视频数据；
    将所述目标视频数据的至少部分缓存至所述一个视频数据处理子模块。
  14. 一种芯片，其特征在于，包括分别用于缓存不同数据类型视频数据的多个视频数据处理子模块、中控模块和预取数据单元；
    所述中控模块被配置为根据待缓存视频数据的视频数据处理子模块的标识信息确定目标视频数据；以及确定外部存储器中所述目标视频数据的数据存储地址；
    所述预取数据单元被配置为根据所述数据存储地址从所述外部存储器中获取对应的目标视频数据。
  15. 一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现权利要求1至13任一所述方法。
  16. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1至13任一所述方法。
  17. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序，所述计算机程序被处理器执行时实现权利要求1至13任一所述方法。
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