WO2024036985A1 - 存储***及其计算存储处理器、固体硬盘和数据读写方法 - Google Patents

存储***及其计算存储处理器、固体硬盘和数据读写方法 Download PDF

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Publication number
WO2024036985A1
WO2024036985A1 PCT/CN2023/086244 CN2023086244W WO2024036985A1 WO 2024036985 A1 WO2024036985 A1 WO 2024036985A1 CN 2023086244 W CN2023086244 W CN 2023086244W WO 2024036985 A1 WO2024036985 A1 WO 2024036985A1
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Prior art keywords
data
flash memory
address
ssd
storage
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PCT/CN2023/086244
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English (en)
French (fr)
Inventor
戴瑾
张云森
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北京超弦存储器研究院
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Application filed by 北京超弦存储器研究院 filed Critical 北京超弦存储器研究院
Priority to EP23853680.9A priority Critical patent/EP4375842A1/en
Priority to US18/312,968 priority patent/US11928345B1/en
Publication of WO2024036985A1 publication Critical patent/WO2024036985A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present disclosure relate to data storage technology, and in particular, to a storage system and its computing storage processor, solid hard disk and data reading and writing method.
  • CSP computational Storage Processor, Computational Storage Processor
  • the instructions required for object storage or key-value storage received by storage devices are no longer Read and write instructions based on block addresses. Therefore, when CSP does front-end processing, a large amount of data will flow through CSP. The redundant data copy increases CSP latency and power consumption.
  • This problem can be solved by adding one or more CSPs, but this solution is very cost-effective. Therefore, there is an urgent need to research an effective solution.
  • Some embodiments of the present application provide a storage system, which may include a solid state drive (SSD) and a computing storage processor (CSP). Between the SSD and the CSP and between the SSD, the CSP and the outside of the storage system, a high-speed serial computer is used to expand The point-to-point communication protocol of the bus standard PCIe bus communicates:
  • the CSP is configured to receive an external first operation instruction based on the storage object, according to the first Using the information carried by the first operation instruction and the locally maintained SSD resource information, a second operation instruction based on the flash memory address is generated and sent to the SSD;
  • the SSD is configured to, after receiving the second operation instruction, exchange the data of the storage object with the outside based on the information carried by the second operation instruction;
  • the first operation instruction includes a first deposit instruction and a first read instruction
  • the second operation instruction includes a second deposit instruction and a second read instruction
  • Some embodiments of this application provide a computing storage processor CSP in a storage system, which may include:
  • a first high-speed serial computer expansion bus standard PCIe bus interface configured to be connected to the PCIe bus to communicate with the solid state drive SSD in the storage system and external communication with the storage system through the PCIe bus;
  • the storage management system is configured to receive an external first operation instruction based on the storage object through the first PCIe bus interface, and generate a second operation based on the flash memory address based on the information carried by the first operation instruction and the locally maintained SSD resource information.
  • the instruction is sent to the SSD; wherein, the first operation instruction includes a first deposit instruction and a first read instruction, and the second operation instruction includes a second deposit instruction and a second read instruction; and,
  • An information manager configured to maintain SSD resource information in the storage system.
  • SSD solid state drive
  • main control chip may include:
  • the second high-speed serial computer expansion bus standard PCIe bus interface is configured to be connected to the PCIe bus to communicate with the computing storage processor CSP in the storage system and the external communication of the storage system through the PCIe bus;
  • the storage controller is configured to receive a second operation instruction based on the flash memory address sent by the CSP, and exchange data of the storage object with the outside according to the information carried by the second operation instruction; wherein the second operation instruction includes the second operation instruction.
  • the second operation instruction includes the second operation instruction.
  • Some embodiments of the present application provide a data storage method, which is applied to the computing storage processor CSP in the storage system.
  • the CSP communicates with the solid state drive SSD and the solid state drive in the storage system through the high-speed serial computer expansion bus standard PCIe bus.
  • the method may include:
  • a second deposit instruction based on the flash memory address is generated and sent to the SSD.
  • Some embodiments of the present application provide a data storage method, which is applied to the solid state drive SSD in the storage system.
  • the SSD communicates with the computing storage processor CSP and the computing storage processor CSP in the storage system through the high-speed serial computer expansion bus standard PCIe bus.
  • the method may include:
  • the data of the storage object is read from the outside and stored in the parsed flash memory address.
  • Some embodiments of the present application provide a data reading method, which is applied to the computing storage processor CSP in the storage system.
  • the CSP communicates with the solid state drive SSD and the solid state drive in the storage system through the high-speed serial computer expansion bus standard PCIe bus.
  • the method may include:
  • a second read instruction based on the flash memory address is generated and sent to the SSD.
  • Some embodiments of the present application provide a data reading method, which is applied to the solid state drive SSD in the storage system.
  • the SSD communicates with the computing storage processor CSP and the computing storage processor CSP in the storage system through the high-speed serial computer expansion bus standard PCIe bus.
  • the method may include:
  • the data of the storage object is read from the SSD and stored in the parsed starting address of external data reception.
  • Some embodiments of the present application provide a computing storage processor CSP, which may include: a third high-speed serial computer expansion bus standard PCIe bus interface, and a first logic circuit component coupled with the third PCIe bus interface; the first The logic circuit component is configured to perform the data storage method described in the fourth aspect, and the data reading method described in the sixth aspect.
  • Some embodiments of the present application also provide a main control chip of a solid state drive SSD, which may include: a fourth high-speed serial computer expansion bus standard PCIe bus interface, and a second logic circuit component coupled with the fourth PCIe bus interface;
  • the second logic circuit component is configured to perform the data storage method described in the fifth aspect, and the data reading method described in the seventh aspect.
  • Some embodiments of the present application provide a non-volatile storage medium on which a computer program is stored.
  • the computer program is executed by a processor, the data storage method described in the fourth and fifth aspects is performed, and the The data reading methods described in aspects six and seven.
  • Figure 1 is a schematic structural diagram of a storage system according to an embodiment of the present application.
  • FIG. 2 is a first component block diagram of the CSP in the storage system according to the embodiment of the present application.
  • Figure 3 is a first component block diagram of the SSD in the storage system according to the embodiment of the present application.
  • FIG. 4 is a flow chart of the CSP side data storage method according to the embodiment of the present application.
  • Figure 5 is a flow chart of the data storage method on the SSD side according to the embodiment of the present application.
  • FIG. 6 is a flow chart of the CSP side data reading method according to the embodiment of the present application.
  • Figure 7 is a flow chart of the SSD side data reading method according to the embodiment of the present application.
  • FIG. 8 is a second component block diagram of the CSP in the storage system according to the embodiment of the present application.
  • Figure 9 is a second component block diagram of an SSD in the storage system according to the embodiment of the present application.
  • Some embodiments of the present application provide a storage system, as shown in Figure 1, which may include a solid-state drive (SSD) and a computational storage processor (CSP);
  • SSD solid-state drive
  • CSP computational storage processor
  • the SSD and the CSP, as well as the SSD, the CSP and the outside of the storage system can communicate through the point-to-point communication protocol of the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) bus:
  • PCIe Peripheral Component Interconnect Express
  • the CSP is configured to receive an external first operation instruction based on a storage object, generate a second operation instruction based on a flash memory address and send it to the SSD based on the information carried by the first operation instruction and the locally maintained SSD resource information. ;
  • the SSD is configured to, after receiving the second operation instruction, exchange the data of the storage object with the outside based on the information carried by the second operation instruction;
  • the first operation instruction includes a first deposit instruction and a first read instruction
  • the second operation instruction includes a second deposit instruction and a second read instruction
  • one or more requesters may be included outside the storage system.
  • the storage system may include one CSP and multiple SSDs, and the one CSP and multiple SSDs are all connected to the PCIe bus and communicate through a point-to-point communication protocol.
  • the CSP receives an external storage request through the PCIe bus, that is, the above-mentioned first operation instruction (the first operation instruction may be a first storage instruction or a first read instruction)
  • the first operation instruction may include relevant information of the storage object.
  • the SSD address of the data of the storage object may be allocated, or the address where the data of the storage object is stored may be searched.
  • the SSD address is processed, and a corresponding second operation instruction is generated according to the processing result (corresponding to the above-mentioned first operation instruction, the second operation instruction is a second storage instruction or a second read instruction, that is, the first When the operation instruction is the first storage instruction, the second operation instruction is the second storage instruction; when the first operation instruction is the first read instruction, the second operation instruction is the second read instruction), using the points of the PCIe bus With the point-to-point communication mechanism, the CSP can send the generated second operation instruction to the assigned or queried SSD, so that the SSD can directly communicate with the external requester (which can also be called external at this time) according to the second operation instruction.
  • data The exchange party) exchanges data no longer through the CSP. Only instructions are transmitted between the CSP and the SSD. There will not be a large amount of data flowing through the CSP, and the CSP will not copy redundant data, thus greatly reducing the workload of the CSP. , reducing latency and power consumption.
  • the first storage instruction when the first operation instruction sent externally is a first storage instruction, the first storage instruction may include but is not limited to: the identification of the storage object, the data length information, and the entire data. Starting source address.
  • the SSD resource information includes resource occupancy information in the SSD;
  • the CSP is configured to generate a second operation instruction based on the flash memory address in the following manner after receiving the first storage instruction. and send to SSD:
  • the SSD According to the data length information and the resource occupation information in the SSD, allocate flash memory addresses in one or more SSDs for storing the data of the storage object; and according to the starting source address of the entire data of the storage object, The offset of the partial data of the storage object to be stored each time in the entire data of the storage object determines the starting source address of the partial data to be stored each time;
  • Each second storage instruction carries the starting source address of the data to be stored in the SSD, and provides The flash memory address where the data is stored.
  • the flash memory address is any form of address externally provided by the SSD, for example: it may be the address of a flash memory page, a flash memory block or a storage block, or it may be an address of a flash memory page, a flash memory block or a storage block. address segment.
  • the flash memory address is a storage block address
  • the SSD provides a logical address to the outside world.
  • the flash memory address is a flash memory page or flash memory block address
  • the SSD provides a physical address operation interface to the outside world.
  • the flash memory address is an address of a flash memory page or a flash memory block as an example for explanation.
  • resource occupation information in SSDs may include but is not limited to: addresses of all SSDs included in the storage system, addresses of at least one of flash memory pages and flash memory blocks in each SSD, each Resource occupation information of flash memory pages, storage pairs corresponding to each occupied flash memory page Object identification and offset, etc.
  • the CSP can determine the flash memory address in one or more SSDs that can store the storage object data currently to be stored based on the resource occupancy information, and determine the flash memory address according to the data amount of the storage object to be stored.
  • the storage object is assigned one or more of the flash memory addresses.
  • the CSP can determine whether the data of the storage object to be stored is large data or small data based on the data length information carried by the first storage instruction, and allocate the corresponding flash memory address according to the determined data size.
  • the data to be stored may be divided into more categories, or the data to be stored may not be classified into big data and small data, and so on.
  • the data when the data length information is less than or equal to the preset first data amount threshold, the data can be determined to be small data; when the data length information is greater than the preset first data amount threshold , the data can be determined as big data.
  • the first data amount threshold may be the storage data amount of one flash memory page, or may be other customized data amounts.
  • the detailed value of the first data amount threshold will not be determined here. limited.
  • the CSP when the data to be stored is small data, the CSP can allocate only one flash memory page for the data. When the data to be stored is large data, the CSP can allocate multiple flash memory pages for the data. Flash pages, or allocate one or more Flash blocks.
  • the multiple flash memory pages may be flash memory pages with consecutive addresses, and the multiple flash memory blocks may be address Contiguous blocks of flash memory, so that a contiguous address segment can be allocated for this large data.
  • a second storage instruction when a large number of storage objects to be stored are small data, a second storage instruction can be generated each time a small data is written.
  • multiple small data that need to be written continuously can be merged and then written, that is, a second storage instruction can be generated after merging, thereby reducing the task load of the storage system and improving the performance of the storage system. Reduce power consumption.
  • the information carried by the multiple first write instructions can be merged, and the information carried by the multiple first write instructions can be merged according to the merged information and locally maintained SSD resource information, generate a second save command and send it to SSD, and then the SSD obtains each small data separately according to the corresponding starting source address and stores it in the allocated flash memory address.
  • the multiple small data when the starting source addresses of multiple small data are consecutive, can be allocated according to the arrangement order of the small data stored in the multiple starting source addresses. Multiple consecutive flash memory addresses, and the arrangement order of the small data stored in the multiple consecutive flash memory addresses is the same as the arrangement order of the small data stored in the multiple starting source addresses.
  • the amount of data required for each flash memory address can be obtained from an external requester. to the flash memory address. Therefore, it can be determined based on the starting source address of the entire storage object data and the offset of the partial data of the storage object to be stored each time in the entire storage object data. The starting source address of the part of data to be stored each time; thereby obtaining the corresponding data for storage based on the starting source address of the part of the data.
  • a second deposit instruction when the CSP sends a second deposit instruction to the SSD, a second deposit instruction may be sent to each allocated flash memory address, or a second deposit instruction may be sent to multiple consecutive flash memory addresses ( That is, the address segment) sends a second deposit instruction.
  • the second storage instruction may include but is not limited to an NVMe (Non-Volatile Memory express, volatile memory) storage instruction.
  • NVMe Non-Volatile Memory express, volatile memory
  • NVMe is the mainstream SSD protocol currently on the market. It is a transmission protocol based on the physical layer of the PCIe bus. It is characterized by only sending read and write instructions and does not directly guide data exchange. For example, the read command only includes the storage address of the SSD and the address for data reception. In this way, the SSD can execute a large number of instructions in a sequence that suits it. When data transmission is required, the data is transferred to the receiving address through the PCIe transmission mechanism.
  • the SSD is configured to exchange the data of the storage object with the outside after receiving the second deposit instruction in the following manner: parsing the start value carried by the second deposit instruction.
  • Source address and flash memory address read data of the default size of the storage object from the outside according to the parsed starting source address, and store the read data into the parsed flash memory address; or,
  • the second deposit instruction sent by the CSP also carries the number of the storage objects to be deposited.
  • the SSD is configured to exchange the data of the storage object with the outside when receiving the second storage instruction in the following manner: parsing the starting source address carried by the second storage instruction, the flash memory Address and data amount information, according to the parsed starting source address and the data amount information, read the data of the corresponding data amount of the storage object from the outside, and store the read data into the parsed all the flash memory address.
  • the corresponding data amount is the data amount indicated by the data amount information.
  • the second deposit instruction may only include the starting source address of the storage object and the flash memory address, or may include both the starting source address of the storage object and the flash memory address (for example, multiple flash memory addresses).
  • the starting address of the page or flash memory block which also contains information on the data volume of the stored object.
  • the NVMe storage instruction when the second storage instruction is an NVMe storage instruction, can be an ordinary NVMe instruction, including: the starting source address of the storage object and the flash memory address; or,
  • the NVMe storage command may be an extended NVMe command, including: the starting source address of the storage object, data amount information, and flash memory address.
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the data can be stored through only one flash memory page. Therefore, one flash memory page can be allocated for the small data, and only the storage is included in the second store instruction.
  • the starting source address of the object and the address of the flash memory page are sufficient.
  • multiple flash memory pages are needed to store the data. Therefore, multiple flash memory pages can be allocated for the big data and accompanied by data amount information, for example, with the required flash memory pages.
  • the total amount, and the second storage instruction includes the starting source address of the storage object, the flash memory address (the starting address of at least one of the allocated flash memory pages, and the flash memory block) and the data amount information.
  • the principle is the same, and I will not repeat it here.
  • the first read instruction when the first operation instruction sent externally is the first read instruction, When requested, the first read instruction may include but is not limited to: the identification of the storage object and the starting address of data reception.
  • the SSD resource information includes the flash memory address in the SSD where the data of the storage object is stored; the CSP is configured to, after receiving the first read instruction, generate based on The second operation instruction of the flash memory address is sent to the SSD:
  • Each second read instruction carries the data to be read in the SSD. Flash memory address and starting address for data reception.
  • the CSP can query the flash memory address of the data of the storage object to be read in the SSD based on the identification of the storage object contained in the first read instruction, and combine the flash memory address with the external request The starting address of the party's data reception is carried in the second read command and sent to the SSD.
  • the data of the storage object to be read may be big data, or it may be small data.
  • the data of the storage object is big data, it is occupied (such as just full, or not full).
  • the second read instruction may only carry the address of the one or more complete flash memory pages or at least one of the flash memory blocks and the start of data reception. starting address.
  • the data of the storage object is large data and occupies at least one of multiple consecutive flash memory pages and flash memory blocks, the start of at least one of the multiple consecutive flash memory pages and flash memory blocks can be carried in the second read instruction.
  • the second read instruction can carry the starting address of at least one of the multiple consecutive flash memory pages and flash memory blocks, and the storage object.
  • the data amount information and the starting address of data reception When the data of the storage object is small data and only occupies a part of the space of a flash memory page, and another part of the space of the flash memory page is occupied by other data, the second read instruction not only carries the address of the flash memory page, It can also carry the offset of the flash memory address of the storage object to be read, so that the required data can be accurately read in the flash memory page according to the offset. Therefore, the second read instruction can carry the address of the flash memory page and its address. offset, and the starting address of data reception.
  • the second read instruction may include but is not limited to an NVMe read instruction.
  • the second read instruction may be an NVMe read instruction, and the flash memory address carried by the NVMe read instruction is the address of a flash memory page; or,
  • the second read command may be an extended NVMe store command.
  • the flash memory address carried by the extended NVMe read command is an address segment composed of the addresses of multiple consecutive flash memory pages.
  • the address segment may use a starting address. and data volume information representation.
  • the NVMe read instruction when the second read instruction is an NVMe read instruction, the NVMe read instruction may be an ordinary NVMe instruction, including: the flash memory address of the storage object and the starting address of data reception;
  • the NVMe storage command may be an extended NVMe command, including: the flash memory address of the storage object, data amount information, and the starting address of data reception.
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the offset refers to the offset of the small data in a flash memory page relative to the flash memory address of the flash memory page, and the offset can be represented by two offsets.
  • small data may be stored only in one flash memory page, may completely occupy a flash memory page, or may only occupy a part of the flash memory page, and the other part may be occupied by other small data. Therefore, for small data that completely occupies one flash memory page, the second read instruction only contains the starting address of the data reception of the storage object and the address of the flash memory page.
  • Small data, in the second read command may include the starting address of the data reception of the storage object, the address of the flash memory page and the offset of the small data, which is used for the SSD to read the data from the flash memory page and then read from the The required data is intercepted based on the offset from the fetched data.
  • the second read instruction includes the starting address of the data reception of the storage object, the flash memory address (the starting address of at least one of the stored one or more flash memory pages and flash memory blocks) and the data amount information.
  • the truth They are the same and will not be repeated here.
  • the SSD is configured to exchange the data of the storage object with the outside after receiving the second read instruction in the following manner: parsing the flash memory address carried by the second read instruction. and the start address of data reception, read the data to be read from the SSD according to the parsed flash memory address, and send the read data to the external start address of data reception.
  • the SSD can store the corresponding one or more flash memory pages in the SSD based on the flash memory address. , all the data stored in at least one of the flash memory blocks is taken out and stored to the starting address of data reception.
  • the second read instruction sent by the CSP may also carry data amount information of the storage object
  • the SSD is configured to receive the second read instruction in the following manner.
  • the SSD can read the corresponding multiple flash memories according to the flash memory address and data amount information. All the data stored in at least one of the page and the flash memory block is taken out and stored to the starting address of data reception.
  • the second read instruction sent by the CSP may also carry the offset of the flash memory address of the storage object
  • the SSD is configured to, when receiving the second read instruction, pass The data of the storage object is exchanged with the outside in the following manner: parsing the flash memory address and its offset carried by the second read instruction, as well as the starting address of data reception, and reading the data from a flash memory according to the parsed flash memory address and its offset.
  • Read part of the data stored in the page, or read one page of data from a flash memory page according to the parsed flash memory address intercept the required data from the page of data according to the offset, and store it externally.
  • the starting address of the data reception is
  • the SSD can fetch all the data stored in the corresponding flash memory page according to the flash memory address, and extract the required data from the read data according to the offset, and put The extracted data is stored to the starting address of data reception; alternatively, part of the stored data can be read from a flash memory page based on the parsed flash memory address and its offset.
  • the SSD may be further configured to return a success response to the CSP after successfully exchanging the data of the storage object with the outside based on the information carried by the second operation instruction;
  • the CSP may also be configured to, after receiving successful responses from all second operation instructions sent, return a success response to the sender of the first operation instruction, and update the maintained SSD resource information.
  • This embodiment of the present application provides a computing storage processor in a storage system, as shown in Figure 2, which may include:
  • the first PCIe bus interface 11 is configured to be connected to the PCIe bus to communicate with the solid state drive SSD in the storage system and the outside of the storage system through the PCIe bus;
  • the storage management system 12 is configured to receive an external first operation instruction based on the storage object through the first PCIe bus interface 11, and generate a flash memory address-based operation instruction based on the information carried by the first operation instruction and the locally maintained SSD resource information.
  • the second operation instruction is sent to the SSD; wherein, the first operation instruction includes a first deposit instruction and a first read instruction, and the second operation instruction includes a second deposit instruction and a second read instruction; as well as,
  • the information manager 13 is configured to maintain SSD resource information in the storage system.
  • the storage management system 12 of the CSP receives an external storage request through the first PCIe bus interface 11, that is, the above-mentioned first operation instruction (the first operation instruction may be a first storage instruction). or a first read instruction), the first operation instruction may include relevant information of the storage object, and the SSD address of the data of the storage object may be calculated based on the relevant information of the storage object and the resource information of each SSD stored by the information manager 13 Allocate, or search for the SSD address where the data of the storage object is stored, and generate corresponding second operation instructions based on the processing results.
  • the second operation instruction is a second storage instruction or a second read instruction).
  • the storage management system 12 can generate the second The operation command is sent to the assigned or queried SSD, so that the SSD directly exchanges data with the external requester according to the second operation command, and no longer passes through the CSP. Only instructions are transmitted between the CSP and the SSD, and there will be no A large amount of data flows through the CSP, and the CSP will not copy redundant data, thus greatly reducing the workload of the CSP and reducing latency and power consumption.
  • the storage management system 12 may include a storage processor 121, and the storage processing module 121 may be configured as:
  • the SSD According to the data length information and the resource occupation information in the SSD, allocate flash memory addresses in one or more SSDs for storing the data of the storage object; and according to the starting source address of the entire data of the storage object, The offset of the partial data of the storage object to be stored each time in the entire data of the storage object determines the starting source address of the partial data to be stored each time;
  • Each second storage instruction carries the starting source address of the data to be stored in the SSD, and provides The flash memory address where the data is stored.
  • the flash memory address is any form of address provided externally by the SSD.
  • it may be the address of a flash memory page, a flash memory block or a storage block, or it may be an address of a flash memory page, a flash memory block or a storage block. address segment.
  • the flash memory address is a storage block address
  • the SSD provides a logical address to the outside world.
  • the flash memory address is a flash memory page or flash memory block address
  • the SSD provides a physical address operation interface to the outside world.
  • the flash memory address is an address of a flash memory page or a flash memory block as an example for description.
  • the first deposit instruction may include but is not limited to: the identification of the storage object, data length information and the entire The starting source address of the data.
  • the resource occupation information in the SSD may include but is not limited to: The addresses of all SSDs included in the storage system, the address of at least one of the flash memory pages and flash memory blocks in each SSD, the resource occupation information of each flash memory page, the identification and offset of the storage object corresponding to each occupied flash memory page. Move, wait.
  • the storage processor 121 can determine, based on the resource occupancy information, the flash memory address in one or more SSDs that can store the storage object data currently to be stored, and determine the flash memory address according to the storage object data to be stored.
  • the amount of data allocated to the storage object is one or more of the flash memory addresses.
  • the storage processor 121 can determine whether the data of the storage object to be stored is large data or small data according to the data length information carried by the first storage instruction, and allocate data according to the determined data size. corresponding flash memory address.
  • the data when the data length information is less than or equal to the preset first data amount threshold, the data can be determined to be small data; when the data length information is greater than the preset first data amount threshold , the data can be determined as big data.
  • the first data volume threshold may be the storage data volume of one flash memory page, or may be a customized data volume. The detailed value of the first data volume threshold is not limited here.
  • the storage processor 121 may allocate only one flash memory page to the data, and when the data to be stored is large data, the storage processor 121 The processor 121 may allocate multiple pages of flash memory to the data, or alternatively, allocate one or more blocks of flash memory.
  • the multiple flash memory pages may be flash memory pages with consecutive addresses.
  • the block can be a flash memory block with consecutive addresses, so that the large data can be allocated an address segment with consecutive addresses.
  • a second storage instruction when a large number of storage objects to be stored are small data, a second storage instruction can be generated each time a small data is written.
  • multiple small data that need to be written continuously can be merged and then written, that is, a second storage instruction can be generated after merging, thereby reducing the task load of the storage system and improving the performance of the storage system. , reduce power consumption.
  • the information carried by the multiple first write instructions is merged, and based on the merged information and the locally maintained SSD resource information, a second deposit instruction is generated and sent to the SSD, and then Each small data is obtained by the SSD according to the corresponding starting source address and stored in the allocated flash memory address.
  • multiple small data when the starting source addresses of multiple small data are consecutive, multiple small data can be allocated to the multiple small data according to the arrangement order of the small data stored in the multiple starting source addresses.
  • consecutive flash memory addresses and the arrangement order of the small data stored in the multiple consecutive flash memory addresses is the same as the arrangement order of the small data stored in the multiple starting source addresses.
  • the amount of data required for each flash memory address can be obtained from an external requester. to the flash memory address. Therefore, it can be determined based on the starting source address of the entire storage object data and the offset of the partial data of the storage object to be stored each time in the entire storage object data. The starting source address of the part of data to be stored each time; thereby obtaining the corresponding data for storage based on the starting source address of the part of the data.
  • a second deposit instruction when the deposit processor 121 sends a second deposit instruction to the SSD, a second deposit instruction may be sent to each allocated flash memory address, or may be directed to multiple addresses.
  • a second store command is sent to consecutive flash memory addresses (i.e., address segments).
  • the second deposit instruction may include but is not limited to an NVMe deposit instruction.
  • the flash memory address carried by the second store instruction may be represented by the address of a flash memory page
  • the storage processor 121 When the storage processor 121 generates one or more second storage instructions for each SSD allocated with a flash memory address, it generates a second storage instruction for each flash memory page allocated in the SSD, carrying the data to be stored. The starting source address of the data entering the flash memory page, and the address of the flash memory page.
  • the flash memory address carried by the second deposit instruction may be an address segment composed of the addresses of multiple consecutive flash memory pages, and the address segment is represented by a starting address and data amount information;
  • the storage processor 121 generates one or more second memory addresses for each SSD allocated with a flash memory address.
  • a second deposit instruction can be generated for each address segment in the SSD, carrying the starting source address of the data to be stored in the address segment, and the starting address and data amount of the address segment. information.
  • the second deposit instruction may only include the starting source address of the storage object and the flash memory address, or may include both the starting source address of the storage object and the flash memory address (for example, multiple flash memory addresses).
  • the starting address of the page or flash memory block which also contains information on the data volume of the stored object.
  • the NVMe storage instruction when the second storage instruction is an NVMe storage instruction, can be an ordinary NVMe instruction, including: the starting source address of the storage object and the flash memory address; or,
  • the NVMe storage command can be an extended NVMe command, including: the starting source address of the storage object, data amount information and flash memory address;
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the data can be stored through only one flash memory page. Therefore, one flash memory page can be allocated for the small data, and only the storage is included in the second store instruction.
  • the starting source address of the object and the address of the flash memory page are sufficient.
  • multiple flash memory pages are needed to store the data. Therefore, multiple flash memory pages can be allocated for the big data and accompanied by data amount information, for example, with the required flash memory pages.
  • the total number of storage objects, and the second storage instruction includes the starting source address of the storage object, the flash memory address (the starting address of at least one of the allocated flash memory page and the flash memory block) and the data amount information.
  • the principle is the same, and I will not repeat it here.
  • the deposit processor 121 is further configured to generate one or more second deposit instructions for each SSD allocated with a flash memory address and send them to the SSD. After successful responses to all second deposit instructions sent, the sender of the first deposit instruction The sender returns a success response and notifies the information manager 13 to record the identification of the storage object and the flash memory address in the allocated SSD.
  • the storage management system 12 may include a read processor 122 configured to:
  • Each second read instruction carries the flash memory address of the data to be read in the SSD. And the starting address of data reception.
  • the first read instruction when the first operation instruction sent by the external requester is a first read instruction, the first read instruction may include but is not limited to: the identification of the storage object and the start of data reception. address.
  • the CSP can query the flash memory address of the data of the storage object to be read in the SSD based on the identification of the storage object contained in the first read instruction, and combine the flash memory address with the external request The starting address of the party's data reception is carried in the second read command and sent to the SSD.
  • the data of the storage object to be read may be big data, or it may be small data.
  • the data of the storage object is big data, it is occupied (such as just full, or not full).
  • the second read instruction may only carry the address of the one or more complete flash memory pages or at least one of the flash memory blocks and the start of data reception. starting address.
  • the data of the storage object is large data and occupies at least one of multiple consecutive flash memory pages and flash memory blocks, the start of at least one of the multiple consecutive flash memory pages and flash memory blocks can be carried in the second read instruction.
  • the second read instruction can carry the starting address of at least one of the multiple consecutive flash memory pages and flash memory blocks, and the storage object.
  • the data amount information and the starting address of data reception When the data of the storage object is small data and only occupies a part of the space of a flash memory page, and And when another part of the flash memory page is occupied by other data, the second read instruction not only carries the address of the flash memory page, but also carries the offset of the data of the storage object to be read, so as to facilitate reading according to the offset.
  • the required data is accurately read in the flash memory page, so the second read command can carry the address, offset and starting address of data reception of the flash memory page.
  • the second read instruction may include but is not limited to an NVMe read instruction.
  • the second read instruction may be an NVMe read instruction, and the flash memory address carried by the NVMe read instruction is the address of a flash memory page; or,
  • the second read command may be an extended NVMe store command.
  • the flash memory address carried by the extended NVMe read command is an address segment composed of the addresses of one flash memory page or multiple consecutive flash memory pages.
  • the address segment may be Indicated by starting address and data amount information.
  • the NVMe read instruction when the second read instruction is an NVMe read instruction, the NVMe read instruction may be an ordinary NVMe instruction, including: the flash memory address of the storage object and the starting address of data reception;
  • the NVMe storage command may be an extended NVMe command, including: the flash memory address of the storage object, data amount information, and the starting address of data reception.
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the offset refers to the offset of the small data in a flash memory page relative to the flash memory address of the flash memory page, and the offset can be represented by two offsets.
  • small data may be stored only in one flash memory page, may completely occupy a flash memory page, or may only occupy a part of the flash memory page, and the other part may be occupied by other small data. Therefore, for small data that completely occupies one flash memory page, the second read instruction only contains the starting address of the data reception of the storage object and the address of the flash memory page.
  • Small data, in the second read command may include the starting address of the data reception of the storage object, the address of the flash memory page and the offset of the small data, which is used for the SSD to read the data from the flash memory page and then read from the The required data is intercepted based on the offset from the fetched data.
  • the second read instruction includes the starting address of data reception of the storage object, the flash memory address (the starting address of at least one of the flash memory page and flash memory block where the data is stored), and data amount information.
  • the principle is the same, and I will not repeat it here.
  • the flash memory address carried by the second read instruction may be represented by the address of a flash memory page
  • the read processor 122 When the read processor 122 generates one or more second read instructions for each SSD that stores the secondary read data, it may generate a second read instruction for each flash memory page allocated in the SSD.
  • the read command carries the address of the flash memory page to be read and the starting address of data reception.
  • the SSD can store the corresponding one or more flash memory pages in the SSD based on the flash memory address. , all the data stored in at least one of the flash memory blocks is taken out and stored to the starting address of data reception.
  • the flash memory address carried by the second read instruction may be represented by the address of a flash memory page
  • the read processor 122 When the read processor 122 generates one or more second read instructions for each SSD that stores the secondary read data, it may generate a second read instruction for each flash memory page allocated in the SSD.
  • the read instruction carries the address of the flash memory page to be read, the offset of the data to be read this time relative to the address of the flash memory page, and the starting address of data reception.
  • the SSD can read all the data stored in the corresponding flash memory page according to the flash memory address. Take out, extract the required data from the read data based on the offset, and store the extracted data to the starting address of data reception; or, extract the required data from a flash memory based on the parsed flash memory address and its offset. Read part of the data stored in the page.
  • the flash memory address carried by the second read instruction may be an address segment composed of the addresses of multiple consecutive flash memory pages.
  • the address segment uses a starting address and data amount information. information expression
  • the read processor 122 When the read processor 122 generates one or more second read instructions for each SSD allocated with a flash memory address, it may generate a second read instruction for each address segment in the SSD, carrying the data to be read. Get the starting address and data amount information of the address segment, as well as the starting address of data reception.
  • the SSD can read the corresponding multiple flash memories according to the flash memory address and data amount information. All the data stored in at least one of the page and the flash memory block is taken out and stored to the starting address of data reception.
  • the third aspect is a first aspect:
  • the embodiment of the present application provides a solid state drive SSD in a storage system. As shown in Figure 3, it may include a main control chip 21 and a flash memory chip 22.
  • the main control chip 21 may include:
  • the second PCIe bus interface 211 is configured to be connected to the PCIe bus to communicate with the CSP in the storage system and the external communication of the storage system through the PCIe bus;
  • the storage controller 212 is configured to receive the second operation instruction based on the flash memory address sent by the CSP, and exchange the data of the storage object with the outside according to the information carried by the second operation instruction; wherein the second operation instruction includes A second store command and a second read command.
  • the CSP receives an external storage request through the first PCIe bus interface 11, that is, the above-mentioned first operation instruction.
  • the first operation instruction may include relevant information of the storage object.
  • the relevant information and the resource information of each SSD stored can be used to allocate SSD addresses to the data of the storage object, or find the SSD address where the data of the storage object is stored, and generate corresponding second operation instructions based on the processing results, using PCIe
  • the CSP can send the generated second operation command to the assigned or queried main control chip 21 of the SSD through the second PCIe bus interface 211, so that the main control chip 21 of the SSD
  • the storage controller 212 directly exchanges data with the external requester according to the second operation instruction, no longer through the CSP. Only instructions are transmitted between the CSP and the SSD. There will not be a large amount of data flowing through the CSP, and the CSP will not copy redundant data. data, thus greatly reducing the workload of C
  • the storage controller 212 may include a deposit controller 2121, and the deposit controller 2121 is configured to:
  • Receive the second deposit instruction parse the starting source address of the data of the storage object carried by the second deposit instruction and the flash memory address for data storage in this SSD;
  • the data of the storage object is read from the outside according to the parsed starting source address, and the read data is stored in the parsed flash memory address.
  • the storage processor 121 when the storage processor 121 sends a second storage instruction to the SSD, it may send a second storage instruction to each allocated flash memory address, or it may continuously target multiple addresses. Send a second store instruction to the flash memory address (ie, address segment).
  • the second deposit instruction may include but is not limited to an NVMe deposit instruction.
  • the flash memory address is any form of address provided externally by the SSD.
  • it may be the address of a flash memory page, a flash memory block or a storage block, or it may be an address of a flash memory page, a flash memory block or a storage block. address segment.
  • the flash memory address is a storage block address
  • the SSD provides a logical address to the outside world.
  • the flash memory address is a flash memory page or flash memory block address
  • the SSD provides a physical address operation interface to the outside world.
  • the flash memory address is an address of a flash memory page or a flash memory block as an example for explanation.
  • the parsed flash memory address may be the address of a flash memory page; the storage controller 2121 may be configured to read from the outside based on the parsed starting source address.
  • the data of one flash memory page size of the storage object is stored in the parsed address of the flash memory page; or,
  • the parsed flash memory address may be an address segment represented by a starting source address and data amount information; the address segment contains the addresses of multiple complete flash memory pages; the storage controller 2121 may be configured to perform the processing according to the parsed The starting source address and data volume information are obtained, and the corresponding data volume of the storage object is read from the outside and stored in the parsed address segment.
  • the second storage instruction may only include the starting source address of the storage object and the flash memory address, or may include both the starting source address of the storage object and the flash memory address. address (for example, the starting address of multiple flash pages or flash blocks), which also contains information about the data volume of the stored object.
  • the NVMe storage instruction when the second storage instruction is an NVMe storage instruction, can be an ordinary NVMe instruction, including: the starting source address of the storage object and the flash memory address; or,
  • the NVMe storage command may be an extended NVMe command, including: the starting source address of the storage object, data amount information, and flash memory address.
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the data can be stored through only one flash memory page. Therefore, one flash memory page can be allocated for the small data, and only the storage is included in the second store instruction.
  • the starting source address of the object and the address of the flash memory page are sufficient.
  • multiple flash memory pages are needed to store the data. Therefore, multiple flash memory pages can be allocated for the big data and accompanied by data amount information, for example, with the required flash memory pages.
  • the total amount, and the second storage instruction includes the starting source address of the storage object, the flash memory address (the starting address of at least one of the allocated flash memory page or flash memory blocks) and the data amount information.
  • the principle is the same and will not be repeated here.
  • the deposit controller 2121 is further configured to return a success response to the CSP after successfully receiving the second deposit instruction sent by the CSP and successfully writing the data. It may be that a success response is returned after data is successfully written according to each second deposit instruction, or a success response is returned after data is successfully written according to all second deposit instructions.
  • the storage controller 212 may include a read controller 2122 configured to:
  • the data of the storage object is read from the SSD according to the parsed flash memory address, and the read data is stored in the starting address of the external data reception.
  • the CSP can query the flash memory address of the data of the storage object to be read in the SSD based on the identification of the storage object contained in the first read instruction, and combine the flash memory address with the external request The starting address of the party's data reception is carried in the second read command and sent to the SSD.
  • the data of the storage object to be read may be big data, or may be small data.
  • the data of the storage object is big data, it is occupied (such as just full, or not occupied).
  • the second read instruction may only carry the address of the one or more complete flash memory pages or at least one of the flash memory blocks, as well as the address of the data received. initial address.
  • the data of the storage object is large data and occupies at least one of multiple consecutive flash memory pages and flash memory blocks, the start of at least one of the multiple consecutive flash memory pages and flash memory blocks can be carried in the second read instruction.
  • the second read instruction can carry the starting address of at least one of the multiple consecutive flash memory pages and flash memory blocks, and the storage object.
  • the data amount information and the starting address of data reception When the data of the storage object is small data and only occupies a part of the space of a flash memory page, and another part of the space of the flash memory page is occupied by other data, the second read instruction not only carries the address of the flash memory page, It can also carry the offset of the data of the storage object to be read, so that the required data can be accurately read in the flash memory page according to the offset. Therefore, the second read instruction can carry the address and offset of the flash memory page. And the starting address of data reception.
  • the second read instruction may include but is not limited to an NVMe read instruction.
  • the second read instruction may be an NVMe read instruction, and the flash memory address carried by the NVMe read instruction is the address of a flash memory page; or,
  • the second read command may be an extended NVMe store command.
  • the flash memory address carried by the extended NVMe read command is an address segment composed of the addresses of multiple consecutive flash memory pages.
  • the address segment may use a starting address. and data volume information representation.
  • the NVMe read instruction when the second read instruction is an NVMe read instruction, may be an ordinary NVMe instruction, including: the flash memory address and data of the storage object.
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the offset refers to the offset of the small data in a flash memory page to the flash memory address of the flash memory page, and the offset can be represented by two offsets.
  • small data may be stored only in one flash memory page, may completely occupy a flash memory page, or may only occupy a part of the flash memory page, and the other part may be occupied by other small data. Therefore, for small data that completely occupies one flash memory page, the second read instruction only contains the starting address of the data reception of the storage object and the address of the flash memory page.
  • Small data, in the second read command may include the starting address of the data reception of the storage object, the address of the flash memory page and the offset of the small data, which is used for the SSD to read the data from the flash memory page and then read from the The required data is intercepted based on the offset from the fetched data.
  • the second read instruction includes the starting address of the data reception of the storage object, the flash memory address (the starting address of at least one of the flash memory page and the flash memory block where the data is stored), and data amount information.
  • the principle is the same, and I will not repeat it here.
  • the parsed flash memory address may be the address of a flash memory page; the read controller 2122 is configured to read from the SSD based on the parsed address of the flash memory page. Get the data of the storage object and store the starting address of the parsed data reception.
  • the SSD can store the corresponding one or more flash memory pages in the SSD based on the flash memory address. , all the data stored in at least one of the flash memory blocks is taken out and stored to the starting address of data reception.
  • the parsed flash memory address may be an address segment represented by a starting address and data amount information; the read controller 2122 is configured to perform the parsed flash memory address according to the parsed starting address. Address and data volume information, read the corresponding data volume of the storage object from this SSD and store the parsed starting address of data reception.
  • the SSD can read the corresponding multiple flash memories according to the flash memory address and data amount information. All the data stored in at least one of the page and the flash memory block is taken out and stored to the starting address of data reception.
  • the parsed flash memory address may be the address of a flash memory page and the offset of the secondary read data relative to the address of the flash memory page; the read controller 2122 It is configured to read one page of data from this SSD according to the parsed address of the flash memory page, and intercept the required data from the page of data according to the offset and store the parsed data at the beginning of reception. starting address.
  • the SSD can read all the data stored in the corresponding flash memory page according to the flash memory address. Take out, extract the required data from the read data based on the offset, and store the extracted data to the starting address of data reception; or, extract the required data from a flash memory based on the parsed flash memory address and its offset. Read part of the data stored in the page.
  • the read controller 2122 is further configured to return a success response to the CSP after successfully receiving the second read instruction sent by the CSP and successfully reading the data.
  • the fourth aspect is a first aspect:
  • the embodiment of the present application provides a data storage method, which is applied to the CSP in the storage system.
  • the CSP can communicate with the SSD in the storage system and the outside of the storage system through the high PCIe bus, as shown in Figure 4 , the method may include steps S101-S102:
  • the CSP communicates with an external requester based on a point-to-point communication mechanism through the PCIe bus, and receives an external storage request, such as the above-mentioned first storage instruction,
  • the first storage instruction may include information related to the storage object.
  • the first storage instruction may include but is not limited to: the identification of the storage object, data length information, and the starting source address of the entire data.
  • the SSD resource information may include resource occupancy information in the SSD; the resource occupancy information in the SSD may include but is not limited to: the addresses of all SSDs included in the storage system, each The address of at least one of the flash memory pages and flash memory blocks in the SSD, the resource occupation information of each flash memory page, the identification and offset of the storage object corresponding to each occupied flash memory page, and so on.
  • the CSP can perform SSD address allocation and other processing on the data of the storage object based on the relevant information of the storage object and the resource information of each stored SSD, and generate the corresponding second storage based on the processing results.
  • CSP can send the generated second operation instruction to the assigned SSD, so that the SSD directly exchanges data with the external requester according to the second deposit instruction, no longer through CSP only transmits instructions between CSP and SSD. There will not be a large amount of data flowing through CSP, and CSP will not copy redundant data, thus greatly reducing the workload of CSP and reducing latency and power consumption.
  • generating a second storage instruction based on the flash memory address and sending it to the SSD based on the information carried by the first storage instruction and the locally maintained SSD resource information may include:
  • the SSD According to the data length information and the resource occupation information in the SSD, allocate one or more flash memory addresses in the SSD for storing the data of the storage object; and according to the starting source address of the entire data, each request The offset of the stored partial data of the storage object in the entire data of the storage object determines the starting source address of the partial data to be stored each time;
  • Each second deposit instruction carries the starting source address of the data to be stored in the SSD. and the flash memory address for data storage.
  • the flash memory address is any form of address provided externally by the SSD.
  • it may be the address of a flash memory page, a flash memory block or a storage block, or it may be a flash memory page, a flash memory block or a storage block. address segment.
  • the flash memory address is a storage block address
  • the SSD provides a logical address to the outside world.
  • the flash memory address is a flash memory page or flash memory block address
  • the SSD provides a physical address operation interface to the outside world.
  • the flash memory address is an address of a flash memory page or a flash memory block as an example for description.
  • the CSP can determine the flash memory address in one or more SSDs that can store the storage object data currently to be stored based on the resource occupancy information of the SSD, and determine the flash memory address based on the data of the storage object to be stored. Allocate one or more of the flash memory addresses to the storage object.
  • the CSP may first determine whether the data of the storage object to be stored is large data or small data based on the data length information carried by the first storage instruction, and allocate the corresponding flash memory based on the determined data size. address.
  • the data when the data length information is less than or equal to the preset first data amount threshold, the data can be determined to be small data; when the data length information is greater than the preset first data amount threshold , the data can be determined as big data.
  • the first data volume threshold may be the storage data volume of one flash memory page, or may be a customized data volume.
  • the detailed value of the first data volume threshold is not limited here. .
  • the CSP when the data to be stored is small data, the CSP can allocate only one flash memory page for the data. When the data to be stored is large data, the CSP can allocate multiple flash memory pages for the data. Flash pages, or allocate one or more Flash blocks.
  • the multiple flash memory pages may be flash memory pages with consecutive addresses, and the multiple flash memory blocks may be address Contiguous blocks of flash memory, so that a contiguous address segment can be allocated for this large data.
  • a second storage instruction can be generated every time a small data is written.
  • Multiple small data that need to be written continuously can be merged and then written, that is, a second save instruction can be generated after merging, thereby reducing the task load of the storage system, improving storage system performance, and reducing power consumption.
  • the information carried by the multiple first write instructions can be merged, and the information carried by the multiple first write instructions can be merged according to the merged information and locally maintained SSD resource information, a second storage command is generated and sent to the SSD, and then the SSD obtains each small data according to the corresponding starting source address and stores it in the allocated flash memory address.
  • the multiple small data when the starting source addresses of multiple small data are consecutive, can be allocated according to the arrangement order of the small data stored in the multiple starting source addresses. Multiple consecutive flash memory addresses, and the arrangement order of the small data stored in the multiple consecutive flash memory addresses is the same as the arrangement order of the small data stored in the multiple starting source addresses.
  • the amount of data required for each flash memory address can be obtained from an external requester. to the flash memory address. Therefore, it can be determined based on the starting source address of the entire storage object data and the offset of the partial data of the storage object to be stored each time in the entire storage object data. The starting source address of the part of data to be stored each time; thereby obtaining the corresponding data for storage based on the starting source address of the part of the data.
  • a second deposit instruction may be sent to each allocated flash memory address, or a second deposit instruction may be sent to multiple consecutive flash memory addresses. (i.e. address segment) sends a second deposit instruction.
  • the second deposit instruction may include but is not limited to an NVMe deposit instruction.
  • the second storage instruction may be an NVMe storage instruction, and the flash memory address carried by the NVMe storage instruction is the address of a flash memory page; or,
  • the second save command may be an extended NVMe save command.
  • the flash memory address carried by the extended NVMe save command is an address segment composed of the addresses of multiple consecutive flash memory pages.
  • the address segment may use a starting address. and data volume information representation.
  • the second deposit instruction may only include the starting source address of the storage object and the flash memory address, or may include both the starting source address of the storage object and the flash memory address (for example, multiple flash memory addresses).
  • the starting address of the page or flash memory block which also contains information on the data volume of the stored object.
  • the NVMe storage instruction when the second storage instruction is an NVMe storage instruction, can be an ordinary NVMe instruction, including: the starting source address of the storage object and the flash memory address; or,
  • the NVMe storage command may be an extended NVMe command, including: the starting source address of the storage object, data amount information, and flash memory address.
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the data can be stored through only one flash memory page. Therefore, one flash memory page can be allocated for the small data, and only the storage is included in the second store instruction.
  • the starting source address of the object and the address of the flash memory page are sufficient.
  • multiple flash memory pages are needed to store the data. Therefore, multiple flash memory pages can be allocated for the big data and accompanied by data amount information, for example, with the required flash memory pages.
  • the total amount, and the second storage instruction includes the starting source address of the storage object, the flash memory address (the starting address of at least one of the allocated flash memory page or flash memory blocks) and the data amount information.
  • the principle is the same and will not be repeated here.
  • the CSP will also receive a success response returned by the SSD after successfully receiving the second deposit instruction and successfully writing the data.
  • the embodiment of the present application provides a data storage method, which is applied to an SSD in a storage system.
  • the SSD communicates with the CSP in the storage system and the outside of the storage system through the PCIe bus.
  • the method may include steps S201-S202:
  • S201 Receive the second storage instruction based on the flash memory address sent by the CSP, and parse the starting source address of the data to be stored carried in the second storage instruction and the flash memory address in this SSD.
  • each flash memory address may receive a second storage instruction respectively, or multiple flash memory addresses with consecutive addresses (i.e., address segments) may be received. ) receives a second deposit instruction.
  • the second deposit instruction may include but is not limited to an NVMe deposit instruction.
  • the second deposit instruction may only include the starting source address of the storage object and the flash memory address, or may include both the starting source address of the storage object and the flash memory address (for example, multiple flash memory addresses).
  • the starting address of the page or flash memory block which also contains information on the data volume of the stored object.
  • the NVMe storage instruction when the second storage instruction is an NVMe storage instruction, can be an ordinary NVMe instruction, including: the starting source address of the storage object and the flash memory address; or,
  • the NVMe storage command can be an extended NVMe command, including: the starting source address of the storage object, data amount information and flash memory address;
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the data can be stored through only one flash memory page. Therefore, one flash memory page can be allocated for the small data, and only the storage is included in the second store instruction.
  • the starting source address of the object and the address of the flash memory page are sufficient.
  • multiple flash memory pages are needed to store the data. Therefore, multiple flash memory pages can be allocated for the big data and accompanied by data amount information, for example, with the required flash memory pages.
  • the total amount, and the second storage instruction includes the starting source address of the storage object, the flash memory address (the starting address of at least one of the allocated flash memory page or flash memory blocks) and the data amount information.
  • the principle is the same and will not be repeated here.
  • the second save command may be an NVMe save command
  • the flash memory address carried by the NVMe save command is the address of a flash memory page
  • Reading the data of the storage object from the outside according to the parsed starting source address and storing it in the parsed flash memory address includes: reading one of the storage objects from the outside according to the parsed starting source address.
  • the data of the size of the flash memory page is stored in the parsed address of the flash memory page.
  • the second save command may be an extended NVMe save command
  • the flash memory address carried by the extended NVMe save command is an address composed of the addresses of multiple consecutive flash memory pages. Segment, the address segment is represented by the starting address and data amount information;
  • Reading the data of the storage object from the outside according to the parsed starting source address and storing it in the parsed flash memory address includes: reading all the data from the outside according to the parsed starting source address and data amount information. The corresponding data amount of the storage object is described and stored in the parsed address segment.
  • the SSD after the SSD successfully receives the second deposit instruction sent by the CSP and successfully writes the data, it returns a success response to the CSP. It may be that a success response is returned after data is successfully written according to each second deposit instruction, or a success response is returned after data is successfully written according to all second deposit instructions.
  • the sixth aspect is a first aspect:
  • the embodiment of the present application provides a data reading method, which is applied to the CSP in the storage system.
  • the CSP communicates with the SSD in the storage system and the outside of the storage system through the PCIe bus, as shown in Figure 6.
  • the method may include steps S301-S302:
  • the CSP communicates with an external requester based on a point-to-point communication mechanism through the PCIe bus, and receives an external storage request, such as the above-mentioned first read instruction.
  • the first read instruction may include the need to read Retrieve the relevant information of the storage object.
  • the first read instruction may include, but is not limited to: an identification of the storage object and a starting address of data reception.
  • the SSD resource information may include but is not limited to: the addresses of all SSDs included in the storage system, the address of at least one of the flash memory pages and flash memory blocks in each SSD, the address of each flash memory page. Resource occupancy information, the identification and offset of the storage object corresponding to each occupied flash memory page, etc.
  • the CSP can query the flash memory address of the data of the storage object to be read in the SSD based on the identification of the storage object contained in the first read instruction, and combine the flash memory address with the external request The starting address of the party's data reception is carried in the second read command and sent to the SSD.
  • generating a second read instruction based on the flash memory address and sending it to the SSD based on the information carried by the first read instruction and the locally maintained SSD resource information may include:
  • Each second read instruction carries the information of the secondary read data in the SSD. Flash memory address and starting address for data reception.
  • the data of the storage object to be read may be big data, or may be small data.
  • the data of the storage object is big data, it is occupied (such as just full, or not occupied).
  • the second read instruction may only carry the address of the one or more complete flash memory pages or at least one of the flash memory blocks, as well as the address of the data received. initial address.
  • the data of the storage object is large data and occupies at least one of multiple consecutive flash memory pages and flash memory blocks, the start of at least one of the multiple consecutive flash memory pages and flash memory blocks can be carried in the second read instruction.
  • the second read instruction may carry the plurality of consecutive flash memory pages, the starting address of at least one of the flash memory blocks, the data amount information of the storage object, and the starting address of data reception.
  • the second read instruction not only carries the address of the flash memory page, It can also carry the offset of the data of the storage object to be read, so that the required data can be accurately read in the flash memory page according to the offset. Therefore, the second read instruction can carry the address and offset of the flash memory page. And the starting address of data reception.
  • a second read instruction when the CSP sends a second read instruction to the SSD, a second read instruction may be sent to each allocated flash memory address, or a second read instruction may be sent to multiple consecutive flash memory addresses. (i.e. address segment) sends a second read instruction.
  • the second read instruction may include but is not limited to an NVMe read instruction.
  • the second read instruction may be an NVMe read instruction, and the flash memory address carried by the NVMe read instruction is the address of a flash memory page; or,
  • the second read command may be an extended NVMe store command.
  • the flash memory address carried by the extended NVMe read command is an address segment composed of the addresses of one flash memory page or multiple consecutive flash memory pages.
  • the address segment is represented by Starting address and data volume information are indicated.
  • the NVMe read instruction when the second read instruction is an NVMe read instruction, the NVMe read instruction may be an ordinary NVMe instruction, including: the flash memory address of the storage object and the starting address of data reception;
  • the NVMe storage command may be an extended NVMe command, including: the flash memory address of the storage object, data amount information, and the starting address of data reception.
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64K, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the offset refers to the offset of the small data in a flash memory page relative to the flash memory address of the flash memory page, and the offset can be represented by two offsets.
  • small data may be stored only in one flash memory page, may completely occupy a flash memory page, or may only occupy a part of the flash memory page, and the other part may be occupied by other small data. Therefore, for small data that completely occupies one flash page, the second read The fetch instruction only contains the starting address of the data reception of the storage object and the address of the flash memory page. For small data that occupies one flash memory page with other small data, the data of the storage object can be included in the second read instruction. The received starting address, the address of the flash memory page and the offset of the small data are used by the SSD to read the data from the flash memory page and then intercept the required data from the read data based on the offset.
  • the second read instruction includes the starting address of the data reception of the storage object, the flash memory address (the starting address of at least one of the flash memory page and the flash memory block where the data is stored), and data amount information.
  • the principle is the same, and I will not repeat it here.
  • the seventh aspect is a first aspect:
  • the embodiment of the present application provides a data reading method, which is applied to the SSD in the storage system.
  • the SSD communicates with the CSP in the storage system and the outside of the storage system through the PCIe bus, as shown in Figure 7.
  • the method may include steps S401-S402:
  • the CSP can query the flash memory address of the data of the storage object to be read in the SSD based on the identification of the storage object contained in the first read instruction sent by the received external requester, and The flash memory address and the starting address of the external requester's data reception are carried in the second read command and sent to the SSD.
  • the data of the storage object to be read may be big data, or may be small data.
  • the data of the storage object is big data, it is occupied (such as just full, or not occupied).
  • the second read instruction may only carry the address of at least one of the one or more complete flash memory pages or flash memory blocks, so as to and the starting address of data reception.
  • the data of the storage object is large data and occupies at least one of multiple consecutive flash memory pages and flash memory blocks
  • the start of at least one of the multiple consecutive flash memory pages and flash memory blocks can be carried in the second read instruction. address, and use data amount information to indicate the number of at least one of flash memory pages and flash memory blocks.
  • the second read instruction can carry the starting address of at least one of the multiple consecutive flash memory pages and flash memory blocks, and the storage object.
  • the second read instruction not only carries the address of the flash memory page, It can also carry the offset of the data of the storage object to be read, so that the required data can be accurately read in the flash memory page according to the offset. Therefore, the second read instruction can carry the address and offset of the flash memory page. And the starting address of data reception.
  • a second read instruction when the CSP sends a second read instruction to the SSD, a second read instruction may be sent to each allocated flash memory address, or it may be directed to multiple consecutive flash memory addresses ( That is, the address segment) sends a second read instruction.
  • the second read instruction may include but is not limited to an NVMe read instruction.
  • the second read instruction may be an NVMe read instruction, and the flash memory address carried by the NVMe read instruction is the address of a flash memory page; or,
  • the second read command may be an extended NVMe store command.
  • the flash memory address carried by the extended NVMe read command is an address segment composed of the addresses of one flash memory page or multiple consecutive flash memory pages.
  • the address segment may be Indicated by starting address and data amount information.
  • the NVMe read instruction when the second read instruction is an NVMe read instruction, the NVMe read instruction may be an ordinary NVMe instruction, including: the flash memory address of the storage object and the starting address of data reception;
  • the NVMe storage command may be an extended NVMe command, including: the flash memory address of the storage object, data amount information, and the starting address of data reception.
  • the data amount information may include but is not limited to: total data capacity (eg, 32K, 64k, etc.), required flash memory pages, the total number of at least one of the flash memory blocks, etc.
  • the offset refers to the offset of the small data in a flash memory page relative to the flash memory address of the flash memory page, and the offset can be represented by two offsets.
  • small data may be stored only in one flash memory page, may completely occupy a flash memory page, or may only occupy a part of the flash memory page, and the other part may be occupied by other small data. Therefore, for small data that completely occupies one flash memory page, the second read instruction only contains the starting address of the data reception of the storage object and the address of the flash memory page.
  • Small data, in the second read command may include the starting address of the data reception of the storage object, the address of the flash memory page and the offset of the small data, which is used for the SSD to read the data from the flash memory page and then read from the The required data is intercepted based on the offset from the fetched data.
  • the second read instruction includes the starting address of the data reception of the storage object, the flash memory address (the starting address of at least one of the stored one or more flash memory pages and flash memory blocks) and the data amount information.
  • the principle is the same, and I will not repeat it here.
  • the second read instruction is an NVMe read instruction
  • the flash memory address carried by the NVMe read instruction is the address of a flash memory page or flash memory block
  • the method of reading the data of the storage object from the SSD based on the parsed flash memory address and storing it in the parsed starting address of external data reception may include: based on the parsed address of the flash memory page or flash memory block. Read all the data of the corresponding flash memory page or flash memory block from this SSD and store it in the parsed starting address of external data reception.
  • the SSD can store the corresponding one or more flash memory pages in the SSD based on the flash memory address. , all the data stored in at least one of the flash memory blocks is taken out and stored to the starting address of data reception.
  • the second read command may be an extended NVMe read command
  • the flash memory address carried by the extended NVMe read command is an address composed of the addresses of multiple consecutive flash memory pages. Segment, the address segment is represented by the starting address and data amount information;
  • Reading the data of the storage object from this SSD based on the parsed flash memory address and storing it in the parsed start address of external data reception may include: based on the parsed address segment and data amount information, Data corresponding to the amount of data of the storage object is read from this SSD and stored in the parsed starting address of external data reception.
  • the SSD can read the corresponding multiple flash memories according to the flash memory address and data amount information. All the data stored in at least one of the page and the flash memory block is taken out and stored to the starting address of data reception.
  • the SSD after the SSD successfully receives the second read instruction sent by the CSP and successfully reads the data, the SSD returns a success response to the CSP.
  • the eighth aspect is a first aspect:
  • the embodiment of the present application provides a CSP, as shown in Figure 8, which may include: a third PCIe bus interface 31, and a first logic circuit component 32 coupled with the third PCIe bus interface 31; the first logic circuit component 32 is configured to perform the data storage method described in the fourth aspect, and the data reading method described in the sixth aspect.
  • any embodiment in the foregoing fourth aspect and sixth aspect is applicable to the content of the eighth aspect, and will not be described again one by one.
  • the embodiment of the present application also provides an SSD main control chip 21, as shown in Figure 9, which may include: a fourth PCIe bus interface 41, and a second logic circuit component 42 coupled with the fourth PCIe bus interface 41;
  • the second logic circuit component 42 is configured to perform the data storage method described in the fifth aspect and the data reading method described in the seventh aspect.
  • Embodiments of the present application provide a non-volatile storage medium on which a computer program is stored.
  • the computer program is executed by a processor
  • the data storage methods described in the fourth and fifth aspects are executed, and the sixth aspect is and the data reading method described in the seventh aspect.
  • any of the foregoing embodiments from the first to seventh aspects are applicable to the contents of the tenth aspect, and will not be described again one by one.
  • computer storage media includes volatile and nonvolatile media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. removable, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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Abstract

一种存储***及其计算存储处理器、固体硬盘和数据读写方法，该存储***包括固态硬盘SSD和计算存储处理器CSP，SSD与CSP之间以及SSD、CSP与存储***外部之间通过高速串行计算机扩展总线标准PCIe总线点对点通信协议进行通信：CSP被配置为接收外部的第一操作指令，根据第一操作指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二操作指令并发送给SSD；SSD被配置为接收到所述第二操作指令后，根据第二操作指令携带的信息与外部交换所述存储对象的数据。

Description

存储***及其计算存储处理器、固体硬盘和数据读写方法
本申请要求于2022年8月17日提交中国专利局、申请号为202210985642.6、发明名称为“存储***及其计算存储处理器、固体硬盘和数据读写方法”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及数据存储技术，尤指一种存储***及其计算存储处理器、固体硬盘和数据读写方法。
背景技术
目前计算机存储领域的一些架构是基于CSP(Computational Storage Processor，计算存储处理器)做前端的存储架构，随着计算存储领域的发展，要求存储设备接收的对象存储或键值存储的指令不再是基于块地址的读写指令，因此，CSP做前端处理时，会有大量的数据流经CSP，多余的数据拷贝增加了CSP时延和功耗，为了基于目前已有的相关设备适应计算存储领域的发展，可以通过增加一个或多个CSP来解决该问题，但这一方案费效比很高，因此，亟需研究一种有效的解决方案。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请一些实施例提供了一种存储***，可以包括固态硬盘SSD和计算存储处理器CSP，所述SSD与CSP之间以及所述SSD、CSP与存储***的外部之间通过高速串行计算机扩展总线标准PCIe总线的点对点通信协议进行通信：
所述CSP被配置为接收外部基于存储对象的第一操作指令，根据所述第 一操作指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二操作指令并发送给SSD；
所述SSD被配置为接收到所述第二操作指令后，根据所述第二操作指令携带的信息与外部交换所述存储对象的数据；
其中，所述第一操作指令包括第一存入指令和第一读取指令，所述第二操作指令包括第二存入指令和第二读取指令。
本申请一些实施例提供了一种存储***中的计算存储处理器CSP，可以包括：
第一高速串行计算机扩展总线标准PCIe总线接口，被配置为与PCIe总线连接，以通过所述PCIe总线与所述存储***中的固态硬盘SSD及所述存储***的外部通信；
存储管理***，被配置为通过第一PCIe总线接口接收外部基于存储对象的第一操作指令，根据所述第一操作指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二操作指令并发送给SSD；其中，所述第一操作指令包括第一存入指令和第一读取指令，所述第二操作指令包括第二存入指令和第二读取指令；以及，
信息管理器，被配置为维护所述存储***中的SSD资源信息。
本申请一些实施例提供了一种存储***中的固态硬盘SSD，可以包括主控芯片和闪存芯片，所述主控芯片可以包括：
第二高速串行计算机扩展总线标准PCIe总线接口，被配置为与PCIe总线连接，以通过所述PCIe总线与所述存储***中的计算存储处理器CSP及所述存储***的外部通信；以及，
存储控制器，被配置为接收所述CSP发送的基于闪存地址的第二操作指令，根据所述第二操作指令携带的信息与外部交换存储对象的数据；其中，所述第二操作指令包括第二存入指令和第二读取指令。
本申请一些实施例提供了一种数据存入方法，应用于存储***中的计算存储处理器CSP，所述CSP通过高速串行计算机扩展总线标准PCIe总线与所述存储***中的固态硬盘SSD和所述存储***的外部通信，所述方法可以 包括：
接收外部基于存储对象的第一存入指令；
根据所述第一存入指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二存入指令并发送给SSD。
本申请一些实施例提供了一种数据存入方法，应用于存储***中的固态硬盘SSD，所述SSD通过高速串行计算机扩展总线标准PCIe总线与所述存储***中的计算存储处理器CSP和所述存储***的外部通信，所述方法可以包括：
接收CSP发送的基于闪存地址的第二存入指令，解析所述第二存入指令携带的此次要存入的数据的起始来源地址，及本SSD中的闪存地址；
根据解析出的所述起始来源地址，从外部读取所述存储对象的数据并存入解析出的所述闪存地址。
本申请一些实施例提供了一种数据读取方法，应用于存储***中的计算存储处理器CSP，所述CSP通过高速串行计算机扩展总线标准PCIe总线与所述存储***中的固态硬盘SSD和所述存储***的外部通信，所述方法可以包括：
接收外部基于存储对象的第一读取指令；
根据所述第一读取指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二读取指令并发送给SSD。
本申请一些实施例提供了一种数据读取方法，应用于存储***中的固态硬盘SSD，所述SSD通过高速串行计算机扩展总线标准PCIe总线与所述存储***中的计算存储处理器CSP和所述存储***的外部通信，所述方法可以包括：
接收所述CSP发送的基于闪存地址的第二读取指令，解析所述第二读取指令携带的此次要读取的数据在本SSD中的闪存地址以及数据接收的起始地址；
根据解析出的闪存地址，从本SSD中读取所述存储对象的数据并存入解析出的外部的数据接收的起始地址。
本申请一些实施例提供了一种计算存储处理器CSP，可以包括：第三高速串行计算机扩展总线标准PCIe总线接口，及与第三PCIe总线接口耦合的第一逻辑电路组件；所述第一逻辑电路组件被配置为执行第四方面所述的数据存入方法，以及第六方面所述的数据读取方法。
本申请一些实施例还提供了一种固态硬盘SSD的主控芯片，可以包括：第四高速串行计算机扩展总线标准PCIe总线接口，及与第四PCIe总线接口耦合的第二逻辑电路组件；所述第二逻辑电路组件被配置为执行第五方面所述的数据存入方法，以及第七方面所述的数据读取方法。
本申请一些实施例提供了一种非易失性存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时执行第四方面和第五方面所述的数据存入方法，以及第六和第七方面所述的数据读取方法。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释技术方案，并不构成对技术方案的限制。
图1为本申请实施例的存储***结构示意图；
图2为本申请实施例的存储***中的CSP第一组成框图；
图3为本申请实施例的存储***中的SSD第一组成框图；
图4为本申请实施例的CSP侧数据存入方法流程图；
图5为本申请实施例的SSD侧数据存入方法流程图；
图6为本申请实施例的CSP侧数据读取方法流程图；
图7为本申请实施例的SSD侧数据读取方法流程图；
图8为本申请实施例的存储***中的CSP第二组成框图；
图9为本申请实施例的存储***中的SSD第二组成框图。
具体实施方式
本申请描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本申请所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本申请包括并设想了与本领域普通技术人员已知的特征和元件的组合。本申请已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的独特的发明方案。任何实施例的任何特征或元件也可以与来自其它发明方案的特征或元件组合，以形成另一个由权利要求限定的独特的发明方案。因此，应当理解，在本申请中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本申请实施例的精神和范围内。
第一方面：
本申请一些实施例提供了一种存储***，如图1所示，可以包括固态硬盘(Solid-State Drive，SSD)和计算存储处理器(CSP)；
所述SSD与所述CSP之间以及所述SSD、所述CSP与存储***的外部之间可以通过高速串行计算机扩展总线标准(Peripheral Component Interconnect Express，PCIe)总线的点对点通信协议进行通信：
所述CSP被配置为接收外部基于存储对象的第一操作指令，根据所述第一操作指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二操作指令并发送给所述SSD；
所述SSD被配置为接收到所述第二操作指令后，根据所述第二操作指令携带的信息与外部交换所述存储对象的数据；
其中，所述第一操作指令包括第一存入指令和第一读取指令，所述第二操作指令包括第二存入指令和第二读取指令。
在本申请的示例性实施例中，存储***的外部可以包括一个或多个请求方。
在本申请的示例性实施例中，所述存储***中可以包括一个CSP和多个SSD，该一个CSP和多个SSD都接入到PCIe总线上，并通过点对点通信协议进行通信。
在本申请的示例性实施例中，所述CSP通过PCIe总线接收外部的存储请求，即上述的第一操作指令(所述第一操作指令可以为第一存入指令或第一读取指令)，该第一操作指令可以包含存储对象的相关信息，根据该存储对象的相关信息以及存储的每个SSD的资源信息可以对存储对象的数据进行SSD地址分配，或者查找存储对象的数据所存储的SSD地址等处理，并根据处理结果生成相应的第二操作指令(与上述的第一操作指令相对应，该所述第二操作指令为第二存入指令或第二读取指令，即第一操作指令为第一存入指令时，第二操作指令为第二存入指令，第一操作指令为第一读取指令时，第二操作指令为第二读取指令)，利用PCIe总线的点到点通讯机制，所述CSP可以将生成的第二操作指令发送给所分配到的或所查询到的SSD，从而使得SSD根据第二操作指令直接和外部请求方(此时也可以称为外部数据 交换方)交换数据，不再通过CSP，CSP与SSD之间仅进行指令的传输，不会有大量的数据流经CSP，CSP也不会拷贝多余数据，从而大幅度减小了CSP的工作量，降低了时延和功耗。
下面分别从写入数据和读取数据两个方面详细介绍本申请实施例方案。
在本申请的示例性实施例中，当外部发送的第一操作指令为第一存入指令时，该第一存入指令可以包括但不限于：存储对象的标识、数据长度信息和整个数据的起始来源地址。
在本申请的示例性实施例中，所述SSD资源信息包括SSD中的资源占用信息；所述CSP被配置为接收到第一存入指令后，通过以下方式生成基于闪存地址的第二操作指令并发送给SSD：
解析所述第一存入指令携带的存储对象的标识、数据长度信息和整个数据的起始来源地址；
根据所述数据长度信息和SSD中的资源占用信息，分配供所述存储对象的数据存入的一个或多个SSD中的闪存地址；以及根据所述存储对象的整个数据的起始来源地址、每次要存入的所述存储对象的部分数据在所述存储对象的整个数据中的偏移，确定每次要存入的部分数据的起始来源地址；
为分配有闪存地址的每一SSD生成一条或多条第二存入指令并发送给该SSD，每条第二存入指令携带该SSD此次要存入的数据的起始来源地址，及供数据存入的闪存地址。
在本申请的示例性实施例中，该闪存地址即SSD对外提供的任何形式的地址，例如：可以是闪存页、闪存块或存储块的地址，或者可以是闪存页、闪存块或存储块的地址段。当该闪存地址是存储块地址时，SSD对外提供逻辑地址，当该闪存地址是闪存页或闪存块的地址时，SSD对外提供物理地址的操作接口。在本申请实施例中以闪存地址为闪存页或闪存块的地址为例进行说明。
在本申请的示例性实施例中，SSD中的资源占用信息可以包括但不限于：存储***所包含的全部SSD的地址，每个SSD中的闪存页、闪存块至少之一的地址，每个闪存页的资源占用信息、每个被占用的闪存页对应的存储对 象的标识以及偏移，等等。
在本申请的示例性实施例中，CSP可以根据该资源占用信息确定出可存储当前待存储的存储对象数据的一个或多个SSD中的闪存地址，并根据待存储的存储对象的数据量大小为该存储对象分配一个或多个所述闪存地址。
在本申请的示例性实施例中，CSP可以根据第一存入指令携带的数据长度信息确定待存储的存储对象的数据为大数据还是小数据，并根据确定出的数据大小分配相应的闪存地址。但本公开实施例不限于此，可以将待存储的数据分为更多类，或者，不对待存储的数据进行大数据和小数据的分类，等等。
在本申请的示例性实施例中，当数据长度信息小于或等于预设的第一数据量阈值时，可以将该数据确定为小数据；当数据长度信息大于预设的第一数据量阈值时，可以将该数据确定为大数据。
在本申请的示例性实施例中，该第一数据量阈值可以为一个闪存页的存储数据量，或者，可以为自定义的其它数据量，在此对于第一数据量阈值的详细数值不做限定。
在本申请的示例性实施例中，当待存入的数据为小数据时，CSP可以仅为该数据分配一个闪存页，当待存入的数据为大数据时，CSP可以为该数据分配多个闪存页，或者，分配一个或多个闪存块。
在本申请的示例性实施例中，当CSP为大数据分配多个闪存页、多个闪存块至少之一时，该多个闪存页可以为地址连续的闪存页，该多个闪存块可以为地址连续的闪存块，从而可以为该大数据分配一个地址连续的地址段。
在本申请的示例性实施例中，当待存入的大量的存储对象均为小数据时，在每次写入一个小数据时可以生成一个第二存入指令。在另一实施例中可以对多个需要连续写入的小数据进行合并后再写入，即合并后生成一个第二存入指令即可，从而减少存储***的任务负载，提高存储***性能，降低功耗。
在本申请的示例性实施例中，例如，可以在接收到关于多个小数据的多个第一写入指令后，对该多个第一写入指令携带的信息进行合并，并根据合并后的信息和本地维护的SSD资源信息，生成一个第二存入指令并发送给 SSD，再由SSD根据相应的起始来源地址分别获取每个小数据并存储到所分配的闪存地址中。
在本申请的示例性实施例中，当多个小数据的起始来源地址是连续的时，可以根据该多个起始来源地址所存储的小数据的排列顺序，为该多个小数据分配多个连续的闪存地址，并且该多个连续的闪存地址所存储的小数据的排列顺序与多个起始来源地址所存储的小数据的排列顺序相同。
在本申请的示例性实施例中，当存储对象被分配到多个不同的SSD中，或同一SSD中的不同的闪存地址时，可以从外部请求方获取每个闪存地址所需的数据量存储到该闪存地址中，因此，可以根据整个所述存储对象的数据的起始来源地址、每次要存入的所述存储对象的部分数据在整个所述存储对象的数据中的偏移，确定每次要存入的部分数据的起始来源地址；从而根据该部分数据的起始来源地址获取相应的数据进行存储。
在本申请的示例性实施例中，在CSP向SSD发送第二存入指令时，可以向分配的每个闪存地址分别发送一个第二存入指令，或者，可以针对多个连续的闪存地址(即地址段)发送一条第二存入指令。
在本申请的示例性实施例中，该第二存入指令可以包括但不限于NVMe(Non-Volatile Memory express，易失性存储器)存入指令。
NVMe是目前市场上的主流SSD协议，它是基于PCIe总线物理层上的传输协议，特点是只发送读写指令，不直接指导数据交换。例如读指令只包括SSD的存储地址和数据接收的地址，这样SSD可以按照适合自己的顺序执行大量指令，需要进行数据传输时再通过PCIe的传输机制向接收地址传数据。
在本申请的示例性实施例中，所述SSD被配置为接收到第二存入指令后，通过以下方式与外部交换所述存储对象的数据：解析所述第二存入指令携带的起始来源地址和闪存地址，根据解析出的所述起始来源地址从外部读取所述存储对象的默认大小的数据，及将读取的数据存入解析出的所述闪存地址；或者，
所述CSP发送的第二存入指令还携带此次要存入的所述存储对象的数 据量信息，所述SSD被配置为接收到所述第二存入指令时，通过以下方式与外部交换所述存储对象的数据：解析所述第二存入指令携带的起始来源地址、闪存地址和数据量信息，根据解析出的所述起始来源地址和所述数据量信息，从外部读取所述存储对象的相应数据量的数据，及将读取的数据存入解析出的所述闪存地址。所述相应数据量即为所述数据量信息指示的数据量。
在本申请的示例性实施例中，第二存入指令可以仅包含存储对象的起始来源地址和闪存地址，或者，可以既包含存储对象的起始来源地址和闪存地址(例如，多个闪存页或闪存块的起始地址)，又包含存储对象的数据量信息。
在本申请的示例性实施例中，当第二存入指令为NVMe存入指令时，该NVMe存入指令可以为普通的NVMe指令，包括：存储对象的起始来源地址和闪存地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的起始来源地址、数据量信息和闪存地址。
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，例如，针对小数据，仅通过一个闪存页便可以存储该数据，因此，可以为该小数据分配一个闪存页，并在第二存入指令中仅包含存储对象的起始来源地址和该闪存页的地址即可。
在本申请的示例性实施例中，例如，针对大数据，需要多个闪存页存储该数据，因此，可以为该大数据分配多个闪存页并附带数据量信息，例如，附带所需闪存页的总数量，并在第二存入指令中包含存储对象的起始来源地址、闪存地址(分配的多个闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸可以是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
在本申请的示例性实施例中，当外部发送的第一操作指令为第一读取指 令时，该第一读取指令可以包括但不限于：存储对象的标识以及数据接收的起始地址。
在本申请的示例性实施例中，所述SSD资源信息包括存储对象的数据所存入的SSD中的闪存地址；所述CSP被配置为接收到第一读取指令后，通过以下方式生成基于闪存地址的第二操作指令并发送给SSD：
解析所述第一读取指令携带的存储对象的标识以及数据接收的起始地址；
根据所述存储对象的标识查阅预先保存的所述存储对象的数据所存入的一个或多个SSD中的闪存地址；
为存储有所述存储对象的数据的每一个SSD生成一条或多条第二读取指令并发送给该SSD，每条所述第二读取指令携带该SSD中此次要读取的数据的闪存地址以及数据接收的起始地址。
在本申请的示例性实施例中，CSP可以根据该第一读取指令中包含的存储对象的标识查询将要读取的存储对象的数据在SSD中的闪存地址，并将该闪存地址和外部请求方的数据接收的起始地址携带在第二读取指令中发送给SSD。
在本申请的示例性实施例中，待读取的存储对象的数据可能为大数据，或者可能为小数据，当该存储对象的数据为大数据，占用(如正好占满，或未占满存在浪费)了一个或多个完整的闪存页、闪存块至少之一时，可以仅在第二读取指令中携带该一个或多个闪存页、闪存块至少之一的地址，以及数据接收的起始地址。当该存储对象的数据为大数据，并且占用多个连续的闪存页、闪存块至少之一时，可以在第二读取指令中携带该多个连续的闪存页、闪存块至少之一的起始地址，并用数据量信息指示闪存页、闪存块至少之一的数量，因此，该第二读取指令中可以携带该多个连续的闪存页、闪存块至少之一的起始地址、该存储对象的数据量信息以及数据接收的起始地址。当该存储对象的数据为小数据，并且仅占用了一个闪存页的一部分空间，而且该闪存页的另一部分空间被其他数据占用时，在第二读取指令中不仅携带该闪存页的地址，还可以携带待读取的该存储对象的闪存地址的偏移，以便于根据该偏移在该闪存页中准确读取需要的数据，因此该第二读取指令可以携带闪存页的地址及其偏移，以及数据接收的起始地址。
在本申请的示例性实施例中，所述第二读取指令可以包含但不限于NVMe读取指令。
在本申请的示例性实施例中，所述第二读取指令可以是NVMe读取指令，所述NVMe读取指令携带的闪存地址是一个闪存页的地址；或者，
所述第二读取指令可以是扩展的NVMe存入指令，所述扩展的NVMe读取指令携带的闪存地址是多个连续闪存页的地址构成的一地址段，该地址段可以用起始地址和数据量信息表示。
在本申请的示例性实施例中，当第二读取指令为NVMe读取指令时，该NVMe读取指令可以为普通的NVMe指令，包括：存储对象的闪存地址和数据接收的起始地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的闪存地址、数据量信息和数据接收的起始地址。
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，该偏移是指一个闪存页中的小数据相对于该闪存页的闪存地址的偏移，该偏移可以用两个偏移量表示。
在本申请的示例性实施例中，针对小数据，可能仅存储在一个闪存页内，可能完全占有一个闪存页，或者，有可能仅占有该闪存页的一部分，另一部分由其他小数据占用，因此，对于完全占用一个闪存页的小数据，在第二读取指令中仅包含存储对象的数据接收的起始地址和该闪存页的地址即可，对于与其他小数据合占一个闪存页的小数据，在第二读取指令中可以包含存储对象的数据接收的起始地址、该闪存页的地址以及该小数据的偏移，用于SSD从该闪存页读取出数据以后再从读取的数据中根据该偏移截取所需的数据。
在本申请的示例性实施例中，针对大数据，需要多个闪存页存储该数据，因此，读取该大数据时可以附带数据量信息(如，附带所存储的闪存页的总数量)，并在第二读取指令中包含存储对象的数据接收的起始地址、闪存地址(所存储的一个或多个闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸可以是16kB，那么第 一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
在本申请的示例性实施例中，所述SSD被配置为接收到第二读取指令后，通过以下方式与外部交换所述存储对象的数据：解析所述第二读取指令携带的闪存地址和数据接收的起始地址，根据解析出的闪存地址从SSD中读取此次要读取的数据，并将读取的数据发送至外部的所述数据接收的起始地址。
在本申请的示例性实施例中，针对仅包含闪存地址和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址在本SSD中把相应的一个或多个闪存页、闪存块至少之一中存储的数据全部取出，并存储到数据接收的起始地址。
在本申请的示例性实施例中，所述CSP发送的第二读取指令还可以携带所述存储对象的数据量信息，所述SSD被配置为接收到第二读取指令时，通过以下方式与外部交换所述存储对象的数据：解析所述第二读取指令携带的闪存地址、数据接收的起始地址和数据量信息，根据解析出的闪存地址和所述数据量信息从SSD中读取此次待读取的数据，并将读取的数据发送至外部的所述数据接收的起始地址。
在本申请的示例性实施例中，针对包含闪存地址、数据量信息和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址和数据量信息把相应的多个闪存页、闪存块至少之一中存储的数据全部取出，并存储到数据接收的起始地址。
在本申请的示例性实施例中，所述CSP发送的第二读取指令还可以携带所述存储对象的闪存地址的偏移，所述SSD被配置为接收到第二读取指令时，通过以下方式与外部交换所述存储对象的数据：解析所述第二读取指令携带的闪存地址及其偏移，以及数据接收的起始地址，根据解析出的闪存地址及其偏移从一个闪存页中读取存储的部分数据，或者，根据解析出的闪存地址从一个闪存页中读取一页数据，并根据所述偏移从所述一页数据中截取所需要的数据，存入外部的所述数据接收的起始地址。
在本申请的示例性实施例中，针对包含闪存地址、偏移和数据接收的起 始地址的第二读取指令，所述SSD可以根据该闪存地址把相应的一个闪存页中存储的数据全部取出，并根据该偏移从读取出的数据中提取所需的数据，并将提取出的数据存储到数据接收的起始地址；或者，可以根据解析出的闪存地址及其偏移从一个闪存页中读取存储的部分数据。
在本申请的示例性实施例中，所述SSD还可以被配置为根据所述第二操作指令携带的信息与外部交换所述存储对象的数据成功之后，向所述CSP返回成功响应；
所述CSP还可以被配置为接收到发送的所有第二操作指令的成功响应后，向所述第一操作指令的发送方返回成功响应，并更新维护的SSD资源信息。
第二方面：
本申请实施例提供了一种存储***中的计算存储处理器，如图2所示，可以包括：
第一PCIe总线接口11，被配置为与PCIe总线连接，以通过所述PCIe总线与所述存储***中的固态硬盘SSD及所述存储***外部通信；
存储管理***12，被配置为通过所述第一PCIe总线接口11接收外部基于存储对象的第一操作指令，根据所述第一操作指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二操作指令并发送给SSD；其中，所述第一操作指令包括第一存入指令和第一读取指令，所述第二操作指令包括第二存入指令和第二读取指令；以及，
信息管理器13，被配置为维护所述存储***中的SSD资源信息。
在本申请的示例性实施例中，CSP的存储管理***12通过第一PCIe总线接口11接收外部的存储请求，即上述的第一操作指令(所述第一操作指令可以为第一存入指令或第一读取指令)，该第一操作指令可以包含存储对象的相关信息，根据该存储对象的相关信息以及信息管理器13存储的每个SSD的资源信息可以对存储对象的数据进行SSD地址分配，或者查找存储对象的数据所存储的SSD地址等处理，并根据处理结果生成相应的第二操作指令 (与上述的第一操作指令相对应，该第二操作指令为第二存入指令或第二读取指令)，利用PCIe总线的点到点通讯机制，存储管理***12可以将生成的第二操作指令发送给所分配到的或所查询到的SSD，从而使得SSD根据第二操作指令直接和外部请求方交换数据，不再通过CSP，CSP与SSD之间仅进行指令的传输，不会有大量的数据流经CSP，CSP也不会拷贝多余数据，从而大幅度减小了CSP的工作量，降低了时延和功耗。
下面分别从写入数据和读取数据两个方面详细介绍本申请实施例方案。
在本申请的示例性实施例中，所述存储管理***12可以包括存入处理器121，所述存入处理模块器121可以被配置为：
通过第一PCIe总线接口11接收外部的第一存入指令，解析所述第一存入指令携带的存储对象的标识、数据长度信息和整个数据的起始来源地址；
根据所述数据长度信息和SSD中的资源占用信息，分配供所述存储对象的数据存入的一个或多个SSD中的闪存地址；以及根据所述存储对象的整个数据的起始来源地址、每次要存入的所述存储对象的部分数据在所述存储对象的整个数据中的偏移，确定每次要存入的部分数据的起始来源地址；
为分配有闪存地址的每一SSD生成一条或多条第二存入指令并发送给该SSD，每条第二存入指令携带该SSD此次要存入的数据的起始来源地址，及供数据存入的闪存地址。
在本申请的示例性实施例中，该闪存地址即SSD对外提供的任何形式的地址，例如：可以是闪存页、闪存块或存储块的地址，也可以是闪存页、闪存块或存储块的地址段。当该闪存地址是存储块地址时，SSD对外提供逻辑地址，当该闪存地址是闪存页或闪存块的地址时，SSD对外提供物理地址的操作接口。在本申请实施例中以闪存地址为闪存页或闪存块的地址为例进行说明。
在本申请的示例性实施例中，当外部请求方发送的第一操作指令为第一存入指令时，该第一存入指令可以包括但不限于：存储对象的标识、数据长度信息和整个数据的起始来源地址。
在本申请的示例性实施例中，SSD中的资源占用信息可以包括但不限于： 存储***所包含的全部SSD的地址，每个SSD中的闪存页、闪存块至少之一的地址，每个闪存页的资源占用信息、每个被占用的闪存页对应的存储对象的标识以及偏移，等等。
在本申请的示例性实施例中，存入处理器121可以根据该资源占用信息确定出可存储当前待存储的存储对象数据的一个或多个SSD中的闪存地址，并根据待存储的存储对象的数据量大小为该存储对象分配一个或多个所述闪存地址。
在本申请的示例性实施例中，存入处理器121可以根据第一存入指令携带的数据长度信息确定待存储的存储对象的数据为大数据还是小数据，并根据确定出的数据大小分配相应的闪存地址。
在本申请的示例性实施例中，当数据长度信息小于或等于预设的第一数据量阈值时，可以将该数据确定为小数据；当数据长度信息大于预设的第一数据量阈值时，可以将该数据确定为大数据。该第一数据量阈值可以为一个闪存页的存储数据量，或者，可以为自定义的数据量，在此对于第一数据量阈值的详细数值不做限定。
在本申请的示例性实施例中，当待存入的数据为小数据时，存入处理器121可以仅为该数据分配一个闪存页，当待存入的数据为大数据时，存入处理器121可以为该数据分配多个闪存页，或者，分配一个或多个闪存块。
在本申请的示例性实施例中，当存入处理器121为大数据分配多个闪存页、多个闪存块至少之一时，该多个闪存页可以为地址连续的闪存页，该多个闪存块可以为地址连续的闪存块，从而可以为该大数据分配一个地址连续的地址段。
在本申请的示例性实施例中，当待存入的大量的存储对象均为小数据时，可以在每次写入一个小数据时生成一个第二存入指令。在另一实施例中，可以对多个需要连续写入的小数据进行合并后再写入，即合并后生成一个第二存入指令即可，从而减少存储***的任务负载，提高存储***性能，降低功耗。
在本申请的示例性实施例中，例如，可以在接收到关于多个小数据的多 个第一写入指令后，对该多个第一写入指令携带的信息进行合并，并根据合并后的信息和本地维护的SSD资源信息，生成一个第二存入指令并发送给SSD，再由SSD根据相应的起始来源地址分别获取每个小数据并存储到所分配的闪存地址中。
在本申请的示例性实施例中，当多个小数据的起始来源地址是连续的，可以根据该多个起始来源地址所存储的小数据的排列顺序，为该多个小数据分配多个连续的闪存地址，并且该多个连续的闪存地址所存储的小数据的排列顺序与多个起始来源地址所存储的小数据的排列顺序相同。
在本申请的示例性实施例中，当存储对象被分配到多个不同的SSD中，或同一SSD中的不同的闪存地址时，可以从外部请求方获取每个闪存地址所需的数据量存储到该闪存地址中，因此，可以根据整个所述存储对象的数据的起始来源地址、每次要存入的所述存储对象的部分数据在整个所述存储对象的数据中的偏移，确定每次要存入的部分数据的起始来源地址；从而根据该部分数据的起始来源地址获取相应的数据进行存储。
在本申请的示例性实施例中，在存入处理器121向SSD发送第二存入指令时，可以向分配的每个闪存地址分别发送一个第二存入指令，或者，可以针对多个地址连续的闪存地址(即地址段)发送一条第二存入指令。
在本申请的示例性实施例中，该第二存入指令可以包括但不限于NVMe存入指令。
在本申请的示例性实施例中，所述第二存入指令携带的闪存地址可以用一个闪存页的地址表示；
所述存入处理器121为分配有闪存地址的每一SSD生成一条或多条第二存入指令时，是对该SSD中分配的每一闪存页生成一条第二存入指令，携带要存入该闪存页的数据的起始来源地址，及该闪存页的地址。
在本申请的示例性实施例中，所述第二存入指令携带的闪存地址可以是多个连续闪存页的地址构成的一个地址段，该地址段用起始地址和数据量信息表示；
所述存入处理器121为分配有闪存地址的每一SSD生成一条或多条第二 存入指令时，可以是对该SSD中的每一地址段生成一条第二存入指令，携带要存入该地址段的数据的起始来源地址，及该地址段的起始地址和数据量信息。
在本申请的示例性实施例中，第二存入指令可以仅包含存储对象的起始来源地址和闪存地址，或者，可以既包含存储对象的起始来源地址和闪存地址(例如，多个闪存页或闪存块的起始地址)，又包含存储对象的数据量信息。
在本申请的示例性实施例中，当第二存入指令为NVMe存入指令时，该NVMe存入指令可以为普通的NVMe指令，包括：存储对象的起始来源地址和闪存地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的起始来源地址、数据量信息和闪存地址；
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，例如，针对小数据，仅通过一个闪存页便可以存储该数据，因此，可以为该小数据分配一个闪存页，并在第二存入指令中仅包含存储对象的起始来源地址和该闪存页的地址即可。
在本申请的示例性实施例中，例如，针对大数据，需要多个闪存页存储该数据，因此，可以为该大数据分配多个闪存页并附带数据量信息，例如，附带所需闪存页的总数量，并在第二存入指令中包含存储对象的起始来源地址、闪存地址(分配的闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸可以是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
在本申请的示例性实施例中，所述存入处理器121还被配置为，为分配有闪存地址的每一SSD生成一条或多条第二存入指令并发送给该SSD之后，在接收到发送的所有第二存入指令的成功响应后，向所述第一存入指令的发 送方返回成功响应，并通知所述信息管理器13记录所述存储对象的标识及所述分配的SSD中的闪存地址。
在本申请的示例性实施例中，所述存储管理***12可以包括读取处理器122，所述读取处理器122被配置为：
通过第一PCIe总线接口11接收外部的第一读取指令，解析所述第一读取指令携带的存储对象的标识以及数据接收的起始地址；
根据所述存储对象的标识查阅预先保存的所述存储对象的数据所存入的一个或多个SSD中的闪存地址；
为存储有所述存储对象的数据的每一个SSD生成一条或多条第二读取指令并发送给该SSD，每条第二读取指令携带该SSD中此次要读取的数据的闪存地址以及数据接收的起始地址。
在本申请的示例性实施例中，当外部请求方发送的第一操作指令为第一读取指令时，该第一读取指令可以包括但不限于：存储对象的标识以及数据接收的起始地址。
在本申请的示例性实施例中，CSP可以根据该第一读取指令中包含的存储对象的标识查询将要读取的存储对象的数据在SSD中的闪存地址，并将该闪存地址和外部请求方的数据接收的起始地址携带在第二读取指令中发送给SSD。
在本申请的示例性实施例中，待读取的存储对象的数据可能为大数据，或者可能为小数据，当该存储对象的数据为大数据，占用(如正好占满，或未占满存在浪费)了一个或多个完整的闪存页、闪存块至少之一时，可以仅在第二读取指令中携带该一个或多个闪存页、闪存块至少之一的地址，以及数据接收的起始地址。当该存储对象的数据为大数据，并且占用多个连续的闪存页、闪存块至少之一时，可以在第二读取指令中携带该多个连续的闪存页、闪存块至少之一的起始地址，并用数据量信息指示闪存页、闪存块至少之一的数量，因此，该第二读取指令中可以携带该多个连续的闪存页、闪存块至少之一的起始地址、该存储对象的数据量信息以及数据接收的起始地址。当该存储对象的数据为小数据，并且仅占用了一个闪存页的一部分空间，而 且该闪存页的另一部分空间被其他数据占用时，在第二读取指令中不仅携带该闪存页的地址，还可以携带待读取的该存储对象的数据的偏移，以便于根据该偏移在该闪存页中准确读取需要的数据，因此该第二读取指令可以携带闪存页的地址、偏移以及数据接收的起始地址。
在本申请的示例性实施例中，所述第二读取指令可以包含但不限于NVMe读取指令。
在本申请的示例性实施例中，所述第二读取指令可以是NVMe读取指令，所述NVMe读取指令携带的闪存地址是一个闪存页的地址；或者，
所述第二读取指令可以是扩展的NVMe存入指令，所述扩展的NVMe读取指令携带的闪存地址是一个闪存页或多个连续闪存页的地址构成的一地址段，该地址段可以用起始地址和数据量信息表示。
在本申请的示例性实施例中，当第二读取指令为NVMe读取指令时，该NVMe读取指令可以为普通的NVMe指令，包括：存储对象的闪存地址和数据接收的起始地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的闪存地址、数据量信息和数据接收的起始地址。
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，该偏移是指一个闪存页中的小数据相对于该闪存页的闪存地址的偏移，该偏移可以用两个偏移量表示。
在本申请的示例性实施例中，针对小数据，可能仅存储在一个闪存页内，可能完全占有一个闪存页，或者，有可能仅占有该闪存页的一部分，另一部分由其他小数据占用，因此，对于完全占用一个闪存页的小数据，在第二读取指令中仅包含存储对象的数据接收的起始地址和该闪存页的地址即可，对于与其他小数据合占一个闪存页的小数据，在第二读取指令中可以包含存储对象的数据接收的起始地址、该闪存页的地址以及该小数据的偏移，用于SSD从该闪存页读取出数据以后再从读取的数据中根据该偏移截取所需的数据。
在本申请的示例性实施例中，针对大数据，需要多个闪存页存储该数据，因此，读取该大数据时可以附带数据量信息(如，附带所存储的闪存页的总 数量)，并在第二读取指令中包含存储对象的数据接收的起始地址、闪存地址(存储数据的闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸可以是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
在本申请的示例性实施例中，所述第二读取指令携带的闪存地址可以用一个闪存页的地址表示；
所述读取处理器122为存储有所述此次要读取数据的每一SSD生成一条或多条第二读取指令时，可以是对该SSD中分配的每一闪存页生成一条第二读取指令，携带要读取的该闪存页的地址以及数据接收的起始地址。
在本申请的示例性实施例中，针对仅包含闪存地址和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址在本SSD中把相应的一个或多个闪存页、闪存块至少之一中存储的数据全部取出，并存储到数据接收的起始地址。
在本申请的示例性实施例中，所述第二读取指令携带的闪存地址可以用一个闪存页的地址表示；
所述读取处理器122为存储有所述此次要读取数据的每一SSD生成一条或多条第二读取指令时，可以是对该SSD中分配的每一闪存页生成一条第二读取指令，携带待读取的该闪存页的地址、此次待读取数据相对于所述闪存页的地址的偏移以及数据接收的起始地址。
在本申请的示例性实施例中，针对包含闪存地址、偏移和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址把相应的一个闪存页中存储的数据全部取出，并根据该偏移从读取出的数据中提取所需的数据，并将提取出的数据存储到数据接收的起始地址；或者，根据解析出的闪存地址及其偏移从一个闪存页中读取存储的部分数据。
在本申请的示例性实施例中，所述第二读取指令携带的闪存地址可以是多个连续闪存页的地址构成的一个地址段，该地址段用起始地址和数据量信 息表示；
所述读取处理器122为分配有闪存地址的每一SSD生成一条或多条第二读取指令时，可以是对该SSD中的每一地址段生成一条第二读取指令，携带要读取的该地址段的起始地址和数据量信息，以及数据接收的起始地址。
在本申请的示例性实施例中，针对包含闪存地址、数据量信息和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址和数据量信息把相应的多个闪存页、闪存块至少之一中存储的数据全部取出，并存储到数据接收的起始地址。
第三方面：
本申请实施例提供了一种存储***中的固态硬盘SSD，如图3所示，可以包括主控芯片21和闪存芯片22，所述主控芯片21可以包括：
第二PCIe总线接口211，被配置为与PCIe总线连接，以通过所述PCIe总线与所述存储***中的CSP及所述存储***的外部通信；以及，
存储控制器212，被配置为接收所述CSP发送的基于闪存地址的第二操作指令，根据所述第二操作指令携带的信息与外部交换存储对象的数据；其中，所述第二操作指令包括第二存入指令和第二读取指令。
在本申请的示例性实施例中，CSP通过第一PCIe总线接口11接收外部的存储请求，即上述的第一操作指令，该第一操作指令可以包含存储对象的相关信息，根据该存储对象的相关信息以及存储的每个SSD的资源信息可以对存储对象的数据进行SSD地址分配，或者查找存储对象的数据所存储的SSD地址等处理，并根据处理结果生成相应的第二操作指令，利用PCIe总线的点到点通讯机制，CSP可以将生成的第二操作指令通过第二PCIe总线接口211发送给所分配到的或所查询到的SSD的主控芯片21，从而使得SSD的主控芯片21的存储控制器212根据第二操作指令直接和外部请求方交换数据，不再通过CSP，CSP与SSD之间仅进行指令的传输，不会有大量的数据流经CSP，CSP也不会拷贝多余数据，从而大幅度减小了CSP的工作量，降低了时延和功耗。
下面分别从写入数据和读取数据两个方面详细介绍本申请实施例方案。
在本申请的示例性实施例中，所述存储控制器212可以包括存入控制器2121，所述存入控制器2121被配置为：
接收所述第二存入指令，解析所述第二存入指令携带的所述存储对象的数据的起始来源地址以及在本SSD中进行数据存储的闪存地址；
根据解析出的起始来源地址从外部读取所述存储对象的数据，将读取的数据存入解析出的闪存地址。
在本申请的示例性实施例中，在存入处理器121向SSD发送第二存入指令时，可以向分配的每个闪存地址分别发送一个第二存入指令，也可以针对多个地址连续的闪存地址(即地址段)发送一条第二存入指令。
在本申请的示例性实施例中，该第二存入指令可以包括但不限于NVMe存入指令。
在本申请的示例性实施例中，该闪存地址即SSD对外提供的任何形式的地址，例如：可以是闪存页、闪存块或存储块的地址，也可以是闪存页、闪存块或存储块的地址段。当该闪存地址是存储块地址时，SSD对外提供逻辑地址，当该闪存地址是闪存页或闪存块的地址时，SSD对外提供物理地址的操作接口。在本申请实施例中以闪存地址为闪存页或闪存块的地址为例进行说明。
在本申请的示例性实施例中，所述解析出的闪存地址可以是一个闪存页的地址；所述存入控制器2121可以是被配置为根据解析出的起始来源地址，从外部读取所述存储对象的一个闪存页大小的数据并存入解析出的该闪存页的地址；或者，
所述解析出的闪存地址可以是用起始来源地址和数据量信息表示的一个地址段；该地址段包含多个完整闪存页的地址；所述存入控制器2121可以是被配置为根据解析出的起始来源地址和数据量信息，从外部读取所述存储对象的相应数据量的数据并存入解析出的该地址段。
在本申请的示例性实施例中，第二存入指令可以仅包含存储对象的起始来源地址和闪存地址，或者，可以既包含存储对象的起始来源地址和闪存地 址(例如，多个闪存页或闪存块的起始地址)，又包含存储对象的数据量信息。
在本申请的示例性实施例中，当第二存入指令为NVMe存入指令时，该NVMe存入指令可以为普通的NVMe指令，包括：存储对象的起始来源地址和闪存地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的起始来源地址、数据量信息和闪存地址。
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，例如，针对小数据，仅通过一个闪存页便可以存储该数据，因此，可以为该小数据分配一个闪存页，并在第二存入指令中仅包含存储对象的起始来源地址和该闪存页的地址即可。
在本申请的示例性实施例中，例如，针对大数据，需要多个闪存页存储该数据，因此，可以为该大数据分配多个闪存页并附带数据量信息，例如，附带所需闪存页的总数量，并在第二存入指令中包含存储对象的起始来源地址、闪存地址(分配的一个或多个闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
在本申请的示例性实施例中，所述存入控制器2121还被配置为在成功接收到CSP发送的第二存入指令并写入数据成功后，向CSP返回成功响应。可以是根据每条第二存入指令写入数据成功后返回一次成功响应，或者，根据所有第二存入指令写入数据成功后返回成功响应。
在本申请的示例性实施例中，所述存储控制器212可以包括读取控制器2122，所述读取控制器2122被配置为：
接收所述第二读取指令，解析所述第二读取指令携带的所述存储对象的数据在本SSD中进行数据存储的闪存地址以及数据接收的起始地址；
根据解析出的闪存地址从本SSD中读取所述存储对象的数据，将读取的数据存入外部的数据接收的起始地址。
在本申请的示例性实施例中，CSP可以根据该第一读取指令中包含的存储对象的标识查询将要读取的存储对象的数据在SSD中的闪存地址，并将该闪存地址和外部请求方的数据接收的起始地址携带在第二读取指令中发送给SSD。
在本申请的示例性实施例中，待读取的存储对象的数据可能为大数据，或者，可能为小数据，当该存储对象的数据为大数据，占用(如正好占满，或未占满存在浪费)了一个或多个完整的闪存页、闪存块至少之一时，可以仅在第二读取指令中携带该一个或多个闪存页、闪存块至少之一的地址，以及数据接收的起始地址。当该存储对象的数据为大数据，并且占用多个连续的闪存页、闪存块至少之一时，可以在第二读取指令中携带该多个连续的闪存页、闪存块至少之一的起始地址，并用数据量信息指示闪存页、闪存块至少之一的数量，因此，该第二读取指令中可以携带该多个连续的闪存页、闪存块至少之一的起始地址、该存储对象的数据量信息以及数据接收的起始地址。当该存储对象的数据为小数据，并且仅占用了一个闪存页的一部分空间，而且该闪存页的另一部分空间被其他数据占用时，在第二读取指令中不仅携带该闪存页的地址，还可以携带待读取的该存储对象的数据的偏移，以便于根据该偏移在该闪存页中准确读取需要的数据，因此该第二读取指令可以携带闪存页的地址、偏移以及数据接收的起始地址。
在本申请的示例性实施例中，所述第二读取指令可以包含但不限于NVMe读取指令。
在本申请的示例性实施例中，所述第二读取指令可以是NVMe读取指令，所述NVMe读取指令携带的闪存地址是一个闪存页的地址；或者，
所述第二读取指令可以是扩展的NVMe存入指令，所述扩展的NVMe读取指令携带的闪存地址是多个连续闪存页的地址构成的一地址段，该地址段可以用起始地址和数据量信息表示。
在本申请的示例性实施例中，当第二读取指令为NVMe读取指令时，该NVMe读取指令可以为普通的NVMe指令，包括：存储对象的闪存地址和数 据接收的起始地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的闪存地址、数据量信息和数据接收的起始地址。
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，该偏移是指一个闪存页中的小数据针对该闪存页的闪存地址的偏移，该偏移可以用两个偏移量表示。
在本申请的示例性实施例中，针对小数据，可能仅存储在一个闪存页内，可能完全占有一个闪存页，或者，有可能仅占有该闪存页的一部分，另一部分由其他小数据占用，因此，对于完全占用一个闪存页的小数据，在第二读取指令中仅包含存储对象的数据接收的起始地址和该闪存页的地址即可，对于与其他小数据合占一个闪存页的小数据，在第二读取指令中可以包含存储对象的数据接收的起始地址、该闪存页的地址以及该小数据的偏移，用于SSD从该闪存页读取出数据以后再从读取的数据中根据该偏移截取所需的数据。
在本申请的示例性实施例中，针对大数据，需要多个闪存页存储该数据，因此，读取该大数据时可以附带数据量信息(如，附带所存储的闪存页的总数量)，并在第二读取指令中包含存储对象的数据接收的起始地址、闪存地址(存储数据的闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸可以是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
在本申请的示例性实施例中，所述解析出的闪存地址可以是一个闪存页的地址；所述读取控制器2122是被配置为根据解析出的该闪存页的地址，从本SSD读取所述存储对象的数据并存入解析出的数据接收的起始地址。
在本申请的示例性实施例中，针对仅包含闪存地址和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址在本SSD中把相应的一个或多个闪存页、闪存块至少之一中存储的数据全部取出，并存储到数据接收的起始地址。
在本申请的示例性实施例中，所述解析出的闪存地址可以是用起始地址和数据量信息表示的一个地址段；所述读取控制器2122是被配置为根据解析出的起始地址和数据量信息，从本SSD读取所述存储对象的相应数据量的数据并存入解析出的数据接收的起始地址。
在本申请的示例性实施例中，针对包含闪存地址、数据量信息和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址和数据量信息把相应的多个闪存页、闪存块至少之一中存储的数据全部取出，并存储到数据接收的起始地址。
在本申请的示例性实施例中，所述解析出的闪存地址可以是一个闪存页的地址以及此次要读取数据相对于所述闪存页的地址的偏移；所述读取控制器2122是被配置为根据解析出的所述闪存页的地址从本SSD读取一页数据，并根据所述偏移从所述一页数据中截取所需要的数据存入解析出的数据接收的起始地址。
在本申请的示例性实施例中，针对包含闪存地址、偏移和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址把相应的一个闪存页中存储的数据全部取出，并根据该偏移从读取出的数据中提取所需的数据，并将提取出的数据存储到数据接收的起始地址；或者，根据解析出的闪存地址及其偏移从一个闪存页中读取存储的部分数据。
在本申请的示例性实施例中，所述读取控制器2122还被配置为在成功接收到CSP发送的第二读取指令并读取数据成功后，向CSP返回成功响应。
第四方面：
本申请实施例提供了一种数据存入方法，应用于存储***中的CSP，所述CSP可以通过高PCIe总线与所述存储***中的SSD和所述存储***外部通信，如图4所示，所述方法可以包括步骤S101-S102：
S101、接收外部基于存储对象的第一存入指令。
在本申请的示例性实施例中，CSP通过PCIe总线基于点对点通信机制与外部请求方进行通信，接收外部的存储请求，例如上述的第一存入指令， 该第一存入指令可以包含存储对象的相关信息。
在本申请的示例性实施例中，该第一存入指令可以包括但不限于：存储对象的标识、数据长度信息和整个数据的起始来源地址。
S102、根据所述第一存入指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二存入指令并发送给SSD。
在本申请的示例性实施例中，所述SSD资源信息可以包括SSD中的资源占用信息；所述SSD中的资源占用信息可以包括但不限于：存储***所包含的全部SSD的地址，每个SSD中的闪存页、闪存块至少之一的地址，每个闪存页的资源占用信息、每个被占用的闪存页对应的存储对象的标识以及偏移，等等。
在本申请的示例性实施例中，CSP根据该存储对象的相关信息以及存储的每个SSD的资源信息可以对存储对象的数据进行SSD地址分配等处理，并根据处理结果生成相应的第二存入指令，利用PCIe总线的点到点通讯机制，CSP可以将生成的第二操作指令发送给所分配到的SSD，从而使得SSD根据第二存入指令直接和外部请求方交换数据，不再通过CSP，CSP与SSD之间仅进行指令的传输，不会有大量的数据流经CSP，CSP也不会拷贝多余数据，从而大幅度减小了CSP的工作量，降低了时延和功耗。
在本申请的示例性实施例中，所述根据所述第一存入指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二存入指令并发送给SSD，可以包括：
解析所述第一存入指令携带的存储对象的标识、数据长度信息和整个数据的起始来源地址；
根据所述数据长度信息和SSD中的资源占用信息，分配供所述存储对象的数据存入的一个或多个SSD中的闪存地址；以及根据所述整个数据的起始来源地址、每次要存入的所述存储对象的部分数据在所述存储对象的整个数据中的偏移，确定每次要存入的部分数据的起始来源地址；
为分配有闪存地址的每一SSD生成一条或多条第二存入指令并发送给该SSD，每条第二存入指令携带该SSD此次要存入的数据的起始来源地址， 及供数据存入的闪存地址。
在本申请的示例性实施例中，该闪存地址即SSD对外提供的任何形式的地址，例如：可以是闪存页、闪存块或存储块的地址，或者，可以是闪存页、闪存块或存储块的地址段。当该闪存地址是存储块地址时，SSD对外提供逻辑地址，当该闪存地址是闪存页或闪存块的地址时，SSD对外提供物理地址的操作接口。在本申请实施例中以闪存地址为闪存页或闪存块的地址为例进行说明。
在本申请的示例性实施例中，CSP可以根据该SSD的资源占用信息确定出可存储当前待存储的存储对象数据的一个或多个SSD中的闪存地址，并根据待存储的存储对象的数据量大小为该存储对象分配一个或多个所述闪存地址。
在本申请的示例性实施例中，CSP可以首先根据第一存入指令携带的数据长度信息确定待存储的存储对象的数据为大数据还是小数据，并根据确定出的数据大小分配相应的闪存地址。
在本申请的示例性实施例中，当数据长度信息小于或等于预设的第一数据量阈值时，可以将该数据确定为小数据；当数据长度信息大于预设的第一数据量阈值时，可以将该数据确定为大数据。
在本申请的示例性实施例中，该第一数据量阈值可以为一个闪存页的存储数据量，或者，可以为自定义的数据量，在此对于第一数据量阈值的详细数值不做限定。
在本申请的示例性实施例中，当待存入的数据为小数据时，CSP可以仅为该数据分配一个闪存页，当待存入的数据为大数据时，CSP可以为该数据分配多个闪存页，或者，分配一个或多个闪存块。
在本申请的示例性实施例中，当CSP为大数据分配多个闪存页、多个闪存块至少之一时，该多个闪存页可以为地址连续的闪存页，该多个闪存块可以为地址连续的闪存块，从而可以为该大数据分配一个地址连续的地址段。
在本申请的示例性实施例中，当待存入的大量的存储对象均为小数据时，可以在每次写入一个小数据时均生成一个第二存入指令，在另一实施例中， 可以对多个需要连续写入的小数据进行合并后再写入，即合并后生成一个第二存入指令即可，从而减少存储***的任务负载，提高存储***性能，降低功耗。
在本申请的示例性实施例中，例如，可以在接收到关于多个小数据的多个第一写入指令后，对该多个第一写入指令携带的信息进行合并，并根据合并后的信息和本地维护的SSD资源信息，生成一个第二存入指令并发送给SSD，再由SSD根据相应的起始来源地址分别获取每个小数据并存储到所分配的闪存地址中。
在本申请的示例性实施例中，当多个小数据的起始来源地址是连续的时，可以根据该多个起始来源地址所存储的小数据的排列顺序，为该多个小数据分配多个连续的闪存地址，并且该多个连续的闪存地址所存储的小数据的排列顺序与多个起始来源地址所存储的小数据的排列顺序相同。
在本申请的示例性实施例中，当存储对象被分配到多个不同的SSD中，或同一SSD中的不同的闪存地址时，可以从外部请求方获取每个闪存地址所需的数据量存储到该闪存地址中，因此，可以根据整个所述存储对象的数据的起始来源地址、每次要存入的所述存储对象的部分数据在整个所述存储对象的数据中的偏移，确定每次要存入的部分数据的起始来源地址；从而根据该部分数据的起始来源地址获取相应的数据进行存储。
在本申请的示例性实施例中，在CSP向SSD发送第二存入指令时，可以向分配的每个闪存地址分别发送一个第二存入指令，或者，可以针对多个地址连续的闪存地址(即地址段)发送一条第二存入指令。
在本申请的示例性实施例中，该第二存入指令可以包括但不限于NVMe存入指令。
在本申请的示例性实施例中，所述第二存入指令可以是NVMe存入指令，所述NVMe存入指令携带的闪存地址是一个闪存页的地址；或者，
所述第二存入指令可以是扩展的NVMe存入指令，所述扩展的NVMe存入指令携带的闪存地址是多个连续闪存页的地址构成的一地址段，该地址段可以用起始地址和数据量信息表示。
在本申请的示例性实施例中，第二存入指令可以仅包含存储对象的起始来源地址和闪存地址，或者，可以既包含存储对象的起始来源地址和闪存地址(例如，多个闪存页或闪存块的起始地址)，又包含存储对象的数据量信息。
在本申请的示例性实施例中，当第二存入指令为NVMe存入指令时，该NVMe存入指令可以为普通的NVMe指令，包括：存储对象的起始来源地址和闪存地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的起始来源地址、数据量信息和闪存地址。
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，例如，针对小数据，仅通过一个闪存页便可以存储该数据，因此，可以为该小数据分配一个闪存页，并在第二存入指令中仅包含存储对象的起始来源地址和该闪存页的地址即可。
在本申请的示例性实施例中，例如，针对大数据，需要多个闪存页存储该数据，因此，可以为该大数据分配多个闪存页并附带数据量信息，例如，附带所需闪存页的总数量，并在第二存入指令中包含存储对象的起始来源地址、闪存地址(分配的一个或多个闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
在本申请的示例性实施例中，CSP还会接收SSD在成功接收到第二存入指令并写入数据成功返回的成功响应。
第五方面：
本申请实施例提供了一种数据存入方法，应用于存储***中的SSD，所述SSD通过PCIe总线与所述存储***中的CSP和所述存储***的外部通信， 如图5所示，所述方法可以包括步骤S201-S202：
S201、接收CSP发送的基于闪存地址的第二存入指令，解析所述第二存入指令携带的此次要存入的数据的起始来源地址，及本SSD中的闪存地址。
在本申请的示例性实施例中，在SSD接收CSP发送第二存入指令时，可以是每个闪存地址分别接收一个第二存入指令，也可以多个地址连续的闪存地址(即地址段)接收一条第二存入指令。
在本申请的示例性实施例中，该第二存入指令可以包括但不限于NVMe存入指令。
在本申请的示例性实施例中，第二存入指令可以仅包含存储对象的起始来源地址和闪存地址，或者，可以既包含存储对象的起始来源地址和闪存地址(例如，多个闪存页或闪存块的起始地址)，又包含存储对象的数据量信息。
在本申请的示例性实施例中，当第二存入指令为NVMe存入指令时，该NVMe存入指令可以为普通的NVMe指令，包括：存储对象的起始来源地址和闪存地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的起始来源地址、数据量信息和闪存地址；
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，例如，针对小数据，仅通过一个闪存页便可以存储该数据，因此，可以为该小数据分配一个闪存页，并在第二存入指令中仅包含存储对象的起始来源地址和该闪存页的地址即可。
在本申请的示例性实施例中，例如，针对大数据，需要多个闪存页存储该数据，因此，可以为该大数据分配多个闪存页并附带数据量信息，例如，附带所需闪存页的总数量，并在第二存入指令中包含存储对象的起始来源地址、闪存地址(分配的一个或多个闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，例如，每一个闪存块的尺寸是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地 址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
S202、根据解析出的起始来源地址，从外部读取所述存储对象的数据并存入解析出的闪存地址。
在本申请的示例性实施例中，所述第二存入指令可以是NVMe存入指令，所述NVMe存入指令携带的闪存地址是一个闪存页的地址；
所述根据解析出的起始来源地址，从外部读取所述存储对象的数据并存入解析出的闪存地址，包括：根据解析出的起始来源地址从外部读取所述存储对象的一个闪存页大小的数据，存入解析出的该闪存页的地址。
在本申请的示例性实施例中，所述第二存入指令可以是扩展的NVMe存入指令，所述扩展的NVMe存入指令携带的闪存地址是多个连续闪存页的地址构成的一地址段，该地址段用起始地址和数据量信息表示；
所述根据解析出的起始来源地址，从外部读取所述存储对象的数据并存入解析出的闪存地址，包括：根据解析出的起始来源地址和数据量信息，从外部读取所述存储对象的相应数据量的数据并存入解析出的地址段。
在本申请的示例性实施例中，SSD在成功接收到CSP发送的第二存入指令并写入数据成功后，向CSP返回成功响应。可以是根据每条第二存入指令写入数据成功后返回一次成功响应，或者，根据所有第二存入指令写入数据成功后返回成功响应。
第六方面：
本申请实施例提供了一种数据读取方法，应用于存储***中的CSP，所述CSP通过PCIe总线与所述存储***中的SSD和所述存储***的外部通信，如图6所示，所述方法可以包括步骤S301-S302：
S301、接收外部基于存储对象的第一读取指令。
在本申请的示例性实施例中，CSP通过PCIe总线基于点对点通信机制与外部请求方进行通信，接收外部的存储请求，例如上述的第一读取指令，该第一读取指令可以包含需要读取的存储对象的相关信息。
在本申请的示例性实施例中，该第一读取指令可以包括但不限于：存储对象的标识以及数据接收的起始地址。
S302、根据所述第一读取指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二读取指令并发送给SSD。
在本申请的示例性实施例中，SSD资源信息可以包括但不限于：存储***所包含的全部SSD的地址，每个SSD中的闪存页、闪存块至少之一的地址，每个闪存页的资源占用信息、每个被占用的闪存页对应的存储对象的标识以及偏移，等等。
在本申请的示例性实施例中，CSP可以根据该第一读取指令中包含的存储对象的标识查询将要读取的存储对象的数据在SSD中的闪存地址，并将该闪存地址以及外部请求方的数据接收的起始地址携带在第二读取指令中发送给SSD。
在本申请的示例性实施例中，所述根据所述第一读取指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二读取指令并发送给SSD，可以包括：
解析所述第一读取指令携带的存储对象的标识以及数据接收的起始地址；
根据所述存储对象的标识查阅预先保存的此次要读取数据所存入的一个或多个SSD中的闪存地址；
为存储有所述此次要读取数据的每一个SSD生成一条或多条第二读取指令并发送给该SSD，每条第二读取指令携带该SSD中此次要读取的数据的闪存地址以及数据接收的起始地址。
在本申请的示例性实施例中，待读取的存储对象的数据可能为大数据，或者，可能为小数据，当该存储对象的数据为大数据，占用(如正好占满，或未占满存在浪费)了一个或多个完整的闪存页、闪存块至少之一时，可以仅在第二读取指令中携带该一个或多个闪存页、闪存块至少之一的地址，以及数据接收的起始地址。当该存储对象的数据为大数据，并且占用多个连续的闪存页、闪存块至少之一时，可以在第二读取指令中携带该多个连续的闪存页、闪存块至少之一的起始地址，并用数据量信息指示闪存页、闪存块至 少之一的数量，因此，该第二读取指令中可以携带该多个连续的闪存页、闪存块至少之一的起始地址、该存储对象的数据量信息以及数据接收的起始地址。当该存储对象的数据为小数据，并且仅占用了一个闪存页的一部分空间，而且该闪存页的另一部分空间被其他数据占用时，在第二读取指令中不仅携带该闪存页的地址，还可以携带待读取的该存储对象的数据的偏移，以便于根据该偏移在该闪存页中准确读取需要的数据，因此该第二读取指令可以携带闪存页的地址、偏移以及数据接收的起始地址。
在本申请的示例性实施例中，在CSP向SSD发送第二读取指令时，可以向分配的每个闪存地址分别发送一个第二读取指令，或者，可以针对多个地址连续的闪存地址(即地址段)发送一条第二读取指令。
在本申请的示例性实施例中，该第二读取指令可以包括但不限于NVMe读取指令。
在本申请的示例性实施例中，所述第二读取指令可以是NVMe读取指令，所述NVMe读取指令携带的闪存地址是一个闪存页的地址；或者，
所述第二读取指令可以是扩展的NVMe存入指令，所述扩展的NVMe读取指令携带的闪存地址是一个闪存页或多个连续闪存页的地址构成的一地址段，该地址段用起始地址和数据量信息表示。
在本申请的示例性实施例中，当第二读取指令为NVMe读取指令时，该NVMe读取指令可以为普通的NVMe指令，包括：存储对象的闪存地址和数据接收的起始地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的闪存地址、数据量信息和数据接收的起始地址。
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64K等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，该偏移是指一个闪存页中的小数据相对于该闪存页的闪存地址的偏移，该偏移可以用两个偏移量表示。
在本申请的示例性实施例中，针对小数据，可能仅存储在一个闪存页内，可能完全占有一个闪存页，或者，有可能仅占有该闪存页的一部分，另一部分由其他小数据占用，因此，对于完全占用一个闪存页的小数据，在第二读 取指令中仅包含存储对象的数据接收的起始地址和该闪存页的地址即可，对于与其他小数据合占一个闪存页的小数据，在第二读取指令中可以包含存储对象的数据接收的起始地址、该闪存页的地址以及该小数据的偏移，用于SSD从该闪存页读取出数据以后再从读取的数据中根据该偏移截取所需的数据。
在本申请的示例性实施例中，针对大数据，需要多个闪存页存储该数据，因此，读取该大数据时可以附带数据量信息(如，附带所存储的闪存页的总数量)，并在第二读取指令中包含存储对象的数据接收的起始地址、闪存地址(存储数据的闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸可以是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
第七方面：
本申请实施例提供了一种数据读取方法，应用于存储***中的SSD，所述SSD通过PCIe总线与所述存储***中的CSP和所述存储***的外部通信，如图7所示，所述方法可以包括步骤S401-S402：
S401、接收CSP发送的基于闪存地址的第二读取指令，解析所述第二读取指令携带的此次要读取的数据在本SSD中的闪存地址以及数据接收的起始地址。
在本申请的示例性实施例中，CSP可以根据接收到的外部请求方发送的第一读取指令中包含的存储对象的标识查询将要读取的存储对象的数据在SSD中的闪存地址，并将该闪存地址以及外部请求方的数据接收的起始地址携带在第二读取指令中发送给SSD。
在本申请的示例性实施例中，待读取的存储对象的数据可能为大数据，或者，可能为小数据，当该存储对象的数据为大数据，占用(如正好占满，或未占满存在浪费)了一个或多个完整的闪存页、闪存块至少之一时，可以仅在第二读取指令中携带该一个或多个闪存页、闪存块至少之一的地址，以 及数据接收的起始地址。当该存储对象的数据为大数据，并且占用多个连续的闪存页、闪存块至少之一时，可以在第二读取指令中携带该多个连续的闪存页、闪存块至少之一的起始地址，并用数据量信息指示闪存页、闪存块至少之一的数量，因此，该第二读取指令中可以携带该多个连续的闪存页、闪存块至少之一的起始地址、该存储对象的数据量信息以及数据接收的起始地址。当该存储对象的数据为小数据，并且仅占用了一个闪存页的一部分空间，而且该闪存页的另一部分空间被其他数据占用时，在第二读取指令中不仅携带该闪存页的地址，还可以携带待读取的该存储对象的数据的偏移，以便于根据该偏移在该闪存页中准确读取需要的数据，因此该第二读取指令可以携带闪存页的地址、偏移以及数据接收的起始地址。
在本申请的示例性实施例中，在CSP向SSD发送第二读取指令时，可以向分配的每个闪存地址分别发送一个第二读取指令，也可以针对多个地址连续的闪存地址(即地址段)发送一条第二读取指令。
在本申请的示例性实施例中，该第二读取指令可以包括但不限于NVMe读取指令。
在本申请的示例性实施例中，所述第二读取指令可以是NVMe读取指令，所述NVMe读取指令携带的闪存地址是一个闪存页的地址；或者，
所述第二读取指令可以是扩展的NVMe存入指令，所述扩展的NVMe读取指令携带的闪存地址是一个闪存页或多个连续闪存页的地址构成的一地址段，该地址段可以用起始地址和数据量信息表示。
在本申请的示例性实施例中，当第二读取指令为NVMe读取指令时，该NVMe读取指令可以为普通的NVMe指令，包括：存储对象的闪存地址和数据接收的起始地址；或者，该NVMe存入指令可以为扩展的NVMe指令，包括：存储对象的闪存地址、数据量信息和数据接收的起始地址。
在本申请的示例性实施例中，该数据量信息可以包含但不限于：数据总容量(例如，32K、64k等)、所需的闪存页、闪存块至少之一的总数量等。
在本申请的示例性实施例中，该偏移是指一个闪存页中的小数据相对于该闪存页的闪存地址的偏移，该偏移可以用两个偏移量表示。
在本申请的示例性实施例中，针对小数据，可能仅存储在一个闪存页内，可能完全占有一个闪存页，或者，有可能仅占有该闪存页的一部分，另一部分由其他小数据占用，因此，对于完全占用一个闪存页的小数据，在第二读取指令中仅包含存储对象的数据接收的起始地址和该闪存页的地址即可，对于与其他小数据合占一个闪存页的小数据，在第二读取指令中可以包含存储对象的数据接收的起始地址、该闪存页的地址以及该小数据的偏移，用于SSD从该闪存页读取出数据以后再从读取的数据中根据该偏移截取所需的数据。
在本申请的示例性实施例中，针对大数据，需要多个闪存页存储该数据，因此，读取该大数据时可以附带数据量信息(如，附带所存储的闪存页的总数量)，并在第二读取指令中包含存储对象的数据接收的起始地址、闪存地址(所存储的一个或多个闪存页、闪存块至少之一的起始地址)以及数据量信息。
在本申请的示例性实施例中，每一个闪存块的尺寸可以是16kB，那么第一个闪存块的起始地址＝原起始地址，第二个闪存块的起始地址＝原起始地址+16kB，依次类推，可以确定出任何一个闪存块的起始地址，对于闪存页，道理相同，在此不再一一赘述。
S402、根据解析出的闪存地址，从本SSD中读取所述存储对象的数据并存入解析出的外部的数据接收的起始地址。
在本申请的示例性实施例中，所述第二读取指令是NVMe读取指令，所述NVMe读取指令携带的闪存地址是一个闪存页或闪存块的地址；
所述根据解析出的闪存地址，从本SSD中读取所述存储对象的数据并存入解析出的外部的数据接收的起始地址，可以包括：根据解析出的闪存页或闪存块的地址从本SSD读取相应的闪存页或闪存块的全部数据，并存入解析出的外部的数据接收的起始地址。
在本申请的示例性实施例中，针对仅包含闪存地址和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址在本SSD中把相应的一个或多个闪存页、闪存块至少之一中存储的数据全部取出，并存储到数据接收的起始地址。
在本申请的示例性实施例中，所述第二读取指令可以是扩展的NVMe读取指令，所述扩展的NVMe读取指令携带的闪存地址是多个连续闪存页的地址构成的一地址段，该地址段用起始地址和数据量信息表示；
所述根据解析出的闪存地址，从本SSD中读取所述存储对象的数据并存入解析出的外部的数据接收的起始地址，可以包括：根据解析出的地址段和数据量信息，从本SSD中读取所述存储对象的相应数据量的数据并存入解析出的外部的数据接收的起始地址。
在本申请的示例性实施例中，针对包含闪存地址、数据量信息和数据接收的起始地址的第二读取指令，所述SSD可以根据该闪存地址和数据量信息把相应的多个闪存页、闪存块至少之一中存储的数据全部取出，并存储到数据接收的起始地址。
在本申请的示例性实施例中，SSD在成功接收到CSP发送的第二读取指令并读取数据成功后，向CSP返回成功响应。
第八方面：
本申请实施例提供了一种CSP，如图8所示，可以包括：第三PCIe总线接口31，及与第三PCIe总线接口31耦合的第一逻辑电路组件32；所述第一逻辑电路组件32被配置为执行第四方面所述的数据存入方法，以及第六方面所述的数据读取方法。
在本申请的示例性实施例中，前述的第四方面和第六方面中的任何实施例均适用于该第八方面的内容中，在此不再一一赘述。
第九方面：
本申请实施例还提供了一种SSD的主控芯片21，如图9所示，可以包括：第四PCIe总线接口41，及与第四PCIe总线接口41耦合的第二逻辑电路组件42；所述第二逻辑电路组件42被配置为执行第五方面所述的数据存入方法，以及第七方面所述的数据读取方法。
在本申请的示例性实施例中，前述的第一方面至第七方面中的任何实施 例均适用于该第九方面的内容中，在此不再一一赘述。
第十方面：
本申请实施例提供了一种非易失性存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时执行第四方面和第五方面所述的数据存入方法，以及第六和第七方面所述的数据读取方法。
在本申请的示例性实施例中，前述的第一方面至第七方面中的任何实施例均适用于该第十方面的内容中，在此不再一一赘述。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、***、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。

Claims (36)

  1. 一种存储***，包括固态硬盘SSD和计算存储处理器CSP，所述SSD与CSP之间以及所述SSD、CSP与存储***的外部之间通过高速串行计算机扩展总线标准PCIe总线的点对点通信协议进行通信：
    所述CSP被配置为接收外部基于存储对象的第一操作指令，根据所述第一操作指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二操作指令并发送给SSD；
    所述SSD被配置为接收到所述第二操作指令后，根据所述第二操作指令携带的信息与外部交换所述存储对象的数据；
    其中，所述第一操作指令包括第一存入指令和第一读取指令，所述第二操作指令包括第二存入指令和第二读取指令。
  2. 如权利要求1所述的存储***，其中，所述SSD资源信息包括SSD中的资源占用信息；
    所述CSP被配置为接收到第一存入指令后，通过以下方式生成基于闪存地址的第二操作指令并发送给SSD：
    解析所述第一存入指令携带的存储对象的标识、数据长度信息和整个数据的起始来源地址；
    根据所述数据长度信息和SSD中的资源占用信息，分配供所述存储对象的数据存入的一个或多个SSD中的闪存地址；以及根据所述整个数据的起始来源地址、每次要存入的所述存储对象的部分数据在所述存储对象的整个数据中的偏移，确定每次要存入的部分数据的起始来源地址；
    为分配有闪存地址的每一SSD生成一条或多条第二存入指令并发送给该SSD，每条所述第二存入指令携带该SSD此次要存入的数据的起始来源地址，及供数据存入的闪存地址。
  3. 如权利要求2所述的存储***，其中，
    所述SSD被配置为接收到第二存入指令后，通过以下方式与外部交换所述存储对象的数据：解析所述第二存入指令携带的起始来源地址和闪存地址， 根据解析出的所述起始来源地址从外部读取所述存储对象的默认大小的数据，及将读取的数据存入解析出的所述闪存地址；或者，
    所述CSP发送的第二存入指令还携带此次要存入的所述存储对象的数据量信息，所述SSD被配置为接收到第二存入指令时，通过以下方式与外部交换所述存储对象的数据：解析所述第二存入指令携带的起始来源地址、闪存地址和数据量信息，根据解析出的所述起始来源地址和所述数据量信息，从外部读取所述存储对象的相应数据量的数据，及将读取的数据存入解析出的所述闪存地址。
  4. 如权利要求1所述的存储***，其中，
    所述SSD资源信息包括存储对象的数据所存入的SSD中的闪存地址；
    所述CSP被配置为接收到第一读取指令后，通过以下方式生成基于闪存地址的第二操作指令并发送给SSD：
    解析所述第一读取指令携带的存储对象的标识以及数据接收的起始地址；
    根据所述存储对象的标识查阅预先保存的所述存储对象的数据所存入的一个或多个SSD中的闪存地址；
    为存储有所述存储对象的数据的每一个SSD生成一条或多条第二读取指令并发送给该SSD，每条所述第二读取指令携带该SSD中此次要读取的数据的闪存地址以及数据接收的起始地址。
  5. 如权利要求4所述的存储***，其中，
    所述SSD被配置为接收到第二读取指令后，通过以下方式与外部交换所述存储对象的数据：解析所述第二读取指令携带的所述闪存地址和所述数据接收的起始地址，根据解析出的所述闪存地址从一个或多个SSD中读取此次要读取的数据，并将读取的数据发送至外部的所述数据接收的起始地址；或者，
    所述CSP发送的第二读取指令还携带所述存储对象的数据量信息，所述SSD被配置为接收到第二读取指令时，通过以下方式与外部交换所述存储对象的数据：解析所述第二读取指令携带的所述闪存地址、所述数据接收的起始地址和所述数据量信息，根据解析出的所述闪存地址和所述数据量信息从 SSD中读取此次要读取的数据，并将读取的数据发送至外部的所述数据接收的起始地址；或者，
    所述CSP发送的第二读取指令还携带所述存储对象的闪存地址的偏移，所述SSD被配置为接收到第二读取指令时，通过以下方式与外部交换所述存储对象的数据：解析所述第二读取指令携带的所述闪存地址及其偏移、所述数据接收的起始地址，根据解析出的所述闪存地址及其偏移从一个闪存页中读取存储的部分数据，存入外部的所述数据接收的起始地址；或者，读出闪存页的全部数据，根据所述偏移从所述全部数据中截取所需要的数据存入外部所述数据接收的起始地址。
  6. 如权利要求1所述的存储***，其中
    所述SSD还被配置为根据所述第二操作指令携带的信息与外部交换所述存储对象的数据成功之后，向所述CSP返回成功响应；
    所述CSP还被配置为接收到发送的所有第二操作指令的成功响应后，向所述第一操作指令的发送方返回成功响应，并更新所述本地维护的SSD资源信息。
  7. 一种存储***中的计算存储处理器CSP，包括：
    第一高速串行计算机扩展总线标准PCIe总线接口，被配置为与PCIe总线连接，以通过所述PCIe总线与所述存储***中的固态硬盘SSD及所述存储***的外部通信；
    存储管理***，被配置为通过第一PCIe总线接口接收外部基于存储对象的第一操作指令，根据所述第一操作指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二操作指令并发送给SSD；其中，所述第一操作指令包括第一存入指令和第一读取指令，所述第二操作指令包括第二存入指令和第二读取指令；以及，
    信息管理器，被配置为维护所述存储***中的SSD资源信息。
  8. 如权利要求7所述的CSP，其中：
    所述SSD资源信息包括SSD中的资源占用信息；
    所述存储管理***包括存入处理器，所述存入处理器被配置为：
    通过所述第一PCIe总线接口接收外部的第一存入指令，解析所述第一存入指令携带的存储对象的标识、数据长度信息和整个数据的起始来源地址；
    根据所述数据长度信息和SSD中的资源占用信息，分配供所述存储对象的数据存入的一个或多个SSD中的闪存地址；以及根据所述整个数据的起始来源地址、每次要存入的所述存储对象的部分数据在所述存储对象的整个数据中的偏移，确定每次要存入的部分数据的起始来源地址；
    为分配有闪存地址的每一SSD生成一条或多条第二存入指令并发送给该SSD，每条所述第二存入指令携带该SSD此次要存入的数据的起始来源地址，及供数据存入的闪存地址。
  9. 如权利要求8所述的CSP，其中，
    所述第二存入指令携带的闪存地址用一个闪存页的地址表示；
    所述存入处理器为分配有闪存地址的每一SSD生成一条或多条第二存入指令时，是对该SSD中分配的每一闪存页生成一条第二存入指令，携带要存入该闪存页的数据的起始来源地址，及该闪存页的地址。
  10. 如权利要求8所述的CSP，其中，
    所述第二存入指令携带的闪存地址是一个闪存页或多个连续闪存页的地址构成的一个地址段，该地址段用起始地址和数据量信息表示；
    所述存入处理器为分配有闪存地址的每一SSD生成一条或多条第二存入指令时，是对该SSD中的每一地址段生成一条第二存入指令，携带要存入该地址段的数据的起始来源地址，及该地址段的起始地址和数据量信息。
  11. 如权利要求8所述的CSP，其中，
    所述存入处理器还被配置为，为分配有闪存地址的每一SSD生成一条或多条第二存入指令并发送给该SSD之后，在接收到发送的所有第二存入指令的成功响应后，向所述第一存入指令的发送方返回成功响应，并通知所述信息管理器记录所述存储对象的标识及所述分配的SSD中的闪存地址。
  12. 如权利要求7所述的CSP，其中，
    所述SSD资源信息包括存储对象的数据所存入的SSD中的闪存地址；
    所述存储管理***包括读取处理器，所述读取处理器被配置为：
    通过所述第一PCIe总线接口接收外部的第一读取指令，解析所述第一读取指令携带的存储对象的标识以及数据接收的起始地址；
    根据所述存储对象的标识查阅预先保存的所述存储对象的数据所存入的一个或多个SSD中的闪存地址；
    为存储有所述存储对象的数据的每一个SSD生成一条或多条第二读取指令并发送给该SSD，每条所述第二读取指令携带该SSD中此次要读取的数据的闪存地址以及数据接收的起始地址。
  13. 如权利要求12所述的CSP，其中，
    所述第二读取指令携带的闪存地址用一个闪存页的地址表示；
    所述读取处理器为存储有所述此次要读取数据的每一SSD生成一条或多条第二读取指令时，是对该SSD中分配的每一闪存页生成一条第二读取指令，携带要读取的该闪存页的地址以及数据接收的起始地址。
  14. 如权利要求12所述的CSP，其中，
    所述第二读取指令携带的闪存地址用一个闪存页的地址表示；
    所述读取处理器为存储有所述此次要读取数据的每一SSD生成一条或多条第二读取指令时，是对该SSD中分配的每一闪存页生成一条第二读取指令，携带要读取的该闪存页的地址、此次要读取数据在所述闪存页的存储数据中的偏移以及数据接收的起始地址。
  15. 如权利要求12所述的CSP，其中，
    所述第二读取指令携带的闪存地址是一个闪存页或多个连续闪存页的地址构成的一个地址段，该地址段用起始地址和数据量信息表示；
    所述读取处理器为分配有闪存地址的每一SSD生成一条或多条第二读取指令时，是对该SSD中的每一地址段生成一条第二读取指令，携带要读取的该地址段的起始地址和数据量信息，以及数据接收的起始地址。
  16. 一种存储***中的固态硬盘SSD，包括主控芯片和闪存芯片，所述主控芯片包括：
    第二高速串行计算机扩展总线标准PCIe总线接口，被配置为与PCIe总线连接，以通过所述PCIe总线与所述存储***中的计算存储处理器CSP及所述存储***的外部通信；以及，
    存储控制器，被配置为接收所述CSP发送的基于闪存地址的第二操作指令，根据所述第二操作指令携带的信息与外部交换存储对象的数据；其中，所述第二操作指令包括第二存入指令和第二读取指令。
  17. 如权利要求16所述的SSD，其中，
    所述存储控制器包括存入控制器，所述存入控制器被配置为：
    接收所述第二存入指令，解析所述第二存入指令携带的所述存储对象的数据的起始来源地址以及在本SSD中进行数据存储的闪存地址；
    根据解析出的起始来源地址从外部读取所述存储对象的数据，将读取的数据存入解析出的闪存地址。
  18. 如权利要求17所述的SSD，其中，
    所述解析出的闪存地址是一个闪存页的地址；所述存入控制器是被配置为根据解析出的起始来源地址，从外部读取所述存储对象的一个闪存页大小的数据并存入解析出的该闪存页的地址；或者，
    所述解析出的闪存地址是用起始地址和数据量信息表示的一个地址段；该地址段包含多个完整闪存页的地址；所述存入控制器是被配置为根据解析出的起始来源地址和数据量信息，从外部读取所述存储对象的相应数据量的数据并存入解析出的该地址段。
  19. 如权利要求16所述的SSD，其中，
    所述存储控制器包括读取控制器，所述读取控制器被配置为：
    接收所述第二读取指令，解析所述第二读取指令携带的所述存储对象的数据在本SSD中进行数据存储的闪存地址以及数据接收的起始地址；
    根据解析出的闪存地址从本SSD中读取所述存储对象的数据，将读取的数据存入外部的数据接收的起始地址。
  20. 如权利要求19所述的SSD，其中，
    所述解析出的闪存地址是一个闪存页的地址；所述读取控制器是被配置为根据解析出的该闪存页的地址，从本SSD读取所述存储对象的数据并存入解析出的数据接收的起始地址；或者，
    所述解析出的闪存地址是用起始地址和数据量信息表示的一个地址段；该地址段包含多个完整闪存页的地址；所述读取控制器是被配置为根据解析出的起始地址和数据量信息，从本SSD读取所述存储对象的相应数据量的数据并存入解析出的数据接收的起始地址。
  21. 如权利要求19所述的SSD，其中，
    所述解析出的闪存地址是一个闪存页的地址以及此次要读取数据相对于所述闪存页的地址的偏移；所述读取控制器是被配置为根据解析出的闪存地址及其偏移从一个闪存页中读取存储的部分数据，或者，根据解析出的所述闪存页的地址从本SSD中读取该闪存页的全部数据，并根据所述偏移从读取的所述全部数据中截取所需要的数据存入解析出的数据接收的起始地址。
  22. 一种数据存入方法，应用于存储***中的计算存储处理器CSP，所述CSP通过高速串行计算机扩展总线标准PCIe总线与所述存储***中的固态硬盘SSD和所述存储***的外部通信，所述方法包括：
    接收外部基于存储对象的第一存入指令；
    根据所述第一存入指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二存入指令并发送给SSD。
  23. 如权利要求22所述的数据存入方法，其中，
    所述SSD资源信息包括SSD中的资源占用信息；
    所述根据所述第一存入指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二存入指令并发送给SSD，包括：
    解析所述第一存入指令携带的存储对象的标识、数据长度信息和整个数据的起始来源地址；
    根据所述数据长度信息和所述SSD中的资源占用信息，分配供所述存储对象的数据存入的一个或多个SSD中的闪存地址；以及根据所述整个数据的起始来源地址、每次要存入的所述存储对象的部分数据在所述存储对象的整 个数据中的偏移，确定每次要存入的部分数据的起始来源地址；
    为分配有闪存地址的每一SSD生成一条或多条第二存入指令并发送给该SSD，每条所述第二存入指令携带该SSD此次要存入的数据的起始来源地址，及供数据存入的闪存地址。
  24. 如权利要求23所述的数据存入方法，其中，
    所述第二存入指令是NVMe存入指令，所述NVMe存入指令携带的闪存地址是一个闪存页的地址；或者，
    所述第二存入指令是扩展的NVMe存入指令，所述扩展的NVMe存入指令携带的闪存地址是一个闪存页或多个连续闪存页的地址构成的一地址段，该地址段用起始地址和数据量信息表示。
  25. 一种数据存入方法，应用于存储***中的固态硬盘SSD，所述SSD通过高速串行计算机扩展总线标准PCIe总线与所述存储***中的计算存储处理器CSP和所述存储***的外部通信，所述方法包括：
    接收所述CSP发送的基于闪存地址的第二存入指令，解析所述第二存入指令携带的此次要存入的数据的起始来源地址，及本SSD中的闪存地址；
    根据解析出的所述起始来源地址，从外部读取所述存储对象的数据并存入解析出的所述闪存地址。
  26. 如权利要求25所述的数据存入方法，其中
    所述第二存入指令是NVMe存入指令，所述NVMe存入指令携带的所述闪存地址是一个闪存页的地址；
    所述根据解析出的所述起始来源地址，从外部读取所述存储对象的数据并存入解析出的所述闪存地址，包括：根据解析出的所述起始来源地址从外部读取所述存储对象的一个闪存页大小的数据，存入解析出的该闪存页的地址。
  27. 如权利要求25所述的数据存入方法，其中，
    所述第二存入指令是扩展的NVMe存入指令，所述扩展的NVMe存入指令携带的所述闪存地址是多个连续闪存页的地址构成的一地址段，该地址 段用起始地址和数据量信息表示；
    所述根据解析出的所述起始来源地址，从外部读取所述存储对象的数据并存入解析出的所述闪存地址，包括：根据解析出的所述起始来源地址和所述数据量信息，从外部读取所述存储对象的相应数据量的数据并存入解析出的所述地址段。
  28. 一种数据读取方法，应用于存储***中的计算存储处理器CSP，所述CSP通过高速串行计算机扩展总线标准PCIe总线与所述存储***中的固态硬盘SSD和所述存储***的外部通信，所述方法包括：
    接收外部基于存储对象的第一读取指令；
    根据所述第一读取指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二读取指令并发送给SSD。
  29. 如权利要求28所述的数据读取方法，其中，
    所述SSD资源信息包括存储对象的数据所存入的SSD中的闪存地址；
    所述根据所述第一读取指令携带的信息及本地维护的SSD资源信息，生成基于闪存地址的第二读取指令并发送给SSD，包括：
    解析所述第一读取指令携带的存储对象的标识以及数据接收的起始地址；
    根据所述存储对象的标识查阅预先保存的此次要读取数据所存入的SSD中的闪存地址；
    为存储有所述此次要读取数据的每一个SSD生成一条或多条第二读取指令并发送给该SSD，每条所述第二读取指令携带该SSD中此次要读取的数据的闪存地址以及数据接收的起始地址。
  30. 如权利要求29所述的数据读取方法，其中，
    所述第二读取指令是NVMe读取指令，所述NVMe读取指令携带的所述闪存地址是一个闪存页的地址；或者，
    所述第二读取指令是扩展的NVMe存入指令，所述扩展的NVMe读取指令携带的所述闪存地址是一个闪存页或多个连续闪存页的地址构成的一地址段，该地址段用起始地址和数据量信息表示。
  31. 一种数据读取方法，应用于存储***中的固态硬盘SSD，所述SSD通过高速串行计算机扩展总线标准PCIe总线与所述存储***中的计算存储处理器CSP和所述存储***的外部通信，所述方法包括：
    接收所述CSP发送的基于闪存地址的第二读取指令，解析所述第二读取指令携带的此次要读取的数据在本SSD中的闪存地址以及数据接收的起始地址；
    根据解析出的所述闪存地址，从本SSD中读取所述存储对象的数据并存入解析出的外部的所述数据接收的起始地址。
  32. 如权利要求31所述的数据读取方法，其中，
    所述第二读取指令是NVMe读取指令，所述NVMe读取指令携带的所述闪存地址是一个闪存页的地址；
    所述根据解析出的所述闪存地址，从本SSD中读取所述存储对象的数据并存入解析出的外部的所述数据接收的起始地址，包括：根据解析出的所述闪存页的地址从本SSD读取一页数据，存入解析出的外部的所述数据接收的起始地址。
  33. 如权利要求31所述的数据读取方法，其中，
    所述第二读取指令是扩展的NVMe读取指令，所述扩展的NVMe读取指令携带的所述闪存地址是多个连续闪存页的地址构成的一地址段，该地址段用起始地址和数据量信息表示；
    所述根据解析出的所述闪存地址，从本SSD中读取所述存储对象的数据并存入解析出的外部的所述数据接收的起始地址，包括：根据解析出的所述地址段和所述数据量信息，从本SSD中读取所述存储对象的相应数据量的数据并存入解析出的外部的所述数据接收的起始地址。
  34. 一种计算存储处理器CSP，包括：第三高速串行计算机扩展总线标准PCIe总线接口，及与所述第三PCIe总线接口耦合的第一逻辑电路组件；所述第一逻辑电路组件被配置为执行如权利要求22至24中任一所述的数据存入方法，以及如权利要求28至30中任一所述的数据读取方法。
  35. 一种固态硬盘SSD的主控芯片，包括：第四高速串行计算机扩展总 线标准PCIe总线接口，及与所述第四PCIe总线接口耦合的第二逻辑电路组件；所述第二逻辑电路组件被配置为执行如权利要求25至27中任一所述的数据存入方法，以及如权利要求31至33中任一所述的数据读取方法。
  36. 一种非易失性存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时执行如权利要求22至27中任一所述的数据存入方法，以及如权利要求28至33中任一所述的数据读取方法。
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