WO2024036897A1 - 像素补偿电路及显示面板 - Google Patents

像素补偿电路及显示面板 Download PDF

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Publication number
WO2024036897A1
WO2024036897A1 PCT/CN2023/076473 CN2023076473W WO2024036897A1 WO 2024036897 A1 WO2024036897 A1 WO 2024036897A1 CN 2023076473 W CN2023076473 W CN 2023076473W WO 2024036897 A1 WO2024036897 A1 WO 2024036897A1
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Prior art keywords
signal
transistor
terminal
gate
driving transistor
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PCT/CN2023/076473
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English (en)
French (fr)
Inventor
张丽君
Original Assignee
惠州华星光电显示有限公司
深圳市华星光电半导体显示技术有限公司
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Publication of WO2024036897A1 publication Critical patent/WO2024036897A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance

Definitions

  • the present application relates to the field of display technology, and specifically to a pixel compensation circuit and a display panel.
  • a current driving method is often used to drive the light-emitting device to emit light.
  • the above-mentioned driving method is relatively sensitive to the electrical variation of the driving transistor, and the threshold voltage drift of the driving transistor will affect the brightness uniformity of the screen display.
  • External compensation has a wide compensation range for the threshold voltage of the driving transistor, but the driving system is complex and costly.
  • the internal compensation drive system is relatively simple and low-cost, but internal compensation requires multiple sets of row scan level transmission signals.
  • the present application provides a pixel compensation circuit and a display panel to solve the technical problem in the prior art that the internal compensation circuit requires multiple sets of row scanning level transmission signals.
  • This application provides a pixel compensation circuit, which includes:
  • a driving transistor the source of the driving transistor is connected to the first power terminal, and the drain of the driving transistor is connected to the first node;
  • the light-emitting module includes a first control end, a first end and a second end; the first control end is connected to the first signal line, the first end is connected to the second power end, and the second end is connected to the The first node, the light-emitting module is used to emit light under the control of the first global signal transmitted by the first signal line;
  • the compensation module includes a second control end, a third end and a fourth end.
  • the second control end is connected to the second signal line, the third end is connected to the first node, and the fourth end is connected to The first gate of the driving transistor, the compensation module is used to compensate the threshold voltage of the driving transistor under the control of the second global signal transmitted by the second signal line;
  • the first writing module includes a third control terminal, a fourth control terminal, a first input terminal, a second input terminal, a first output terminal and a second output terminal, the third control terminal is connected to the third signal line, The first input terminal is connected to the first wiring, the fourth control terminal is connected to the fourth signal line, the second input terminal is connected to the second wiring, and the first output terminal is connected to the second node. , the second output terminal is connected to the first gate of the driving transistor; the first writing module is used to write the first writing module under the control of the third global signal transmitted by the third signal line.
  • the first initialization signal transmitted by the wire is output to the second node, and under the control of the fourth global signal transmitted by the fourth signal line, the second initialization signal transmitted by the second wire is output to the second node. the first gate of the driving transistor;
  • the second writing module includes a fifth control terminal, a third input terminal and a third output terminal.
  • the fifth control terminal is connected to the scan line
  • the third input terminal is connected to the data line
  • the third output terminal Connected to the second node, the second writing module is configured to output the data signal transmitted by the data line to the second node under the control of the scan signal transmitted by the scan line;
  • a first capacitor, one end of the first capacitor is connected to the second node, and the other end of the first capacitor is connected to the first gate of the driving transistor;
  • a second capacitor one end of the second capacitor is connected to the first gate of the driving transistor, and the other end of the second capacitor is connected to the first power terminal.
  • the first writing module includes a first transistor and a second transistor
  • the gate of the first transistor is connected to the third signal line, the source of the first transistor is connected to the first wiring, and the drain of the first transistor is connected to the second Node; the gate of the second transistor is connected to the fourth signal line, the source of the second transistor is connected to the second wiring, and the drain of the second transistor is connected to the driving transistor. the first gate.
  • the first initialization signal is a signal connected to the first power supply terminal
  • the second initialization signal is a signal connected to the second power supply terminal
  • both the first initialization signal and the data signal are output by the corresponding data lines, and the second initialization signal is a signal connected to the second power terminal.
  • the first initialization signal and the signal connected to the first power terminal are independent of each other, and the second initialization signal and the signal connected to the second power terminal are independent of each other. independent.
  • the voltage value of the first initialization signal is smaller than the voltage value of the data signal.
  • the driving transistor is a double-gate transistor, and the second gate of the driving transistor is connected to the third signal line to receive an adjustment signal.
  • the adjustment signal is a DC signal
  • the adjustment signal is negative pressure or positive pressure
  • the compensation module includes a compensation transistor
  • the gate electrode of the compensation transistor is connected to the second signal line
  • the source electrode of the compensation transistor is connected to the first gate electrode of the driving transistor
  • the drain electrode of the compensation transistor is connected to the first gate electrode of the driving transistor. node.
  • the light-emitting module includes a switching transistor and a light-emitting device
  • the gate of the switching transistor is connected to the first signal line, the source of the switching transistor is connected to the second power terminal, and the drain of the switching transistor is connected to the anode of the light-emitting device, The cathode of the light-emitting device is connected to the first node;
  • the gate of the switching transistor is connected to the first signal line
  • the source of the switching transistor is connected to the cathode of the light-emitting device
  • the drain of the switching transistor is connected to the first node, so The anode of the light-emitting device is connected to the second power terminal.
  • the voltage value of the second initialization signal is greater than the sum of the voltage value of the signal connected to the first power supply terminal and the threshold voltage of the driving transistor.
  • the potential of the signal connected to the first power supply terminal is smaller than the potential of the signal connected to the second power supply terminal.
  • this application also provides a display panel, which includes a plurality of pixel units arranged in an array, and each of the pixel units includes the pixel compensation circuit described in any one of the above.
  • the pixel compensation circuit includes a driving transistor, a compensation module, a first writing module, a second writing module, a light emitting module, a first capacitor and a second capacitor.
  • the pixel compensation circuit provided by this application can internally compensate the threshold voltage drift of the driving transistor by setting a compensation module, thereby improving the brightness uniformity of the display panel.
  • the second global signal, the third global signal, the fourth global signal and the first global signal are used to control the compensation module, the first writing module and the light-emitting module respectively, and the progressive scanning signal is The number is reduced to one, and the circuit structure is simple, which is conducive to narrowing the frame of the display panel or reducing chip power consumption.
  • Figure 1 is a schematic structural diagram of a pixel compensation circuit provided by this application.
  • Figure 2 is a first circuit schematic diagram of the pixel compensation circuit provided by this application.
  • Figure 3 is a signal timing diagram of the pixel compensation circuit shown in Figure 2;
  • Figure 4 is a second circuit schematic diagram of the pixel compensation circuit provided by this application.
  • Figure 5 is a third circuit schematic diagram of the pixel compensation circuit provided by this application.
  • Figure 6 is a fourth circuit schematic diagram of the pixel compensation circuit provided by this application.
  • Figure 7 is a signal timing diagram of the pixel compensation circuit shown in Figure 6;
  • Figure 8 is a fifth circuit schematic diagram of the pixel compensation circuit provided by this application.
  • Figure 9 is a schematic structural diagram of a display panel provided by this application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the described features, and therefore cannot be construed as a limitation of the present application.
  • the terms “connected” and “connected” should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be a direct connection or a connection through The intermediate medium is indirectly connected, which can be the internal connection between two components.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • This application provides a pixel compensation circuit and a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • the pixel compensation circuit 10 includes a driving transistor Td, a compensation module 102, a first writing module 104, a second writing module 101, a light emitting module 103, a first capacitor C1 and a second capacitor Cst.
  • the source of the driving transistor Td is connected to the first power supply terminal VSS.
  • the drain of the driving transistor Td is connected to the first node P.
  • the light emitting module 103 includes a first control terminal a, a first terminal b and a second terminal c.
  • the first control terminal a is connected to the first signal line 21 to access the first global signal EM.
  • the first terminal b is connected to the second power terminal VDD.
  • the second terminal c is connected to the first node P.
  • the light emitting module 103 is used to emit light under the control of the first global signal EM.
  • the compensation module 102 includes a second control terminal d, a third terminal e, and a fourth terminal f.
  • the second control terminal d is connected to the second signal line 22 to access the second global signal Comp.
  • the third terminal e is connected to the first node P.
  • the fourth terminal f is connected to the first gate of the driving transistor Td.
  • the compensation module 102 is used to compensate the threshold voltage of the driving transistor Td under the control of the second global signal Comp.
  • the first writing module 104 includes a third control terminal g, a fourth control terminal h, a first input terminal i, a second input terminal j, a first output terminal k and a second output terminal m.
  • the third control terminal g is connected to the third signal line 23 to access the third global signal Ctr.
  • the first input terminal i is connected to the first trace 25 to receive the first initialization signal V1.
  • the fourth control terminal h is connected to the fourth signal line 24 to access the fourth global signal Res.
  • the second input terminal j is connected to the second trace 26 to receive the second initialization signal V2.
  • the first output terminal k is connected to the second node Q.
  • the second output terminal m is connected to the first gate of the driving transistor Td.
  • the first writing module 104 is used to output the first initialization signal V1 to the second node Q under the control of the third global signal Ctr, and to output the fourth global signal Res to the second node Q under the control of the fourth global signal Res.
  • the first gate of the drive transistor Td is used to output the first initialization signal V1 to the second node Q under the control of the third global signal Ctr, and to output the fourth global signal Res to the second node Q under the control of the fourth global signal Res.
  • the second writing module 101 includes a fifth control terminal r, a third input terminal s and a third output terminal t.
  • the fifth control terminal r is connected to the scan line 27 to receive the scan signal SPAM.
  • the third input terminal s is connected to the data line 28 to receive the data signal Da.
  • the third output terminal t is connected to the second node Q.
  • the second writing module 101 is used to output the data signal Da to the second node Q under the control of the scanning signal SPAM.
  • one end of the first capacitor C1 is connected to the second node Q.
  • the other end of the first capacitor C1 is connected to the first gate of the driving transistor Td.
  • One end of the second capacitor Cst is connected to the first gate of the driving transistor Td.
  • the other end of the second capacitor Cst is connected to the first power terminal VSS.
  • the compensation module 102 in the pixel compensation circuit 10
  • the threshold voltage drift of the driving transistor Td can be compensated and the brightness uniformity of the display panel can be improved.
  • the second global signal Comp, the third global signal Ctr, the fourth global signal Res and the first global signal EM are used in the pixel compensation circuit 10 to respectively respond to the compensation module 102, the first writing module 104 and the light emitting module 103.
  • Control can make multiple pixel compensation circuits 10 in the display panel perform steps such as reset, threshold voltage compensation, and data writing at the same time, thereby reducing the number of progressive scanning signals to one, that is, only the scanning signal SPAM is multi-level. It transmits signals and has a simple circuit structure.
  • the pixel compensation circuit 10 in the embodiment of the present application only requires a set of GOA circuits.
  • the circuit structure is simple and is conducive to narrowing the frame of the display panel.
  • the cascade scanning signal is generated by the chip, the internal circuit structure of the chip can be simplified and the power consumption of the chip can be reduced.
  • both the first power terminal VSS and the second power terminal VDD are used to receive a preset voltage signal.
  • the potential of the signal connected to the first power supply terminal VSS is smaller than the potential of the signal connected to the second power supply terminal VDD.
  • the potential of the signal connected to the first power supply terminal VSS may be the potential of the ground terminal.
  • the potential of the signal connected to the first power supply terminal VSS can also be other.
  • FIG. 2 is a first circuit schematic diagram of the pixel compensation circuit provided by the present application.
  • the first writing module 104 includes a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is connected to the third signal line 23 to access the third global signal Ctr.
  • the source of the first transistor T1 is connected to the first wiring 25 to receive the first initialization signal V1.
  • the drain of the first transistor T1 is connected to the second node Q.
  • the gate of the second transistor T2 is connected to the fourth signal line 24 to access the fourth global signal Res.
  • the source of the second transistor T2 is connected to the second wiring 26 to receive the second initialization signal V2.
  • the drain of the second transistor T2 is connected to the first gate of the driving transistor Td.
  • Compensation module 102 includes compensation transistor T4.
  • the gate of the compensation transistor T4 is connected to the second signal line 22 to access the second global signal Comp.
  • the source of the compensation transistor T4 is connected to the first gate of the driving transistor Td.
  • the drain of the compensation transistor T4 is connected to the drain of the drive transistor Td.
  • the second writing module 101 includes a third transistor T3.
  • the gate of the third transistor T3 is connected to the scan line 27 to receive the scan signal SPAM.
  • the source of the third transistor T3 is connected to the data line 28 to receive the data signal Da.
  • the drain of the third transistor T3 is connected to the second node Q.
  • the second writing module 101 can also be formed by using multiple transistors connected in series.
  • the light emitting module 103 includes a switching transistor T5 and a light emitting device D.
  • the gate of the switching transistor T5 is connected to the first signal line 21 to access the first global signal EM.
  • the source of the switching transistor T5 is connected to the second power supply terminal VDD.
  • the drain of the switching transistor T5 is connected to the anode of the light emitting device D.
  • the cathode of the light emitting device D is connected to the drain of the driving transistor Td.
  • the light-emitting module 103 may include 2, 3, 4 or more transistors. Each transistor is connected in series between the first power terminal VSS and the second power terminal VDD. Multiple transistors can be connected to the same first global signal EM, or can be connected to different lighting control signals.
  • the transistors used in all embodiments of the present application can be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, their source and drain The poles are interchangeable. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate electrode, one electrode is called the source electrode and the other electrode is called the drain electrode. According to the shape in the attached figure, the middle terminal of the switching transistor is the gate, the signal input terminal is the source, and the output terminal is the drain. In addition, the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors.
  • the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level.
  • the N-type transistor is when the gate is at a high level. It is turned on when the gate is high and turned off when the gate is low.
  • each transistor in the pixel compensation circuit 10 is an N-type transistor, but this should not be understood as a limitation of the present application.
  • Figure 3 is a signal timing diagram of the pixel compensation circuit shown in Figure 2.
  • the combination of the second global signal Comp, the third global signal Ctr, the fourth global signal Res, the first global signal EM and the scan signal SPAM successively corresponds to the reset phase t1, the threshold voltage compensation phase t2, and the data Writing phase t3 and lighting phase t4. That is, within one frame, the driving control sequence of the pixel compensation circuit 10 provided by the embodiment of the present application includes a reset phase t1, a threshold voltage compensation phase t2, a data writing phase t3, and a light emitting phase t4.
  • the third global signal Ctr and the fourth global signal Res are both at high potential, and the second global signal Comp, the first global signal EM and the scan signal SPAM are all at low potential.
  • the first transistor T1 and the first transistor T1 are at a low potential.
  • the second transistor T2 is turned on, the third transistor T3, the compensation transistor T4 and the switching transistor T5 are all turned off, and the first initialization signal V1 is output to the second node Q through the first transistor T1.
  • the second initialization signal V2 is output to the first gate of the driving transistor Td through the second transistor T2.
  • the potential of the second node Q is reset to the potential of the first initialization signal V1.
  • the potential of the first gate of the driving transistor Td is reset to the potential of the second initialization signal V2.
  • the timing of the third global signal Ctr precedes the timing of the fourth global signal Res. That is, the third global signal Ctr is at a high potential first, and after a period of time, the fourth global signal Res changes from a low potential to a high potential.
  • the third global signal Ctr first changes from a low potential to a high potential, the first transistor T1 is first turned on, and the potential of the second node Q is reset to the potential of the first initialization signal V1. Then, when the fourth global signal Res changes from a low potential to a high potential, and the potential of the first gate of the driving transistor Td is reset to the potential of the second initialization signal V2, since the first transistor T1 continues to be turned on, the second node can be turned on.
  • the potential of Q is stabilized at the potential of the first initialization signal V1 to prevent the potential of the first gate of the driving transistor Td from being coupled to the second node Q through the first capacitor C1, thus avoiding affecting subsequent threshold voltage compensation.
  • the third global signal Ctr and the second global signal Comp are both at high potential, and the fourth global signal Res, the first global signal EM and the scan signal SPAM are all at low potential.
  • the second transistor T2 , the third transistor T3 and the switching transistor T5 are both turned off, the first transistor T1 remains on to stabilize the potential of the second node Q at the potential of the first initialization signal V1, the compensation transistor T4 and the driving transistor Td are turned on, and the driving transistor Td
  • the potential of the first gate begins to leak through the compensation transistor T4, the driving transistor Td and the first power terminal VSS until the driving transistor Td is turned off.
  • the potential of the first gate of the driving transistor Td is Vss+Vth.
  • Vth is the threshold voltage of the driving transistor Td
  • Vss represents the potential of the signal connected to the first power terminal VSS.
  • the driving transistor Td is in an open state driven by the second initialization signal V2. Therefore, the voltage value of the second initialization signal V2 needs to be greater than the sum of the voltage value of the signal connected to the first power supply terminal VSS and the threshold voltage of the driving transistor Td.
  • the scanning signal SPAM is at a high level
  • the third transistor T3 is turned on
  • the data signal Da is written to the first gate of the driving transistor Td through the third transistor T3 and the first capacitor C1.
  • the second global signal Comp, the third global signal Ctr, the fourth global signal Res and the first global signal EM are all at low potential
  • the first transistor T1, the second transistor T2, the compensation transistor T4 and the switching transistor T5 are all turned off.
  • the driving transistor Td is turned on by the voltage written to the first gate of the driving transistor Td.
  • the voltage Vg written into the first gate of the driving transistor Td Vss+Vth+(Da-V1)*C1/(C1+Cst).
  • the first global signal EM is at a high potential
  • the second global signal Comp is turned on
  • the first The transistor T1, the second transistor T2, the third transistor T3 and the compensation transistor T4 are all turned off.
  • the second power supply terminal VDD, the light emitting device D, the switching transistor T5, the driving transistor Td and the first power supply terminal VSS form a path, and the driving transistor Td passes through
  • the potential of the first gate generates a drive current corresponding to the data signal Da.
  • the driving current flows through the light-emitting device D, driving the light-emitting device D to emit light. Since the first global signal EM is a global signal, all the light-emitting devices D in the display panel emit light at the same time, thereby displaying one frame of picture.
  • the current flowing through the light-emitting device D has nothing to do with the threshold voltage Vth of the driving transistor Td, thereby ensuring that the current flowing through the light-emitting device D remains unchanged. Even if the threshold voltage Vth of the driving transistor Td drifts, the normal operation of the light-emitting device D will not be affected. Emit light, thereby improving the luminescence uniformity of the display panel.
  • the pixel compensation circuit 10 provided by the embodiment of the present application can maintain the current change of the threshold voltage offset ⁇ Vth of the driving transistor Td within 0 ⁇ nV within 5%.
  • the value of n depends on the voltage value of the data voltage Da, the first initialization signal V1, etc.
  • the voltage value of the first initialization signal V1 needs to be smaller than the voltage value of the data signal Da, so as to ensure that the light-emitting device D emits light normally.
  • the first initialization signal V1 is a signal connected to the first power terminal VSS.
  • the second initialization signal V2 is a signal connected to the second power supply terminal VDD.
  • the pixel compensation circuit 10 by setting the first initialization signal V1 and the signal connected to the first power supply terminal VSS to be the same signal, and setting the second initialization signal V2 and the signal connected to the second power supply terminal VDD to be the same signal, it is possible to reduce The signals required by the pixel compensation circuit 10 simplify the circuit arrangement.
  • FIG. 4 is a second circuit schematic diagram of the pixel compensation circuit provided by this application.
  • the difference from the pixel compensation circuit 10 shown in Figure 2 is that in the light-emitting module 103 of the embodiment of the present application, the gate of the switching transistor T5 is connected to the first signal line 21 to access the first global signal EM;
  • the source of the switching transistor T5 is connected to the cathode of the light-emitting device D; the drain of the switching transistor T5 is connected to the drain of the driving transistor Td; and the anode of the light-emitting device D is connected to the second power terminal VDD.
  • the signal driving timing of the pixel compensation circuit 10 in this embodiment is the same as the signal driving timing of the pixel compensation circuit 10 shown in FIG. 2.
  • the signal driving timing of the pixel compensation circuit 10 shown in FIG. 2 please refer to the above embodiment and will not be described again here.
  • FIG. 5 is a third circuit schematic diagram of the pixel compensation circuit provided by this application.
  • the difference from the pixel compensation circuit 10 shown in FIG. 2 is that in the embodiment of the present application, the first initialization signal V1 and the signal connected to the first power supply terminal VSS are independent of each other, and the second initialization signal V2 and the second power supply terminal VSS are independent of each other.
  • the signals connected to terminal VDD are independent of each other.
  • the signal driving timing of the pixel compensation circuit 10 in this embodiment can also refer to the above embodiment, and will not be described again.
  • the current flowing through the light-emitting device D has nothing to do with the signal connected to the first power terminal VSS, which can reduce the voltage connected to the first power terminal VSS.
  • the incoming signal is affected by uneven display due to IR drop (voltage drop).
  • FIG. 6 is a fourth circuit schematic diagram of the pixel compensation circuit provided by this application.
  • the difference from the pixel compensation circuit 10 shown in FIG. 2 is that in the embodiment of the present application, the first initialization signal V1 and the data signal Da are both output by the corresponding data lines 28, and the second initialization signal V2 and the second power supply The signal connected to terminal VDD is the same signal.
  • FIG. 7 is a signal timing diagram of the pixel compensation circuit 10 shown in FIG. 6 .
  • the data line outputs the data signal Da twice within a frame display period.
  • the data signal Da output by the data line is the first initialization signal V1 to initialize the potential of the second node Q.
  • the data line outputs the data signal Da to the first gate of the driving transistor Td.
  • the first initialization signal V1 output by the data line and the signal connected to the first power terminal VSS are independent of each other, so the current flowing through the light-emitting device D has nothing to do with the signal connected to the first power terminal VSS, which can reduce the first The signal connected to the VSS at the power supply end has uneven display due to IR drop (voltage drop).
  • the first initialization signal V1 outputted via the data line can further simplify the in-plane signal wiring.
  • FIG. 8 is a fifth circuit schematic diagram of the pixel compensation circuit provided by this application.
  • the driving transistor Td is a double-gate transistor.
  • the second gate of the driving transistor Td is connected to the third signal line 29 to receive an adjustment signal BG.
  • the adjustment signal BG is a direct current signal.
  • the adjustment signal BG is a negative voltage
  • the threshold voltage Vth of the driving transistor Td can be adjusted in the positive direction.
  • the adjustment signal BG is a positive voltage
  • the threshold voltage Vth of the driving transistor Td can be adjusted in the negative direction.
  • Embodiments of the present application can also increase the compensation range of the threshold voltage Vth, so that the compensable range is shifted from 0 ⁇ nV to -mV ⁇ +pV, realizing negative drift compensation of the threshold voltage, thereby realizing the threshold voltage Vth in the case of positive and negative drift. compensate.
  • n, m and p can be determined by the actual application of the driving transistor Td.
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • An embodiment of the present application also provides a display panel 100 including a plurality of pixel units 11 arranged in an array.
  • Each pixel unit 11 includes the above-mentioned pixel compensation circuit 10.
  • pixel compensation circuit 10 For details, reference may be made to the above description of the pixel compensation circuit 10, which will not be described again here.
  • the display panel 100 may be an OLED (Organic Light-Emitting Diode, active matrix organic light-emitting diode) display panel, a Mini-LED (Mini Light-Emitting Diode, mini light-emitting diode) display panel, a Micro -LED (Micro Light-Emitting Diode, micron light-emitting diode) display panel, etc.
  • OLED Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • Mini-LED Mini Light-Emitting Diode, mini light-emitting diode
  • Micro -LED Micro Light-Emitting Diode, micron light-emitting diode
  • the pixel compensation circuit 10 includes a driving transistor, a compensation module, a first writing module, a second writing module, a light emitting module, a first capacitor and a second capacitor.
  • the pixel compensation circuit 10 provided in the embodiment of the present application can compensate for the threshold voltage difference of the driving transistor by setting a compensation module, thereby improving the brightness uniformity of the display panel 100 .
  • the second global signal, the third global signal, the fourth global signal and the first global signal are used in the pixel compensation circuit 10 to control the compensation module, the first writing module and the light-emitting module respectively, and only one set of rows is required.
  • Internal compensation can be achieved by scanning signals at a scanning level, and the circuit structure is simple, which is beneficial to narrowing the frame of the display panel 100 or reducing chip power consumption.

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Abstract

一种像素补偿电路(10)及显示面板(100)。像素补偿电路(10)中，补偿模块(102)接入第二全局信号(Comp)，并连接于第一节点(P)以及驱动晶体管(Td)的第一栅极；第一写入模块(104)接入第三全局信号(Ctr)、第一初始化信号(V1)、第四全局信号(Res)以及第二初始化信号(V2)，并连接于第二节点(Q)和驱动晶体管(Td)的第一栅极；发光模块(103)接入第一全局信号(EM)，并串联在第二电源端(VDD)与第一节点(P)之间。

Description

像素补偿电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素补偿电路及显示面板。
 背景技术
在现有的像素补偿电路中，常采用电流驱动方式驱动发光器件发光。但是，上述驱动方式对驱动晶体管的电性变异较为敏感，驱动晶体管的阈值电压飘移会影响画面显示的亮度均匀性。
目前主流的阈值电压补偿方式有两种，分别是外部补偿和内部补偿。外部补偿对驱动晶体管的阈值电压补偿范围大，但驱动***复杂、成本高。内部补偿驱动***相对简单、成本低，但内部补偿需要多组行扫描级传信号。
 技术问题
本申请提供一种像素补偿电路及显示面板，以解决现有技术中内部补偿电路需要多组行扫描级传信号的技术问题。
 技术解决方案
本申请提供一种像素补偿电路，其包括：
驱动晶体管，所述驱动晶体管的源极与第一电源端连接，所述驱动晶体管的漏极与第一节点连接；
发光模块，包括第一控制端、第一端以及第二端；所述第一控制端与第一信号线连接，所述第一端与第二电源端连接，所述第二端连接于所述第一节点，所述发光模块用于在所述第一信号线传输的第一全局信号的控制下发光；
补偿模块，包括第二控制端、第三端以及第四端，所述第二控制端与第二信号线连接，所述第三端连接于所述第一节点，所述第四端连接于所述驱动晶体管的第一栅极，所述补偿模块用于在所述第二信号线传输的第二全局信号的控制下对所述驱动晶体管的阈值电压进行补偿；
第一写入模块，包括第三控制端、第四控制端、第一输入端、第二输入端、第一输出端以及第二输出端，所述第三控制端与第三信号线连接、所述第一输入端与第一走线连接、所述第四控制端与第四信号线连接，所述第二输入端与第二走线连接，所述第一输出端连接于第二节点，所述第二输出端连接于所述驱动晶体管的第一栅极；所述第一写入模块用于在所述第三信号线传输的第三全局信号的控制下，将所述第一走线传输的第一初始化信号输出至所述第二节点，以及在所述第四信号线传输的第四全局信号的控制下，将所述第二走线传输的第二初始化信号输出至所述驱动晶体管的第一栅极；
第二写入模块，包括第五控制端、第三输入端以及第三输出端，所述第五控制端与扫描线连接，所述第三输入端与数据线连接，所述第三输出端连接于所述第二节点，所述第二写入模块用于在所述扫描线传输的扫描信号的控制下，将所述数据线传输的数据信号输出至所述第二节点；
第一电容，所述第一电容的一端与所述第二节点连接，所述第一电容的另一端与所述驱动晶体管的第一栅极连接；以及
第二电容，所述第二电容的一端与所述驱动晶体管的第一栅极连接，所述第二电容的另一端与所述第一电源端连接。
可选的，在本申请一些实施例中，所述第一写入模块包括第一晶体管和第二晶体管；
其中，所述第一晶体管的栅极与所述第三信号线连接，所述第一晶体管的源极与所述第一走线连接，所述第一晶体管的漏极连接于所述第二节点；所述第二晶体管的栅极与所述第四信号线连接，所述第二晶体管的源极与所述第二走线连接，所述第二晶体管的漏极连接于所述驱动晶体管的第一栅极。
可选的，在本申请一些实施例中，所述第一初始化信号为所述第一电源端接入的信号，所述第二初始化信号为所述第二电源端接入的信号。
可选的，在本申请一些实施例中，所述第一初始化信号与所述数据信号均由相应的所述数据线输出，所述第二初始化信号为所述第二电源端接入的信号。
可选的，在本申请一些实施例中，所述第一初始化信号与所述第一电源端接入的信号相互独立，所述第二初始化信号与所述第二电源端接入的信号相互独立。
可选的，在本申请一些实施例中，所述第一初始化信号的电压值小于所述数据信号的电压值。
可选的，在本申请一些实施例中，所述驱动晶体管为双栅晶体管，所述驱动晶体管的第二栅极与第三信号线连接，以接入一调整信号。
可选的，在本申请一些实施例中，所述调整信号为直流信号，所述调整信号为负压或正压。
可选的，在本申请一些实施例中，所述补偿模块包括补偿晶体管；
其中，所述补偿晶体管的栅极与所述第二信号线连接，所述补偿晶体管的源极连接于所述驱动晶体管的第一栅极，所述补偿晶体管的漏极连接于所述第一节点。
可选的，在本申请一些实施例中，所述发光模块包括开关晶体管和发光器件；
其中，所述开关晶体管的栅极与所述第一信号线连接，所述开关晶体管的源极连接于所述第二电源端，所述开关晶体管的漏极连接于所述发光器件的阳极，所述发光器件的阴极连接于所述第一节点；
或者，所述开关晶体管的栅极与所述第一信号线连接，所述开关晶体管的源极连接于所述发光器件的阴极，所述开关晶体管的漏极连接于所述第一节点，所述发光器件的阳极连接于所述第二电源端。
可选的，在本申请一些实施例中，所述第二初始化信号的电压值大于所述第一电源端接入的信号的电压值与所述驱动晶体管的阈值电压之和。
可选的，在本申请一些实施例中，所述第一电源端接入的信号的电位小于所述第二电源端接入的信号的电位。
相应的，本申请还提供一种显示面板，所述显示面板包括多个呈阵列排布的像素单元，每一所述像素单元均包括上述任一项所述的像素补偿电路。
 有益效果
本申请提供一种像素补偿电路及显示面板。像素补偿电路包括驱动晶体管、补偿模块、第一写入模块、第二写入模块、发光模块、第一电容以及第二电容。本申请提供的像素补偿电路通过设置补偿模块可以对驱动晶体管的阈值电压漂移进行内部补偿，提升显示面板的亮度均一性。此外，在像素补偿电路中采用第二全局信号、第三全局信号、第四全局信号以及第一全局信号分别对补偿模块、第一写入模块以及发光模块进行相应控制，将逐行扫描信号的数量降低为一个，电路结构简单，利于实现显示面板的窄边框化或者降低芯片功耗。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1是本申请提供的像素补偿电路的结构示意图；
图2是本申请提供的像素补偿电路的第一电路示意图；
图3是图2所示的像素补偿电路的信号时序图；
图4是本申请提供的像素补偿电路的第二电路示意图；
图5是本申请提供的像素补偿电路的第三电路示意图；
图6是本申请提供的像素补偿电路的第四电路示意图；
图7是图6所示的像素补偿电路的信号时序图；
图8是本申请提供的像素补偿电路的第五电路示意图；
图9是本申请提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。此外，需要说明的是，除非另有明确的规定和限定，术语“相连”、“连接”应做广义理解，例如，可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
本申请提供一种像素补偿电路及显示面板，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1是本申请提供的像素补偿电路的结构示意图。在本申请实施例中，像素补偿电路10包括驱动晶体管Td、补偿模块102、第一写入模块104、第二写入模块101、发光模块103、第一电容C1以及第二电容Cst。
其中，驱动晶体管Td的源极与第一电源端VSS连接。驱动晶体管Td的漏极与第一节点P连接。
其中，发光模块103包括第一控制端a、第一端b以及第二端c。第一控制端a与第一信号线21连接，以接入第一全局信号EM。第一端b与第二电源端VDD连接。第二端c连接于第一节点P。发光模块103用于在第一全局信号EM的控制下发光。
其中，补偿模块102包括第二控制端d、第三端e以及第四端f。第二控制端d与第二信号线22连接，以接入第二全局信号Comp。第三端e连接于第一节点P。第四端f连接于驱动晶体管Td的第一栅极。补偿模块102用于在第二全局信号Comp的控制下对驱动晶体管Td的阈值电压进行补偿。
其中，第一写入模块104包括第三控制端g、第四控制端h、第一输入端i、第二输入端j、第一输出端k以及第二输出端m。第三控制端g与第三信号线23连接，以接入第三全局信号Ctr。第一输入端i与第一走线25连接，以接入第一初始化信号V1。第四控制端h与第四信号线24连接，以接入第四全局信号Res。第二输入端j与第二走线26连接，以接入第二初始化信号V2。第一输出端k连接于第二节点Q。第二输出端m连接于驱动晶体管Td的第一栅极。第一写入模块104用于在第三全局信号Ctr的控制下，将第一初始化信号V1输出至第二节点Q，以及在第四全局信号Res的控制下，将第四全局信号Res输出至驱动晶体管Td的第一栅极。
其中，第二写入模块101包括第五控制端r、第三输入端s以及第三输出端t。第五控制端r与扫描线27连接，以接入扫描信号SPAM。第三输入端s与数据线28连接，以接入数据信号Da。第三输出端t连接于第二节点Q。第二写入模块101用于在扫描信号SPAM的控制下，将数据信号Da输出至第二节点Q。
其中，第一电容C1的一端与第二节点Q连接。第一电容C1的另一端与驱动晶体管Td的第一栅极连接。
其中，第二电容Cst的一端与驱动晶体管Td的第一栅极连接。第二电容Cst的另一端接入与第一电源端VSS连接。
本申请实施例通过在像素补偿电路10中设置补偿模块102，可以对驱动晶体管Td的阈值电压漂移进行补偿，提升显示面板的亮度均一性。此外，在像素补偿电路10中采用第二全局信号Comp、第三全局信号Ctr、第四全局信号Res以及第一全局信号EM分别对补偿模块102、第一写入模块104以及发光模块103进行相应控制，可以使显示面板内的多个像素补偿电路10同时执行复位、阈值电压补偿、数据写入等步骤，从而将逐行扫描信号的数量降低为一个，也即只有扫描信号SPAM为多级级传信号，电路结构简单。
具体的，当级传扫描信号由GOA电路产生时，本申请实施例中的像素补偿电路10仅需要一组GOA电路即可，电路结构简单，利于实现显示面板的窄边框化。当级传扫描信号由芯片产生时，可以简化芯片的内部电路结构，降低芯片的功耗。
在本申请实施例中，第一电源端VSS和第二电源端VDD均用于接入一预设电压信号。此外，在本申请实施例中，第一电源端VSS接入的信号的电位小于第二电源端VDD接入的信号的电位。具体的，第一电源端VSS接入的信号的电位可以为接地端的电位。当然，可以理解地，第一电源端VSS接入的信号的电位还可以为其它。
在本申请实施例中，请参阅图2，图2为本申请提供的像素补偿电路的第一电路示意图。结合图1和图2所示，第一写入模块104包括第一晶体管T1和第二晶体管T2。
其中，第一晶体管T1的栅极与第三信号线23连接，以接入第三全局信号Ctr。第一晶体管T1的源极与第一走线25连接，以接入第一初始化信号V1。第一晶体管T1的漏极连接于第二节点Q。第二晶体管T2的栅极与第四信号线24连接，以接入第四全局信号Res。第二晶体管T2的源极与第二走线26连接，以接入第二初始化信号V2。第二晶体管T2的漏极连接于驱动晶体管Td的第一栅极。
补偿模块102包括补偿晶体管T4。补偿晶体管T4的栅极与第二信号线22连接，以接入第二全局信号Comp。补偿晶体管T4的源极连接于驱动晶体管Td的第一栅极。补偿晶体管T4的漏极与驱动晶体管Td的漏极连接。
第二写入模块101包括第三晶体管T3。第三晶体管T3的栅极与扫描线27连接，以接入扫描信号SPAM。第三晶体管T3的源极与数据线28连接，以接入数据信号Da。第三晶体管T3的漏极连接于第二节点Q。当然，可以理解地，第二写入模块101还可以采用多个晶体管串联形成。
发光模块103包括开关晶体管T5和发光器件D。开关晶体管T5的栅极与第一信号线21连接，以接入第一全局信号EM。开关晶体管T5的源极与第二电源端VDD连接。开关晶体管T5的漏极与发光器件D的阳极连接。发光器件D的阴极与驱动晶体管Td的漏极连接。
当然，可以理解地，在本申请实施例提供的像素补偿电路10中，发光模块103可以包括2个、3个、4个或更多个晶体管。每一晶体管均串接于第一电源端VSS和第二电源端VDD之间。多个晶体管可以接入同一第一全局信号EM，也可以接入不同的发光控制信号。
需要说明的是，本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
此外，本申请以下实施例均以像素补偿电路10中的各晶体管为N型晶体管为例进行说明，但不能理解为对本申请的限定。
请参阅图3，图3是图2所示的像素补偿电路的信号时序图。结合图2和图3，第二全局信号Comp、第三全局信号Ctr、第四全局信号Res、第一全局信号EM以及扫描信号SPAM相组合先后对应于复位阶段t1、阈值电压补偿阶段t2、数据写入阶段t3以及发光阶段t4。也即，在一帧时间内，本申请实施例提供的像素补偿电路10的驱动控制时序包括复位阶段t1、阈值电压补偿阶段t2、数据写入阶段t3以及发光阶段t4。
在复位阶段t1，第三全局信号Ctr和第四全局信号Res均为高电位，第二全局信号Comp、第一全局信号EM以及扫描信号SPAM均为低电位，此时，第一晶体管T1和第二晶体管T2打开，第三晶体管T3、补偿晶体管T4以及开关晶体管T5均关闭，第一初始化信号V1通过第一晶体管T1输出至第二节点Q。第二初始化信号V2通过第二晶体管T2输出至驱动晶体管Td的第一栅极。第二节点Q的电位复位至第一初始化信号V1的电位。驱动晶体管Td的第一栅极的电位复位至第二初始化信号V2的电位。
在一些实施例中，在复位阶段，第三全局信号Ctr的时序先于第四全局信号Res的时序。也即，第三全局信号Ctr先为高电位，经过一段时间之后，第四全局信号Res才由低电位转变为高电位。
可以理解的是，第三全局信号Ctr先由低电位转变为高电位，第一晶体管T1先打开，第二节点Q的电位复位至第一初始化信号V1的电位。然后，当第四全局信号Res由低电位转变为高电位，驱动晶体管Td的第一栅极的电位复位至第二初始化信号V2的电位后，由于第一晶体管T1持续打开，可以将第二节点Q的电位稳定在第一初始化信号V1的电位，避免驱动晶体管Td的第一栅极的电位通过第一电容C1耦合至第二节点Q，从而避免影响后续的阈值电压补偿。
在阈值电压补偿阶段t2，第三全局信号Ctr和第二全局信号Comp均为高电位，第四全局信号Res、第一全局信号EM以及扫描信号SPAM均为低电位，此时，第二晶体管T2、第三晶体管T3以及开关晶体管T5均关闭，第一晶体管T1保持打开状态，以将第二节点Q的电位稳定在第一初始化信号V1的电位，补偿晶体管T4和驱动晶体管Td打开，驱动晶体管Td的第一栅极的电位经补偿晶体管T4、驱动晶体管Td以及第一电源端VSS开始漏电，直至驱动晶体管Td关闭，此时驱动晶体管Td的第一栅极的电位为Vss+Vth。其中，Vth为驱动晶体管Td的阈值电压，Vss表示第一电源端VSS接入的信号的电位。
可以理解的是，驱动晶体管Td在第二初始化信号V2的驱动下处于打开状态。因此，第二初始化信号V2的电压值需要大于第一电源端VSS接入的信号的电压值与驱动晶体管Td的阈值电压之和。
在数据写入阶段t3，扫描信号SPAM为高电位，第三晶体管T3打开，数据信号Da通过第三晶体管T3、第一电容C1写入至驱动晶体管Td的第一栅极。此时，第二全局信号Comp、第三全局信号Ctr、第四全局信号Res以及第一全局信号EM均为低电位，第一晶体管T1、第二晶体管T2、补偿晶体管T4以及开关晶体管T5均关闭。驱动晶体管Td在写入至驱动晶体管Td的第一栅极的电压的作用下打开。
其中，写入驱动晶体管Td的第一栅极的电压Vg=Vss+Vth+(Da-V1)*C1/(C1+Cst)。
需要说明的是，在复位阶段t1和阈值电压补偿阶段t2，由于像素补偿电路10采用的第二全局信号Comp、第三全局信号Ctr、第四全局信号Res、第一全局信号EM均为全局信号，因此显示面板中所有像素补偿电路10同时进行复位以及阈值电压补偿。在本申请实施例中，仅扫描信号SPAM为级联信号，需要由一组GOA电路输出。在数据写入阶段t3，多行扫描信号SPAM（比如，SPAM(1)、SPAM(2)、SPAM(n)）依次输出，数据信号Da逐行写入相应的像素补偿电路10。
在发光阶段t4，第一全局信号EM为高电位，第二全局信号Comp、第三全局信号Ctr、第四全局信号Res以及扫描信号SPAM均为低电位，此时，开关晶体管T5打开，第一晶体管T1、第二晶体管T2、第三晶体管T3以及补偿晶体管T4均关闭，第二电源端VDD、发光器件D、开关晶体管T5、驱动晶体管Td以及第一电源端VSS形成一通路，驱动晶体管Td通过第一栅极的电位产生与数据信号Da相对应的驱动电流。驱动电流流经发光器件D，驱动发光器件D发光。由于第一全局信号EM为全局信号，显示面板中所有的发光器件D同时发光，从而显示一帧画面。
在发光阶段t4，驱动晶体管Td的栅源压差Vgs=Vss+Vth+(Da-V1)*C1/(C1+Cst)-Vss=Vth+(Da-V1)*C1/(C1+Cst)。由于驱动晶体管Td工作在饱和区，流经发光器件D的电流I=k(Vgs-Vth) 2=k[(Da-V1)*C1/(C1+Cst)] 2，其中k表示迁移率。因此，流经发光器件D的电流与驱动晶体管Td的阈值电压Vth无关，从而保证流经发光器件D的电流不变，即使驱动晶体管Td的阈值电压Vth发生飘移，也不影响发光器件D的正常发光，从而提高显示面板的发光均一性。
理论上，本申请实施例提供的像素补偿电路10可使驱动晶体管Td的阈值电压偏移量ΔVth在0~nV内的电流变化维持在5%的变化量以内。其中，n的数值取决于数据电压Da、第一初始化信号V1等的电压值。
此外，由流经发光器件D的电流的计算公式可知，第一初始化信号V1的电压值需要小于数据信号Da的电压值，从而保证发光器件D正常发光。
请继续参阅图2，在本申请实施例中，第一初始化信号V1为第一电源端VSS接入的信号。第二初始化信号V2为第二电源端VDD接入的信号。此时，写入驱动晶体管Td的第一栅极的电压Vg=Vss+Vth+(Da-Vss)*C1/(C1+Cst)。流经发光器件D的电流I=k(Vgs-Vth) 2=k[(Da-Vss)*C1/(C1+Cst)] 2，同样与驱动晶体管Td的阈值电压Vth无关。
本申请实施例通过将第一初始化信号V1与第一电源端VSS接入的信号设置为同一信号，以及将第二初始化信号V2与第二电源端VDD接入的信号设置为同一信号，可以减少像素补偿电路10所需的信号，简化线路排布。
请参阅图4，图4是本申请提供的像素补偿电路的第二电路示意图。与图2所示的像素补偿电路10的不同之处在于，在本申请实施例的发光模块103中，开关晶体管T5的栅极与第一信号线21连接，以接入第一全局信号EM；开关晶体管T5的源极与发光器件D的阴极连接；开关晶体管T5的漏极与驱动晶体管Td的漏极连接；发光器件D的阳极与第二电源端VDD连接。
需要说明的是，本实施例中的像素补偿电路10的信号驱动时序与图2所示的像素补偿电路10的信号驱动时序相同，具体可参阅上述实施例，在此不再赘述。
请参阅图5，图5是本申请提供的像素补偿电路的第三电路示意图。与图2所示的像素补偿电路10的不同之处在于，在本申请实施例中，第一初始化信号V1与第一电源端VSS接入的信号相互独立，第二初始化信号V2与第二电源端VDD接入的信号相互独立。
本实施例中的像素补偿电路10的信号驱动时序同样可以参阅上述实施例，在此不再赘述。此时，写入驱动晶体管Td的第一栅极的电压Vg=Vss+Vth+(Da-V1)*C1/(C1+Cst)。流经发光器件D的电流I=k(Vgs-Vth) 2=k[(Da-V1)*C1/(C1+Cst)] 2，同样与驱动晶体管Td的阈值电压Vth无关。
同时，由于第一初始化信号V1与第一电源端VSS接入的信号相互独立，则流经发光器件D的电流与第一电源端VSS接入的信号无关，可降低第第一电源端VSS接入的信号由于IR drop（电压降）导致显示不均的影响。
请参阅图6，图6是本申请提供的像素补偿电路的第四电路示意图。与图2所示的像素补偿电路10的不同之处在于，在本申请实施例中，第一初始化信号V1与数据信号Da均由相应的数据线28输出，第二初始化信号V2与第二电源端VDD接入的信号为同一信号。
具体的，请参阅图7，图7是图6所示的像素补偿电路10的信号时序图。与图3所示的信号时序图的不同之处在于，在本申请实施例中，数据线在一帧画面显示周期内输出两次数据信号Da。第一次在复位阶段t1，数据线输出的数据信号Da为第一初始化信号V1，以初始化第二节点Q的电位。第二次在数据写入阶段t3，数据线输出数据信号Da至驱动晶体管Td的第一栅极。
同样的，由数据线输出的第一初始化信号V1与第一电源端VSS接入的信号相互独立，则流经发光器件D的电流与第一电源端VSS接入的信号无关，可降低第一电源端VSS接入的信号由于IR drop（电压降）导致显示不均的影响。并且经由数据线输出的第一初始化信号V1，可以进一步简化面内的信号布线。
请参阅图8，图8是本申请提供的像素补偿电路的第五电路示意图。与图2所示的像素补偿电路10的不同之处在于，在本申请实施例中，驱动晶体管Td为双栅晶体管。驱动晶体管Td的第二栅极与第三信号线29连接，以接入一调整信号BG。
具体的，调整信号BG是直流信号。当调整信号BG为负压时，可以将驱动晶体管Td的阈值电压Vth向正方向调。当调整信号BG为正压时，可以将驱动晶体管Td的阈值电压Vth向负方向调。
本申请实施例还可以增大阈值电压Vth的补偿范围，使可补偿范围由0~nV平移至-mV~+pV，实现阈值电压负漂补偿，从而实现阈值电压Vth在正负漂情况下的补偿。其中，n、m、p可由驱动晶体管Td的实际应用情况决定。
请参阅图9，图9为本申请实施例提供的显示面板的一种结构示意图。本申请实施例还提供一种显示面板100，包括多个呈阵列排布的像素单元11。每一像素单元11均包括以上所述的像素补偿电路10，具体可参照以上对该像素补偿电路10的描述，在此不做赘述。
在本申请实施例中，显示面板100可以是OLED（Organic Light-Emitting Diode，有源矩阵有机发光二极体）显示面板、Mini-LED（Mini Light-Emitting Diode，迷你发光二极管）显示面板、Micro-LED（Micro Light-Emitting Diode，微米发光二极管）显示面板等。
在本申请实施例提供的显示面板100中，像素补偿电路10包括驱动晶体管、补偿模块、第一写入模块、第二写入模块、发光模块、第一电容以及第二电容。本申请实施例提供的像素补偿电路10通过设置补偿模块可以对驱动晶体管的阈值电压差异进行补偿，提升显示面板100的亮度均一性。此外，在像素补偿电路10中采用第二全局信号、第三全局信号、第四全局信号以及第一全局信号分别对补偿模块、第一写入模块以及发光模块进行相应控制，仅需1组行扫描级传信号即可实现内部补偿，电路结构简单，利于实现显示面板100的窄边框化或者降低芯片功耗。
以上对本申请实施例提供的像素补偿电路及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种像素补偿电路，其包括：
    驱动晶体管，所述驱动晶体管的源极与第一电源端连接，所述驱动晶体管的漏极与第一节点连接；
    发光模块，包括第一控制端、第一端以及第二端；所述第一控制端与第一信号线连接，所述第一端与第二电源端连接，所述第二端连接于所述第一节点，所述发光模块用于在所述第一信号线传输的第一全局信号的控制下发光；
    补偿模块，包括第二控制端、第三端以及第四端，所述第二控制端与第二信号线连接，所述第三端连接于所述第一节点，所述第四端连接于所述驱动晶体管的第一栅极，所述补偿模块用于在所述第二信号线传输的第二全局信号的控制下对所述驱动晶体管的阈值电压进行补偿；
    第一写入模块，包括第三控制端、第四控制端、第一输入端、第二输入端、第一输出端以及第二输出端，所述第三控制端与第三信号线连接、所述第一输入端与第一走线连接、所述第四控制端与第四信号线连接，所述第二输入端与第二走线连接，所述第一输出端连接于第二节点，所述第二输出端连接于所述驱动晶体管的第一栅极；所述第一写入模块用于在所述第三信号线传输的第三全局信号的控制下，将所述第一走线传输的第一初始化信号输出至所述第二节点，以及在所述第四信号线传输的第四全局信号的控制下，将所述第二走线传输的第二初始化信号输出至所述驱动晶体管的第一栅极；
    第二写入模块，包括第五控制端、第三输入端以及第三输出端，所述第五控制端与扫描线连接，所述第三输入端与数据线连接，所述第三输出端连接于所述第二节点，所述第二写入模块用于在所述扫描线传输的扫描信号的控制下，将所述数据线传输的数据信号输出至所述第二节点；
    第一电容，所述第一电容的一端与所述第二节点连接，所述第一电容的另一端与所述驱动晶体管的第一栅极连接；以及
    第二电容，所述第二电容的一端与所述驱动晶体管的第一栅极连接，所述第二电容的另一端与所述第一电源端连接。
  2. 根据权利要求1所述的像素补偿电路，其中，所述第一写入模块包括第一晶体管和第二晶体管；
    其中，所述第一晶体管的栅极与所述第三信号线连接，所述第一晶体管的源极与所述第一走线连接，所述第一晶体管的漏极连接于所述第二节点；所述第二晶体管的栅极与所述第四信号线连接，所述第二晶体管的源极与所述第二走线连接，所述第二晶体管的漏极连接于所述驱动晶体管的第一栅极。
  3. 根据权利要求1所述的像素补偿电路，其中，所述第一初始化信号为所述第一电源端接入的信号，所述第二初始化信号为所述第二电源端接入的信号。
  4. 根据权利要求1所述的像素补偿电路，其中，所述第一初始化信号与所述数据信号均由相应的所述数据线输出，所述第二初始化信号为所述第二电源端接入的信号。
  5. 根据权利要求1所述的像素补偿电路，其中，所述第一初始化信号与所述第一电源端接入的信号相互独立，所述第二初始化信号与所述第二电源端接入的信号相互独立。
  6. 根据权利要求1所述的像素补偿电路，其中，所述第一初始化信号的电压值小于所述数据信号的电压值。
  7. 根据权利要求1所述的像素补偿电路，其中，所述驱动晶体管为双栅晶体管，所述驱动晶体管的第二栅极与第三信号线连接，以接入一调整信号。
  8. 根据权利要求7所述的像素补偿电路，其中，所述调整信号为直流信号，所述调整信号为负压或正压。
  9. 根据权利要求1所述的像素补偿电路，其中，所述补偿模块包括补偿晶体管；
    其中，所述补偿晶体管的栅极与所述第二信号线连接，所述补偿晶体管的源极连接于所述驱动晶体管的第一栅极，所述补偿晶体管的漏极连接于所述第一节点。
  10. 根据权利要求1所述的像素补偿电路，其中，所述发光模块包括开关晶体管和发光器件；
    其中，所述开关晶体管的栅极与所述第一信号线连接，所述开关晶体管的源极连接于所述第二电源端，所述开关晶体管的漏极连接于所述发光器件的阳极，所述发光器件的阴极连接于所述第一节点；
    或者，所述开关晶体管的栅极与所述第一信号线连接，所述开关晶体管的源极连接于所述发光器件的阴极，所述开关晶体管的漏极连接于所述第一节点，所述发光器件的阳极连接于所述第二电源端。
  11. 根据权利要求1所述的像素补偿电路，其中，所述第二初始化信号的电压值大于所述第一电源端接入的信号的电压值与所述驱动晶体管的阈值电压之和。
  12. 根据权利要求1所述的像素补偿电路，其中，所述第一电源端接入的信号的电位小于所述第二电源端接入的信号的电位。
  13. 一种显示面板，其中，所述显示面板包括多个呈阵列排布的像素单元，每一所述像素单元均包括如权利要求1所述的像素补偿电路。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板为OLED显示面板、Mini-LED显示面板或Micro-LED显示面板。
  15. 根据权利要求13所述的显示面板，其中，所述第一初始化信号为所述第一电源端接入的信号，所述第二初始化信号为所述第二电源端接入的信号。
  16. 根据权利要求13所述的显示面板，其中，所述第一初始化信号与所述数据信号均由相应的所述数据线输出，所述第二初始化信号为所述第二电源端接入的信号。
  17. 根据权利要求13所述的显示面板，其中，所述第一初始化信号与所述第一电源端接入的信号相互独立，所述第二初始化信号与所述第二电源端接入的信号相互独立。
  18. 根据权利要求13所述的显示面板，其中，所述第一初始化信号的电压值小于所述数据信号的电压值。
  19. 根据权利要求13所述的显示面板，其中，所述驱动晶体管为双栅晶体管，所述驱动晶体管的第二栅极与第三信号线连接，以接入一调整信号。
PCT/CN2023/076473 2022-08-19 2023-02-16 像素补偿电路及显示面板 WO2024036897A1 (zh)

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