WO2024036770A1 - Semiconductor package substrate and manufacturing method therefor, and semiconductor package structure - Google Patents

Semiconductor package substrate and manufacturing method therefor, and semiconductor package structure Download PDF

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Publication number
WO2024036770A1
WO2024036770A1 PCT/CN2022/130398 CN2022130398W WO2024036770A1 WO 2024036770 A1 WO2024036770 A1 WO 2024036770A1 CN 2022130398 W CN2022130398 W CN 2022130398W WO 2024036770 A1 WO2024036770 A1 WO 2024036770A1
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Prior art keywords
depth
gold
gold finger
hole
finger body
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PCT/CN2022/130398
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French (fr)
Chinese (zh)
Inventor
王海林
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长鑫存储技术有限公司
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Publication of WO2024036770A1 publication Critical patent/WO2024036770A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Definitions

  • the present disclosure relates to the field of semiconductor technology, and specifically, to a semiconductor packaging substrate, a manufacturing method of a semiconductor packaging substrate, and a semiconductor packaging structure.
  • Gold fingers are metal contacts arranged close to the edge of the printed circuit board. They can be used for connections between printed circuit boards and can transmit signals.
  • gold wires need to be welded on the surface of the gold fingers.
  • the surface width of gold fingers gradually decreases, and the diameter of gold wires also decreases.
  • a semiconductor packaging substrate including: a substrate; a gold finger body formed on the substrate; wherein a recessed area is formed on the surface of the gold finger body, and the recessed area is formed by For pressing alloy wire.
  • the recessed area includes at least one via hole.
  • the depth of the via hole is less than 3um.
  • the etched hole has a stepped structure.
  • the stepped structure includes a first depth hole and a second depth hole, and the depth of the first depth hole is greater than the depth of the second depth hole.
  • the depth of the first depth hole is less than or equal to 1/3 times the diameter of the gold wire.
  • the step position of the stepped structure is located below the impact point of the indenter.
  • the cross-sectional shape of the via hole is one of a circle, a star, a triangle, and a polygon.
  • the recessed area is located at a solder joint of the gold finger body.
  • a method for manufacturing a semiconductor packaging substrate including: providing a substrate; forming a gold finger body on the substrate; etching a recessed area on the surface of the gold finger body, the recessed area Used for pressing alloy wires; plating nickel or gold on the surface of the gold finger body etched with the recessed area.
  • etching a recessed area on the surface of the gold finger body includes: coating a photoresist on the surface of the gold finger body; forming a first photoresist on the photoresist.
  • Mask layer, the first mask layer has a first opening, the shape of the first opening is the same as the shape of the recessed area; the first mask layer is exposed to develop the photoresist , exposing the area of the gold finger body corresponding to the first opening; and etching the area of the gold finger body corresponding to the first opening to form the recessed area.
  • the recessed area includes an etching hole with a stepped structure
  • the stepped structure includes a first depth hole and a second depth hole, and the depth of the first depth hole is greater than the etching hole. The depth of the second depth hole.
  • etching a recessed area on the surface of the gold finger body includes: coating a photoresist on the surface of the gold finger body; forming a second photoresist on the photoresist.
  • Mask layer, the second mask layer has a second opening, the shape of the second opening is the same as the shape of the first depth hole; the second mask layer is exposed to make the light Resist development to expose the area of the gold finger body corresponding to the second opening; etching the area of the gold finger body corresponding to the second opening to form a partial area of the first depth hole;
  • the second mask layer is removed, and a third mask layer is formed on the photoresist.
  • the third mask layer has a third opening, and the third opening is used to expose the first depth hole.
  • the area of the body corresponding to the third opening is etched to form the recessed area.
  • the etching depth of the area corresponding to the gold finger body and the second opening is a depth difference between the first depth hole and the second depth hole. ;
  • the etching depth of the area corresponding to the gold finger body and the third opening is the depth of the second depth hole.
  • a semiconductor packaging structure including: a packaging substrate, the packaging substrate includes a substrate and a gold finger formed on the substrate, and a recessed area is formed on the surface of the gold finger. The recessed area is used to press one end of the alloy wire; the chip stack structure is provided on the packaging substrate, and the other end of the gold wire is press-welded on the chip stack structure.
  • Figure 1 is a schematic diagram of a golden finger arrangement provided by an exemplary embodiment of the present disclosure.
  • Figure 2 is a partial enlarged view of Figure 1.
  • FIG. 3 is a schematic structural diagram of a semiconductor packaging substrate provided by an exemplary embodiment of the present disclosure.
  • 4-6 are schematic structural diagrams of a gold finger body with different numbers of via holes provided by an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a stepped via hole provided by an exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic flowchart of a packaging wiring process provided by an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a welding head pressing an alloy wire in a stepped etching hole according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a flow chart of a method for manufacturing a semiconductor packaging substrate according to an exemplary embodiment of the present disclosure.
  • 11(a)-11(f) are process step diagrams of a method for manufacturing a semiconductor packaging substrate provided by an exemplary embodiment of the present disclosure.
  • 12(a) to 12(f) are process step diagrams of another method of manufacturing a semiconductor packaging substrate provided by an exemplary embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a semiconductor packaging structure provided by an exemplary embodiment of the present disclosure.
  • Figure 14 is a schematic structural diagram of an adhesive layer provided by an exemplary embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a semiconductor packaging structure provided by an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • printed circuit boards not only have high-precision features such as high aperture ratio and fine lines, but also high-density circuit board designs such as gold fingers for high-speed communications.
  • high-speed storage products in order to reduce the loss of signal transmission, high-speed storage products generally need to use circuit boards with golden finger designs as carrier boards.
  • Gold fingers are composed of many golden conductive contacts. The surface is plated with gold that is resistant to oxidation and has strong conductivity. The conductive contacts are arranged like fingers, so they are called "gold fingers".
  • Connecting Finger usually refers to the connecting component formed on the circuit board for connecting the slot. All signals are transmitted through the connecting finger, so the connecting finger is very important for the performance of the circuit board. For example, for the memory unit in a personal computer, all data flows and electron flows of the memory processing unit are exchanged with the PC system through the contact between the gold finger and the memory slot, which is the output and input port of the memory.
  • Gold fingers are used for connections between printed circuit boards, capable of connecting circuits and transmitting signals.
  • the nickel-gold layer on the surface of the gold finger can improve the insertion and removal resistance, conductivity and oxidation resistance of this part.
  • Gold fingers are generally divided into equal-length gold fingers, graded gold fingers and segmented gold fingers. The design of graded and segmented gold fingers breaks through the original gold finger design concept and designs the gold fingers into different lengths or segmented structures. , which forms an effective time difference during the signal transmission process, facilitates the transmission of high-frequency signals, and can implement hot-swap technology, thus facilitating subsequent upgrades and maintenance.
  • the semiconductor packaging process it often involves a bonding operation (Wire Bonding) that connects the electrodes on the chip (Die) and the gold fingers on the lead frame (Frame) or substrate (Substrate) with gold wires.
  • Wire Bonding Wired Bonding
  • the gold wire passes Welded to the surface of the gold finger.
  • the surface of the gold fingers is all smooth. After the solder joints on the gold fingers are formed by hot pressing, they need to have sufficient bonding force to ensure the stability of the welding quality.
  • the size of the bonding force is positively correlated with the contact area of the solder joint.
  • FIG. 1 a schematic diagram of a gold finger arrangement provided by an exemplary embodiment of the present disclosure is shown.
  • the distance between two adjacent gold fingers is called the center pitch of the gold fingers.
  • the center distance of the gold fingers is constant, the surface width (top width) and gap (space) of the gold fingers restrict each other. It can be seen from the partial enlarged view of Figure 2 that the sum of the surface width and the gap of the gold finger constitutes a center spacing.
  • the gap between the gold fingers can still meet the requirements for reliable ion migration while ensuring the surface width of the gold fingers.
  • packaging requirements continue to increase, resulting in the center distance of gold fingers getting smaller and smaller. Since the gap between gold fingers cannot be reduced when it comes to quality reliability, the purpose of reducing the center distance can only be achieved by reducing the surface width of the gold fingers.
  • the contact area of the solder points on the surface of the gold finger also becomes smaller.
  • reducing the diameter of the gold wire will inevitably lead to a smaller bonding area of the solder joints between the gold wire and the surface of the gold finger, which in turn will lead to a reduction in the bonding force between the gold wire and the surface of the gold finger.
  • the resulting semiconductor packaging structure will have quality risks.
  • the semiconductor packaging substrate 300 includes a substrate 310 and a gold finger body 320 , wherein the gold finger body 320 is formed on the substrate 310 , and , a recessed area is formed on the surface of the gold finger body 320, and the recessed area is used for pressing alloy wires.
  • the bonding area between the gold wire and the gold finger surface can be increased, thereby increasing the bonding area between the gold wire and the gold finger surface.
  • the bonding force between the gold wire and the gold finger surface is increased, thereby improving the quality of the semiconductor packaging substrate 300 .
  • gold wire has the advantages of low hardness, low stress, not prone to craters, good oxidation resistance, and good long-term reliability in high temperature and high humidity environments. Therefore, gold wires are usually used to connect gold fingers and other Components, for example, connection chips, etc.
  • the substrate 310 is the basic material for manufacturing PCB.
  • the full name of PCB is Printed Circuit Board, which in Chinese is printed circuit board or printed circuit board, hereinafter referred to as circuit board; circuit board is the carrier of electronic components.
  • PCB boards tend to develop in the direction of short, small, light and thin, and their integration is very high.
  • New products have a demand for golden fingers.
  • golden fingers are used in areas where fiber optic modules, computer graphics cards, memory sticks, and various related devices containing USB interfaces are in contact with other substrates.
  • the substrate 310 is a copper clad laminate.
  • Single-sided and double-sided printed boards are manufactured on the substrate material - copper clad laminate (Copper Clad Laminate, CCL), with selective hole processing and chemical processing. Copper plating, copper electroplating, etching and other processes can be used to obtain the required circuit pattern.
  • CCL Copper Clad Laminate
  • Another type of multi-layer printed board manufacturing also uses an inner core thin copper-clad cladding board as the base.
  • the conductive pattern layers and prepreg sheets are alternately laminated and bonded together at one time to form more than three layers of conductive pattern interconnections. It has three functions: conduction, insulation and support. The performance, quality, processability in manufacturing, manufacturing cost, manufacturing level, etc. of printed boards largely depend on the substrate material.
  • the manufacturing method of the substrate 310 includes a subtractive method and an additive method.
  • the subtractive method is a method of selectively removing part of the copper foil on the surface of the copper-clad laminate to obtain a conductive pattern.
  • the subtractive method is the main method for manufacturing printed circuits today. Its biggest advantage is that the process is mature, stable and reliable.
  • the additive method is a method of selectively depositing conductive metal on the surface of an insulating substrate to form a conductive pattern.
  • Additive methods include: Full Additive Process (FAP), Semi-additive Process (SAP) and improved semi-additive method (MSAP).
  • FAP Full Additive Process
  • SAP Semi-additive Process
  • MSAP improved semi-additive method
  • the full additive method uses only chemical precipitation.
  • the copper method is an additive process for forming conductive patterns.
  • the semi-additive method is an additive process that uses chemical deposition of metal on the surface of an insulating substrate, combined with electroplating and etching, or a combination of the three to form a conductive pattern.
  • the SAP method is often used.
  • the cost of the SAP method is higher.
  • the process is complex.
  • the improved semi-additive method is a cheaper ultra-thin copper-skin SAP simulation method proposed in view of the high cost of the SAP process.
  • the process flow of making gold fingers on PCB boards mainly includes the following processes: first cutting the PCB ⁇ making inner layer graphics ⁇ automatic optical inspection of the inner layer ⁇ laminating the inner and outer layers ⁇ drilling the outer layer ⁇ immersing copper ⁇ Full board electroplating ⁇ Outer layer pattern production ⁇ Graphic electroplating ⁇ Outer layer etching ⁇ Outer layer automatic optical inspection ⁇ Silk screen anti-electric gold oil ⁇ Second outer layer pattern production ⁇ Nickel gold plating ⁇ Partial electroplating ⁇ Film removal ⁇ The third time Outer layer pattern production ⁇ second outer layer etching ⁇ second outer layer stripping ⁇ second outer layer automatic optical inspection ⁇ silk screen solder mask ⁇ characters ⁇ process tape ⁇ immersed nickel gold ⁇ finished circuit board shape ⁇ electrical test ⁇ final Inspect ⁇ Pack.
  • photoresist in the process of forming the gold finger body 320 on the substrate 310, photoresist may be coated on the substrate 310, and then the photoresist may be developed to obtain a developed area, and then a photoresist may be used in the developed area.
  • Use methods such as FAP, SAP or MSAP to immerse yourself in copper to obtain the gold finger body 320.
  • a recessed area needs to be formed on the surface of the gold finger body 320 .
  • the formation process of the recessed area will be described in detail in subsequent embodiments and will not be described in detail here.
  • the recessed area formed on the surface of the gold finger body 320 may include at least one over-etched hole. As shown in FIG. 3 , two gold finger bodies 320 are shown on the substrate 310 , and the recessed area formed on each gold finger body 320 has two through-etch holes 322 .
  • the number of through-etch holes 322 in the recessed area may be one, two, or three or four. In the case where there are multiple through-etch holes 322, the number of through-etch holes 322 may be 322 can be arranged in array. Referring to Figures 4-6, the arrangement of over-etched holes on the gold finger body is shown. In Figure 4, there are two through-etched holes 322, and the two through-etched holes 322 are arranged in a line, specifically along the The gold wires are arranged in the extending direction of the gold finger body 320 . In Figure 5, there are three etched holes 322, and the three etched holes 322 are arranged in a triangle.
  • these three etched holes 322 need to be under the solder joint between the gold wire and the gold finger body 320. Solder joint coverage.
  • the multiple via holes 322 can be arranged along the extension direction of the gold wire on the gold finger body 320 , and it is necessary to ensure that the gold wires are
  • the solder joints between the wire and the gold finger body 320 cover all the over-etched holes 322, so that when welding the gold wire and the gold finger body 320, part of the gold wire can enter all the over-etched holes 322, thereby increasing the size of the gold wire and the gold finger.
  • the contact area on the surface of the body 320 makes the bonding area of the solder joint larger and the bonding force stronger.
  • the contact between the gold wire and the surface of the gold finger body 320 can be increased. area; when the recessed area includes multiple etching holes 322, the contact area between the gold wire and the surface of the gold finger body 320 can be further increased to improve the bonding force of the solder joints.
  • the contact area between the gold wire and the surface of the gold finger body 320 can be further increased by increasing the cross-sectional area of the through-etch hole 322 to obtain a higher the binding force.
  • the size of the recessed area can be determined according to the surface size of the gold finger body 320.
  • the width of the recessed area must be smaller than the surface width of the gold finger body 320. Examples of this disclosure The specific embodiment does not specifically limit the size of the recessed area.
  • the cross-sectional shape of the through-etch hole 322 may be in a variety of shapes, such as a circle, a star, a triangle, a polygon, etc., among which the cross-sectional shape of the through-etch hole 322 is a polygon, because the cross-sectional shape is a polygon.
  • the surface area of the hole wall of the through-etch hole 322 can be increased, so that the contact area between the gold wire and the through-etch hole 322 is larger.
  • the corners of polygons need to be rounded and connected.
  • the depth of the over-etched hole 322 must be less than the thickness of the gold finger body 320.
  • the depth of the over-etched hole 322 is less than 3um, etc.
  • the exemplary embodiment of this disclosure The specific depth of the over-etch hole 322 is not particularly limited in the embodiment.
  • the through-etch hole 322 in addition to having the above-mentioned hole-like structure, another structural form of the through-etch hole 322 is shown with reference to FIG. 7 , that is, as shown in FIG. 7 , the through-etch hole 322 also has It may be a stepped structure, that is, one over-etch hole 322 includes multiple holes with different depths.
  • the stepped structure of the over-etch hole 322 shown in FIG. 7 includes a first depth hole 3221 and a second depth hole 3222, wherein the depth of the first depth hole 3221 is greater than the depth of the second depth hole 3222. Setting the over-etch holes 322 into a stepped structure is related to the wire bonding process of the gold wire on the gold finger body 320 .
  • the first step is step 1.
  • the welding head 810 burns the gold wire at the ignition height. ball process; then, enter step 2, the welding head 810 drops from the ignition height to the first soldering point to weld the gold wire 820 to the chip 830; after completing the first point pressure welding, the welding head 810 rises and moves to the gold finger Above 840, make the gold wire 820 pull out a wire arc, as shown in step 3.
  • step 4 the welding head 810 descends to the second soldering point, and the welding head 810 melts the gold wire 820 by heating, so that the gold wire 820 is pressure-welded to the gold finger 840; then, in step 5, the welding head 810 Lift up, pull off the gold wire 820 and separate it from the gold finger 840; finally, as shown in step 6, the welding head 810 drives the remaining gold wire 820 back to its original position.
  • the exemplary embodiment of the present disclosure will The over-etched holes 322 are arranged in a stepped structure, and the depth holes included in the stepped structure have different depths.
  • the initial contact point between the gold wire 820 and the gold finger 840 is exactly at the position of the second depth hole 3222.
  • the final solder joint may be located exactly at the position of the first depth hole 3221. Since the final solder joint is subject to greater extrusion force, more gold wires 820 will be fused into the first depth hole 3221. Therefore, the first depth hole 3221 will be The depth hole 3221 is set deeper to accommodate more gold wires 820; while the second depth hole 3222 is set shallower to ensure that the gold finger 840 has sufficient strength while accommodating the gold wires 820.
  • the depth of the first depth hole 3221 cannot be too deep.
  • the depth of the first depth hole 3221 can be set to less than or equal to 1/3 times the diameter of the gold wire 820.
  • the exemplary embodiment of this disclosure The embodiment does not specifically limit the specific depths of the first depth hole 3221 and the second depth hole 3222.
  • the step position of the stepped structure of the over-etch hole 322 is located below the contact point of the indenter, that is, below the contact point of the welding head 810 on the gold finger.
  • the step-like structure of the over-etch hole 322 increases in depth along the force direction of the indenter, which allows more gold wires 820 to enter deeper holes. into the deep hole, thereby increasing the contact area between the gold wire 820 and the over-etched hole 322, making the solder joint stronger.
  • the semiconductor packaging substrate provided by the exemplary embodiments of the present disclosure can increase the gold line pressure by arranging a recessed area on the gold finger body and making the recessed area contain an etching hole.
  • the over-etching hole has a stepped structure. During the bonding process, the contact area with the gold fingers enhances the bonding force of the solder joints, thus increasing the quality of the semiconductor packaging substrate.
  • exemplary embodiments of the present disclosure also provide a method for manufacturing a semiconductor packaging substrate.
  • the process steps of the manufacturing method of the semiconductor packaging substrate are as follows:
  • Step S1010 provide a substrate
  • Step S1020 Form a gold finger body on the substrate
  • Step S1030 Etch a recessed area on the surface of the gold finger body, and the recessed area is used to press the alloy wire;
  • Step S1040 Plate nickel or gold on the surface of the gold finger body with the recessed area etched.
  • the manufacturing method of a semiconductor packaging substrate provided by exemplary embodiments of the present disclosure is different from the manufacturing method of a conventional semiconductor packaging substrate in that a recessed area is etched on the surface of the gold finger body, and a gold wire is pressed into the recessed area. , can increase the bonding area between the gold wire and the surface of the gold finger body, thereby increasing the bonding force and improving the quality of welding.
  • a substrate 310 is first provided.
  • the provided substrate 310 is a copper-clad laminate.
  • the substrate 310 can be produced by a subtractive method or an additive method.
  • Lay a layer of photoresist 1110 on the substrate 310 develop the photoresist 1110 to obtain a first through groove, so that the first through groove exposes the surface of the substrate 310 , specifically by laying a mask on the photoresist 1110
  • the board is used for development, so I won’t go into details here.
  • the gold finger body 320 is filled in the first through groove, so that the gold finger body 320 is formed on the substrate 310.
  • the gold finger body 320 can be made of copper material. It is formed by electroplating in the first through groove.
  • a recessed area can be etched on the surface of the gold finger body 320.
  • a photoresist 1120 can be coated on the surface of the gold finger body 320, where the photoresist 1120 is a photosensitive material, divided into two types: positive photoresist and negative photoresist.
  • positive photoresist the part exposed to light will dissolve in the photoresist developer, while the part not exposed to light will not dissolve in the photoresist developer; for negative photoresist, the part exposed to light will not dissolve in the photoresist developer.
  • the part that is not exposed to light will not dissolve in the photoresist developer, while the part that is not exposed to light will dissolve in the photoresist developer. This characteristic of photoresist can be used for developing operations.
  • a first mask layer 1130 can be formed on the photoresist 1120 as shown in Figure 11(d).
  • the layer 1130 has a first opening, the shape of the first opening is the same as the shape of the recessed area, and is ultimately used to expose the recessed area.
  • the first mask layer 1130 formed above is exposed to develop the photoresist 1120 corresponding to the first opening, and the area of the gold finger body 320 corresponding to the first opening is exposed. .
  • the structure obtained in Figure 11(e) is unmasked, that is, the first mask layer 1130 is removed, and the area of the gold finger body 320 corresponding to the first opening is etched to A depressed area is formed, as shown in Figure 3.
  • Wet etching or dry etching may be used during the etching process.
  • the exemplary embodiments of the present disclosure do not limit the specific etching method.
  • step S1040 after etching a recessed area on the gold finger body 320, it is also necessary to plate nickel or gold on the surface of the gold finger body 320 with the recessed area etched as described in step S1040. Mainly, the electroplating process is used to plate nickel and then gold on the gold finger body 320, and finally the gold finger is produced.
  • the recessed area cannot be filled.
  • the nickel electroplated on the surface of the gold finger body 320 can have a uniform thickness, and the gold electroplated on the nickel surface can have a uniform thickness. , so that the height of the recessed area can be kept lower than the height of other unetched areas.
  • the gold finger body 320 can be electroplated with nickel gold or immersed gold.
  • nickel gold its thickness can reach 3-50u", so Due to its superior conductivity, oxidation resistance and wear resistance, it is widely used on gold finger PCBs that require frequent plugging and unplugging or PCB boards that require frequent mechanical friction.
  • the cost of gold plating is extremely high, it is only used on gold fingers.
  • the color of the electric gold process is silvery white, not as yellow as the immersion gold. The disadvantage is that the weldability is slightly poorer.
  • the thickness is conventionally 1u" and can reach up to 3u" due to its superior conductivity.
  • Electroless plating is to deposit nickel sulfate on the copper surface and then use a chemical reaction to deposit gold on the surface of nickel sulfate to form gold fingers; electroplating is to The copper surface is electroplated with nickel sulfamate, and then the nickel surface is electroplated with gold to form a gold finger. Since the nickel sulfate in the gold fingers generated during the electroless plating process is relatively hard, the gold fingers are prone to breakage due to external forces during assembly, causing functional defects in the product. Therefore, currently, when product performance requirements are high, often The electroplating process is used to produce plug-in gold fingers. The nickel sulfamate in the gold fingers will hardly break due to external forces during assembly.
  • the recessed area obtained by etching may also be an etching hole including a step-like structure.
  • the step-like structure includes a first depth hole 3221 and a second depth hole 3222, and the first depth hole 3221 Taking the depth greater than the depth of the second depth hole 3222 as an example, the formation process of this type of recessed area is briefly described as follows:
  • photoresist 1210 is coated on the surface of the gold finger body 320; and a second mask layer is formed on the photoresist 1210. 1220, wherein the second mask layer 1220 has a second opening, and the shape of the second opening is the same as the shape of the first depth hole; here it mainly refers to the cross-sectional shape of the second opening and the shape of the first depth hole.
  • the cross-sectional shapes are the same, so as to facilitate subsequent etching of the first depth hole along the second opening.
  • the second mask layer 1220 is exposed to develop the photoresist 1210 to expose the area of the gold finger body 320 corresponding to the second opening, as shown in FIG. 12(b) .
  • the first step of etching is performed, that is, as shown in FIG. 12(c) , the area of the gold finger body 320 corresponding to the second opening is etched to form part of the first depth hole 3221, that is, to form a first depth hole 3221.
  • the upper part of the hole 3221, wherein the depth of the upper part is the depth difference between the first depth hole 3221 and the second depth hole 3222.
  • the etching depth equivalent to etching the area of the gold finger body 320 corresponding to the second opening is the depth difference between the first depth hole 3221 and the second depth hole 3222 .
  • the second mask layer 1220 can be removed, and a third mask layer 1230 is formed on the photoresist 1210. As shown in FIG. 12(d), the third mask layer 1230 has The third opening may be used to expose the corresponding areas of the first depth hole 3221 and the second depth hole 3222. That is to say, the third opening can expose the area corresponding to the recessed area, and the cross-sectional shape of the third opening is the same as the cross-sectional shape of the recessed area.
  • the third mask layer 1230 can be exposed to develop the photoresist 1210 to expose the area of the gold finger body 320 corresponding to the third opening, that is, the gold finger body 320 is exposed.
  • a second step of etching is performed, that is, the area of the gold finger body 320 corresponding to the third opening is etched to form a recessed area, as shown in Figure 12(f).
  • the etching depth of this second step of etching is the depth of the second depth hole 3222. That is to say, the etching depth of the area corresponding to the gold finger body 320 and the third opening is the depth of the second depth hole 3222, and The lower part of the first depth hole 3221 is etched, so that the etching of the first depth hole 3221 is completed through the above two etchings.
  • a recessed area with a ladder-like structure is etched on the surface of the gold finger body, and the gold wire can be further enlarged by pressing the gold wire into the ladder-shaped structure.
  • the bonding area with the gold finger body surface further increases the bonding force and improves the quality of welding.
  • the manufacturing method of the semiconductor packaging substrate provided by the exemplary embodiments of the present disclosure is only a schematic description, and the present disclosure does not limit the manufacturing process of each component.
  • the semiconductor packaging structure 1300 includes a packaging substrate 1310 and a chip stack structure 1320, wherein,
  • the packaging substrate 1310 includes a substrate 310 and a gold finger 1311 formed on the substrate 310.
  • a recessed area is formed on the surface of the gold finger 1311, and the recessed area is used to press one end of the alloy wire 1312; wherein, the structural form of the recessed area and the recessed area.
  • chip stack structure 1320 is disposed on the packaging substrate 1310, and the other end of the gold wire 1312 is pressure-welded on the chip stack structure 1320.
  • the chip stack structure 1320 usually includes a die chip 1321 and an adhesive layer 1322, where the adhesive layer 1322 is used to bond the chip 1321 to the packaging substrate 1310.
  • the adhesive layer 1322 is used to bond the chip 1321 to the packaging substrate 1310.
  • adjacent chips 1321 are also connected through an adhesive layer 1322 .
  • the above-mentioned adhesive layer 1322 not only has viscosity, but also has insulating properties to play an insulating role between the chip 1321 and the chip 1321, or between the chip 1321 and the packaging substrate 1310.
  • the gold fingers 1311 on the packaging substrate 1310 and the chip 1321 are connected through gold wires 1312.
  • the specific connection process please refer to the aforementioned packaging wiring process, which will not be described again here.
  • a bonding pad may be provided on the chip 1321 to weld the gold wire 1312 on the bonding pad.
  • the semiconductor packaging structure 1300 provided by the exemplary embodiment of the present disclosure can increase the distance between the gold wire 1312 and the surface of the gold finger 1311 by arranging a recessed area on the gold finger 1311 of the packaging substrate and by pressing the gold wire 1312 in the recessed area.
  • the contact area can be increased, thereby increasing the bonding force between the gold wire 1312 and the gold finger 1311, and improving the yield of the soldering package.
  • the adhesive layer 1322 may include a first adhesive layer 13221 and a second adhesive layer 13222 .
  • the second adhesive layer 13222 is located on the first adhesive layer 13221.
  • the first adhesive layer 13221 may contact the active surface (front surface) of the chip 1321
  • the second adhesive layer 13222 may contact the back surface of the chip 1321 . Since the active surface of the chip 1321 will generate more heat, the heat dissipation coefficient of the first adhesive layer 13221 is greater than the heat dissipation coefficient of the second adhesive layer 13222, thereby preventing the first adhesive layer 13221 from being affected by heat. Big deformation.
  • metal powder may be doped in the first bonding layer 13221 to achieve rapid heat dissipation.
  • the first adhesive layer 13221 may be in contact with the substrate 1310, and the second adhesive layer 13222 may be in contact with the chip 1321.
  • the elastic modulus of the first adhesive layer 13221 is smaller than the elastic modulus of the second adhesive layer 13222.
  • the first adhesive layer 13221 realizes bonding with the substrate 1310, and the second adhesive layer 13222 directly bonds with the chip 1321, reducing the Warping during cutting.
  • the entire wafer can be placed on the second adhesive layer 13222, and then a cutting process is performed. During the cutting process, since the second adhesive layer 13222 has a high elastic modulus, warping will not occur during the cutting process.
  • the first adhesive layer 13221 has a low elastic modulus, the adhesive force between the chip 1321 and the substrate 1310 will not be reduced.
  • the first adhesive layer 13221 and the second adhesive layer 13222 are, for example, DAF, and the elastic modulus is adjusted, for example, by improving the ratio of their polymer resins.
  • the semiconductor packaging structure may further include a molding layer 140 .
  • the molding layer 140 is located on the substrate 1310 and completely covers the chip stack structure, thereby protecting the chip stack structure.
  • the molding layer 140 is, for example, an epoxy resin material.
  • the epoxy resin material can be doped with a certain volume of filler, for example, including large particle fillers and small particle fillers.
  • the filler can be spherical.
  • the thickness of the molding layer 140 may be greater than or equal to the sum of the thickness of the chip stack structure and three times the diameter of the filler (the maximum diameter of the filler). The distance from the dotted line in the figure to the top of the molding layer 140 may be equal to 3 times the diameter of the filler.
  • the molding layer 140 has a good thermal expansion coefficient and elastic modulus, so that the semiconductor packaging structure has a good warpage state. If the thickness of the molding layer 140 is too small, the thermal expansion coefficient and elastic modulus of the molding layer 140 may not match the thermal expansion coefficient and elastic modulus of the substrate 1310. At the same time, when marking the semiconductor packaging structure, The laser may penetrate the molding layer 140 and cause damage to the chip stack structure.
  • sequence numbers of the above-mentioned processes do not mean the order of execution.
  • the execution order of each process should be determined by its functions and internal logic, and should not be used in the exemplary implementation of the present disclosure.
  • the implementation process of the method constitutes no limitation.

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Abstract

A semiconductor package substrate (300), a manufacturing method for the semiconductor package substrate (300), and a semiconductor package structure (1300). The semiconductor package substrate (300) comprises: a substrate (310); and a gold finger body (320) formed on the substrate (310), wherein a recessed area is formed on the surface of the gold finger body (320), and is used for press fitting of a gold wire. The bonding force of solder joints between the gold finger and the gold wire can be improved.

Description

半导体封装基板及其制造方法、半导体封装结构Semiconductor packaging substrate and manufacturing method thereof, semiconductor packaging structure
相关申请的交叉引用Cross-references to related applications
本申请要求于2022年08月19日提交的申请号为202210999345.7、名称为“半导体封装基板及其制造方法、半导体封装结构”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。This application claims priority to the Chinese patent application with application number 202210999345.7 and titled "Semiconductor Packaging Substrate and Manufacturing Method, and Semiconductor Packaging Structure" submitted on August 19, 2022. The entire content of this Chinese patent application is fully incorporated by reference. Incorporated herein.
技术领域Technical field
本公开涉及半导体技术领域，具体而言，涉及一种半导体封装基板、半导体封装基板的制造方法及半导体封装结构。The present disclosure relates to the field of semiconductor technology, and specifically, to a semiconductor packaging substrate, a manufacturing method of a semiconductor packaging substrate, and a semiconductor packaging structure.
背景技术Background technique
金手指是在印刷电路板上靠近板边的位置布置的金属触片，可以用于印刷电路板之间的连接，能够起到传输信号的作用。Gold fingers are metal contacts arranged close to the edge of the printed circuit board. They can be used for connections between printed circuit boards and can transmit signals.
在半导体封装打线过程中，金手指表面需要焊接金线。随着封装要求的提升，金手指的表面宽度逐渐减小，金线的直径也随之减小。During the wiring process of semiconductor packaging, gold wires need to be welded on the surface of the gold fingers. As packaging requirements increase, the surface width of gold fingers gradually decreases, and the diameter of gold wires also decreases.
然而，金线的直径减小，必然导致焊点的结合面积变小，结合力降低，焊接质量下降。However, as the diameter of the gold wire decreases, the bonding area of the solder joints will inevitably decrease, the bonding force will decrease, and the welding quality will decrease.
发明内容Contents of the invention
根据本公开的第一方面，提供一种半导体封装基板，包括：基板；金手指本体，形成于所述基板上；其中，所述金手指本体的表面上形成有凹陷区域，所述凹陷区域用于压合金线。According to a first aspect of the present disclosure, a semiconductor packaging substrate is provided, including: a substrate; a gold finger body formed on the substrate; wherein a recessed area is formed on the surface of the gold finger body, and the recessed area is formed by For pressing alloy wire.
本公开的一种示例性实施方式中，所述凹陷区域包括至少一个过蚀孔。In an exemplary embodiment of the present disclosure, the recessed area includes at least one via hole.
本公开的一种示例性实施方式中，所述过蚀孔的深度小于3um。In an exemplary embodiment of the present disclosure, the depth of the via hole is less than 3um.
本公开的一种示例性实施方式中，所述过蚀孔为阶梯状结构。In an exemplary embodiment of the present disclosure, the etched hole has a stepped structure.
本公开的一种示例性实施方式中，所述阶梯状结构包括第一深度孔和第二深度孔，所述第一深度孔的深度大于所述第二深度孔的深度。In an exemplary embodiment of the present disclosure, the stepped structure includes a first depth hole and a second depth hole, and the depth of the first depth hole is greater than the depth of the second depth hole.
本公开的一种示例性实施方式中，所述第一深度孔的深度小于或等于1/3倍的所述金线的直径。In an exemplary embodiment of the present disclosure, the depth of the first depth hole is less than or equal to 1/3 times the diameter of the gold wire.
本公开的一种示例性实施方式中，所述阶梯状结构的阶梯位置位于压头着力点下方。In an exemplary embodiment of the present disclosure, the step position of the stepped structure is located below the impact point of the indenter.
本公开的一种示例性实施方式中，所述过蚀孔的截面形状为圆形、星形、三角形和多边形中的一种。In an exemplary embodiment of the present disclosure, the cross-sectional shape of the via hole is one of a circle, a star, a triangle, and a polygon.
本公开的一种示例性实施方式中，所述过蚀孔有多个，多个所述过蚀孔阵列排布。In an exemplary embodiment of the present disclosure, there are multiple via holes, and a plurality of via holes are arranged in an array.
本公开的一种示例性实施方式中，所述凹陷区域位于所述金手指本体的焊点处。In an exemplary embodiment of the present disclosure, the recessed area is located at a solder joint of the gold finger body.
根据本公开的第二方面，提供一种半导体封装基板的制作方法，包括：提供基板；在所述基板上形成金手指本体；在所述金手指本体的表面刻蚀凹陷区域，所述凹陷区域用于压合金线；在刻蚀有所述凹陷区域的所述金手指本体的表面镀镍、镀金。According to a second aspect of the present disclosure, a method for manufacturing a semiconductor packaging substrate is provided, including: providing a substrate; forming a gold finger body on the substrate; etching a recessed area on the surface of the gold finger body, the recessed area Used for pressing alloy wires; plating nickel or gold on the surface of the gold finger body etched with the recessed area.
本公开的一种示例性实施方式中，所述在所述金手指本体的表面刻蚀凹陷区域，包括：在所述金手指本体的表面涂覆光阻；在所述光阻上形成第一掩膜层，所述第一掩膜层具有第一开孔，所述第一开孔的形状与所述凹陷区域的形状相同；对所述第一掩膜层曝光，使所述光阻显影，暴露所述金手指本体与所述第一开孔对应的区域；对所述金手指本体与所述第一开孔对应的区域进行蚀刻，形成所述凹陷区域。In an exemplary embodiment of the present disclosure, etching a recessed area on the surface of the gold finger body includes: coating a photoresist on the surface of the gold finger body; forming a first photoresist on the photoresist. Mask layer, the first mask layer has a first opening, the shape of the first opening is the same as the shape of the recessed area; the first mask layer is exposed to develop the photoresist , exposing the area of the gold finger body corresponding to the first opening; and etching the area of the gold finger body corresponding to the first opening to form the recessed area.
本公开的一种示例性实施方式中，所述凹陷区域包括阶梯状结构的刻蚀孔，所述阶梯状结构包括第一深度孔和第二深度孔，所述第一深度孔的深度大于所述第二深度孔的深度。In an exemplary embodiment of the present disclosure, the recessed area includes an etching hole with a stepped structure, the stepped structure includes a first depth hole and a second depth hole, and the depth of the first depth hole is greater than the etching hole. The depth of the second depth hole.
本公开的一种示例性实施方式中，所述在所述金手指本体的表面刻蚀凹陷区域，包括：在所述金手指本体的表面涂覆光阻；在所述光阻上形成第二掩膜层，所述第二掩膜层具有 第二开孔，所述第二开孔的形状与所述第一深度孔的形状相同；对所述第二掩膜层曝光，使所述光阻显影，暴露所述金手指本体与所述第二开孔对应的区域；对所述金手指本体与所述第二开孔对应的区域进行蚀刻，形成所述第一深度孔的部分区域；去除所述第二掩膜层，在所述光阻上形成第三掩膜层，所述第三掩膜层具有第三开孔，所述第三开孔用于暴露所述第一深度孔和所述第二深度孔对应的区域；对所述第三掩膜层曝光，使所述光阻显影，暴露所述金手指本体与所述第三开孔对应的区域；对所述金手指本体与所述第三开孔对应的区域进行蚀刻，形成所述凹陷区域。In an exemplary embodiment of the present disclosure, etching a recessed area on the surface of the gold finger body includes: coating a photoresist on the surface of the gold finger body; forming a second photoresist on the photoresist. Mask layer, the second mask layer has a second opening, the shape of the second opening is the same as the shape of the first depth hole; the second mask layer is exposed to make the light Resist development to expose the area of the gold finger body corresponding to the second opening; etching the area of the gold finger body corresponding to the second opening to form a partial area of the first depth hole; The second mask layer is removed, and a third mask layer is formed on the photoresist. The third mask layer has a third opening, and the third opening is used to expose the first depth hole. The area corresponding to the second depth hole; exposing the third mask layer to develop the photoresist to expose the area of the gold finger body corresponding to the third opening; exposing the gold finger The area of the body corresponding to the third opening is etched to form the recessed area.
本公开的一种示例性实施方式中，对所述金手指本体与所述第二开孔对应的区域进行蚀刻的蚀刻深度为所述第一深度孔和所述第二深度孔的深度差值；对所述金手指本体与所述第三开孔对应的区域进行蚀刻的蚀刻深度为所述第二深度孔的深度。In an exemplary embodiment of the present disclosure, the etching depth of the area corresponding to the gold finger body and the second opening is a depth difference between the first depth hole and the second depth hole. ; The etching depth of the area corresponding to the gold finger body and the third opening is the depth of the second depth hole.
根据本公开的第三方面，提供一种半导体封装结构，包括：封装基板，所述封装基板包括基板和形成于所述基板上的金手指，所述金手指的表面上形成有凹陷区域，所述凹陷区域用于压合金线的一端；芯片堆叠结构，设置在所述封装基板上，所述金线的另一端压焊在所述芯片堆叠结构上。According to a third aspect of the present disclosure, a semiconductor packaging structure is provided, including: a packaging substrate, the packaging substrate includes a substrate and a gold finger formed on the substrate, and a recessed area is formed on the surface of the gold finger. The recessed area is used to press one end of the alloy wire; the chip stack structure is provided on the packaging substrate, and the other end of the gold wire is press-welded on the chip stack structure.
附图说明Description of drawings
图1为本公开示例性实施方式提供的一种金手指排布示意图。Figure 1 is a schematic diagram of a golden finger arrangement provided by an exemplary embodiment of the present disclosure.
图2为图1中的局部放大图。Figure 2 is a partial enlarged view of Figure 1.
图3为本公开示例性实施方式提供的一种半导体封装基板的结构示意图。FIG. 3 is a schematic structural diagram of a semiconductor packaging substrate provided by an exemplary embodiment of the present disclosure.
图4-图6为本公开示例性实施方式提供的一种具有不同数量过蚀孔的金手指本体的结构示意图。4-6 are schematic structural diagrams of a gold finger body with different numbers of via holes provided by an exemplary embodiment of the present disclosure.
图7为本公开示例性实施方式提供的一种阶梯状过蚀孔的结构示意图。FIG. 7 is a schematic structural diagram of a stepped via hole provided by an exemplary embodiment of the present disclosure.
图8为本公开示例性实施方式提供的一种封装打线过程的流程示意图。FIG. 8 is a schematic flowchart of a packaging wiring process provided by an exemplary embodiment of the present disclosure.
图9为本公开示例性实施方式提供的一种焊头压合金线在阶梯状过蚀孔内的结构示意图。FIG. 9 is a schematic structural diagram of a welding head pressing an alloy wire in a stepped etching hole according to an exemplary embodiment of the present disclosure.
图10为本公开示例性实施方式提供的一种半导体封装基板的制作方法的步骤流程图。FIG. 10 is a flow chart of a method for manufacturing a semiconductor packaging substrate according to an exemplary embodiment of the present disclosure.
图11(a)-图11(f)为本公开示例性实施方式提供的一种半导体封装基板的制作方法的工艺步骤图。11(a)-11(f) are process step diagrams of a method for manufacturing a semiconductor packaging substrate provided by an exemplary embodiment of the present disclosure.
图12(a)-图12(f)为本公开示例性实施方式提供的另一种半导体封装基板的制作方法的工艺步骤图。12(a) to 12(f) are process step diagrams of another method of manufacturing a semiconductor packaging substrate provided by an exemplary embodiment of the present disclosure.
图13为本公开示例性实施方式提供的一种半导体封装结构的结构示意图。FIG. 13 is a schematic structural diagram of a semiconductor packaging structure provided by an exemplary embodiment of the present disclosure.
图14为本公开示例性实施方式提供的粘结层的结构示意图。Figure 14 is a schematic structural diagram of an adhesive layer provided by an exemplary embodiment of the present disclosure.
图15为本公开示例性实施方式提供的一种半导体封装结构的结构示意图。FIG. 15 is a schematic structural diagram of a semiconductor packaging structure provided by an exemplary embodiment of the present disclosure.
具体实施方式Detailed ways
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art. The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能 实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and/or processor devices and/or microcontroller devices.
附图中所示的流程图仅是示例性说明，不是必须包括所有的步骤。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。另外，下面所有的术语“第一”、“第二”、“第三”仅是为了区分的目的，不应作为本公开内容的限制。The flowcharts shown in the figures are illustrative only and do not necessarily include all steps. For example, some steps can be decomposed, and some steps can be merged or partially merged, so the actual order of execution may change according to the actual situation. In addition, all the following terms "first", "second" and "third" are only for the purpose of distinction and should not be used to limit the present disclosure.
为了满足电子产品功能的多样化、便携化的发展要求，印制电路板不仅出现高孔径比、精细线路的高精密特征，还出现了金手指等应用于高速通讯的高密度电路板设计。在电子类产品功能应用上，为了减少讯号传输的损失，高速存储产品一般都需要使用带金手指设计的电路板作为载板。金手指由众多金黄色的导电触片组成，其表面镀有抗氧化性、传导性极强的金、而且导电触片排列如手指状，所以称为“金手指”。In order to meet the development requirements of diversified functions and portability of electronic products, printed circuit boards not only have high-precision features such as high aperture ratio and fine lines, but also high-density circuit board designs such as gold fingers for high-speed communications. In the functional application of electronic products, in order to reduce the loss of signal transmission, high-speed storage products generally need to use circuit boards with golden finger designs as carrier boards. Gold fingers are composed of many golden conductive contacts. The surface is plated with gold that is resistant to oxidation and has strong conductivity. The conductive contacts are arranged like fingers, so they are called "gold fingers".
金手指(Connecting Finger)通常指形成于电路板上用于连接插槽的连接部件，所有的信号都是通过金手指进行传送的，因此金手指对于电路板的性能来说是很重要的，举例来说，对于个人电脑中的内存单元来说，内存处理单元的所有数据流、电子流正是通过金手指与内存插槽的接触与PC***进行交换，是内存的输出输入端口。Connecting Finger usually refers to the connecting component formed on the circuit board for connecting the slot. All signals are transmitted through the connecting finger, so the connecting finger is very important for the performance of the circuit board. For example For the memory unit in a personal computer, all data flows and electron flows of the memory processing unit are exchanged with the PC system through the contact between the gold finger and the memory slot, which is the output and input port of the memory.
金手指用于印刷电路板之间的连接，能够连接电路和传输信号。金手指表面的镍金层能够提高该部位的耐插拔性、导电性和抗氧化性。金手指一般分为等长金手指、分级金手指以及分段金手指，分级、分段金手指在设计上突破了原始的金手指设计理念，将金手指设计为长短不一或分段的结构，这样在信号传输过程中形成有效的时间差，便于高频信号的传输，而且可以实现带电热拔插技术，从而对后续的升级维护提供便利。Gold fingers are used for connections between printed circuit boards, capable of connecting circuits and transmitting signals. The nickel-gold layer on the surface of the gold finger can improve the insertion and removal resistance, conductivity and oxidation resistance of this part. Gold fingers are generally divided into equal-length gold fingers, graded gold fingers and segmented gold fingers. The design of graded and segmented gold fingers breaks through the original gold finger design concept and designs the gold fingers into different lengths or segmented structures. , which forms an effective time difference during the signal transmission process, facilitates the transmission of high-frequency signals, and can implement hot-swap technology, thus facilitating subsequent upgrades and maintenance.
在半导体封装制程中，经常会涉及将晶片(Die)上的电极与导线架(Frame)或基板(Substrate)上的金手指以金线连接的键合(Wire Bonding)操作，通常，金线通过焊接的形式连接在金手指表面上。金手指表面均为光滑表面，金手指上的焊点通过热压成型后，需要保证具有足够的结合力以确保焊接质量的稳定。一般，结合力的大小与焊点的接触面积成正相关关系。In the semiconductor packaging process, it often involves a bonding operation (Wire Bonding) that connects the electrodes on the chip (Die) and the gold fingers on the lead frame (Frame) or substrate (Substrate) with gold wires. Usually, the gold wire passes Welded to the surface of the gold finger. The surface of the gold fingers is all smooth. After the solder joints on the gold fingers are formed by hot pressing, they need to have sufficient bonding force to ensure the stability of the welding quality. Generally, the size of the bonding force is positively correlated with the contact area of the solder joint.
参照图1，示出了本公开示例性实施方式提供的一种金手指排布示意图，如图1所示，相邻两个金手指之间的距离称为金手指的中心间距(pitch)，当金手指的中心间距一定时，金手指的表面宽度(top width)和间隙(space)相互制约。结合图2的局部放大图可以看出，金手指的表面宽度和间隙之和构成一个中心间距。Referring to Figure 1 , a schematic diagram of a gold finger arrangement provided by an exemplary embodiment of the present disclosure is shown. As shown in Figure 1 , the distance between two adjacent gold fingers is called the center pitch of the gold fingers. When the center distance of the gold fingers is constant, the surface width (top width) and gap (space) of the gold fingers restrict each other. It can be seen from the partial enlarged view of Figure 2 that the sum of the surface width and the gap of the gold finger constitutes a center spacing.
在金手指的中心间距较大时，在保证金手指表面宽度的情况下，金手指的间隙仍能满足可靠性离子迁移的要求。然而，随着半导体封装技术的不断提升，封装要求不断提高，导致金手指的中心间距越来越小。由于金手指的间隙涉及到质量可靠性不能减小，因此，只能通过减小金手指的表面宽度来达到减小中心间距的目的。When the center spacing of the gold fingers is large, the gap between the gold fingers can still meet the requirements for reliable ion migration while ensuring the surface width of the gold fingers. However, with the continuous improvement of semiconductor packaging technology, packaging requirements continue to increase, resulting in the center distance of gold fingers getting smaller and smaller. Since the gap between gold fingers cannot be reduced when it comes to quality reliability, the purpose of reducing the center distance can only be achieved by reducing the surface width of the gold fingers.
随着金手指的表面宽度的减小，金手指表面焊点的接触面积也变小了，为了避免焊点超出金手指表面，通常需要减小金线的直径。然而，减小金线的直径必然导致金线与金手指表面之间焊点的结合面积变小，进而导致金线和金手指表面的结合力降低，所制成的半导体封装结构存在品质风险。As the surface width of the gold finger decreases, the contact area of the solder points on the surface of the gold finger also becomes smaller. In order to prevent the solder points from exceeding the surface of the gold finger, it is usually necessary to reduce the diameter of the gold wire. However, reducing the diameter of the gold wire will inevitably lead to a smaller bonding area of the solder joints between the gold wire and the surface of the gold finger, which in turn will lead to a reduction in the bonding force between the gold wire and the surface of the gold finger. The resulting semiconductor packaging structure will have quality risks.
基于此，本公开示例性实施方式提供了一种半导体封装基板，参照图3所示，该半导体封装基板300包括基板310和金手指本体320，其中，金手指本体320形成于基板310上，并且，金手指本体320的表面上形成有凹陷区域，该凹陷区域用于压合金线。Based on this, exemplary embodiments of the present disclosure provide a semiconductor packaging substrate. Referring to FIG. 3 , the semiconductor packaging substrate 300 includes a substrate 310 and a gold finger body 320 , wherein the gold finger body 320 is formed on the substrate 310 , and , a recessed area is formed on the surface of the gold finger body 320, and the recessed area is used for pressing alloy wires.
本公开示例性实施方式提供的半导体封装基板300，通过在金手指本体320的表面形成凹陷区域，在将金线压合于凹陷区域后，可以增大金线与金手指表面的结合面积，进而增大金线与金手指表面的结合力，从而可以提高半导体封装基板300的品质。In the semiconductor packaging substrate 300 provided by the exemplary embodiment of the present disclosure, by forming a recessed area on the surface of the gold finger body 320, after the gold wire is pressed into the recessed area, the bonding area between the gold wire and the gold finger surface can be increased, thereby increasing the bonding area between the gold wire and the gold finger surface. The bonding force between the gold wire and the gold finger surface is increased, thereby improving the quality of the semiconductor packaging substrate 300 .
在实际应用中，金线具有硬度低、应力小、不容易产生弹坑、抗氧化性好、在高温高 湿环境下的长期可靠性好等优点，因此，通常通过金线来连接金手指和其他元件，例如，连接芯片等。In practical applications, gold wire has the advantages of low hardness, low stress, not prone to craters, good oxidation resistance, and good long-term reliability in high temperature and high humidity environments. Therefore, gold wires are usually used to connect gold fingers and other Components, for example, connection chips, etc.
在实际应用中，基板310是制造PCB的基本材料，其中，PCB全称为Printed Circuit Board，中文为印刷线路板或印制电路板，以下简称线路板；线路板为电子元件的载体。随着电子技术的发展，各类电子产品对印制线路板有着最新的要求，PCB板趋于向短、小、轻、薄的方向发展，其集成度很高，新型产品对金手指的需求越来越高，“金手指”用于光纤模块、计算机显卡、内存条以及各种含有USB接口的相关设备与其它基板相接触的部位。In practical applications, the substrate 310 is the basic material for manufacturing PCB. The full name of PCB is Printed Circuit Board, which in Chinese is printed circuit board or printed circuit board, hereinafter referred to as circuit board; circuit board is the carrier of electronic components. With the development of electronic technology, various electronic products have the latest requirements for printed circuit boards. PCB boards tend to develop in the direction of short, small, light and thin, and their integration is very high. New products have a demand for golden fingers. Increasingly, "golden fingers" are used in areas where fiber optic modules, computer graphics cards, memory sticks, and various related devices containing USB interfaces are in contact with other substrates.
一般情况下，基板310就是覆铜箔层压板，单、双面印制板在制造中是在基板材料-覆铜箔层压板(Copper Clad Laminate，CCL)上，有选择地进行孔加工、化学镀铜、电镀铜、蚀刻等加工，得到所需电路图形。另一类多层印制板的制造，也是以内芯薄型覆铜箔板为基底，将导电图形层与半固化片交替地经一次性层压黏合在一起，形成3层以上导电图形层间互连。它具有导电、绝缘和支撑三个方面的功能。印制板的性能、质量、制造中的加工性、制造成本、制造水平等，在很大程度上取决于基板材料。Under normal circumstances, the substrate 310 is a copper clad laminate. Single-sided and double-sided printed boards are manufactured on the substrate material - copper clad laminate (Copper Clad Laminate, CCL), with selective hole processing and chemical processing. Copper plating, copper electroplating, etching and other processes can be used to obtain the required circuit pattern. Another type of multi-layer printed board manufacturing also uses an inner core thin copper-clad cladding board as the base. The conductive pattern layers and prepreg sheets are alternately laminated and bonded together at one time to form more than three layers of conductive pattern interconnections. It has three functions: conduction, insulation and support. The performance, quality, processability in manufacturing, manufacturing cost, manufacturing level, etc. of printed boards largely depend on the substrate material.
通常，基板310的制作方法包括减成法和加成法，减成法(Subtractive)工艺是在覆铜箔层压板表面上，有选择性除去部分铜箔来获得导电图形的方法。减成法是当今印制电路制造的主要方法，它的最大优点是工艺成熟、稳定和可靠。加成法是在绝缘基材表面上，有选择性地沉积导电金属而形成导电图形的方法。Generally, the manufacturing method of the substrate 310 includes a subtractive method and an additive method. The subtractive method is a method of selectively removing part of the copper foil on the surface of the copper-clad laminate to obtain a conductive pattern. The subtractive method is the main method for manufacturing printed circuits today. Its biggest advantage is that the process is mature, stable and reliable. The additive method is a method of selectively depositing conductive metal on the surface of an insulating substrate to form a conductive pattern.
加成法包括：全加成法(Full Additive Process,FAP)、半加成法(Semi-additive Process,SAP)和改进半加成法(MSAP)，其中，全加成法是仅用化学沉铜方法形成导电图形的加成法工艺。半加成法是在绝缘基材表面上，用化学沉积金属，结合电镀蚀刻或者三者并用形成导电图形的加成法工艺，当线宽间距小于25um时多采用SAP法，SAP法成本较高，工艺复杂。改进半加成法是针对SAP工艺成本较高，提出的采用较便宜的超薄铜皮式的SAP模拟法。Additive methods include: Full Additive Process (FAP), Semi-additive Process (SAP) and improved semi-additive method (MSAP). Among them, the full additive method uses only chemical precipitation. The copper method is an additive process for forming conductive patterns. The semi-additive method is an additive process that uses chemical deposition of metal on the surface of an insulating substrate, combined with electroplating and etching, or a combination of the three to form a conductive pattern. When the line width and spacing are less than 25um, the SAP method is often used. The cost of the SAP method is higher. , the process is complex. The improved semi-additive method is a cheaper ultra-thin copper-skin SAP simulation method proposed in view of the high cost of the SAP process.
在实际应用中，在PCB板上制作金手指的工艺流程主要包括以下工序：先对PCB开料→内层图形制作→内层自动光学检测→内外层压合→外层钻孔→沉铜→全板电镀→外层图形制作→图形电镀→外层蚀刻→外层自动光学检测→丝印抗电金油→第二次外层图形制作→电镀镍金→局部电金→退膜→第三次外层图形制作→第二次外层蚀刻→第二次退膜→第二次外层自动光学检测→丝印阻焊→字符→过程胶带→沉镍金→锣电路板成品外形→电测试→终检→包装。In practical applications, the process flow of making gold fingers on PCB boards mainly includes the following processes: first cutting the PCB → making inner layer graphics → automatic optical inspection of the inner layer → laminating the inner and outer layers → drilling the outer layer → immersing copper → Full board electroplating → Outer layer pattern production → Graphic electroplating → Outer layer etching → Outer layer automatic optical inspection → Silk screen anti-electric gold oil → Second outer layer pattern production → Nickel gold plating → Partial electroplating → Film removal → The third time Outer layer pattern production → second outer layer etching → second outer layer stripping → second outer layer automatic optical inspection → silk screen solder mask → characters → process tape → immersed nickel gold → finished circuit board shape → electrical test → final Inspect → Pack.
本公开示例性实施方式中，在基板310上形成金手指本体320的过程中，可以是在基板310上涂覆光刻胶，然后对光刻胶进行显影得到显影区域，再在显影区域内采用FAP、SAP或MSAP等方法沉铜获得金手指本体320。In an exemplary embodiment of the present disclosure, in the process of forming the gold finger body 320 on the substrate 310, photoresist may be coated on the substrate 310, and then the photoresist may be developed to obtain a developed area, and then a photoresist may be used in the developed area. Use methods such as FAP, SAP or MSAP to immerse yourself in copper to obtain the gold finger body 320.
与上述金手指的工艺流程不同的是，本公开示例性实施方式在沉铜获得金手指本体320后，需要在金手指本体320的表面上形成凹陷区域。其中对于凹陷区域的形成过程将在后续实施方式中进行详细说明，此处不作赘述。Different from the above-mentioned gold finger process flow, in the exemplary embodiment of the present disclosure, after the gold finger body 320 is obtained by immersing copper, a recessed area needs to be formed on the surface of the gold finger body 320 . The formation process of the recessed area will be described in detail in subsequent embodiments and will not be described in detail here.
由于凹陷区域主要是通过过蚀刻的方式获得的，因此，本公开示例性实施方式中，金手指本体320表面上形成的凹陷区域可以包括至少一个过蚀孔。如图3所示，基板310上示出了两个金手指本体320，每个金手指本体320上所形成的凹陷区域均具有两个过蚀孔322。Since the recessed area is mainly obtained by over-etching, in the exemplary embodiment of the present disclosure, the recessed area formed on the surface of the gold finger body 320 may include at least one over-etched hole. As shown in FIG. 3 , two gold finger bodies 320 are shown on the substrate 310 , and the recessed area formed on each gold finger body 320 has two through-etch holes 322 .
在实际应用中，凹陷区域的过蚀孔322可以是一个、可以是两个，也可以是三个、四个等多个，在过蚀孔322有多个的情况下，多个过蚀孔322可以阵列排布。参照图4-图6，示出了金手指本体上过蚀孔的排列方式，图4中，过蚀孔322有两个，两个过蚀孔322排列在一条线上，具体可以是沿着金线在金手指本体320上的延伸方向排列。图5中，过蚀孔322有三个，三个过蚀孔322排列成三角形，但需要说明的是，这三个过蚀孔322需要 在金线与金手指本体320的焊点之下，被焊点覆盖。图6中，过蚀孔322有四个，四个过蚀孔322排列成正方形，同样的，这四个过蚀孔322需要在金线与金手指本体320的焊点之下，被焊点覆盖。In practical applications, the number of through-etch holes 322 in the recessed area may be one, two, or three or four. In the case where there are multiple through-etch holes 322, the number of through-etch holes 322 may be 322 can be arranged in array. Referring to Figures 4-6, the arrangement of over-etched holes on the gold finger body is shown. In Figure 4, there are two through-etched holes 322, and the two through-etched holes 322 are arranged in a line, specifically along the The gold wires are arranged in the extending direction of the gold finger body 320 . In Figure 5, there are three etched holes 322, and the three etched holes 322 are arranged in a triangle. However, it should be noted that these three etched holes 322 need to be under the solder joint between the gold wire and the gold finger body 320. Solder joint coverage. In Figure 6, there are four through-etch holes 322, and the four through-etch holes 322 are arranged in a square shape. Similarly, these four through-etch holes 322 need to be under the solder joints between the gold wire and the gold finger body 320. cover.
需要说明的是，本公开示例性实施方式中，在过蚀孔322有多个的情况下，多个过蚀孔322可以沿金线在金手指本体320上的延伸方向排列，并且要确保金线与金手指本体320的焊点覆盖所有过蚀孔322，以使焊接金线与金手指本体320时，部分金线可以进入到所有的过蚀孔322中，从而增大金线与金手指本体320表面的接触面积，使焊点的结合面积变大，结合力变强。It should be noted that in the exemplary embodiment of the present disclosure, when there are multiple via holes 322 , the multiple via holes 322 can be arranged along the extension direction of the gold wire on the gold finger body 320 , and it is necessary to ensure that the gold wires are The solder joints between the wire and the gold finger body 320 cover all the over-etched holes 322, so that when welding the gold wire and the gold finger body 320, part of the gold wire can enter all the over-etched holes 322, thereby increasing the size of the gold wire and the gold finger. The contact area on the surface of the body 320 makes the bonding area of the solder joint larger and the bonding force stronger.
本公开示例性实施方式提供的半导体封装基板，通过在金手指本体320上设置凹陷区域，在凹陷区域只包括一个过蚀孔322的情况下，可以增大金线与金手指本体320表面的接触面积；在凹陷区域包括多个过蚀孔322的情况下，可以进一步增大金线与金手指本体320表面的接触面积，提高焊点的结合力。In the semiconductor packaging substrate provided by the exemplary embodiment of the present disclosure, by providing a recessed area on the gold finger body 320, when the recessed area only includes one through-etch hole 322, the contact between the gold wire and the surface of the gold finger body 320 can be increased. area; when the recessed area includes multiple etching holes 322, the contact area between the gold wire and the surface of the gold finger body 320 can be further increased to improve the bonding force of the solder joints.
需要说明的是，在凹陷区域只包括一个过蚀孔322的情况下，可以通过增大过蚀孔322的截面积来进一步增大金线与金手指本体320表面的接触面积，以获得更高的结合力。It should be noted that when the recessed area only includes one through-etch hole 322, the contact area between the gold wire and the surface of the gold finger body 320 can be further increased by increasing the cross-sectional area of the through-etch hole 322 to obtain a higher the binding force.
在实际应用中，凹陷区域的区域大小，也就是过蚀孔322的截面积可以根据金手指本体320的表面大小来确定，凹陷区域的区域宽度必须小于金手指本体320的表面宽度，本公开示例性实施方式对于凹陷区域的具体区域大小不作特殊限定。In practical applications, the size of the recessed area, that is, the cross-sectional area of the over-etch hole 322, can be determined according to the surface size of the gold finger body 320. The width of the recessed area must be smaller than the surface width of the gold finger body 320. Examples of this disclosure The specific embodiment does not specifically limit the size of the recessed area.
本公开示例性实施方式中，过蚀孔322的截面形状可以有多种，例如，为圆形、星形、三角形和多边形等，其中，过蚀孔322的截面形状以多边形更优，因为多边形可以增大过蚀孔322的孔壁表面积，使得金线与过蚀孔322的接触面积更大。不过在实际应用中，需要对多边形的角进行倒圆角连接过渡。In the exemplary embodiment of the present disclosure, the cross-sectional shape of the through-etch hole 322 may be in a variety of shapes, such as a circle, a star, a triangle, a polygon, etc., among which the cross-sectional shape of the through-etch hole 322 is a polygon, because the cross-sectional shape is a polygon. The surface area of the hole wall of the through-etch hole 322 can be increased, so that the contact area between the gold wire and the through-etch hole 322 is larger. However, in practical applications, the corners of polygons need to be rounded and connected.
在实际应用中，对过蚀孔322的深度也需要有一定的约束，过蚀孔322的深度必须小于金手指本体320的厚度，例如，过蚀孔322的深度小于3um等，本公开示例性实施方式对于过蚀孔322的具体深度不作特殊限定。In practical applications, there are also certain constraints on the depth of the over-etched hole 322. The depth of the over-etched hole 322 must be less than the thickness of the gold finger body 320. For example, the depth of the over-etched hole 322 is less than 3um, etc. The exemplary embodiment of this disclosure The specific depth of the over-etch hole 322 is not particularly limited in the embodiment.
本公开示例性实施方式中，过蚀孔322除过具有上述的孔状结构外，参照图7示出了过蚀孔的另一种结构形式，即如图7所示，过蚀孔322还可以是阶梯状结构，即一个过蚀孔322内包含多个不同深度的孔。In the exemplary embodiment of the present disclosure, in addition to having the above-mentioned hole-like structure, another structural form of the through-etch hole 322 is shown with reference to FIG. 7 , that is, as shown in FIG. 7 , the through-etch hole 322 also has It may be a stepped structure, that is, one over-etch hole 322 includes multiple holes with different depths.
图7所示的过蚀孔322的阶梯状结构包括第一深度孔3221和第二深度孔3222，其中，第一深度孔3221的深度大于第二深度孔3222的深度。将过蚀孔322设置成阶梯状结构是与金线在金手指本体320的打线压合过程有关的。The stepped structure of the over-etch hole 322 shown in FIG. 7 includes a first depth hole 3221 and a second depth hole 3222, wherein the depth of the first depth hole 3221 is greater than the depth of the second depth hole 3222. Setting the over-etch holes 322 into a stepped structure is related to the wire bonding process of the gold wire on the gold finger body 320 .
参照图8，示出了一种封装打线过程的流程示意图。如图8所示，在焊头810控制金线820以将金线820先后焊接在芯片830和金手指840的过程中，首先是步骤①，焊头810在打火高度上对金线进行烧球过程；接着，进入步骤②，焊头810由打火高度下降到第一焊点，以将金线820焊接在芯片830上；完成第一点压焊后，焊头810上升移动到金手指840的上方，使得金线820拉出线弧，如步骤③所示。接着，进入步骤④，焊头810下降到第二焊点，焊头810通过加热使得金线820融化，从而将金线820压焊在金手指840上；接着，在步骤⑤中，焊头810提升，将金线820拉断与金手指840分离；最后如步骤⑥所示，焊头810带动剩余的金线820回原位。Referring to FIG. 8 , a schematic flow chart of a packaging wiring process is shown. As shown in Figure 8, in the process of the welding head 810 controlling the gold wire 820 to weld the gold wire 820 to the chip 830 and the gold finger 840, the first step is step ①. The welding head 810 burns the gold wire at the ignition height. ball process; then, enter step ②, the welding head 810 drops from the ignition height to the first soldering point to weld the gold wire 820 to the chip 830; after completing the first point pressure welding, the welding head 810 rises and moves to the gold finger Above 840, make the gold wire 820 pull out a wire arc, as shown in step ③. Then, enter step ④, the welding head 810 descends to the second soldering point, and the welding head 810 melts the gold wire 820 by heating, so that the gold wire 820 is pressure-welded to the gold finger 840; then, in step ⑤, the welding head 810 Lift up, pull off the gold wire 820 and separate it from the gold finger 840; finally, as shown in step ⑥, the welding head 810 drives the remaining gold wire 820 back to its original position.
在上述封装打线过程中，特别是步骤④中将金线820压焊在金手指840上的过程中，随着焊头810的逐渐下降，金线820的压焊点会有所偏移，并且金线820受到的焊头810的压力也会逐渐增大，起初的焊点和最终的焊点相比，最终的焊点受到的挤压力更大，因此，本公开示例性实施方式将过蚀孔322设置成阶梯状结构，且阶梯状结构所包含的深度孔的深度不同。During the above package wiring process, especially the process of pressing the gold wire 820 on the gold finger 840 in step ④, as the welding head 810 gradually descends, the pressure soldering point of the gold wire 820 will shift. In addition, the pressure of the welding head 810 on the gold wire 820 will also gradually increase. Compared with the initial solder joint and the final solder joint, the final solder joint will receive a greater extrusion force. Therefore, the exemplary embodiment of the present disclosure will The over-etched holes 322 are arranged in a stepped structure, and the depth holes included in the stepped structure have different depths.
如图9所示，焊头810在将金线820压焊在金手指840的过程中，金线820与金手指840的初始接触点，即初始焊点正好位于第二深度孔3222的位置，最终的焊点可能正好位 于第一深度孔3221的位置，由于最终的焊点受到的挤压力更大，会有更多的金线820融合在第一深度孔3221内，因此，将第一深度孔3221设置的更深一些，可以容纳更多的金线820；而将第二深度孔3222设置的较浅一些，以在满足容纳金线820的情况下，确保金手指840具有足够的强度。As shown in Figure 9, when the welding head 810 presses and welds the gold wire 820 to the gold finger 840, the initial contact point between the gold wire 820 and the gold finger 840, that is, the initial soldering point is exactly at the position of the second depth hole 3222. The final solder joint may be located exactly at the position of the first depth hole 3221. Since the final solder joint is subject to greater extrusion force, more gold wires 820 will be fused into the first depth hole 3221. Therefore, the first depth hole 3221 will be The depth hole 3221 is set deeper to accommodate more gold wires 820; while the second depth hole 3222 is set shallower to ensure that the gold finger 840 has sufficient strength while accommodating the gold wires 820.
当然，在实际应用中，第一深度孔3221的深度也不能太深，一般可以将第一深度孔3221的深度设置为小于或等于1/3倍的金线820直径即可，本公开示例性实施方式对于第一深度孔3221和第二深度孔3222的具体深度不作特殊限定。Of course, in practical applications, the depth of the first depth hole 3221 cannot be too deep. Generally, the depth of the first depth hole 3221 can be set to less than or equal to 1/3 times the diameter of the gold wire 820. The exemplary embodiment of this disclosure The embodiment does not specifically limit the specific depths of the first depth hole 3221 and the second depth hole 3222.
本公开示例性实施方式中，过蚀孔322的阶梯状结构的阶梯位置位于压头着力点的下方，也就是位于焊头810在金手指上的着力点的下方。In the exemplary embodiment of the present disclosure, the step position of the stepped structure of the over-etch hole 322 is located below the contact point of the indenter, that is, below the contact point of the welding head 810 on the gold finger.
在实际应用中，由于压头的作用力方向是竖直向下的，过蚀孔322的阶梯状结构沿压头作用力方向梯度深度增加，如此可以使金线820较多地进入较深的深度孔中，从而增加金线820与过蚀孔322的接触面积，使得焊接点更加牢固。In practical applications, since the force direction of the indenter is vertically downward, the step-like structure of the over-etch hole 322 increases in depth along the force direction of the indenter, which allows more gold wires 820 to enter deeper holes. into the deep hole, thereby increasing the contact area between the gold wire 820 and the over-etched hole 322, making the solder joint stronger.
本公开示例性实施方式提供的半导体封装基板，通过在金手指本体上设置凹陷区域，并且使凹陷区域包含过蚀孔，另外，又是过蚀孔为阶梯状结构，都可以增大金线压合过程中，与金手指的接触面积，使得焊点的结合力增强，从而增加半导体封装基板的品质。The semiconductor packaging substrate provided by the exemplary embodiments of the present disclosure can increase the gold line pressure by arranging a recessed area on the gold finger body and making the recessed area contain an etching hole. In addition, the over-etching hole has a stepped structure. During the bonding process, the contact area with the gold fingers enhances the bonding force of the solder joints, thus increasing the quality of the semiconductor packaging substrate.
在上述提供的半导体封装基板的基础上，本公开示例性实施方式还提供了一种半导体封装基板的制作方法。参照图10，该半导体封装基板的制作方法的流程步骤如下：Based on the semiconductor packaging substrate provided above, exemplary embodiments of the present disclosure also provide a method for manufacturing a semiconductor packaging substrate. Referring to Figure 10, the process steps of the manufacturing method of the semiconductor packaging substrate are as follows:
步骤S1010、提供基板；Step S1010, provide a substrate;
步骤S1020、在基板上形成金手指本体；Step S1020: Form a gold finger body on the substrate;
步骤S1030、在金手指本体的表面刻蚀凹陷区域，凹陷区域用于压合金线；Step S1030: Etch a recessed area on the surface of the gold finger body, and the recessed area is used to press the alloy wire;
步骤S1040、在刻蚀有凹陷区域的金手指本体的表面镀镍、镀金。Step S1040: Plate nickel or gold on the surface of the gold finger body with the recessed area etched.
本公开示例性实施方式提供的半导体封装基板的制作方法，与常规半导体封装基板的制作方法不同的是，在金手指本体的表面刻蚀有凹陷区域，并通过将金线压合在凹陷区域内，可以增大金线与金手指本体表面的结合面积，从而增大结合力，提高焊接的品质。The manufacturing method of a semiconductor packaging substrate provided by exemplary embodiments of the present disclosure is different from the manufacturing method of a conventional semiconductor packaging substrate in that a recessed area is etched on the surface of the gold finger body, and a gold wire is pressed into the recessed area. , can increase the bonding area between the gold wire and the surface of the gold finger body, thereby increasing the bonding force and improving the quality of welding.
下面将结合截面图图11(a)-图11(f)详细描述本公开示例性实施方式中半导体封装基板的制作方法。The manufacturing method of the semiconductor packaging substrate in the exemplary embodiment of the present disclosure will be described in detail below with reference to the cross-sectional views of FIGS. 11(a) to 11(f).
如图11(a)所示，先提供基板310，所提供的基板310为覆铜箔层压板，通过减成法或加成法可以制作基板310。在基板310上铺设一层光刻胶1110，对该光刻胶1110进行显影，获得第一通槽，使得第一通槽暴露基板310的表面，具体可以通过在光刻胶1110上铺设掩膜板来进行显影，此处不再赘述。As shown in FIG. 11(a) , a substrate 310 is first provided. The provided substrate 310 is a copper-clad laminate. The substrate 310 can be produced by a subtractive method or an additive method. Lay a layer of photoresist 1110 on the substrate 310 , develop the photoresist 1110 to obtain a first through groove, so that the first through groove exposes the surface of the substrate 310 , specifically by laying a mask on the photoresist 1110 The board is used for development, so I won’t go into details here.
在获得第一通槽后，如图11(b)所示，在第一通槽内填充金手指本体320，使基板310上形成金手指本体320，其中，金手指本体320可以通过将铜材料在第一通槽内电镀而形成。After obtaining the first through groove, as shown in Figure 11(b), the gold finger body 320 is filled in the first through groove, so that the gold finger body 320 is formed on the substrate 310. The gold finger body 320 can be made of copper material. It is formed by electroplating in the first through groove.
在获得金手指本体320后，可以在金手指本体320的表面刻蚀凹陷区域，具体，如图11(c)所示，可以在金手指本体320的表面涂覆光阻1120，其中，光阻1120是一种光敏材料，分为正向光阻和负向光阻两种。对于正向光阻而言，其照到光的部分会溶于光阻显影液，而没有照到光的部分不会溶于光阻显影液；对于负向光阻而言，其照到光的部分不会溶于光阻显影液，而没有照到光的部分会溶于光阻显影液。利用光阻的这个特性可以进行显影操作。After obtaining the gold finger body 320, a recessed area can be etched on the surface of the gold finger body 320. Specifically, as shown in Figure 11(c), a photoresist 1120 can be coated on the surface of the gold finger body 320, where the photoresist 1120 is a photosensitive material, divided into two types: positive photoresist and negative photoresist. For positive photoresist, the part exposed to light will dissolve in the photoresist developer, while the part not exposed to light will not dissolve in the photoresist developer; for negative photoresist, the part exposed to light will not dissolve in the photoresist developer. The part that is not exposed to light will not dissolve in the photoresist developer, while the part that is not exposed to light will dissolve in the photoresist developer. This characteristic of photoresist can be used for developing operations.
本公开示例性实施方式中，在金手指本体320的表面涂覆光阻1120后，可以如图11(d)所示，在光阻1120上形成第一掩膜层1130，该第一掩膜层1130具有第一开孔，第一开孔的形状与凹陷区域的形状相同，最终用于暴露出凹陷区域。In an exemplary embodiment of the present disclosure, after the photoresist 1120 is coated on the surface of the golden finger body 320, a first mask layer 1130 can be formed on the photoresist 1120 as shown in Figure 11(d). The layer 1130 has a first opening, the shape of the first opening is the same as the shape of the recessed area, and is ultimately used to expose the recessed area.
接着，如图11(e)所示，对上述形成的第一掩膜层1130进行曝光，使第一开孔对应的光阻1120显影，暴露出金手指本体320与第一开孔对应的区域。Next, as shown in FIG. 11(e) , the first mask layer 1130 formed above is exposed to develop the photoresist 1120 corresponding to the first opening, and the area of the gold finger body 320 corresponding to the first opening is exposed. .
如图11(f)所示，对图11(e)所获得的结构去掩膜，即去除第一掩膜层1130，并对金手 指本体320与第一开孔对应的区域进行蚀刻，以形成凹陷区域，如图3所示。其中在蚀刻过程中可以采用湿法蚀刻，也可以采用干法蚀刻，本公开示例性实施方式对于具体的蚀刻方法不作限定。As shown in Figure 11(f), the structure obtained in Figure 11(e) is unmasked, that is, the first mask layer 1130 is removed, and the area of the gold finger body 320 corresponding to the first opening is etched to A depressed area is formed, as shown in Figure 3. Wet etching or dry etching may be used during the etching process. The exemplary embodiments of the present disclosure do not limit the specific etching method.
本公开示例性实施方式中，在金手指本体320上刻蚀出凹陷区域后，还需要如步骤S1040所述，在刻蚀有凹陷区域的金手指本体320的表面镀镍、镀金。主要是利用电镀工艺在金手指本体320上面先镀镍再镀金，最后制作完成金手指。In an exemplary embodiment of the present disclosure, after etching a recessed area on the gold finger body 320, it is also necessary to plate nickel or gold on the surface of the gold finger body 320 with the recessed area etched as described in step S1040. Mainly, the electroplating process is used to plate nickel and then gold on the gold finger body 320, and finally the gold finger is produced.
需要说明的是，在镀镍和镀金的过程中，不可以填满凹陷区域，例如，可以使电镀在金手指本体320表面的镍具有均匀的厚度，使电镀在镍表面的金具有均匀的厚度，从而可以保持凹陷区域的高度低于其他未刻蚀区域的高度。It should be noted that during the process of nickel plating and gold plating, the recessed area cannot be filled. For example, the nickel electroplated on the surface of the gold finger body 320 can have a uniform thickness, and the gold electroplated on the nickel surface can have a uniform thickness. , so that the height of the recessed area can be kept lower than the height of other unetched areas.
在实际应用中，金手指本体320在进行表面处理过程中，可以采用电镀镍金的方式，也可以采用沉金的方式，其中，在电镀镍金时，其厚度可达3-50u"，因其优越的导电性、抗氧化性以及耐磨性，被广泛应用于需要经常插拔的金手指PCB或者需要经常进行机械磨擦的PCB板上面，但因为镀金的成本极高所以只应用于金手指等局部镀金处理，电金工艺颜色是银白色的，没有沉金的那么黄，缺点是可焊接略差。在沉金过程中，厚度常规1u"，最高可达3u"，因其优越导电性、平整度以及可焊性，被广泛应用于有按键位、绑定IC、BGA等设计的高精密PCB板，对于耐磨性能要求不高的金手指PCB，也可以选择整板沉金工艺，沉金工艺成本较电金工艺成本低很多。沉金工艺的颜色是金黄色。In practical applications, during the surface treatment process, the gold finger body 320 can be electroplated with nickel gold or immersed gold. When electroplating nickel gold, its thickness can reach 3-50u", so Due to its superior conductivity, oxidation resistance and wear resistance, it is widely used on gold finger PCBs that require frequent plugging and unplugging or PCB boards that require frequent mechanical friction. However, because the cost of gold plating is extremely high, it is only used on gold fingers. For partial gold plating, the color of the electric gold process is silvery white, not as yellow as the immersion gold. The disadvantage is that the weldability is slightly poorer. In the immersion gold process, the thickness is conventionally 1u" and can reach up to 3u" due to its superior conductivity. , flatness and solderability, it is widely used in high-precision PCB boards with button positions, binding IC, BGA and other designs. For gold finger PCBs that do not require high wear resistance, you can also choose the entire board immersion gold process. The cost of the immersion gold process is much lower than the cost of the electric gold process. The color of the immersion gold process is golden yellow.
上述过程实际上是在覆铜板上通过电镀或化学镀工艺再覆上一层金，化学镀是在铜面上沉积硫酸镍后通过化学反应让金沉积在硫酸镍表面形成金手指；电镀是在铜面上电镀上氨基磺酸镍后再用电镀的方式在镍表镀上金最终形成金手指。由于在化学镀过程中生成的金手指中的硫酸镍较硬，金手指在组装时受到外力的作用容易发生断裂，造成产品功能性缺陷，因此目前在对于产品性能要求较高的情况下，往往采用电镀制程生产***式金手指，其金手指中的氨基磺酸镍几乎不会因为组装时受到外力的作用发生断裂。The above process is actually to coat a copper-clad board with a layer of gold through electroplating or electroless plating. Electroless plating is to deposit nickel sulfate on the copper surface and then use a chemical reaction to deposit gold on the surface of nickel sulfate to form gold fingers; electroplating is to The copper surface is electroplated with nickel sulfamate, and then the nickel surface is electroplated with gold to form a gold finger. Since the nickel sulfate in the gold fingers generated during the electroless plating process is relatively hard, the gold fingers are prone to breakage due to external forces during assembly, causing functional defects in the product. Therefore, currently, when product performance requirements are high, often The electroplating process is used to produce plug-in gold fingers. The nickel sulfamate in the gold fingers will hardly break due to external forces during assembly.
本公开示例性实施方式中，所刻蚀获得的凹陷区域还可以是包括阶梯状结构的刻蚀孔，以阶梯状结构包括第一深度孔3221和第二深度孔3222，且第一深度孔3221的深度大于第二深度孔3222的深度为例，对该种凹陷区域的形成过程进行简要说明如下：In an exemplary embodiment of the present disclosure, the recessed area obtained by etching may also be an etching hole including a step-like structure. The step-like structure includes a first depth hole 3221 and a second depth hole 3222, and the first depth hole 3221 Taking the depth greater than the depth of the second depth hole 3222 as an example, the formation process of this type of recessed area is briefly described as follows:
如前述实施例，在基板310上形成金手指本体320后，如图12(a)所示，在金手指本体320的表面涂覆光阻1210；并在光阻1210上形成第二掩膜层1220，其中，该第二掩膜层1220具有第二开孔，第二开孔的形状与第一深度孔的形状相同；此处主要指的是第二开孔的截面形状与第一深度孔的截面形状相同，从而便于后续沿着第二开孔刻蚀出第一深度孔。As in the previous embodiment, after the gold finger body 320 is formed on the substrate 310, as shown in Figure 12(a), photoresist 1210 is coated on the surface of the gold finger body 320; and a second mask layer is formed on the photoresist 1210. 1220, wherein the second mask layer 1220 has a second opening, and the shape of the second opening is the same as the shape of the first depth hole; here it mainly refers to the cross-sectional shape of the second opening and the shape of the first depth hole. The cross-sectional shapes are the same, so as to facilitate subsequent etching of the first depth hole along the second opening.
接着，对第二掩膜层1220进行曝光，使光阻1210显影，暴露出金手指本体320与第二开孔对应的区域，如图12(b)所示。Next, the second mask layer 1220 is exposed to develop the photoresist 1210 to expose the area of the gold finger body 320 corresponding to the second opening, as shown in FIG. 12(b) .
然后，进行第一步蚀刻，即如图12(c)所示，对金手指本体320与第二开孔对应的区域进行蚀刻，形成第一深度孔3221的部分区域，也就是形成第一深度孔3221的上部分，其中，该上部分的深度为第一深度孔3221和第二深度孔3222的深度差值。相当于对金手指本体320与第二开孔对应的区域进行蚀刻的蚀刻深度为第一深度孔3221和第二深度孔3222的深度差值。Then, the first step of etching is performed, that is, as shown in FIG. 12(c) , the area of the gold finger body 320 corresponding to the second opening is etched to form part of the first depth hole 3221, that is, to form a first depth hole 3221. The upper part of the hole 3221, wherein the depth of the upper part is the depth difference between the first depth hole 3221 and the second depth hole 3222. The etching depth equivalent to etching the area of the gold finger body 320 corresponding to the second opening is the depth difference between the first depth hole 3221 and the second depth hole 3222 .
在获得第一深度孔3221的上部分，可以去除第二掩膜层1220，在光阻1210上形成第三掩膜层1230，如图12(d)所示，该第三掩膜层1230具有第三开孔，其第三开孔可以用于暴露第一深度孔3221和第二深度孔3222对应的区域。也就是说，第三开孔可以暴露凹陷区域对应的区域，并且第三开孔的截面形状与凹陷区域的截面形状相同。After obtaining the upper part of the first depth hole 3221, the second mask layer 1220 can be removed, and a third mask layer 1230 is formed on the photoresist 1210. As shown in FIG. 12(d), the third mask layer 1230 has The third opening may be used to expose the corresponding areas of the first depth hole 3221 and the second depth hole 3222. That is to say, the third opening can expose the area corresponding to the recessed area, and the cross-sectional shape of the third opening is the same as the cross-sectional shape of the recessed area.
接着，如图12(e)所示，可以对第三掩膜层1230进行曝光，使光阻1210显影，暴露出金手指本体320与第三开孔对应的区域，即暴露出金手指本体320上凹陷区域对应的区域。Next, as shown in FIG. 12(e) , the third mask layer 1230 can be exposed to develop the photoresist 1210 to expose the area of the gold finger body 320 corresponding to the third opening, that is, the gold finger body 320 is exposed. The area corresponding to the upper concave area.
最后，进行第二步蚀刻，即对金手指本体320与第三开孔对应的区域进行蚀刻，以形成凹陷区域，如图12(f)所示。此次第二步蚀刻的蚀刻深度为第二深度孔3222的深度，也 就是说，对金手指本体320与第三开孔对应的区域进行蚀刻的蚀刻深度为第二深度孔3222的深度，并且蚀刻完第一深度孔3221的下部分，从而通过上述两次蚀刻完成第一深度孔3221的蚀刻。Finally, a second step of etching is performed, that is, the area of the gold finger body 320 corresponding to the third opening is etched to form a recessed area, as shown in Figure 12(f). The etching depth of this second step of etching is the depth of the second depth hole 3222. That is to say, the etching depth of the area corresponding to the gold finger body 320 and the third opening is the depth of the second depth hole 3222, and The lower part of the first depth hole 3221 is etched, so that the etching of the first depth hole 3221 is completed through the above two etchings.
通过上述半导体封装基板的制作方法获得的半导体封装基板，在金手指本体的表面刻蚀形成具有阶梯状结构的凹陷区域，并通过将金线压合在阶梯状结构内，可以进一步增大金线与金手指本体表面的结合面积，从而进一步增大结合力，提高焊接的品质。In the semiconductor packaging substrate obtained by the above-mentioned manufacturing method of the semiconductor packaging substrate, a recessed area with a ladder-like structure is etched on the surface of the gold finger body, and the gold wire can be further enlarged by pressing the gold wire into the ladder-shaped structure. The bonding area with the gold finger body surface further increases the bonding force and improves the quality of welding.
需要说明的是，本公开示例性实施方式提供的半导体封装基板的制作方法仅是示意性说明，本公开对每个部件的制作工艺并不限定。It should be noted that the manufacturing method of the semiconductor packaging substrate provided by the exemplary embodiments of the present disclosure is only a schematic description, and the present disclosure does not limit the manufacturing process of each component.
在上述实施方式的基础上，本公开示例性实施方式还提供了一种半导体封装结构，参照图13所示，该半导体封装结构1300包括封装基板1310和芯片堆叠结构1320，其中，Based on the above embodiments, exemplary embodiments of the present disclosure also provide a semiconductor packaging structure. As shown in FIG. 13 , the semiconductor packaging structure 1300 includes a packaging substrate 1310 and a chip stack structure 1320, wherein,
封装基板1310包括基板310和形成于基板310上的金手指1311，该金手指1311的表面上形成有凹陷区域，凹陷区域用于压合金线1312的一端；其中，凹陷区域的结构形式以及凹陷区域的形成过程已经在前述实施方式中进行了详细描述，因此此处不再赘述。The packaging substrate 1310 includes a substrate 310 and a gold finger 1311 formed on the substrate 310. A recessed area is formed on the surface of the gold finger 1311, and the recessed area is used to press one end of the alloy wire 1312; wherein, the structural form of the recessed area and the recessed area The formation process has been described in detail in the foregoing embodiments, and therefore will not be described again here.
另外，芯片堆叠结构1320设置在封装基板1310上，金线1312的另一端压焊在芯片堆叠结构1320上。In addition, the chip stack structure 1320 is disposed on the packaging substrate 1310, and the other end of the gold wire 1312 is pressure-welded on the chip stack structure 1320.
在实际应用中，芯片堆叠结构1320通常包括有die芯片1321和粘结层1322，其中，粘结层1322用于将芯片1321粘接在封装基板1310上。在有多个芯片1321堆叠的情况下，相邻的芯片1321之间也通过粘结层1322进行连接。In practical applications, the chip stack structure 1320 usually includes a die chip 1321 and an adhesive layer 1322, where the adhesive layer 1322 is used to bond the chip 1321 to the packaging substrate 1310. When multiple chips 1321 are stacked, adjacent chips 1321 are also connected through an adhesive layer 1322 .
在实际应用中，上述的粘结层1322除过具有粘性外，还具有绝缘性能，以在芯片1321和芯片1321之间，或者芯片1321和封装基板1310之间起到绝缘的作用。In practical applications, the above-mentioned adhesive layer 1322 not only has viscosity, but also has insulating properties to play an insulating role between the chip 1321 and the chip 1321, or between the chip 1321 and the packaging substrate 1310.
本公开示例性实施方式中，封装基板1310上的金手指1311与芯片1321之间通过金线1312连接，具体的连接过程可以参照前述的封装打线过程，此处不再赘述。In the exemplary embodiment of the present disclosure, the gold fingers 1311 on the packaging substrate 1310 and the chip 1321 are connected through gold wires 1312. For the specific connection process, please refer to the aforementioned packaging wiring process, which will not be described again here.
需要说明的是，为了便于焊接金线1312，可以在芯片1321上设置焊盘，以将金线1312焊接在焊盘上。It should be noted that, in order to facilitate welding of the gold wire 1312, a bonding pad may be provided on the chip 1321 to weld the gold wire 1312 on the bonding pad.
本公开示例性实施方式提供的半导体封装结构1300，通过在封装基板的金手指1311上设置凹陷区域，通过将金线1312压合在凹陷区域内，可以增大金线1312与金手指1311表面的接触面积，从而可以增大金线1312与金手指1311的结合力，提高焊接封装的良率。The semiconductor packaging structure 1300 provided by the exemplary embodiment of the present disclosure can increase the distance between the gold wire 1312 and the surface of the gold finger 1311 by arranging a recessed area on the gold finger 1311 of the packaging substrate and by pressing the gold wire 1312 in the recessed area. The contact area can be increased, thereby increasing the bonding force between the gold wire 1312 and the gold finger 1311, and improving the yield of the soldering package.
如图14所示，在一些实施例中，粘结层1322可以包括第一粘结层13221和第二粘结层13222。第二粘结层13222位于第一粘结层13221上。第一粘结层13221可以芯片1321的有源面(正面)接触，第二粘结层13222可以与芯片1321的背面接触。由于芯片1321的有源面会产生更多的热量，由此第一粘结层13221的散热系数大于第二粘结层13222的散热系数，从而可以防止第一粘结层13221由于热量影响而出现较大的变形。在一些实施例中，可以在第一粘结层13221中掺杂金属粉末，从而实现快速散热。As shown in FIG. 14 , in some embodiments, the adhesive layer 1322 may include a first adhesive layer 13221 and a second adhesive layer 13222 . The second adhesive layer 13222 is located on the first adhesive layer 13221. The first adhesive layer 13221 may contact the active surface (front surface) of the chip 1321 , and the second adhesive layer 13222 may contact the back surface of the chip 1321 . Since the active surface of the chip 1321 will generate more heat, the heat dissipation coefficient of the first adhesive layer 13221 is greater than the heat dissipation coefficient of the second adhesive layer 13222, thereby preventing the first adhesive layer 13221 from being affected by heat. Big deformation. In some embodiments, metal powder may be doped in the first bonding layer 13221 to achieve rapid heat dissipation.
如图14所示，在一些实施例中，第一粘结层13221可以与基板1310接触，第二粘结层13222与芯片1321接触。第一粘结层13221的弹性模量小于第二粘结层13222的弹性模量，第一粘结层13221与基板1310实现粘结作用，第二粘结层13222直接与芯片1321粘结，降低切割过程中的翘曲。在将最底层的芯片1321设置在基板1310上时，可以将整个晶圆设置在第二粘结层13222上，然后进行切割工艺。在进行切割工艺中，由于第二粘结层13222具有较高的弹性模量，从而使得在切割过程中不会发生翘曲。由于第一粘结层13221具有较低的弹性模量，不会降低芯片1321与基板1310的粘结力。第一粘结层13221和第二粘结层13222例如为DAF，例如通过改善二者的高分子树脂的配比实现弹性模量的调整。As shown in Figure 14, in some embodiments, the first adhesive layer 13221 may be in contact with the substrate 1310, and the second adhesive layer 13222 may be in contact with the chip 1321. The elastic modulus of the first adhesive layer 13221 is smaller than the elastic modulus of the second adhesive layer 13222. The first adhesive layer 13221 realizes bonding with the substrate 1310, and the second adhesive layer 13222 directly bonds with the chip 1321, reducing the Warping during cutting. When the bottom chip 1321 is placed on the substrate 1310, the entire wafer can be placed on the second adhesive layer 13222, and then a cutting process is performed. During the cutting process, since the second adhesive layer 13222 has a high elastic modulus, warping will not occur during the cutting process. Since the first adhesive layer 13221 has a low elastic modulus, the adhesive force between the chip 1321 and the substrate 1310 will not be reduced. The first adhesive layer 13221 and the second adhesive layer 13222 are, for example, DAF, and the elastic modulus is adjusted, for example, by improving the ratio of their polymer resins.
如图15所示，在一些实施例中，该半导体封装结构还可以包括模制层140，模制层140位于基板1310上，且将芯片堆叠结构完全覆盖，从而保护芯片堆叠结构。该模制层140例如为环氧树脂材料，环氧树脂材料内可以掺杂一定体积的填料，例如包括大颗粒的 填料和小颗粒的填料，填料可以为球状。该模制层140的厚度可以大于或等于芯片堆叠结构的厚度与3倍的填料的直径(最大直径的填料)之和。图中虚线至模制层140顶部的距离可以等于填料的直径的3倍。这样可以保证模制层140具有良好的热膨胀系数和弹性模量，从而使得半导体封装结构具有良好的翘曲状态。如果该将模制层140的厚度过小，则有可能导致模制层140的热膨胀系数和弹性模量与基板1310的热膨胀系数和弹性模量不匹配，同时在对半导体封装结构进行标记时，激光有可能透过模制层140，造成芯片堆叠结构损坏。As shown in FIG. 15 , in some embodiments, the semiconductor packaging structure may further include a molding layer 140 . The molding layer 140 is located on the substrate 1310 and completely covers the chip stack structure, thereby protecting the chip stack structure. The molding layer 140 is, for example, an epoxy resin material. The epoxy resin material can be doped with a certain volume of filler, for example, including large particle fillers and small particle fillers. The filler can be spherical. The thickness of the molding layer 140 may be greater than or equal to the sum of the thickness of the chip stack structure and three times the diameter of the filler (the maximum diameter of the filler). The distance from the dotted line in the figure to the top of the molding layer 140 may be equal to 3 times the diameter of the filler. This can ensure that the molding layer 140 has a good thermal expansion coefficient and elastic modulus, so that the semiconductor packaging structure has a good warpage state. If the thickness of the molding layer 140 is too small, the thermal expansion coefficient and elastic modulus of the molding layer 140 may not match the thermal expansion coefficient and elastic modulus of the substrate 1310. At the same time, when marking the semiconductor packaging structure, The laser may penetrate the molding layer 140 and cause damage to the chip stack structure.
应理解，在本公开的各种实施方式中，上述各过程的序号大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开示例性实施方式的实施过程构成任何限定。It should be understood that in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the order of execution. The execution order of each process should be determined by its functions and internal logic, and should not be used in the exemplary implementation of the present disclosure. The implementation process of the method constitutes no limitation.
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (21)

  1. 一种半导体封装基板，包括：A semiconductor packaging substrate, including:
    基板；substrate;
    金手指本体，形成于所述基板上；The gold finger body is formed on the substrate;
    其中，所述金手指本体的表面上形成有凹陷区域，所述凹陷区域用于压合金线。Wherein, a recessed area is formed on the surface of the gold finger body, and the recessed area is used for pressing alloy wires.
  2. 根据权利要求1所述的半导体封装基板，其中，所述凹陷区域包括至少一个过蚀孔。The semiconductor packaging substrate of claim 1, wherein the recessed area includes at least one via hole.
  3. 根据权利要求2所述的半导体封装基板，其中，所述过蚀孔的深度小于3um。The semiconductor packaging substrate according to claim 2, wherein the depth of the through hole is less than 3um.
  4. 根据权利要求2所述的半导体封装基板，其中，所述过蚀孔为阶梯状结构。The semiconductor packaging substrate according to claim 2, wherein the through hole has a stepped structure.
  5. 根据权利要求4所述的半导体封装基板，其中，所述阶梯状结构包括第一深度孔和第二深度孔，所述第一深度孔的深度大于所述第二深度孔的深度。The semiconductor packaging substrate of claim 4, wherein the stepped structure includes a first depth hole and a second depth hole, and a depth of the first depth hole is greater than a depth of the second depth hole.
  6. 根据权利要求5所述的半导体封装基板，其中，所述第一深度孔的深度小于或等于1/3倍的所述金线的直径。The semiconductor packaging substrate of claim 5, wherein a depth of the first depth hole is less than or equal to 1/3 times a diameter of the gold wire.
  7. 根据权利要求4所述的半导体封装基板，其中，所述阶梯状结构的阶梯位置位于压头着力点下方。The semiconductor packaging substrate according to claim 4, wherein the step position of the stepped structure is located below the pressing point of the indenter.
  8. 根据权利要求2所述的半导体封装基板，其中，所述过蚀孔的截面形状为圆形、星形、三角形和多边形中的一种。The semiconductor packaging substrate according to claim 2, wherein the cross-sectional shape of the through hole is one of a circle, a star, a triangle and a polygon.
  9. 根据权利要求2所述的半导体封装基板，其中，所述过蚀孔有多个，多个所述过蚀孔阵列排布。The semiconductor packaging substrate according to claim 2, wherein there are a plurality of through-holes, and a plurality of the through-holes are arranged in an array.
  10. 根据权利要求1-9中任一项所述的半导体封装基板，其中，所述凹陷区域位于所述金手指本体的焊点处。The semiconductor packaging substrate according to any one of claims 1 to 9, wherein the recessed area is located at a solder joint of the gold finger body.
  11. 一种半导体封装基板的制作方法，包括：A method for manufacturing a semiconductor packaging substrate, including:
    提供基板；Provide substrate;
    在所述基板上形成金手指本体；Form a gold finger body on the substrate;
    在所述金手指本体的表面刻蚀凹陷区域，所述凹陷区域用于压合金线；A recessed area is etched on the surface of the gold finger body, and the recessed area is used for pressing alloy wires;
    在刻蚀有所述凹陷区域的所述金手指本体的表面镀镍、镀金。The surface of the gold finger body etched with the recessed area is plated with nickel or gold.
  12. 根据权利要求11所述的方法，其中，所述在所述金手指本体的表面刻蚀凹陷区域，包括：The method according to claim 11, wherein etching a recessed area on the surface of the gold finger body includes:
    在所述金手指本体的表面涂覆光阻；Coat photoresist on the surface of the gold finger body;
    在所述光阻上形成第一掩膜层，所述第一掩膜层具有第一开孔，所述第一开孔的形状与所述凹陷区域的形状相同；A first mask layer is formed on the photoresist, the first mask layer has a first opening, the shape of the first opening is the same as the shape of the recessed area;
    对所述第一掩膜层曝光，使所述光阻显影，暴露所述金手指本体与所述第一开孔对应的区域；Expose the first mask layer to develop the photoresist to expose the area of the gold finger body corresponding to the first opening;
    对所述金手指本体与所述第一开孔对应的区域进行蚀刻，形成所述凹陷区域。The area of the gold finger body corresponding to the first opening is etched to form the recessed area.
  13. 根据权利要求11所述的方法，其中，所述凹陷区域包括阶梯状结构的刻蚀孔，所述阶梯状结构包括第一深度孔和第二深度孔，所述第一深度孔的深度大于所述第二深度孔的深度。The method according to claim 11, wherein the recessed area includes an etching hole with a stepped structure, the stepped structure includes a first depth hole and a second depth hole, and the depth of the first depth hole is greater than the etching hole. The depth of the second depth hole.
  14. 根据权利要求13所述的方法，其中，所述在所述金手指本体的表面刻蚀凹陷区域，包括：The method according to claim 13, wherein etching a recessed area on the surface of the gold finger body includes:
    在所述金手指本体的表面涂覆光阻；Coat photoresist on the surface of the gold finger body;
    在所述光阻上形成第二掩膜层，所述第二掩膜层具有第二开孔，所述第二开孔的形状与所述第一深度孔的形状相同；forming a second mask layer on the photoresist, the second mask layer having a second opening, the shape of the second opening being the same as the shape of the first depth hole;
    对所述第二掩膜层曝光，使所述光阻显影，暴露所述金手指本体与所述第二开孔对应的区域；Expose the second mask layer to develop the photoresist, exposing the area of the gold finger body corresponding to the second opening;
    对所述金手指本体与所述第二开孔对应的区域进行蚀刻，形成所述第一深度孔的部分区域；Etch the area of the gold finger body corresponding to the second opening to form a partial area of the first depth hole;
    去除所述第二掩膜层，在所述光阻上形成第三掩膜层，所述第三掩膜层具有第三开孔，所述第三开孔用于暴露所述第一深度孔和所述第二深度孔对应的区域；The second mask layer is removed, and a third mask layer is formed on the photoresist. The third mask layer has a third opening, and the third opening is used to expose the first depth hole. The area corresponding to the second depth hole;
    对所述第三掩膜层曝光，使所述光阻显影，暴露所述金手指本体与所述第三开孔对应的区域；Expose the third mask layer to develop the photoresist, exposing the area of the gold finger body corresponding to the third opening;
    对所述金手指本体与所述第三开孔对应的区域进行蚀刻，形成所述凹陷区域。The area of the gold finger body corresponding to the third opening is etched to form the recessed area.
  15. 根据权利要求14所述的方法，其中，对所述金手指本体与所述第二开孔对应的区域进行蚀刻的蚀刻深度为所述第一深度孔和所述第二深度孔的深度差值；The method according to claim 14, wherein the etching depth of the area corresponding to the gold finger body and the second opening is a depth difference between the first depth hole and the second depth hole. ;
    对所述金手指本体与所述第三开孔对应的区域进行蚀刻的蚀刻深度为所述第二深度孔的深度。The etching depth of the area corresponding to the third opening of the gold finger body is the depth of the second depth hole.
  16. 一种半导体封装结构，包括：A semiconductor packaging structure including:
    封装基板，所述封装基板包括基板和形成于所述基板上的金手指，所述金手指的表面上形成有凹陷区域，所述凹陷区域用于压合金线的一端；A packaging substrate, the packaging substrate includes a substrate and a gold finger formed on the substrate, a recessed area is formed on the surface of the gold finger, and the recessed area is used to press one end of the alloy wire;
    芯片堆叠结构，设置在所述封装基板上，所述金线的另一端压焊在所述芯片堆叠结构上。A chip stack structure is provided on the packaging substrate, and the other end of the gold wire is pressure-welded on the chip stack structure.
  17. 根据权利要求16所述的半导体封装结构，其中，所述芯片堆叠结构通过粘结层设置在所述封装基板上。The semiconductor packaging structure of claim 16, wherein the chip stack structure is disposed on the packaging substrate through an adhesive layer.
  18. 根据权利要求17所述的半导体封装结构，其中，所述粘结层包括第一粘结层和第二粘结层，所述第二粘结层位于所述第一粘结层上。The semiconductor packaging structure of claim 17, wherein the adhesive layer includes a first adhesive layer and a second adhesive layer, and the second adhesive layer is located on the first adhesive layer.
  19. 根据权利要求18所述的半导体封装结构，其中，所述第一粘结层的散热系数大于所述第二粘结层的散热系数。The semiconductor packaging structure according to claim 18, wherein the heat dissipation coefficient of the first adhesive layer is greater than the heat dissipation coefficient of the second adhesive layer.
  20. 根据权利要求18所述的半导体封装结构，其中，所述第一粘结层的弹性模量大于所述第二粘结层的弹性模量。The semiconductor packaging structure of claim 18, wherein the elastic modulus of the first adhesive layer is greater than the elastic modulus of the second adhesive layer.
  21. 根据权利要求16所述的半导体封装结构，还包括模制层，所述模制层覆盖所述芯片堆叠结构，所述模制层内包括填料，所述模制层的厚度大于或等于所述芯片堆叠结构的厚度与填料最大直径的3倍之和。The semiconductor packaging structure according to claim 16, further comprising a molding layer covering the chip stack structure, the molding layer including filler, the thickness of the molding layer being greater than or equal to the The sum of the thickness of the chip stack and 3 times the maximum diameter of the filler.
PCT/CN2022/130398 2022-08-19 2022-11-07 Semiconductor package substrate and manufacturing method therefor, and semiconductor package structure WO2024036770A1 (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114680A (en) * 1998-09-29 2000-04-21 Sanyo Electric Co Ltd Mounting circuit board and battery
US20050156303A1 (en) * 2004-01-21 2005-07-21 Kai-Chiang Wu Structure of gold fingers
US20100126763A1 (en) * 2008-11-21 2010-05-27 Fujitsu Limited Wire bonding method, electronic apparatus, and method of manufacturing same
JP2011210930A (en) * 2010-03-30 2011-10-20 Murata Mfg Co Ltd Flexible board, and circuit module including the same
CN102556938A (en) * 2011-12-27 2012-07-11 三星半导体(中国)研究开发有限公司 Stacked die package structure and manufacturing method thereof
CN203942697U (en) * 2014-06-05 2014-11-12 嘉兴职业技术学院 Flexible printed wiring board
CN205755053U (en) * 2015-11-30 2016-11-30 厦门天马微电子有限公司 A kind of printed circuit board (PCB) and display device
CN209420009U (en) * 2018-11-23 2019-09-20 惠州拓邦电气技术有限公司 A kind of golden finger and the mold for making golden finger

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114680A (en) * 1998-09-29 2000-04-21 Sanyo Electric Co Ltd Mounting circuit board and battery
US20050156303A1 (en) * 2004-01-21 2005-07-21 Kai-Chiang Wu Structure of gold fingers
US20100126763A1 (en) * 2008-11-21 2010-05-27 Fujitsu Limited Wire bonding method, electronic apparatus, and method of manufacturing same
JP2011210930A (en) * 2010-03-30 2011-10-20 Murata Mfg Co Ltd Flexible board, and circuit module including the same
CN102556938A (en) * 2011-12-27 2012-07-11 三星半导体(中国)研究开发有限公司 Stacked die package structure and manufacturing method thereof
CN203942697U (en) * 2014-06-05 2014-11-12 嘉兴职业技术学院 Flexible printed wiring board
CN205755053U (en) * 2015-11-30 2016-11-30 厦门天马微电子有限公司 A kind of printed circuit board (PCB) and display device
CN209420009U (en) * 2018-11-23 2019-09-20 惠州拓邦电气技术有限公司 A kind of golden finger and the mold for making golden finger

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