WO2024036762A1 - 垂直结构的薄膜晶体管和电子器件 - Google Patents

垂直结构的薄膜晶体管和电子器件 Download PDF

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Publication number
WO2024036762A1
WO2024036762A1 PCT/CN2022/129808 CN2022129808W WO2024036762A1 WO 2024036762 A1 WO2024036762 A1 WO 2024036762A1 CN 2022129808 W CN2022129808 W CN 2022129808W WO 2024036762 A1 WO2024036762 A1 WO 2024036762A1
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Prior art keywords
thin film
film transistor
vertical structure
via hole
doped portion
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PCT/CN2022/129808
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English (en)
French (fr)
Inventor
李治福
刘广辉
艾飞
宋德伟
罗成志
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武汉华星光电技术有限公司
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Publication of WO2024036762A1 publication Critical patent/WO2024036762A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present application relates to the field of display technology, and in particular to a vertical structure thin film transistor and electronic device.
  • the existing vertical structure thin film transistor has a technical problem that ions in the ohmic contact area easily diffuse into the channel, resulting in poor stability of the thin film transistor.
  • Embodiments of the present application provide a vertical structure thin film transistor and an electronic device to alleviate the technical problem in existing vertical structure thin film transistors that ions in the ohmic contact area easily diffuse into the channel, resulting in poor stability of the thin film transistor.
  • Embodiments of the present application provide a vertical structure thin film transistor.
  • the vertical structure thin film transistor includes:
  • An active layer is provided on one side of the insulating substrate, the active layer includes a first doped part, a channel part and a second doped part arranged in a stack;
  • An insulating layer disposed on a side of the channel portion away from the first doped portion, the insulating layer including a via hole;
  • the second doped part is disposed in the via hole, and the second doped part is connected to and partially in contact with the channel part through the via hole.
  • the vertical structure thin film transistor further includes a source-drain layer, the source-drain layer is disposed on a side of the insulating layer away from the active layer, and the source-drain layer includes a third An electrode and a second electrode, the via hole includes a first via hole and a second via hole, the first electrode is electrically connected to the first doped part through the first via hole, the second doped part The doped portion is disposed in the second via hole, and the second electrode is in contact with the second doped portion.
  • the material of the first doped portion includes N-type doped polysilicon
  • the material of the second doped portion includes N-type doped amorphous silicon
  • the doping ion concentration of the first doping portion on the side close to the insulating substrate is greater than the doping ion concentration of the first doping portion on the side close to the channel portion.
  • the first doped portion includes a first heavily doped portion and a first lightly doped portion, and the first heavily doped portion has a doping ion concentration greater than that of the first lightly doped portion. doping ion concentration, and the first lightly doped part is disposed between the first heavily doped part and the channel part.
  • the first lightly doped part includes a third via hole
  • the first electrode is electrically connected to the first heavily doped part through the first via hole and the third via hole.
  • the first electrode is electrically connected to the first lightly doped part through the first via hole and the third via hole.
  • the width of the first heavily doped portion is greater than the width of the first lightly doped portion, and the first electrode is electrically connected to the first heavily doped portion through the first via hole. connect.
  • the material of the first doped portion includes N-type doped amorphous silicon.
  • the doping ion concentration of the second doping portion on a side close to the source and drain layer is greater than the doping concentration of the second doping portion on a side close to the channel portion. ion concentration.
  • the second doped portion includes a second heavily doped portion and a second lightly doped portion, and the second heavily doped portion has a doping ion concentration greater than that of the second lightly doped portion. doping ion concentration, the second lightly doped part is disposed between the second heavily doped part and the channel part, and the second lightly doped part is connected to the second heavily doped part The side parts of the body are in contact.
  • the ratio of the thickness of the second heavily doped portion to the thickness of the second lightly doped portion is greater than or equal to 5.
  • the second electrode extends into the second via hole, and the second heavily doped portion is in contact with a side surface of the second electrode.
  • the doping ion concentration ratio of the second heavily doped part and the second lightly doped part is 10:1.
  • the second doped part includes a first part disposed on the insulating layer away from the channel part and a second part located in the second via hole, and the first part is connected to the Part 2 connects.
  • the second via hole has a pore diameter ranging from 2 microns to 4 microns.
  • the width of the first doped portion is greater than the width of the channel portion.
  • the vertically structured thin film transistor further includes a gate located on a sidewall of the insulating layer, and an orthographic projection of the gate on the sidewall of the insulating layer covers the channel portion. .
  • the vertical structure thin film transistor further includes:
  • a light-shielding layer is provided between the insulating substrate and the active layer, and the orthographic projection of the light-shielding layer on the insulating substrate at least covers the second doped part on the insulating substrate. Orthographic projection.
  • the gate is connected to the light shielding layer.
  • embodiments of the present application provide an electronic device, which includes a vertical structure thin film transistor as described in any of the above embodiments.
  • the present application provides a vertical structure thin film transistor and an electronic device;
  • the vertical structure thin film transistor includes an insulating substrate, an active layer and an insulating layer.
  • the active layer is arranged on one side of the insulating substrate, and the active layer includes a stacked layer.
  • the first doped part, the channel part and the second doped part, the insulating layer is disposed on the side of the channel part away from the first doped part, the insulating layer includes a via hole, wherein the second doped part is disposed on the via hole. In the hole, the second doped part is connected to and partially in contact with the channel part through the via hole.
  • This application can realize a polysilicon thin film transistor with extremely small channel length by arranging the first doped part, the channel part and the second doped part in a stack, and by arranging the second doped part in the via hole of the insulating layer In this way, the second doped part is connected to and partially contacted with the channel part through the via hole, which can reduce the contact area between the second doped part and the channel part, thereby reducing the ions diffusing into the channel region and improving the performance of the thin film transistor. It improves the device stability, reduces the projected area of the thin film transistor, and increases the aperture ratio of the display panel, which is conducive to the development of high-resolution and high-refresh rate products, and even realizes the functions of some chips.
  • Figure 1 is a schematic structural diagram of an existing display device.
  • FIG. 2 is a first schematic diagram of a vertical structure thin film transistor provided by an embodiment of the present application.
  • FIG. 3 is a cross-sectional view of A1-A2 of the vertical structure thin film transistor in FIG. 2 .
  • FIG. 4 is a second schematic diagram of a vertical structure thin film transistor provided by an embodiment of the present application.
  • FIG. 5 is a third schematic diagram of a vertical structure thin film transistor provided by an embodiment of the present application.
  • FIG. 6 is a first schematic diagram of a vertical structure thin film transistor corresponding to each step in the method for manufacturing a vertical structure thin film transistor provided by an embodiment of the present application.
  • FIG. 7 is a second schematic diagram of a vertical structure thin film transistor corresponding to each step in the method for preparing a vertical structure thin film transistor provided by an embodiment of the present application.
  • FIG. 8 is a third schematic diagram of a vertical structure thin film transistor corresponding to each step in the method for manufacturing a vertical structure thin film transistor provided by an embodiment of the present application.
  • the existing display device includes a substrate 11, a light shielding layer 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a gate layer 16, an interlayer insulating layer 17, and a source and drain layer 18. , planarization layer 19, first electrode layer 22, passivation layer 21 and second electrode layer 23.
  • the active layer 14 includes an ohmic contact region 141 and a channel region 142.
  • the ohmic contact region 141 includes In the heavily doped region 141a and the lightly doped region 141b, each area of the active layer is arranged along the horizontal direction, occupying a large area, and is limited by exposure accuracy and etching accuracy.
  • the channel length of the active layer is small, resulting in The mobility of the thin film transistor 10 is low.
  • existing display devices will design vertical structure thin film transistors.
  • the channel length of the active layer is the thickness of the active layer, which can realize thin film transistors with extremely small channel lengths.
  • the existing vertical structure thin film transistor has a technical problem that ions in the ohmic contact area easily diffuse into the channel, resulting in poor stability of the thin film transistor.
  • embodiments of the present application provide a vertical structure thin film transistor and electronic device to alleviate the above technical problems.
  • the vertical structure thin film transistor 3 includes:
  • the active layer 34 is provided on one side of the insulating substrate 31.
  • the active layer 34 includes a first doped part 341, a channel part 342 and a second doped part 343 arranged in a stack;
  • the insulating layer 35 is provided on the side of the channel portion 342 away from the first doped portion 341, and the insulating layer 35 includes a via hole 37;
  • the second doped portion 343 is disposed in the via hole 37 , and the second doped portion 343 is connected to and partially in contact with the channel portion 342 through the via hole 37 .
  • Embodiments of the present application provide a vertical structure thin film transistor.
  • the vertical structure thin film transistor can realize a polysilicon film with extremely small channel length by stacking a first doping part, a channel part and a second doping part. transistor, and by arranging the second doped part in the via hole of the insulating layer, so that the second doped part is connected to the channel part through the via hole and partially in contact, the distance between the second doped part and the channel part can be reduced.
  • the contact area reduces the ions that diffuse into the channel area, improves the device stability of the thin film transistor, reduces the projected area of the thin film transistor, and increases the aperture ratio of the display panel, which is conducive to the development of high resolution and high refresh rate devices. products, and even realize the functions of some chips.
  • FIG. 3 is a cross-sectional view of A1-A2 of the vertical structure thin film transistor in FIG. 2.
  • the second doping part is disposed in the via hole, it is not shown in FIG. 3.
  • the location of the via holes is indicated by the number 37.
  • the vertical structure thin film transistor 3 further includes a source-drain layer 38 , and the source-drain layer 38 is disposed on the insulating layer 35 away from the active layer 34
  • the source and drain layer 38 includes a first electrode 381 and a second electrode 382.
  • the via hole 37 includes a first via hole 371 and a second via hole 372.
  • the first electrode 381 passes through the first via hole 371 and the second via hole 372.
  • a via hole 371 is electrically connected to the first doped part 341, the second doped part 343 is disposed in the second via hole 372, the second electrode 382 and the second doped part 343 touch.
  • the second electrode when the second doping part is arranged in the via hole to reduce the contact area between the second doping part and the channel part, thereby reducing the ions diffusing into the channel, in order to realize the normal function of the thin film transistor, in When connecting the second doped part to the second electrode of the source and drain layer, the second electrode can be directly disposed on the second via hole, so that the second electrode directly contacts the second doped part to achieve electrical connection, without setting
  • the via hole is connected to the second doped part, and for the first doped part, since the first doped part is located under the channel part, the first via hole can be formed by etching the insulating layer to allow the source and drain layers to pass through The first via hole through the insulating layer is connected to the first doping part, thereby realizing connection between the source and drain layers and the active layer.
  • the signal input through the first electrode and the second electrode can realize the normal operation of the thin film transistor.
  • the second electrode is directly connected to the second doped part, and there is no need to provide additional via holes to connect the second doped part and the second electrode, thereby reducing process steps.
  • the material of the first doped part includes N-type doped polysilicon
  • the material of the second doped part includes N-type doped amorphous silicon.
  • the doping ion concentration of the first doping part on the side close to the insulating substrate is greater than the doping ion concentration of the first doping part on the side close to the channel part. .
  • the first doping part becomes bottom heavily doped,
  • the top layer is a lightly doped stacked structure. When electrons move, they need to pass through the heavily doped region and the lightly doped region, reducing the leakage current of the thin film transistor.
  • the first doped part 341 includes a first heavily doped part 341a and a first lightly doped part 341b.
  • the doping of the first heavily doped part 341a The ion concentration is greater than the doping ion concentration of the first lightly doped portion 341b, and the first lightly doped portion 341b is disposed between the first heavily doped portion 341a and the channel portion 342.
  • the first doped part include a first heavily doped part and a first lightly doped part, and making the doping ion concentration of the first heavily doped part greater than the doping ion concentration of the first lightly doped part, it can be formed
  • the stacked structure of the first heavily doped part and the first lightly doped part requires electrons to pass through the first heavily doped part and the first lightly doped part when moving, thereby reducing the leakage current of the thin film transistor.
  • the first lightly doped portion 341b includes a third via hole 373, and the first electrode 381 passes through the first via hole 371 and the third via hole.
  • 373 is electrically connected to the first heavily doped portion 341a
  • the first electrode 381 is electrically connected to the first lightly doped portion 341b through the first via hole 371 and the third via hole 373.
  • the first electrode will be electrically connected to the first lightly doped portion through the first via hole and the third via hole.
  • the first electrode will be electrically connected to the first heavily doped portion through the first via hole and the third via hole. Electrical connection, since the impedance of the first heavily doped part is smaller than the impedance of the first lightly doped part, the electrons will still move from the first heavily doped part to the first lightly doped part, realizing the conduction of the thin film transistor , and reduce the leakage current of the thin film transistor and improve the performance of the thin film transistor.
  • the first via hole and the third via hole are integrally provided, so that when the first via hole and the third via hole are formed, the insulation can be performed in the same process.
  • the layer and the first lightly doped portion are etched to form the first via hole and the third via hole, thereby reducing the process steps of the thin film transistor and improving the preparation efficiency of the thin film transistor.
  • the width L1 of the first heavily doped portion 341a is greater than the width L2 of the first lightly doped portion 341b, and the first electrode 381 passes through the first lightly doped portion 341b.
  • the via hole 371 is electrically connected to the first heavily doped portion 341a.
  • the first electrode can be directly connected to the first heavily doped part through the first via hole, thereby avoiding the first electrode being connected to the first lightly doped part.
  • the partial connection causes the leakage current of the thin film transistor to increase, causing electrons to pass through the first lightly doped part and the first heavily doped part, thereby reducing the leakage current of the thin film transistor and improving the performance of the thin film transistor device.
  • the first electrode 381 is electrically connected to the first heavily doped portion 341a through the first via hole 371. , that is, when disposing the first electrode, the first electrode is electrically connected to the first heavily doped portion in a region located beyond the first lightly doped portion, so that the first electrode can be electrically connected to the first lightly doped portion.
  • the doped parts do not come into contact, which avoids increasing the leakage current of the thin film transistor and improves the performance of the thin film transistor.
  • the material of the first doped portion includes N-type doped amorphous silicon.
  • the first doped part when forming the first lightly doped part and the second lightly doped part, the first doped part can be formed by chemical vapor deposition, and then through Controlling the proportion of phosphine forms a structure with a high doping concentration in the bottom layer and a low doping concentration in the surface layer, allowing electrons to pass through the first heavily doped part and the first lightly doped part in sequence, reducing leakage current and improving the performance of the thin film transistor.
  • the doping ion concentration ratio of the first heavily doped part and the first lightly doped part is 10:1.
  • the doping ion concentration of the second doping portion on a side close to the source and drain layer is greater than that of the second doping portion close to the channel portion. doping ion concentration.
  • the second doping part is lightly doped in the bottom layer. It has a stacked structure with doping and heavy doping on the top layer. When electrons move, they need to pass through the heavily doped area and the lightly doped area to reduce the leakage current of the thin film transistor.
  • the second doped part 343 includes a second heavily doped part 343a and a second lightly doped part 343b.
  • the doping of the second heavily doped part 343a The ion concentration is greater than that of the second lightly doped portion 343b.
  • the second lightly doped portion 343b is disposed between the second heavily doped portion 343a and the channel portion 342, and the second lightly doped portion 343b is disposed between the second heavily doped portion 343a and the channel portion 342.
  • the second lightly doped portion 343b is in contact with the side portion of the second heavily doped portion 343a.
  • the second heavily doped portion includes a second heavily doped portion and a second lightly doped portion, the second heavily doped portion is electrically connected to the first electrode, and the second lightly doped portion is located between the second heavily doped portion and the trench.
  • a stacked structure of a second heavily doped portion and a second lightly doped portion can be formed, so that electrons need to pass through the second heavily doped portion and the second lightly doped portion when moving, reducing the size of the thin film transistor. leakage current.
  • the second lightly doped portion is brought into contact with the side portion of the second heavily doped portion, thereby increasing the contact area between the second lightly doped portion and the second heavily doped portion, thereby improving the performance of the thin film transistor.
  • the ratio of the thickness h1 of the second heavily doped part 343a to the thickness h2 of the second lightly doped part 343b is greater than or equal to 5.
  • the distance between the bottom of the first heavily doped part and the top of the first heavily doped part is used as the thickness of the first heavily doped part
  • the distance between the bottom of the first heavily doped part and the first lightly doped part is used as the thickness of the first heavily doped part.
  • the spacing between the bottoms of the parts serves as the thickness of the first lightly doped part.
  • the second electrode 382 extends into the second via hole 372 , and the second heavily doped portion 343a is in contact with the side surface of the second electrode 382 .
  • the contact area between the second heavily doped part and the second electrode is enlarged, thereby improving the conduction effect between the second electrode and the second heavily doped part and avoiding the second
  • the heavily doped portion has poor contact with the second electrode, thereby improving the performance of the thin film transistor.
  • the doping ion concentration ratio of the second heavily doped part and the second lightly doped part is 10:1.
  • the above embodiments take the first doped part including a first lightly doped part and a first heavily doped part, and the second doped part including a second lightly doped part and a second heavily doped part as an example. has been explained, but the embodiment of the present application is not limited thereto.
  • the first doped part includes a first lightly doped part and a first heavily doped part
  • the second doped part may also include a second lightly doped part and a third
  • the double doped part for the design of the first lightly doped part, the first heavily doped part, the second lightly doped part and the second heavily doped part, please refer to the above embodiments and will not be described again here.
  • the second doped part includes a first part disposed on the insulating layer away from the channel part and a second part located in the second via hole, the first part and the The second part is connected.
  • the second doped portion can also be disposed outside the second via hole.
  • the second doped portion includes a first portion located on the insulating layer and a first portion located on the second via hole.
  • the second part within the second electrode can be brought into contact with the first part to realize the connection between the second electrode and the second doped part, and the contact area between the second doped part and the second electrode can be increased to avoid the second Poor contact between the doped part and the second electrode increases the area of the second doped part and improves the performance of the thin film transistor.
  • amorphous silicon when forming the second doped part, amorphous silicon can be deposited into the via hole, so that the amorphous silicon extends from the insulating layer into the via hole, and the amorphous silicon is etched to form the first part and the second part. Then the first part can be connected to the second electrode to realize the normal operation of the thin film transistor.
  • the hole diameter d of the second via hole 372 ranges from 2 microns to 4 microns.
  • An excessively large pore diameter of the second via hole will cause ions to diffuse into the channel part.
  • An excessively small pore diameter of the second via hole may cause poor contact between the second doping part, the channel part and the second electrode, and the pore diameter of the second via hole will be reduced.
  • the second doped portion in the second via hole can have better contact with the channel portion and the second electrode, and the second via hole will not be too large to cause ions to diffuse into Channel Department.
  • the width of the lower bottom of the inverted trapezoid is used as the aperture of the second via hole.
  • the width of the first doped portion is greater than the width of the channel portion.
  • the vertical structure thin film transistor 3 further includes a gate 36 located on the sidewall of the insulating layer 35 , and the gate 36 is on the side of the insulating layer 35 .
  • the orthographic projection on the side wall covers the channel portion 342 .
  • the vertical structure thin film transistor 3 further includes:
  • the light-shielding layer 32 is disposed between the insulating substrate 31 and the active layer 34 .
  • the orthographic projection of the light-shielding layer 32 on the insulating substrate 31 at least covers the second doped portion 343 .
  • Orthographic projection on the insulating substrate 31 By causing the orthographic projection of the light-shielding layer on the insulating substrate to at least cover the orthographic projection of the second doped portion on the insulating substrate, the light-shielding layer can prevent external light from irradiating the channel portion and prevent the active layer from being exposed to light and causing performance degradation. .
  • the gate is connected to the light-shielding layer.
  • the active layer can be semi-surrounded and the control capability of the gate electrode can be improved.
  • the material of the light-shielding layer includes molybdenum, titanium, tungsten or a stack thereof.
  • the vertical structure thin film transistor 3 further includes a buffer layer 33 .
  • the material of the buffer layer includes silicon oxide, silicon nitride, silicon oxynitride or a stack thereof.
  • the insulating layer 35 includes a gate insulating layer 351 and an interlayer insulating layer 352 .
  • the material of the gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof.
  • the thickness of the gate insulating layer ranges from 30 nanometers to 200 nanometers.
  • the material of the gate layer includes molybdenum, titanium, tungsten or a stack thereof.
  • the thickness of the gate layer ranges from 0.1 micron to 1 micron.
  • the material of the interlayer insulating layer includes a stack of silicon oxide and silicon nitride.
  • the material of the source and drain layers includes molybdenum, titanium, tungsten, aluminum, copper or a stack thereof.
  • embodiments of the present application provide a method for manufacturing a vertical structure thin film transistor.
  • the vertical structure thin film transistor is prepared as the thin film transistor described in any of the above embodiments.
  • the method for manufacturing the vertical structure thin film transistor includes:
  • metal can be deposited on the insulating substrate, and exposed and etched to form a light-shielding layer.
  • amorphous silicon when forming the first doped portion on the buffer layer, amorphous silicon can be formed into a film through chemical vapor deposition, hydrogen silicide and hydrogen gas can be introduced during film formation, and then the amorphous silicon can be converted into polycrystalline silicon through laser annealing. , then pattern the polysilicon through exposure and etching, and finally use ion implantation to perform phosphorus ion doping to obtain the first doped part.
  • the thickness of the first doped part ranges from 10 nanometers to 100 nanometers.
  • the amorphous silicon film can be formed by chemical vapor deposition on the buffer layer, and the amorphous silicon can be sequentially passed through during film formation.
  • Hydrogen silicide, hydrogen and phosphine need to be formed in two steps. In the first step, the flow rate of phosphine is large, and in the second step, the flow rate of phosphine is small. Then the first step is formed through exposure and etching. Doping Department.
  • the amorphous silicon film formation process contains phosphorus ions, no additional ion implantation is required.
  • the thickness of the first doped part ranges from 10 nanometers to 300 nanometers.
  • an amorphous silicon layer is deposited on the first doped part, and the amorphous silicon is converted into polysilicon through laser annealing, and then the polysilicon is patterned to form a channel part through exposure and etching.
  • the thickness of the channel portion ranges from 10 nanometers to 100 nanometers.
  • An interlayer insulating layer is formed on the gate insulating layer, and the interlayer insulating layer is etched to obtain a second via hole; the structure of the vertical structure thin film transistor corresponding to this step is shown in (a) in Figure 7;
  • amorphous silicon when forming the second doped portion on the buffer layer, amorphous silicon can be formed into a film by chemical vapor deposition, hydrogen silicide, hydrogen and phosphine can be introduced during film formation, and then exposed and etched. Amorphous silicon is patterned to obtain the second doped portion. Since the amorphous silicon film formation process contains phosphorus ions, no additional ion implantation is required.
  • the amorphous silicon film can be formed by chemical vapor deposition on the buffer layer, and the amorphous silicon can be sequentially passed through during film formation.
  • Hydrogen silicide, hydrogen and phosphine need to be formed in two steps. In the first step, the flow rate of phosphine is large, and in the second step, the flow rate of phosphine is small. Then the second step is formed through exposure and etching. Doping Department. Since the amorphous silicon film formation process contains phosphorus ions, no additional ion implantation is required.
  • the thickness of the second doped part ranges from 300 nanometers to 1000 nanometers.
  • a source and drain layer is formed on the interlayer insulating layer; the structure of a vertical structure thin film transistor corresponding to this step is shown in Figure 3.
  • Embodiments of the present application provide a method for preparing a vertical structure thin film transistor.
  • the vertical structure thin film transistor prepared by the vertical structure thin film transistor preparation method is provided by stacking a first doped part, a channel part and a second doped part.
  • a polysilicon thin film transistor with extremely small channel length can be realized, and by arranging the second doped part in the via hole of the insulating layer, so that the second doped part is connected to the channel part through the via hole and partially in contact, it can reduce the Smalling the contact area between the second doped part and the channel part reduces the ions that diffuse into the channel area, improves the device stability of the thin film transistor, reduces the projected area of the thin film transistor, and increases the aperture ratio of the display panel. It is beneficial to develop products with high resolution and high refresh rate, and even realize the functions of some chips.
  • embodiments of the present application provide an electronic device, which includes a vertical structure thin film transistor as described in any of the above embodiments.
  • Embodiments of the present application provide a vertical structure thin film transistor and an electronic device;
  • the vertical structure thin film transistor includes an insulating substrate, an active layer and an insulating layer.
  • the active layer is disposed on one side of the insulating substrate.
  • the active layer includes a stacked The first doped part, the channel part and the second doped part are arranged in layers, the insulating layer is arranged on the side of the channel part away from the first doped part, the insulating layer includes a via hole, wherein the second doped part is arranged In the via hole, the second doped part is connected to and partially in contact with the channel part through the via hole.
  • This application can realize a polysilicon thin film transistor with extremely small channel length by arranging the first doped part, the channel part and the second doped part in a stack, and by arranging the second doped part in the via hole of the insulating layer In this way, the second doped part is connected to and partially contacted with the channel part through the via hole, which can reduce the contact area between the second doped part and the channel part, thereby reducing the ions diffusing into the channel region and improving the performance of the thin film transistor. It improves the device stability, reduces the projected area of the thin film transistor, and increases the aperture ratio of the display panel, which is conducive to the development of high-resolution and high-refresh rate products, and even realizes the functions of some chips.

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Abstract

本申请提供一种垂直结构的薄膜晶体管和电子器件；该垂直结构的薄膜晶体管通过将第二掺杂部设置于绝缘层的过孔内，使第二掺杂部通过过孔与沟道部连接且部分接触，可以减小第二掺杂部与沟道部的接触面积，则减少了扩散至沟道区的离子，提高薄膜晶体管的器件稳定性，且减少了薄膜晶体管的投影面积，提高了显示面板的开口率。

Description

垂直结构的薄膜晶体管和电子器件 技术领域
本申请涉及显示技术领域，尤其是涉及一种垂直结构的薄膜晶体管和电子器件。
 背景技术
随着显示技术的发展，现有显示器件为了实现窄边框、高开口率、稿亮度和高分辨率，需要将薄膜晶体管的尺寸和占用面积减小。但多晶硅薄膜晶体管的迁移率较小，为了提高薄膜晶体管的迁移率，需要减小沟道长度也就是增大有源层的占用面积，且沟道长度受到工艺限制导致缩小程度有限，导致显示器件无法兼顾薄膜晶体管的迁移率和尺寸。现有显示器件为了解决这一问题，设计一种垂直结构的薄膜晶体管，通过将有源层的厚度作为薄膜晶体管的沟道长度，不会受到工艺限制，可以实现极小沟道长度的薄膜晶体管。但在垂直结构的薄膜晶体管的制备过程中，由于欧姆接触区设置于沟道区上下两侧，导致欧姆接触区的离子容易扩散至沟道，造成器件稳定性变差。
所以，现有垂直结构的薄膜晶体管存在欧姆接触区的离子容易扩散至沟道导致薄膜晶体管的稳定性较差的技术问题。
 技术问题
本申请实施例提供一种垂直结构的薄膜晶体管和电子器件，用以缓解现有垂直结构的薄膜晶体管存在欧姆接触区的离子容易扩散至沟道导致薄膜晶体管的稳定性较差的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种垂直结构的薄膜晶体管，该垂直结构的薄膜晶体管包括：
绝缘衬底；
有源层，设置于所述绝缘衬底的一侧，所述有源层包括叠层设置的第一掺杂部、沟道部和第二掺杂部；
绝缘层，设置于所述沟道部远离所述第一掺杂部的一侧，所述绝缘层包括过孔；
其中，所述第二掺杂部设置于所述过孔内，所述第二掺杂部通过所述过孔与所述沟道部连接且部分接触。
在一些实施例中，所述垂直结构的薄膜晶体管还包括源漏极层，所述源漏极层设置于所述绝缘层远离所述有源层的一侧，所述源漏极层包括第一电极和第二电极，所述过孔包括第一过孔和第二过孔，所述第一电极通过所述第一过孔与所述第一掺杂部电连接，所述第二掺杂部设置于所述第二过孔内，所述第二电极与所述第二掺杂部接触。
在一些实施例中，所述第一掺杂部的材料包括N型掺杂的多晶硅，所述第二掺杂部的材料包括N型掺杂的非晶硅。
在一些实施例中，所述第一掺杂部在靠近所述绝缘衬底一侧的掺杂离子浓度大于所述第一掺杂部在靠近所述沟道部一侧的掺杂离子浓度。
在一些实施例中，所述第一掺杂部包括第一重掺杂部和第一轻掺杂部，所述第一重掺杂部的掺杂离子浓度大于所述第一轻掺杂部的掺杂离子浓度，所述第一轻掺杂部设置于所述第一重掺杂部和所述沟道部之间。
在一些实施例中，所述第一轻掺杂部包括第三过孔，所述第一电极通过所述第一过孔和所述第三过孔与所述第一重掺杂部电连接，且所述第一电极通过所述第一过孔和所述第三过孔与所述第一轻掺杂部电连接。
在一些实施例中，所述第一重掺杂部的宽度大于所述第一轻掺杂部的宽度，所述第一电极通过所述第一过孔与所述第一重掺杂部电连接。
在一些实施例中，所述第一掺杂部的材料包括N型掺杂的非晶硅。
在一些实施例中，所述第二掺杂部在靠近所述源漏极层的一侧的掺杂离子浓度大于所述第二掺杂部在靠近所述沟道部的一侧的掺杂离子浓度。
在一些实施例中，所述第二掺杂部包括第二重掺杂部和第二轻掺杂部，所述第二重掺杂部的掺杂离子浓度大于所述第二轻掺杂部的掺杂离子浓度，所述第二轻掺杂部设置于所述第二重掺杂部和所述沟道部之间，且所述第二轻掺杂部与所述第二重掺杂部的侧面部分接触。
在一些实施例中，所述第二重掺杂部的厚度与所述第二轻掺杂部的厚度之比大于或者等于5。
在一些实施例中，所述第二电极延伸至所述第二过孔内，所述第二重掺杂部与所述第二电极的侧面接触。
在一些实施例中，所述第二重掺杂部和所述第二轻掺杂部的掺杂离子浓度比为10：1。
在一些实施例中，所述第二掺杂部包括设置于所述绝缘层远离所述沟道部的第一部分和位于所述第二过孔内的第二部分，所述第一部分与所述第二部分连接。
在一些实施例中，所述第二过孔的孔径范围为2微米至4微米。
在一些实施例中，所述第一掺杂部的宽度大于所述沟道部的宽度。
在一些实施例中，所述垂直结构的薄膜晶体管还包括位于所述绝缘层的侧壁上的栅极，所述栅极在所述绝缘层的侧壁上的正投影覆盖所述沟道部。
在一些实施例中，所述垂直结构的薄膜晶体管还包括：
遮光层，设置于所述绝缘衬底和所述有源层之间，所述遮光层在所述绝缘衬底上的正投影至少覆盖所述第二掺杂部在所述绝缘衬底上的正投影。
在一些实施例中，所述栅极与所述遮光层连接。
同时，本申请实施例提供一种电子器件，该电子器件包括如上述实施例任一所述的垂直结构的薄膜晶体管。
 有益效果
本申请提供一种垂直结构的薄膜晶体管和电子器件；该垂直结构的薄膜晶体管包括绝缘衬底、有源层和绝缘层，有源层设置于绝缘衬底一侧，有源层包括叠层设置的第一掺杂部、沟道部和第二掺杂部，绝缘层设置于沟道部远离第一掺杂部的一侧，绝缘层包括过孔，其中，第二掺杂部设置于过孔内，第二掺杂部通过过孔与沟道部连接且部分接触。本申请通过使第一掺杂部、沟道部和第二掺杂部叠层设置，可以实现极小沟道长度的多晶硅薄膜晶体管，并通过将第二掺杂部设置于绝缘层的过孔内，使第二掺杂部通过过孔与沟道部连接且部分接触，可以减小第二掺杂部与沟道部的接触面积，则减少了扩散至沟道区的离子，提高薄膜晶体管的器件稳定性，且减少了薄膜晶体管的投影面积，提高了显示面板的开口率，有利于开发高分辨率和高刷新率的产品、甚至实现部分芯片的功能。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有显示器件的结构示意图。
图2为本申请实施例提供的垂直结构的薄膜晶体管的第一种示意图。
图3为图2中的垂直结构的薄膜晶体管的A1-A2截面图。
图4为本申请实施例提供的垂直结构的薄膜晶体管的第二种示意图。
图5为本申请实施例提供的垂直结构的薄膜晶体管的第三种示意图。
图6为本申请实施例提供的垂直结构的薄膜晶体管的制备方法中各步骤对应的垂直结构的薄膜晶体管的第一种示意图。
图7为本申请实施例提供的垂直结构的薄膜晶体管的制备方法中各步骤对应的垂直结构的薄膜晶体管的第二种示意图。
图8为本申请实施例提供的垂直结构的薄膜晶体管的制备方法中各步骤对应的垂直结构的薄膜晶体管的第三种示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，现有显示器件包括衬底11、遮光层12、缓冲层13、有源层14、栅极绝缘层15、栅极层16、层间绝缘层17、源漏极层18、平坦化层19、第一电极层22、钝化层21和第二电极层23，从图1可以看到，有源层14包括欧姆接触区141和沟道区142，欧姆接触区141包括重掺杂区141a和轻掺杂区141b，有源层的各个区域沿水平方向设置，占用面积较大，且受到曝光精度和刻蚀精度的限制，有源层的沟道长度较小，导致薄膜晶体管10的迁移率较低。为了提高薄膜晶体管的迁移率，现有显示器件会设计垂直结构的薄膜晶体管，有源层的沟道长度为有源层的厚度，可以实现极小沟道长度的薄膜晶体管。但在垂直结构的薄膜晶体管的制备过程中，由于欧姆接触区设置于沟道区上下两侧，导致欧姆接触区的离子容易扩散至沟道，造成器件稳定性变差。所以，现有垂直结构的薄膜晶体管存在欧姆接触区的离子容易扩散至沟道导致薄膜晶体管的稳定性较差的技术问题。
本申请实施例针对上述技术问题，提供一种垂直结构的薄膜晶体管和电子器件，用以缓解上述技术问题。
如图2、图3所示，本申请实施例提供一种垂直结构的薄膜晶体管，该垂直结构的薄膜晶体管3包括：
绝缘衬底31；
有源层34，设置于所述绝缘衬底31的一侧，所述有源层34包括叠层设置的第一掺杂部341、沟道部342和第二掺杂部343；
绝缘层35，设置于所述沟道部342远离所述第一掺杂部341的一侧，所述绝缘层35包括过孔37；
其中，所述第二掺杂部343设置于所述过孔37内，所述第二掺杂部343通过所述过孔37与所述沟道部342连接且部分接触。
本申请实施例提供一种垂直结构的薄膜晶体管，该垂直结构的薄膜晶体管通过使第一掺杂部、沟道部和第二掺杂部叠层设置，可以实现极小沟道长度的多晶硅薄膜晶体管，并通过将第二掺杂部设置于绝缘层的过孔内，使第二掺杂部通过过孔与沟道部连接且部分接触，可以减小第二掺杂部与沟道部的接触面积，则减少了扩散至沟道区的离子，提高薄膜晶体管的器件稳定性，且减少了薄膜晶体管的投影面积，提高了显示面板的开口率，有利于开发高分辨率和高刷新率的产品、甚至实现部分芯片的功能。
需要说明的是，图3为图2中的垂直结构的薄膜晶体管的A1-A2截面图，在图3中，由于第二掺杂部设置于过孔内，因此，在图3中未示出过孔，以标号37表示过孔的设置位置。
在一种实施例中，如图3所示，所述垂直结构的薄膜晶体管3还包括源漏极层38，所述源漏极层38设置于所述绝缘层35远离所述有源层34的一侧，所述源漏极层38包括第一电极381和第二电极382，所述过孔37包括第一过孔371和第二过孔372，所述第一电极381通过所述第一过孔371与所述第一掺杂部341电连接，所述第二掺杂部343设置于所述第二过孔372内，所述第二电极382与所述第二掺杂部343接触。
在本申请实施例将第二掺杂部设置在过孔内减小第二掺杂部与沟道部的接触面积，从而减少扩散至沟道的离子时，为了实现薄膜晶体管的正常功能，在将第二掺杂部与源漏极层的第二电极连接时，可以直接将第二电极设置在第二过孔上，使第二电极直接与第二掺杂部接触实现电连接，无需设置过孔连接至第二掺杂部，而对于第一掺杂部，由于第一掺杂部位于沟道部下，因此，可以通过对绝缘层刻蚀形成第一过孔，使源漏极层穿过绝缘层的第一过孔连接至第一掺杂部，从而实现源漏极层与有源层的连接，可以通过第一电极和第二电极的信号输入，实现薄膜晶体管的正常工作。且该结构中第二电极直接与第二掺杂部连接，无需设置额外的过孔连接第二掺杂部和第二电极，减少工艺步骤。
针对在过孔内形成的多晶硅结晶效果较差会导致薄膜晶体管的性能较差的技术问题。在一种实施例中，所述第一掺杂部的材料包括N型掺杂的多晶硅，所述第二掺杂部的材料包括N型掺杂的非晶硅。通过使第一掺杂部的材料为N型掺杂的多晶硅，使第一掺杂部与第一电极的导通效果较好，第二掺杂部的材料为N型掺杂的非晶硅，避免第二掺杂部设置在过孔内时出现多晶硅结晶效果较差导致薄膜晶体管的性能较差的问题，提高薄膜晶体管的性能。
针对有源层的沟道尺寸变小会导致漏电流增大的问题。在一种实施例中，所述第一掺杂部在靠近所述绝缘衬底一侧的掺杂离子浓度大于所述第一掺杂部在靠近所述沟道部一侧的掺杂离子浓度。通过使第一掺杂部在靠近绝缘衬底一侧的掺杂离子浓度大于第一掺杂部在靠近沟道部一侧的掺杂离子浓度，使第一掺杂部呈底层重掺杂、顶层轻掺杂的叠层结构，电子移动时需要经过重掺杂区域和轻掺杂区域，减小薄膜晶体管的漏电流。
在一种实施例中，如图4所示，所述第一掺杂部341包括第一重掺杂部341a和第一轻掺杂部341b，所述第一重掺杂部341a的掺杂离子浓度大于所述第一轻掺杂部341b的掺杂离子浓度，所述第一轻掺杂部341b设置于所述第一重掺杂部341a和所述沟道部342之间。通过使第一掺杂部包括第一重掺杂部和第一轻掺杂部，使第一重掺杂部的掺杂离子浓度大于第一轻掺杂部的掺杂离子浓度，则可以形成第一重掺杂部、第一轻掺杂部的叠层结构，使电子移动时需要经过第一重掺杂部和第一轻掺杂部，减小薄膜晶体管的漏电流。
在一种实施例中，如图4所示，所述第一轻掺杂部341b包括第三过孔373，所述第一电极381通过所述第一过孔371和所述第三过孔373与所述第一重掺杂部341a电连接，且所述第一电极381通过所述第一过孔371和所述第三过孔373与所述第一轻掺杂部341b电连接。通过使第一轻掺杂部形成第三过孔，则第一电极可以通过第一过孔和第三过孔连接至第一重掺杂部，使电子能够沿着第一重掺杂部向第一轻掺杂部移动，从而减小薄膜晶体管的漏电流，提高薄膜晶体管的性能。
具体的，第一电极会通过第一过孔和第三过孔与第一轻掺杂部电连接，同时，第一电极会通过第一过孔和第三过孔与第一重掺杂部电连接，由于第一重掺杂部的阻抗小于第一轻掺杂部的阻抗，因此，电子的走向仍然会从第一重掺杂部走向第一轻掺杂部，实现薄膜晶体管的导通，且减小薄膜晶体管的漏电流，提高薄膜晶体管的性能。
具体的，通过对第一轻掺杂部形成第三过孔，第一过孔和第三过孔一体设置，使得在形成第一过孔和第三过孔时，可以在同一工艺中对绝缘层和第一轻掺杂部刻蚀形成第一过孔和第三过孔，减少薄膜晶体管的工艺步骤，提高薄膜晶体管的制备效率。
针对第一电极与第一轻掺杂部连接可能导致电子从第一轻掺杂部移动，出现漏电流，导致薄膜晶体管器件的性能较差的问题。在一种实施例中，如图5所示，所述第一重掺杂部341a的宽度L1大于所述第一轻掺杂部341b的宽度L2，所述第一电极381通过所述第一过孔371与所述第一重掺杂部341a电连接。通过使第一重掺杂部的宽度大于第一轻掺杂部的宽度，使第一电极可以直接通过第一过孔连接至第一重掺杂部，避免第一电极与第一轻掺杂部连接导致薄膜晶体管的漏电流增大，使电子会经过第一轻掺杂部和第一重掺杂部，从而减小薄膜晶体管的漏电流，提高薄膜晶体管器件的性能。
具体的，如图5所示，在第一重掺杂部341a超出第一轻掺杂部341b的区域，第一电极381通过所述第一过孔371与第一重掺杂部341a电连接，即在设置第一电极时，使第一电极在位于第一重掺杂部超出第一轻掺杂部的区域与第一重掺杂部电连接，则可以使第一电极与第一轻掺杂部不发生接触，避免增大薄膜晶体管的漏电流，提高了薄膜晶体管的性能。
针对多晶硅沿着厚度方向难以形成底层掺杂浓度高、表层掺杂浓度低的结构的问题。在一种实施例中，所述第一掺杂部的材料包括N型掺杂的非晶硅。通过采用N型掺杂的非晶硅作为第一掺杂部的材料，在形成第一轻掺杂部和第二轻掺杂部时，可以通过化学气相沉积形成第一掺杂部，然后通过控制磷化氢的比例形成底层掺杂浓度高、表层掺杂浓度低的结构，使得电子能够依次经过第一重掺杂部和第一轻掺杂部，减少漏电流，提高薄膜晶体管的性能。
在一种实施例中，所述第一重掺杂部和所述第一轻掺杂部的掺杂离子浓度比为10：1。
针对有源层的沟道尺寸变小会导致漏电流增大的问题。在一种实施例中，所述第二掺杂部在靠近所述源漏极层的一侧的掺杂离子浓度大于所述第二掺杂部在靠近所述沟道部一。的掺杂离子浓度。通过使第二掺杂部在靠近源漏极层的一侧的掺杂离子浓度大于第二掺杂部在靠近沟道部一侧的掺杂离子浓度，使第二掺杂部呈底层轻掺杂、顶层重掺杂的叠层结构，电子移动时需要经过重掺杂区域和轻掺杂区域，减小薄膜晶体管的漏电流。
在一种实施例中，如图4所示，所述第二掺杂部343包括第二重掺杂部343a和第二轻掺杂部343b，所述第二重掺杂部343a的掺杂离子浓度大于所述第二轻掺杂部343b的掺杂离子浓度，所述第二轻掺杂部343b设置于所述第二重掺杂部343a和所述沟道部342之间，且所述第二轻掺杂部343b与所述第二重掺杂部343a的侧面部分接触。通过使第二掺杂部包括第二重掺杂部和第二轻掺杂部，第二重掺杂部与第一电极电连接，第二轻掺杂部位于第二重掺杂部和沟道部之间，则可以形成第二重掺杂部、第二轻掺杂部的叠层结构，使电子移动时需要经过第二重掺杂部和第二轻掺杂部，减小薄膜晶体管的漏电流。且使得第二轻掺杂部与第二重掺杂部的侧面部分接触，增大第二轻掺杂部和第二重掺杂部的接触面积，提高薄膜晶体管的性能。
在一种实施例中，如图4所示，所述第二重掺杂部343a的厚度h1与所述第二轻掺杂部343b的厚度h2之比大于或者等于5。通过使第二重掺杂部的厚度与第二轻掺杂部的厚度之比大于或者等于5，使第二重掺杂部的厚度较大，则在实现薄膜晶体管的功能时，能够导通有源层，使薄膜晶体管正常工作。
具体的，以第一重掺杂部的底部和第一重掺杂部的顶部之间的间距作为第一重掺杂部的厚度，以第一重掺杂部的底部和第一轻掺杂部的底部之间的间距作为第一轻掺杂部的厚度。
在一种实施例中，如图4所示，所述第二电极382延伸至所述第二过孔372内，所述第二重掺杂部343a与所述第二电极382的侧面接触。通过使第二电极延伸至第二过孔内，使第二重掺杂部与第二电极的接触面积变大，从而提高第二电极和第二重掺杂部的导通效果，避免第二重掺杂部与第二电极接触不良，提高薄膜晶体管的性能。
在一种实施例中，所述第二重掺杂部和所述第二轻掺杂部的掺杂离子浓度比为10：1。
具体的，上述实施例以第一掺杂部包括第一轻掺杂部和第一重掺杂部，第二掺杂部包括第二轻掺杂部和第二重掺杂部为例分别进行了说明，但本申请实施例不限于此，在第一掺杂部包括第一轻掺杂部和第一重掺杂部时，第二掺杂部也可以包括第二轻掺杂部和第二重掺杂部，对于第一轻掺杂部、第一重掺杂部、第二轻掺杂部和第二重掺杂部的设计，可以参见上述实施例，在此不再赘述。
在一种实施例中，所述第二掺杂部包括设置于所述绝缘层远离所述沟道部的第一部分和位于所述第二过孔内的第二部分，所述第一部分和所述第二部分连接。在通过使第二电极与第二掺杂部连接时，还可以使第二掺杂部设置在第二过孔外，第二掺杂部包括位于绝缘层上的第一部分和位于第二过孔内的第二部分，则可以使第二电极与第一部分进行接触实现第二电极与第二掺杂部的连接，且可以增大第二掺杂部与第二电极的接触面积，避免第二掺杂部与第二电极接触不良，增大第二掺杂部的面积，提高薄膜晶体管的性能。
具体的，在形成第二掺杂部时，可以向过孔内沉积非晶硅，使非晶硅从绝缘层延伸至过孔内，并对非晶硅刻蚀形成第一部分和第二部分，则可以使第一部分与第二电极连接，实现薄膜晶体管的正常工作。
在一种实施例中，如图3所示，所述第二过孔372的孔径d范围为2微米至4微米。针对第二过孔的孔径过大会导致离子扩散至沟道部，第二过孔的孔径过小会导致第二掺杂部与沟道部和第二电极接触不良，使第二过孔的孔径范围为2微米至4微米，则可以使第二过孔中的第二掺杂部能与沟道部和第二电极有较好的接触，且第二过孔不会过大导致离子扩散至沟道部。
具体的，如图3所示，在第二过孔的截面为倒梯形时，以倒梯形的下底的宽度作为第二过孔的孔径。
在一种实施例中，所述第一掺杂部的宽度大于所述沟道部的宽度。通过使第一掺杂部的宽度大于所述沟道部的宽度，使得在第一电极与第一掺杂部连接时，第一电极可以与第一掺杂部超出沟道部的部分连接，从而实现第一电极和第一掺杂部的连接。
在一种实施例中，如图3所示，所述垂直结构的薄膜晶体管3还包括位于所述绝缘层35的侧壁上的栅极36，所述栅极36在所述绝缘层35的侧壁上的正投影覆盖所述沟道部342。通过使栅极设置在绝缘层的侧壁上，避免栅极影响第二掺杂部的设置，且栅极在绝缘层的侧壁上的正投影覆盖沟道部，则可以使栅极控制沟道部，实现薄膜晶体管的正常功能。
针对有源层受到光照会导致性能变差的技术问题。在一种实施例中，如图3所示，所述垂直结构的薄膜晶体管3还包括：
遮光层32，设置于所述绝缘衬底31和所述有源层34之间，所述遮光层32在所述绝缘衬底31上的正投影至少覆盖所述第二掺杂部343在所述绝缘衬底31上的正投影。通过使遮光层在绝缘衬底上正投影至少覆盖第二掺杂部在绝缘衬底上的正投影，使得遮光层能够避免外界光线照射到沟道部，避免有源层受到光照导致性能变差。
针对栅极设置在绝缘层侧会存在控制能力不足的问题。在一种实施例中，所述栅极与所述遮光层连接。通过使栅极与遮光层连接，则可以实现对有源层的半包围，提高栅极的控制能力。
在一种实施例中，遮光层的材料包括钼、钛、钨或者其叠层。
在一种实施例中，如图3所示，所述垂直结构的薄膜晶体管3还包括缓冲层33。
在一种实施例中，缓冲层的材料包括氧化硅、氮化硅、氮氧化硅或者其叠层。
在一种实施例中，所述绝缘层35包括栅极绝缘层351和层间绝缘层352。
在一种实施例中，栅极绝缘层的材料包括氧化硅、氮化硅、氮氧化硅或者其叠层。
在一种实施例中，栅极绝缘层的厚度范围为30纳米至200纳米。
在一种实施例中，栅极层的材料包括钼、钛、钨或者其叠层。
在一种实施例中，栅极层的厚度范围为0.1微米至1微米。
在一种实施例中，层间绝缘层的材料包括氧化硅和氮化硅的叠层。
在一种实施例中，源漏极层的材料包括钼、钛、钨、铝、铜或者其叠层。
同时，本申请实施例提供一种垂直结构的薄膜晶体管的制备方法，该垂直结构的薄膜晶体管制备如上述实施例任一所述的薄膜晶体管，该垂直结构的薄膜晶体管的制备方法包括：
提供绝缘衬底，并在绝缘衬底上形成遮光层；该步骤对应的垂直结构的薄膜晶体管的结构如图6中的（a）所示；
具体的，可以在绝缘衬底上沉积金属，并曝光刻蚀形成遮光层。
在遮光层上沉积缓冲层和第一掺杂部；该步骤对应的垂直结构的薄膜晶体管的结构如图6中的（b）所示；
具体的，在缓冲层上形成第一掺杂部时，可以在通过化学气相沉积将非晶硅成膜，在成膜时通入硅化氢和氢气，然后通过激光退火将非晶硅转变为多晶硅，然后通过曝光、刻蚀将多晶硅图案化，最后采用离子注入进行磷离子掺杂，得到第一掺杂部。
具体的，第一掺杂部的厚度范围为10纳米至100纳米。
具体的，在第一掺杂部包括第一轻掺杂部和第一重掺杂部时，可以通过在缓冲层上采用化学气相沉积将非晶硅成膜，并在成膜时依次通入硅化氢、氢气和磷化氢，且需要采用两步成膜，在第一步时磷化氢的流量大，在第二步时磷化氢的流量小，然后通过曝光、刻蚀形成第一掺杂部。
具体的，由于非晶硅成膜过程中含有磷离子，无需进行额外的离子注入。
具体的，第一掺杂部的厚度范围为10纳米至300纳米。
在第一掺杂部上形成沟道部；该步骤对应的垂直结构的薄膜晶体管的结构如图6中的（c）所示；
具体的，在第一掺杂部上沉积非晶硅层，并通过激光退火将非晶硅转变为多晶硅，然后通过曝光、刻蚀将多晶硅图案化形成沟道部。
具体的，沟道部的厚度范围为10纳米至100纳米。
在沟道部上形成栅极绝缘层和栅极层；该步骤对应的垂直结构的薄膜晶体管的结构如图6中的（d）所示；
在栅极绝缘层上形成层间绝缘层，并刻蚀层间绝缘层得到第二过孔；该步骤对应的垂直结构的薄膜晶体管的结构如图7中的（a）所示；
在第二过孔内形成第二掺杂部；该步骤对应的垂直结构的薄膜晶体管的结构如图7中的（b）所示；
具体的，在缓冲层上形成第二掺杂部时，可以在通过化学气相沉积将非晶硅成膜，在成膜时通入硅化氢、氢气和磷化氢，然后通过曝光、刻蚀将非晶硅图案化，得到第二掺杂部。由于非晶硅成膜过程中含有磷离子，无需进行额外的离子注入。
具体的，在第二掺杂部包括第二轻掺杂部和第二重掺杂部时，可以通过在缓冲层上采用化学气相沉积将非晶硅成膜，并在成膜时依次通入硅化氢、氢气和磷化氢，且需要采用两步成膜，在第一步时磷化氢的流量大，在第二步时磷化氢的流量小，然后通过曝光、刻蚀形成第二掺杂部。由于非晶硅成膜过程中含有磷离子，无需进行额外的离子注入。
具体的，第二掺杂部的厚度范围为300纳米至1000纳米。
刻蚀层间绝缘层得到第一过孔；该步骤对应的垂直结构的薄膜晶体管的结构如图8所示；
在层间绝缘层上形成源漏极层；该步骤对应的垂直结构的薄膜晶体管的结构如图3所示。
本申请实施例提供一种垂直结构的薄膜晶体管制备方法，该垂直结构的薄膜晶体管制备方法制备的垂直结构的薄膜晶体管通过使第一掺杂部、沟道部和第二掺杂部叠层设置，可以实现极小沟道长度的多晶硅薄膜晶体管，并通过将第二掺杂部设置于绝缘层的过孔内，使第二掺杂部通过过孔与沟道部连接且部分接触，可以减小第二掺杂部与沟道部的接触面积，则减少了扩散至沟道区的离子，提高薄膜晶体管的器件稳定性，且减少了薄膜晶体管的投影面积，提高了显示面板的开口率，有利于开发高分辨率和高刷新率的产品、甚至实现部分芯片的功能。
同时，本申请实施例提供一种电子器件，该电子器件包括如上述实施例任一所述的垂直结构的薄膜晶体管。
根据上述实施例可知：
本申请实施例提供一种垂直结构的薄膜晶体管和电子器件；该垂直结构的薄膜晶体管包括绝缘衬底、有源层和绝缘层，有源层设置于绝缘衬底一侧，有源层包括叠层设置的第一掺杂部、沟道部和第二掺杂部，绝缘层设置于沟道部远离第一掺杂部的一侧，绝缘层包括过孔，其中，第二掺杂部设置于过孔内，第二掺杂部通过过孔与沟道部连接且部分接触。本申请通过使第一掺杂部、沟道部和第二掺杂部叠层设置，可以实现极小沟道长度的多晶硅薄膜晶体管，并通过将第二掺杂部设置于绝缘层的过孔内，使第二掺杂部通过过孔与沟道部连接且部分接触，可以减小第二掺杂部与沟道部的接触面积，则减少了扩散至沟道区的离子，提高薄膜晶体管的器件稳定性，且减少了薄膜晶体管的投影面积，提高了显示面板的开口率，有利于开发高分辨率和高刷新率的产品、甚至实现部分芯片的功能。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种垂直结构的薄膜晶体管和电子器件进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种垂直结构的薄膜晶体管，其包括：
    绝缘衬底；
    有源层，设置于所述绝缘衬底的一侧，所述有源层包括叠层设置的第一掺杂部、沟道部和第二掺杂部；
    绝缘层，设置于所述沟道部远离所述第一掺杂部的一侧，所述绝缘层包括过孔；
    其中，所述第二掺杂部设置于所述过孔内，所述第二掺杂部通过所述过孔与所述沟道部连接且部分接触。
  2. 如权利要求1所述的垂直结构的薄膜晶体管，其中，所述垂直结构的薄膜晶体管还包括源漏极层，所述源漏极层设置于所述绝缘层远离所述有源层的一侧，所述源漏极层包括第一电极和第二电极，所述过孔包括第一过孔和第二过孔，所述第一电极通过所述第一过孔与所述第一掺杂部电连接，所述第二掺杂部设置于所述第二过孔内，所述第二电极与所述第二掺杂部接触。
  3. 如权利要求2所述的垂直结构的薄膜晶体管，其中，所述第一掺杂部的材料包括N型掺杂的多晶硅，所述第二掺杂部的材料包括N型掺杂的非晶硅。
  4. 如权利要求2所述的垂直结构的薄膜晶体管，其中，所述第一掺杂部在靠近所述绝缘衬底一侧的掺杂离子浓度大于所述第一掺杂部在靠近所述沟道部一侧的掺杂离子浓度。
  5. 如权利要求2所述的垂直结构的薄膜晶体管，其中，所述第一掺杂部包括第一重掺杂部和第一轻掺杂部，所述第一重掺杂部的掺杂离子浓度大于所述第一轻掺杂部的掺杂离子浓度，所述第一轻掺杂部设置于所述第一重掺杂部和所述沟道部之间。
  6. 如权利要求5所述的垂直结构的薄膜晶体管，其中，所述第一轻掺杂部包括第三过孔，所述第一电极通过所述第一过孔和所述第三过孔与所述第一重掺杂部电连接，且所述第一电极通过所述第一过孔和所述第三过孔与所述第一轻掺杂部电连接。
  7. 如权利要求5所述的垂直结构的薄膜晶体管，其中，所述第一重掺杂部的宽度大于所述第一轻掺杂部的宽度，所述第一电极通过所述第一过孔与所述第一重掺杂部电连接。
  8. 如权利要求5所述的垂直结构的薄膜晶体管，其中，所述第一掺杂部的材料包括N型掺杂的非晶硅。
  9. 如权利要求2所述的垂直结构的薄膜晶体管，其中，所述第二掺杂部在靠近所述源漏极层的一侧的掺杂离子浓度大于所述第二掺杂部在靠近所述沟道部的一侧的掺杂离子浓度。
  10. 如权利要求2所述的垂直结构的薄膜晶体管，其中，所述第二掺杂部包括第二重掺杂部和第二轻掺杂部，所述第二重掺杂部的掺杂离子浓度大于所述第二轻掺杂部的掺杂离子浓度，所述第二轻掺杂部设置于所述第二重掺杂部和所述沟道部之间，且所述第二轻掺杂部与所述第二重掺杂部的侧面部分接触。
  11. 如权利要求10所述的垂直结构的薄膜晶体管，其中，所述第二重掺杂部的厚度与所述第二轻掺杂部的厚度之比大于或者等于5。
  12. 如权利要求10所述的垂直结构的薄膜晶体管，其中，所述第二电极延伸至所述第二过孔内，所述第二重掺杂部与所述第二电极的侧面接触。
  13. 如权利要求10所述的垂直结构的薄膜晶体管，其中，所述第二重掺杂部和所述第二轻掺杂部的掺杂离子浓度比为10：1。
  14. 如权利要求2所述的垂直结构的薄膜晶体管，其中，所述第二掺杂部包括设置于所述绝缘层远离所述沟道部的第一部分和位于所述第二过孔内的第二部分，所述第一部分与所述第二部分连接。
  15. 如权利要求2所述的垂直结构的薄膜晶体管，其中，所述第二过孔的孔径范围为2微米至4微米。
  16. 如权利要求1所述的垂直结构的薄膜晶体管，其中，所述第一掺杂部的宽度大于所述沟道部的宽度。
  17. 如权利要求1所述的垂直结构的薄膜晶体管，其中，所述垂直结构的薄膜晶体管还包括位于所述绝缘层的侧壁上的栅极，所述栅极在所述绝缘层的侧壁上的正投影覆盖所述沟道部。
  18. 如权利要求17所述的垂直结构的薄膜晶体管，其中，所述垂直结构的薄膜晶体管还包括：
    遮光层，设置于所述绝缘衬底和所述有源层之间，所述遮光层在所述绝缘衬底上的正投影至少覆盖所述第二掺杂部在所述绝缘衬底上的正投影。
  19. 如权利要求18所述的垂直结构的薄膜晶体管，其中，所述栅极与所述遮光层连接。
  20. 一种电子器件，其中，所述电子器件包括如权利要求1所述的垂直结构的薄膜晶体管。
PCT/CN2022/129808 2022-08-16 2022-11-04 垂直结构的薄膜晶体管和电子器件 WO2024036762A1 (zh)

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CN103311310A (zh) * 2013-05-13 2013-09-18 北京京东方光电科技有限公司 一种薄膜晶体管及其制备方法、阵列基板
CN109473358A (zh) * 2018-10-31 2019-03-15 中国科学院微电子研究所 具有垂直沟道的场效应晶体管及其制备方法
US20200098875A1 (en) * 2018-09-26 2020-03-26 Seung Hoon Sung Epitaxial layers on contact electrodes for thin-film transistors
CN111613654A (zh) * 2020-05-27 2020-09-01 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板制作方法

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Publication number Priority date Publication date Assignee Title
CN103311310A (zh) * 2013-05-13 2013-09-18 北京京东方光电科技有限公司 一种薄膜晶体管及其制备方法、阵列基板
US20200098875A1 (en) * 2018-09-26 2020-03-26 Seung Hoon Sung Epitaxial layers on contact electrodes for thin-film transistors
CN109473358A (zh) * 2018-10-31 2019-03-15 中国科学院微电子研究所 具有垂直沟道的场效应晶体管及其制备方法
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